eroflex Circuit Technology - Advanced Multichip Modules SCD1662 REV B 9/5/01
General Description
The ACTE128K32 is a high
speed, 4 megabit, CMOS
EEPROM multichip module
(MCM) designed for full
temperature range military,
space, or high reliability
applications. The MCM can be
organized as a 256K x 16 bits
or 512K x 8 bits device and is
input and output CMOS and
TTL compatible. Writing is
executed when the write enable
(WE) and chip enable (CE)
inputs are low and output
enable (OE) is high. Reading is
accomplished when WE is high
and CE and OE are both low.
Access times grades of
120, 140, 150, 200, 250 & 300ns
are standard.
The ACTE128K32 is
packaged in a choice of
hermetically sealed co-fired
ceramic packages, a 66 pin,
1.08" sq PGA or a 68 lead, .88"
sq gullwing CQFP. The device
operates over the temperature
range of -55C to +125C and
military environment.
4 Low Power 128K x 8 EEPROM Die in One MCM
Package
Organized as 128K x 32
User Configurable to 256K x 16 or 512K x 8
CMOS and TTL Compatible Inputs and Outputs
Access Times of 120,140,150, 200, 250& 300ns
+5V 10% Supply
Automatic Page Write Operation
Page Write Cycle Time: 10ms Max
Data Retention Ten Years Minimum
Low Power CMOS
Data Polling for End of Write Detection
Industry Standard Pinouts
Packaging Hermetic Ceramic
66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder,
Aeroflex code# "P3"
66 Pin, 1.08" x 1.08" x .185" PGA Type, With
Shoulder, Aeroflex code# "P7"
68 Lead, .88" x .88" x .200" Dual-Cavity Small
Outline Gull Wing, Aeroflex code# "F2"
(Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)
MIL-PRF-38534 Compliant MCMs Available
Hardware and Software Data Protection
Internal Decoupling Capacitors for Low Noise
Operation
Commercial, Industrial and Military Temperature
Ranges
SMD# 596294585 Released (P7 & F2)
Features
128Kx8
128Kx8
128Kx8
CE
4
OE
A
0
A
16
I/O
0-7
I/O
8-15
I/O
16
-
23
I/O
24-31
8
8
8
8
CE
3
WE
4
WE
3
WE
2
WE
1
CE
1
CE
2
128Kx8
Pin Description
I/O
0-31
Data I/O
A
016
Address Inputs
WE
1-4
Write Enables
OE
Output Enable
CE
1-4
Chip Enables
V
CC
Power Supply
GND
Ground
Block Diagram PGA Type Package (P3,P7) & CQFP (F2)
ACTE128K32 High Speed
4 Megabit EEPROM Multichip Module
CIRCUIT TECHNOLOGY
www.aeroflex.com
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SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700
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Absolute Maximum Ratings
Parameter
Symbol
Range
Units
Operating Temperature
T
C
-55 to +125
C
Storage Temperature Range
T
STG
-65 to +150
C
All Input Voltages with respect to Ground
V
G
-0.6 to +6.25
V
All Output Voltages with respect to Ground
-
-0.6 to V
CC
+0.6
V
Voltage on OE and A9 with respect to Ground
-
-0.6 to +13.5
V
NOTICE: Stresses above those listed under "Absolute Maximums Rating" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Symbol
Parameter
Minimum
Maximum
Units
V
CC
Power Supply Voltage
+4.5
+5.5
V
V
IH
Input High Voltage
+2.0
V
CC
+ 0.3
V
V
IL
Input Low Voltage
-0.5
+0.8
V
T
C
Case Operating Temperature (Military)
-55
+125
C
Capacitance
(V
IN
= 0V, f = 1MHz, T
C
= 25C)
Symbol
Parameter
Maximum
Units
C
AD
A
0
A
16
Capacitance
50
pF
C
OE
Output Enable Capacitance
50
pF
C
WE
(1-4)
Write Enable Capacitance
20
pF
C
CE
(1-4)
Chip Enable Capacitance
20
pF
C
I
/
O
I/O0 I/O31 Capacitance
20
pF
DC Characteristics
(Vcc = 5.0V, Vss = 0V, T
C
= -55C to +125C, unless otherwise specified)
Parameter
Sym
Conditions
Minimum
Maximum
Units
Input Leakage Current
I
LI
V
CC
= 5.5V, V
IN
= GND to V
CC
10
A
Output Leakage Current
I
LO
X
32
CE = OE = V
IH
,
V
OUT
= GND to V
CC
10
A
Operating Supply Current x 32 Mode
I
CC
X
32
CE = V
IL
,
OE = V
IH
, f = 5Mhz
250
mA
Operating Supply Current
I
SB
CE = V
IH
, OE = V
IH
,
f = 5Mhz
5
mA
Output Low Voltage
V
OL
I
OL
= +2.1mA, V
CC
= 4.5V
0.45
V
Output High Voltage
V
OH
I
OH
= 400A, V
CC
= 4.5V
2.4
V
Truth Table
CE
OE
WE
Mode
Data I/O
H
X
X
Standby
High Z
L
L
H
Read
Data Out
L
H
L
Write
Data In
X
H
X
Out Disable
High Z
X
X
H
Write
Inhibit
-
X
L
X
-
A
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SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700
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AC Write Characteristics
(V
CC
= 5V, V
SS
= 0V, T
C
= -55C to +125C)
Parameter
Symbol
Min Max
Units
Write Cycle Time
t
WC
10
ms
Address Set-up Time
t
AS
10
ns
Write Pulse Width (WE or CE)
t
WP
150
ns
Chip Enable Set-up Time
t
CE
0
ns
Address Hold Time
t
AH
100
ns
Data Hold Time
t
DH
10
ns
Chip Enable Hold Time
t
CEH
0
ns
Data Set-up Time
t
DS
100
ns
Output Enable Set-up Time
t
OES
10
ns
Output Enable Hold Time
t
OEH
10
ns
AC Read Characteristics
(V
CC
= 5V, V
SS
= 0V, T
C
= -55C to +125C)
Read Cycle Parameter
Symbol
120
Min Max
140
Min Max
150
Min Max
200
Min Max
250
Min Max
300
Min Max
Units
Read Cycle Time
t
RC
120
140
150
200
250
300
ns
Address Access Time
t
ACC
120
140
150
200
250
300
ns
Chip Enable Access Time
t
ACE
120
140
150
200
250
300
ns
Output Hold From Address Change,
OE or CE
t
OH
0
0
0
0
0
0
ns
Output Enable to Output Valid
t
OE
0
55
0
55
0
55
0
55
0
85
0
85
ns
Chip Enable or OE to High Z Output
t
DF
70
70
70
70
70
70
ns
Page Write Characteristics
(V
CC
= 5V, V
SS
= 0V, T
C
= -55C to +125C)
Parameter
Symbol
Minimum
Maximum
Units
Write Cycle Time
t
WC
10
ms
Address Set-up Time
t
AS
10
ns
Address Hold Time , See Note 1
t
AH
100
ns
Data Set-up Time
t
DS
100
ns
Data Hold Time
t
DH
10
ns
Write Pulse Width
t
WP
150
ns
Byte Load Cycle Time
t
BLC
150
s
Write Pulse Width High
t
WPH
50
ns
Note 1 Page Address must remain valid for duration of write cycle.
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Device Operation
The ACT-E128K32 is a high-performance
Electrically Erasable and Programmable
Read Only Memory. It is composed of four 1
megabit memory chips and is organized as
131,072 by 32 bits. The device offers access
times of 120 to 300ns with power dissipation
of 1.375W. When the device is deselected,
the CMOS standby current is less than 5 mA.
The ACT-E128K32 is accessed like a Static
RAM for the read or write cycle without the
need for external components. The device
contains a 128-byte page register to allow
writing of up to 128 bytes simultaneously.
During a write cycle, the address and 1 to
128 bytes of data are internally latched,
freeing the address and data bus for other
operations. Following the initiation of a write
cycle, the device will automatically write the
latched data using an internal control timer.
The end of a write cycle can be detected by
DATA polling of I/O7. Once the end of a write
cycle has been detected a new access for a
read or write can begin.
Aeroflex's ACT-E128K32 has additional
features to ensure high quality and
manufacturability. The device utilizes internal
error correction for extended endurance and
improved data retention characteristics. An
optional software data protection mechanism
is available to guard against inadvertent
writes.
WRITE
A write cycle is initiated when OE is high and
a low pulse is on WE or CE with CE or WE
low. The address is latched on the falling
edge of CE or WE whichever occurs last.
The data is latched by the rising edge of CE
or WE, whichever occurs first. A byte write
operation will automatically continue to
completion.
WRITE CYCLE TIMING
Figures 2 and 3 show the write cycle timing
relationships. A write cycle begins with
address application, write enable and chip
enable. Chip enable is accomplished by
placing the CE line low. Write enable
consists of setting the WE line low. The write
cycle begins when the last of either CE or
WE goes low.
The WE line transition from high to low also
initiates an internal delay timer to permit
page mode operation. Each subsequent WE
transition from high to low that occurs before
the completion of the
t
BLC
time out will restart
the timer from zero. The operation of the
timer is the same as a retriggable one-shot.
READ
The ACT-E128K32 stores data at the
memory location determined by the address
pins. When CE and OE are low and WE is
high, this data is present on the outputs.
When CE and OE are high, the outputs are in
a high impedance state. This two line control
prevents bus contention.
DATA POLLING
The ACT-E128K32 offers a data polling
feature which allows a faster method of
writing to the device. Figure 5 shows the
timing diagram for this function. During a
byte or page write cycle, an attempted read
of the last byte written will result in the
complement of the written data on I/O7 (For
each Chip). Once the write cycle has been
completed, true data is valid on all outputs
and the next cycle may begin. Data polling
may begin at any time during the write cycle.
PAGE WRITE OPERATION
The ACT-E128K32 has a page write
operation that allows one to 128 bytes of data
to be written into the device and
consecutively loads during the internal
programming period. Successive bytes may
be loaded in the same manner after the first
data byte has been loaded. An internal timer
begins a time out operation at each write
cycle. If another write cycle is completed
within
t
BLC
or less, a new time out period
begins. Each write cycle restarts the delay
period. The write cycles can be continued as
long as the interval is less than the time out
period.
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The usual procedure is to increment the least
significant address lines from A0 through A6
at each write cycle. In this manner a page of
up to 128 bytes can be loaded in to the
EEPROM in a burst mode before beginning
the relatively long interval programming
cycle.
After the
t
BLC
time out is completed, the
EEPROM begins an internal write cycle.
During this cycle the entire page will be
written at the same time. The internal
programming cycle is the same regardless of
the number of bytes accessed.
SOFTWARE DATA PROTECTION
A software write protection feature may be
enabled or disabled by the user. When
shipped by Aeroflex Microelectronics, the
ACT-E128K32 has the feature disabled.
Write access to the device is unrestricted.
To enable software write protection, the user
writes three access code bytes to three
special internal locations. Once write
protection has been enabled, each write to
the EEPROM must use the same three byte
write sequence to permit writing. The write
protection feature can be disabled by a six
byte write sequence of specific data to
specific locations. Power transitions will not
reset the software write protection.
Each 128K byte block of the EEPROM has
independent write protection. One or more
blocks may be enabled and the rest disabled
in any combination. The software write
protection guards against inadvertent writes
during power transitions, or unauthorized
modification using a PROM programmer.
HARDWARE DATA PROTECTION
These features protect against inadvertent
writes to the ACT-E128K32. These are
included to improve reliability during normal
operation:
A) Vcc Sense
While below 3.8V typical write cycles
are inhibited.
B) Write inhibiting
Holding OE low and either CE or WE
high inhibits write cycles.
C) Noise filter
Pulses of <10ns (TYP) on WE or CE
will not initiate a write cycle.
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SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700
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Data Polling Characteristics
(V
CC
= 5V, V
SS
= 0V, T
C
= -55C to +125C)
Parameter
Symbol
Min
Max
Units
Data Hold Time
t
DH
10
ns
OE Hold Time
t
OEH
10
ns
OE to Output Valid
t
OE
55
ns
Write Recovery Time
t
WR
0
ns
Guaranteed. But not tested.
I
OL
Parameter
Typical
Units
Input Pulse Level
0 3.0
V
Input Rise and Fall
5
ns
Input and Output Timing Reference Level
1.5
V
Output Lead Capacitance
50
pF
Notes:
1) V
Z
is programmable from -2V to +7V. 2) I
OL
and I
OH
programmable from 0 to 16 mA. 3) Tester Impedance Z
O
= 75
. 4) V
Z
is typically the
midpoint of V
OH
and V
OL
. 5) I
OL
and I
OH
are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance.
I
OH
To Device Under Test
V
Z
~ 1.5 V
Current Source
Current Source
C
L
=
50 pF
Figure 1
AC Test Circuit
Write Waveforms WE Controlled
Figure 2
DATA IN
ADDRESS
CE
WE
OE
t
AS
t
OES
t
WP
t
CE
t
OEH
t
CEH
t
WPH
t
DH
t
DS
t
AH
t
WC
(Bipolar Supply)
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Write Waveforms CE Controlled
Figure 3
DATA IN
ADDRESS
WE
CE
OE
t
AS
t
OES
t
WP
t
CE
t
OEH
t
CEH
t
WPH
t
DH
t
DS
t
AH
t
WC
Notes:
1. OE may be delayed up to t
ACS
t
OE
after the falling edge of CE without impact on t
OE
or by t
ACC
t
OE
after an address change without impact on t
ACC
.
Read Waveforms
Figure 4
OE
CE
ADDRESS
OUTPUT
t
ACE
t
OE
t
ACC
t
DF
t
OH
Output
High Z
Address Valid
Valid
t
RC
A
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SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700
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Figure 5
Data Polling Waveform
t
OEH
t
OE
t
DH
t
WR
CE
1-4
WE
1-4
I/O
7
OE
ADDRESS
High Z
A
N
A
N
A
N
A
N
A
N
CE
X
t
WP
t
WPH
t
BLC
t
AS
t
AH
t
DH
t
DS
t
WC
OE
WE
X
DATA
ADDRESS
Notes:
1. A7 through A16 must specify the sector address during each high to low transition of WE (or CE) after the software codes have been entered.
2. OE must be high when WE and CE are both low.
Valid DATA
Byte 127
Figure 6
Page Mode Write Waveforms
Byte 0
Byte 1
Byte 2
Byte 3
Valid ADD
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Figure 7
Software Data
To
Load Data AA
Address 5555
To
Load Data 55
Address 2AAA
To
Load Data A0
Address 5555
To
Load Data XX
Any Address
(4)
Writes Enabled
(2)
NOTES:
1. Data Format: I/O0 - I/O7 (Hex);
Address Format: A14 - A0 (Hex).
2. Write Protect state will be activated at end ot write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 128 bytes of data may be loaded.
To
Load Data AA
Address 5555
To
Load Data 55
Address 2AAA
To
Load Data 80
Address 5555
To
Load Data AA
Address 5555
(4)
Exit Data
Protect State
(3)
To
Load Data 55
Address 2AAA
To
Load Data 20
Address 5555
To
Load Data XX
Any Address
(4)
Figure 8
Protection Enable Algorithm
(1)
To
Load Last Byte
Last Address
Enter Data
Protect State
Software Data
Protection Disable Algorithm
(1)
To
Load Last Byte
Last Address
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Pin Numbers & Functions
66 Pins -- PGA Type Package
Pin #
Function
Pin #
Function
Pin #
Function
Pin #
Function
1
I/O
8
18
A
12
35
I/O
25
52
WE
3
2
I/O
9
19
Vcc
36
I/O
26
53
CE
3
3
I/O
10
20
CE
1
37
A
6
54
GND
4
A
13
21
NC
38
A
7
55
I/O
19
5
A
14
22
I/O
3
39
NC
56
I/O
31
6
A
15
23
I/O
15
40
A
8
57
I/O
30
7
A
16
24
I/O
14
41
A
9
58
I/O
29
8
NC
25
I/O
13
42
I/O
16
59
I/O
28
9
I/O
0
26
I/O
12
43
I/O
17
60
A
0
10
I/O
1
27
OE
44
I/O
18
61
A
1
11
I/O
2
28
NC
45
V
CC
62
A
2
12
WE
2
29
WE
1
46
CE
4
63
I/O
23
13
CE
2
30
I/O
7
47
WE
4
64
I/O
22
14
GND
31
I/O
6
48
I/O
27
65
I/O
21
15
I/O
11
32
I/O
5
49
A
3
66
I/O
20
16
A
10
33
I/O
4
50
A
4
17
A
11
34
I/O
24
51
A
5
Note: Pins 8, 21, 28 & 39 can be connected to ground by specifing Option "C".
1.085 SQ
1.000
.600
1.000
.100
.020
.016
.100
.180
TYP
1.030
1.040
.160
Pin 56
Pin 66
Pin 11
Pin 1
Bottom View (P7 & P3)
MAX
MAX
"P3" -- 1.08" SQ PGA Type (without shoulder) Package
"P7" -- 1.08" SQ PGA Type (with shoulder) Package
1.030
1.040
.020
.016
.100
.025
.185
MAX
Side View
(P7)
Side View
(P3)
.050
.180
TYP
.035
All dimensions in inches
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Pin Numbers & Functions
68 Pins -- Dual-Cavity CQFP
Pin #
Function
Pin #
Function
Pin #
Function
Pin #
Function
1
GND
18
GND
35
OE
52
GND
2
CE
3
19
I/O
8
36
CE
2
53
I/O
23
3
A
5
20
I/O
9
37
NC
54
I/O
22
4
A
4
21
I/O
10
38
WE
2
55
I/O
21
5
A
3
22
I/O
11
39
WE
3
56
I/O
20
6
A
2
23
I/O
12
40
WE
4
57
I/O
19
7
A
1
24
I/O
13
41
NC
58
I/O
18
8
A
0
25
I/O
14
42
NC
59
I/O
17
9
NC
26
I/O
15
43
NC
60
I/O
16
10
I/O
0
27
V
cc
44
I/O
31
61
V
CC
11
I/O
1
28
A
11
45
I/O
30
62
A
10
12
I/O
2
29
A
12
46
I/O
29
63
A
9
13
I/O
3
30
A
13
47
I/O
28
64
A
8
14
I/O
4
31
A
14
48
I/O
27
65
A
7
15
I/O
5
32
A
15
49
I/O
26
66
A
6
16
I/O
6
33
A
16
50
I/O
25
67
WE1
17
I/O
7
34
CE
1
51
I/O
24
68
CE
4
Top View
All dimensions in inches
Package Outline -- Dual-Cavity CQFP "F2"
.015
.990 SQ
.010
.880 SQ
.010
.800 REF
.050
.946
.010
See Detail "A"
Detail "A"
*.200 MAX
.010 REF
0- 7
.040
0.010 R
.010 .005
TYP
.010
Pin 60
Pin 44
Pin 43
Pin 27
Pin 26
Pin 10
Pin 9
Pin 61
*.180 MAX available, call factory for details
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Ordering Information
Model Number
DESC Drawing Number
Speed
Package
ACT-E128K32N-120P7Q
5962-9458506H4X
120ns
PGA Type
ACT-E128K32C-120P7Q
5962-9458506H5X
120ns
PGA Type
ACT-E128K32N-140P7Q
5962-9458505H4X
140ns
PGA Type
ACT-E128K32C-140P7Q
5962-9458505H5X
140ns
PGA Type
ACT-E128K32N-150P7Q
5962-9458504H4X
150ns
PGA Type
ACT-E128K32C-150P7Q
5962-9458504H5X
150ns
PGA Type
ACT-E128K32N-200P7Q
5962-9458503H4X
200ns
PGA Type
ACT-E128K32C-200P7Q
5962-9458503H5X
200ns
PGA Type
ACT-E128K32N-250P7Q
5962-9458502H4X
250ns
PGA Type
ACT-E128K32C-250P7Q
5962-9458502H5X
250ns
PGA Type
ACT-E128K32N-300P7Q
5962-9458501H4X
300ns
PGA Type
ACT-E128K32C-300P7Q
5962-9458501H5X
300ns
PGA Type
ACT-E128K32N-120F2Q
5962-9458506HMX
120ns
CQFP
ACT-E128K32N-140F2Q
5962-9458505HMX
140ns
CQFP
ACT-E128K32N-150F2Q
5962-9458504HMX
150ns
CQFP
ACT-E128K32N-200F2Q
5962-9458503HMX
200ns
CQFP
ACT-E128K32N-250F2Q
5962-9458502HMX
250ns
CQFP
ACT-E128K32N-300F2Q
5962-9458501HMX
300ns
CQFP
Part Number Breakdown
ACT E 128K 32 N 200 P7 M
Aeroflex Circuit
Technology
Memory Type
E = EEPROM
Memory Depth
Options
Memory Width, Bits
N = None
C = Connect to GND Pins 8,21,28,39 (P3 & P7 Pkg only)
Memory Speed, ns
Package Type & Size
Surface Mount Packages
Thru-Hole Packages
F2 = .88"SQ 68 Lead Dual-Cavity
CQFP
P3 = 1.085"SQ PGA 66 Pins
without shoulder
P7 = 1.085"SQ PGA 66 Pins
with shoulder
C = Commercial Temp, 0C to +70C
I = Industrial Temp, -40C to +85C
T = Military Temp, -55C to +125C
M = Military Temp, -55C to +125C, Screening
*
Q = MIL-PRF-38534 Compliant / SMD
Screening
*
Screened to the individual test methods of MIL-STD-883
Specifications subject to change without notice.
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11830
Telephone: (516) 694-6700
FAX: (516) 694-6715
Toll Free Inquiries: 1-(800) 843-1553
C I R C U I T T E C H N O L O G Y
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