eroflex Circuit Technology - Advanced Multichip Modules © SCD1676 REV A 5/6/98

CIRCUIT TECHNOLOGY

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General Description

The ACTF128K8 is a high

speed, 1 megabit CMOS
monolithic Flash module
designed for full temperature
range military, space, or high
reliability applications.

This device is input TTL and

output CMOS compatible. The
command register is written by
bringing write enable (WE) and
chip enable (CE) to a logic low
level and output enable (OE) to a
logic high level. Reading is
accomplished when WE is high
and CE, OE are both low, see
Figure 9. Access time grades of
60ns, 70ns, 90ns, 120ns and
150ns maximum are standard.

The ACTF128K8 is

available in a choice of

Features

Low Power Monolithic 128K x 8 FLASH

TTL Compatible Inputs and CMOS Outputs

Access Times of 60, 70, 90, 120 and 150ns

+5V Programing, +5V Supply

100,000 Erase / Program Cycles

Low Standby Current

Page Program Operation and Internal

Program Control Time

Supports Full Chip Erase

Embedded Erase and Program Algorithms

Supports Full Chip Erase

MIL-PRF-38534 Compliant Circuits Available

Industry Standard Pinouts

Packaging Hermetic Ceramic

32 Lead, 1.6" x .6" x .20" Dual-in-line Package (DIP),
Aeroflex code# "P4"

32 Lead, .82" x .41" x .125" Ceramic Flat Package
(FP), Aeroflex code# "F6"

32 Lead, .82" x .41" x .132" Ceramic Flat Package
(FP Lead Formed), Aeroflex code# "F7"

Sector Architecture

8 Equal size sectors of 16K bytes each

Any Combination of Sectors can be erased with one
command sequence.

Commercial, Industrial and Military

Temperature Ranges

DESC SMD Pending

5962-96690 (P4,F6,F7)

Block Diagram DIP (P4) & Flat Packages (F6,F7)

512Kx8

I/O

0-7

Vss

Vcc

Pin Description

I/O

0-7

Data I/O

016

Address Inputs

Write Enable

Chip Enable

Output Enable

Power Supply

Ground

Not Connected

ACTF128K8 High Speed

1 Megabit Monolithic FLASH

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hermetically sealed ceramic packages; a
32 lead .82" x .41" x .125" flat package in
both formed or unformed leads or a 32 pin
1.6"x.60" x.20" DIP package for operation
over the temperature range -55°C to
+125°C and military environmental
conditions.

The flash memory is organized as

128Kx8 bits and is designed to be
programmed in-system with the standard
system 5.0V Vcc supply. A 12.0V V

not required for write or erase operations.
The device can also be reprogrammed with
standard EPROM programmers (with the
proper socket).

The standard ACTF128K8 offers

access times between 60ns and 150ns,
allowing operation of high-speed
microprocessors without wait states. To
eliminate bus contention, the device has
separate chip enable (CE), write enable
(WE) and output enable (OE) controls. The
ACTF128K8 is command set compatible
with JEDEC standard 1 Mbit EEPROMs.
Commands are written to the command
register using standard microprocessor
write timings. Register contents serve as
input to an internal state-machine which
controls the erase and programming
circuitry. Write cycles also internally latch
addresses and data needed for the
programming and erase operations.

Reading data out of the device is similar

to reading from 12.0V Flash or EPROM
devices. The ACTF128K8 is programmed
by executing the program command
sequence. This will invoke the Embedded
Program Algorithm which is an internal
algorithm that automatically times the
program pulse widths and verifies proper
cell margin. Typically, each sector can be
programmed and verified in less than 0.3

second. Erase is accomplished by
executing the erase command sequence.
This will invoke the Embedded Erase
Algorithm which is an internal algorithm
that automatically preprograms the array, (if
it is not already programmed before)
executing the erase operation. During
erase, the device automatically times the
erase pulse widths and verifies proper cell
margin.

Also the device features a sector erase

architecture. The sector mode allows for
16K byte blocks of memory to be erased
and reprogrammed without affecting other
blocks. The ACT-F128K8 is erased when
shipped from the factory.

The device features single 5.0V power

supply operation for both read and write
functions. lnternally generated and
regulated voltages are provided for the
program and erase operations. A low V

detector automatically inhibits write
operations on the loss of power. The end of
program or erase is detected by Data
Polling of D7 or by the Toggle Bit feature on
D6. Once the end of a program or erase
cycle has been completed, the device
internally resets to the read mode.

All bits of each die, or all bits within a

sector of a die, are erased via
Fowler-Nordhiem tunneling. Bytes are
programmed one byte at a time by hot
electron injection.

A DESC Standard Military Drawing

(SMD) number is pending.

General Description, Cont'd

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Absolute Maximum Ratings

Parameter

Symbol

Range

Units

Case Operating Temperature

-55 to +125

°C

Storage Temperature Range

STG

-65 to +150

°C

Supply Voltage Range

-2.0 to +7.0

Signal Voltage Range (Any Pin Except A9) Note 1

-2.0 to +7.0

Maximum Lead Temperature (10 seconds)

300

°C

Data Retention

Years

Endurance (Write/Erase cycles)

100,000 Minimum

A9 Voltage for sector protect, Note 2

-2.0 to +14.0

Note 1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot V

to -2.0v for periods of

up to 20ns. Maximum DC voltage on input and I/O pins is V

+ 0.5V. During voltage transitions, inputs and I/O pins may

overshoot to V

+ 2.0V for periods up to 20 ns.

Note 2. Minimum DC input voltage on A9 is -0.5V. During voltage transitions, A9 may undershoot V

to -2.0V for periods of up to 20ns.

Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns.

Normal Operating Conditions

Symbol

Parameter

Minimum

Maximum

Units

Power Supply Voltage

+4.5

+5.5

Input High Voltage

+2.0

+ 0.5

Input Low Voltage

-0.5

+0.8

Operating Temperature (Military)

-55

+125

°C

A9 Voltage for sector protect

11.5

12.5

Capacitance

= 0V, f = 1MHz, Tc = 25°C)

Symbol

Parameter

Maximum

Units

Capacitance

OE Capacitance

Write Enable Capacitance

Chip Enable Capacitance

I/O0 I/O7 Capacitance

Parameters Guaranteed but not tested

DC Characteristics CMOS Compatible

(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C, unless otherwise indicated)

Parameter

Sym

Conditions

Speeds 60, 70, 90, 120 & 150ns

Minimum

Maximum

Units

Input Leakage Current

= 5.5V, V

= GND to V

µA

Output Leakage Current

= 5.5V, V

= GND to V

µA

Active Operating Supply Current for Read (1)

CE = V

OE = V

, f = 5MHz

Active Operating Supply Current for Program or Erase (2)

CE = V

OE = V

Operating Standby Supply Current

= 5.5V, CE = V

, f = 5MHz

1.6

Output Low Voltage

= +8.0 mA, V

= 4.5V

0.45

Output High Voltage

= 2.5 mA, V

= 4.5V

0.85 x V

Low Power Supply Lock-Out Voltage (4)

LKO

3.2

Note 1. The Icc current listed includes both the DC operating current and the frequency dependent component (At 6 MHz). The frequency

component typically is less than 2 mA/MHz, with OE at V

Note 2. Icc active while Embedded Algorithm (Program or Erase) is in progress.
Note 3. DC Test conditions: V

= 0.3V, V

= V

- 0.3V, unless otherwise indicated.

Note 4. Parameter Guaranteed by design, but not tested.

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AC Characteristics Read Only Operations

(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)

Parameter

Symbol

JEDEC Stand'd

60

Min Max

70

Min Max

90

Min Max

120

Min Max

150

Min Max

Units

Read Cycle Time

AVAV

120

150

Address Access Time

AVQV

ACC

120

150

Chip Enable Access Time

ELQV

120

150

Output Enable to Output Valid

GLQV

Chip Enable to Output High Z (1)

EHQZ

Output Enable High to Output High Z(1)

GHQZ

Output Hold from Address, CE or OE Change, Whichever is First

AXQX

Note 1. Guaranteed by design, but not tested

AC Characteristics Write/Erase/Program Operations, WE Controlled

(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)

Parameter

Symbol

JEDEC Stand'd

60

Min Max

70

Min Max

90

Min Max

120

Min Max

150

Min Max

Units

Write Cycle Time

AVAC

120

150

Chip Enable Setup Time

ELWL

Write Enable Pulse Width

WLWH

Address Setup Time

AVWL

Data Setup Time

DVWH

Data Hold Time

WHDX

Address Hold Time

WLAX

Write Enable Pulse Width High

WHWL

WPH

Duration of Byte Programming Operation
Typ = 16 µs

WHWH

TYP

µs

Sector Erase Time

WHWH

Sec

Read Recovery Time before Write

GHWL

µs

Vcc Setup Time

VCE

µs

Chip Programming Time

12.5

Sec

Chip Erase Time

WHWH

120

Sec

AC Characteristics Write/Erase/Program Operations, CE Controlled

(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)

Parameter

Symbol

JEDEC Stand'd

60

Min Max

70

Min Max

90

Min Max

120

Min Max

150

Min Max

Units

Write Cycle Time

AVAC

120

150

Write Enable Setup Time

WLE

Chip Enable Pulse Width

ELEH

Address Setup Time

AVEL

Data Setup Time

DVEH

Data Hold Time

EHDX

Address Hold Time

ELAX

Chip Select Pulse Width High

EHEL

CPH

Duration of Byte Programming

WHWH

TYP

µs

Sector Erase Time

WHWH

Sec

Read Recovery Time

GHEL

Chip Programming Time

12.5

Sec

Chip Erase Time

WHWH

120

Sec

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Device Operation

The ACT-F128K8 Monolithic module is composed of one,
1 megabit flash EEPROM.

Programming of the ACT-F128K8 is accomplished by
executing the program command sequence. The
program algorithm, which is an internal algorithm,
automatically times the program pulse widths and
verifies proper cell status. Sectors can be programed
and verified in less than 0.3 second. Erase is
accomplished by executing the erase command
sequence. The erase algorithm, which is internal,
automatically preprograms the array if it is not already
programed before executing the erase operation. During
erase, the device automatically times the erase pulse
widths and verifies proper cell status. The entire
memory is typically erased and verified in 3 seconds
(if pre-programmed). The sector mode allows for 16K
byte blocks of memory to be erased and reprogrammed
without affecting other blocks.

Bus Operation

READ

The ACT-F128K8 has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output-Enable (OE)
is the output control and should be used to gate data to
the output pins of the chip selected. Figure 7 illustrates
AC read timing waveforms.

OUTPUT DISABLE

With Output-Enable at a logic high level (V

), output

from the device is disabled. Output pins are placed in a
high impedance state.

STANDBY MODE

The ACT-F128K8 has two standby modes, a CMOS
standby mode (CE input held at Vcc + 0.5V), where the
current consumed is typically less than 400 µA; and a
TTL standby mode (CE is held V

) is approximately 1

mA. In the standby mode the outputs are in a high
impedance state, independent of the OE input.

If the device is deselected during erasure or

programming, the device will draw active current until the
operation is completed.

WRITE

Device erasure and programming are accomplished via
the command register. The contents of the register
serve as input to the internal state machine. The state
machine outputs dictate the function of the device.

The command register itself does not occupy an
addressable memory location. The register is a latch
used to store the command, along with address and data
information needed to execute the command. The
command register is written by bringing WE to a logic
low level (V

), while CE is low and OE is at V

Addresses are latched on the falling edge of WE or CE,
whichever happens later. Data is latched on the rising
edge of the WE or CE whichever occurs first. Standard
microprocessor write timings are used. Refer to AC
Program Characteristics and Waveforms, Figures 3,
8 and 13.

Command Definitions

Device operations are selected by writing specific
address and data sequences into the command register.
Table 3 defines these register command sequences.

READ/RESET COMMAND

The read or reset operation is initiated by writing the
read/reset command sequence into the command
register. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for reads
until the command register contents are altered.

The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will
retrieve array data. The device will automatically
power-up in the read/reset state. In this case, a
command sequence is not required to read data.
Standard Microprocessor read cycles will retrieve array
data. This default value ensures that no spurious
alteration of the memory content occurs during the
power transition. Refer to the AC Read Characteristics
and Figure 7 for the specific timing parameters.

Table 1 Bus Operations

Operation

CE OE WE A0 A1 A9

I/O

READ

DOUT

STANDBY

HIGH Z

OUTPUT DISABLE

HIGH Z

WRITE

ENABLE SECTOR

PROTECT

VERIFY SECTOR

PROTECT

Code

Table 2 Sector Addresses Table

A16 A15

A14

Address Range

SA0

00000h 03FFFh

SA1

04000h 07FFFh

SA2

08000h 0BFFFh

SA3

0C000h 0FFFFh

SA4

10000h 13FFFh

SA5

14000h 17FFFh

SA6

18000h 1BFFFh

SA7

1C000h 1FFFFh

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BYTE PROGRAMING

The device is programmed on a byte-byte basis.
Programming is a four bus cycle operation. There are
two "unlock" write cycles. These are followed by the
program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE,
whichever occurs later, while the data is latched on the
rising edge of CE or WE whichever occurs first. The
rising edge of CE or WE (whichever happens first)
begins programming using the Embedded Program
Algorithm. Upon executing the program algorithm
command sequence the system is not required to
provide further controls or timings. The device will
automatically provide adequate internally generated
program pulses and verify the programmed cell.

The automatic programming operation is completed
when the data on D

7 (

also used as Data Polling) is

equivalent to data written to this bit at which time the
device returns to the read mode and addresses are no
longer latched. Therefore, the device requires that a
valid address be supplied by the system at this particular
instance of time for Data Polling operations. Data Polling
must be performed at the memory location which is
being programmed.

Any commands written to the chip during the Embedded
Program Algorithm will be ignored.

Programming is allowed in any sequence and across
sector boundaries. Beware that a data "0" cannot be
programmed back to a "1". Attempting to do so may
cause the device to exceed programming time limits (D5
= 1) or result in an apparent success, according to the
data polling algorithm, but a read from reset/read mode
will show that the data is still "0". Only erase operations
can convert "0"s to "1"s.

Figure 3 illustrates the programming algorithm using
typical command strings and bus operations.

CHIP ERASE

Chip erase is a six bus cycle operation. There are two
'unlock' write cycles. These are followed by writing the
"set-up" command. Two more "unlock" write cycles are
then followed by the chip erase command.

Chip erase does not require the user to program the

device prior to erase. Upon executing the Embedded
Erase Algorithm command sequence (Figure 4) the
device will automatically program and verify the entire
memory for an all zero data pattem prior to electrical
erase. The erase is performed concurrently on all
sectors at the same time . The system is not required to
provide any controls or timings during these operations.
Note: Post Erase data state is all "1"s.

The automatic erase begins on the rising edge of the last
WE pulse in the command sequence and terminates
when the data on D7 is "1" (see Write Operation Status
section - Table 3) at which time the device retums to read
mode. See Figures 4 and 9.

SECTOR ERASE

Sector erase is a six bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"setup" command. Two more "unlock" write cycles are
then followed by the sector erase command. The sector
address (any address location within the desired sector)
is latched on the falling edge of WE, while the command
(30H) is latched on the rising edge of WE. After a
time-out of 80µs from the rising edge of the last sector
erase command, the sector erase operation will begin.

Multiple sectors may be erased concurrently by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the sector erase
command to addresses in other sectors desired to be
concurrently erased. The time between writes must be
less than 80µs otherwise that command will not be
accepted and erasure will start. It is recommended that
processor interrupts be disabled during this time to
guarantee this condition. The interrupts can be
re-enabled after the last Sector Erase command is
written. A time-out of 80µs from the rising edge of the
last WE will initiate the execution of the Sector Erase
command(s). If another falling edge of the WE occurs
within the 80µs time-out window the timer is reset.
(Monitor D3 to determine if the sector erase timer
window is still open, see section D3, Sector Erase
Timer.) Any commarid other than Sector Erase during
this period will reset the device to read mode, ignoring
the previous command string. In that case, restart the
erase on those sectors and allow them to complete.

Table 3 -- Commands Definitions

Command
Sequence

Bus

Write

Cycle

Req'd

First Bus Write

Cycle

Second Bus Write

Cycle

Third Bus Write

Cycle

Fourth Bus

Read/Write

Cycle

Fifth Bus Write

Cycle

Sixth Bus Write

Cycle

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read/Reset

5555H

AAH

2AAAH

55H

5555H

F0H

Byte Program

5555H

AAH

2AAAH

55H

5555H

A0H

Chip Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

5555H

10H

Sector Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

30H

NOTES:
1. Address bit A15 = X = Don't Care. Write Sequences may be initiated with A15 in either state.
2. Address bit A16 = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA).
3. RA = Address of the memory location to be read

PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A16, A15, A14 will uniquely select any sector.

4. RD = Data read from location RA during read Operation.

PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.

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Loading the sector erase buffer may be done in any
sequence and with any number of sectors (0 to 7).

Sector erase does not require the user to program the
device prior to erase. The device automatically
programs all memory locations in the sector(s) to be
erased prior to electrical erase. When erasing a sector
or sectors the remaining unselected sectors are not
affected. The system is not required to provide any
controls or timings during these operations. Post Erase
data state is all "1"s.

The automatic sector erase begins after the 80µs time
out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the
data on D7, Data Polling, is "1" (see Write Operatlon
Status secton) at which time the device returns to read
mode. Data Polling must be performed at an address
within any of the sectors being erased.

Figure 4 illustrates the Embedded Erase Algorithm.

Data Protection

The ACT-F128K8 is designed to offer protection against
accidental erasure or programming caused by spurious
system level singles that may exist during power
transitions. During power up the device automatically
resets the internal state machine in the read mode. Also,
with its control register architecture, alteration of the
memory content only occurs after successful completion
of specific multi-bus cycle command sequences.

The device also incorporates several features to prevent
inadvertent write cycles resulting from Vcc power-up and
power-down transitions or system noise.

LOW V

WRITE INHIBIT

To avoid initiation of a write cycle during Vcc power-up
and power-down, a write cycle is locked out for V

less

than 3.2V (typically 3.7V). If V

< V

LKO

, the command

register is disabled and all internal program/erase
circuits are disabled. Under this condition the device will
reset to read mode. Subsequent writes will be ignored
until the Vcc level is greater than V

LKO

. It is the users

responsibility to ensure that the control pins are logically
correct to prevent unintentional writes when Vcc is above
3.2V.

WRITE PULSE GLITCH PROTECTION

Noise pulses of less than 5ns (typical) on OE, CE or WE
will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding anyone of OE = V

, CE =

or WE = V

. To initiate a write cycle CE and WE

must be logical zero while OE is a logical one.

POWER-UP WRITE INHIBIT

Power-up of the device with WE = CE = V

and OE =

will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the
read mode on power-up.

Write Operation Status

DATA POLLING

The ACT-F128K8 features Data Polling as a method to
indicate to the host that the internal algorithms are in
progress or completed.

During the program algorithm, an attempt to read the
device will produce compliment data of the data last
written to D

. Upon completion of the programming

algorithm an attempt to read the device will produce the
true data last written to D7. Data Polling is valid after the
rising edge of the fourth WE pulse in the four write pulse
sequence.

During the erase algorithm, D7 will be "0" until the erase
operation is completed. Upon completion data at D7 is
"1". For chip erase, the Data Polling is valid after the
rising edge of the sixth WE pulse in the six write pulse
sequence. For sector erase, the Data Polling is Valid
after the last rising edge of the sector erase WE pulse.

The Data Polling feature is only active during the
programming algorithm, erase algorithm, or sector erase
time-out.

See Figures 6 and 10 for the Data Polling specifications.

TOGGLE BIT

The ACT-F128K8 also features the "Toggle Bit" as a
method to indicate to the host system that algorithms are
in progress or completed.

During a program or erase algorithm cycle, successive
attempts to read data from the device will result in D

toggling between one and zero. Once the program or
erase algorithm cycle is completed, D

Will stop toggling

and valid data will be read on successive attempts.
During programming the Toggle Bit is valid after the
rising edge of the fourth WE pulse in the four write pulse
sequence. For chip erase the Toggle Bit is valid after the
rising edge of the sixth

pulse in the six write pulse

sequence. For Sector erase, the Toggle Bit is valid after
the last rising edge of the sector erase

pulse. The

Toggle Bit is active during the sector time out.

See Figure 1 and 5.

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EXCEEDED TIMING LIMITS

will indicate if the program or erase time has

exceeded the specified limits. Under these conditions
D

will produce a "1". The Program or erase cycle was

not successfully completed. Data Polling is the only
operation function of the device under this condition.
The CE circuit will partially power down the device under
these conditions by approximately 8 mA per chip. The
OE and WE pins will control the output disable functions
as shown in Table 1. To reset the device, write the reset
command sequence to the device. This allows the
system to continue to use the other active sectors in the
device.

D4 - HARDWARE SEQUENCE FLAG

If the device has exceeded the specified erase or
program time and D5 is "1", then D4 Will indicate which
step in the algorithm the device exceeded the limits. A
"0" in D4 indicates in programming, a "1" indicates an
erase. (See Table 4)

SECTOR ERASE TIMER

After the completion of the initial sector erase command
sequence the sector erase time-out will begin. D

will

remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase
command sequence.

If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, D

may be

used to determine if the sector erase timer window is still
open. If D

is high ("1") the internally controlled erase

cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If D

is low ("0"), the device will accept

additional sector erase commands. To ensure the
command has been accepted, the software should check
the status of D

prior to and following each subsequent

sector erase command. If D

were high on the second

status check, the command may not have been
accepted.

Sector Protection
Algorithims

SECTOR PROTECTION

The ACT-F128K8 features hardware sector protection
which will disable both program and erase operations to
an individual sector or any group of sectors. To activate
this mode, the programming equipment must force V

on control pin OE and address pin A

. The sector

addresses should be set using higher address lines A

, and A

. The protection mechanism begins on the

falling edge of the WE pulse and is terminated with the
rising edge of the same.

It is also possible to verify if a sector is protected during
the sector protection operation. This is done by setting
CE = OE = V

and WE = V

remains high at V

Reading the device at address location XXX2H, where
the higher order addresses (A16, A15 and A14) define a
particular sector, will produce 01H at data outputs D0 -
D7, for a protected sector.

SECTOR UNPROTECT

The ACT-F128K8 also features a sector unprotect mode,
so that a protected sector may be unprotected to
incorporate any changes in the code. All sectors should
be protected prior to unprotecting any sector.

To activate this mode, the programming equipment must
force V

on control pins OE, CE, and address pin A9.

The address pins A

, A

, and A

should be set to V

and A

6 =

. The unprotection mechanism begins on

the falling edge of the WE pulse and is terminated with
the rising edge of the same.

It is also possible to determine if a sector is unprotected
in the system by writing the autoselect command.
Performing a read operation at address location XXX2H,
where the higher order addresses (A

, A

, and A

)

define a particular sector address, will produce 00H at
data outputs (D

-D

) for an unprotected sector.

Table 4 -- Hardware Sequence Flags

In Progress

Status

 D

Auto-Programming

Toggle

Reserved for

future use

Programming in Auto Erase

Toggle

Erase in Auto Erase

Toggle

Exceeding Time Limits

Auto-Programming

Toggle

Reserved for

future use

Programming in Auto Erase

Toggle

Erase in Auto Erase

Toggle

Aeroflex Circuit Technology

SCD1676 REV A 5/6/98 Plainview NY (516) 694-6700

Ordering Information

Model Number

DESC Drawing Number

Speed

Package

ACTF128K8N150F6Q

5962-9669001HTC*

150 ns

Flat Pack

ACTF128K8N120F6Q

5962-9669002HTC*

120 ns

Flat Pack

ACTF128K8N090F6Q

5962-9669003HTC*

90 ns

Flat Pack

ACTF128K8N070F6Q

5962-9669004HTC*

70 ns

Flat Pack

ACTF128K8N060F6Q

5962-9669005HTC*

60 ns

Flat Pack

ACTF128K8N150F7Q

5962-9669001HUC*

150 ns

Flat Pack (Formed)

ACTF128K8N120F7Q

5962-9669002HUC*

120 ns

Flat Pack (Formed)

ACTF128K8N090F7Q

5962-9669003HUC*

90 ns

Flat Pack (Formed)

ACTF128K8N070F7Q

5962-9669004HUC*

70 ns

Flat Pack (Formed)

ACTF128K8N060F7Q

5962-9669005HUC*

60 ns

Flat Pack (Formed)

ACTF128K8N150P4Q

5962-9669001HYC*

150 ns

DIP Pack

ACTF128K8N120P4Q

5962-9669002HYC*

120 ns

DIP Pack

ACTF128K8N090P4Q

5962-9669003HYC*

90 ns

DIP Pack

ACTF128K8N070P4Q

5962-9669004HYC*

70 ns

DIP Pack

ACTF128K8N060P4Q

5962-9669005HYC*

60 ns

DIP Pack

* Pending

C I R C U I T T E C H N O L O G Y

Part Number Breakdown

ACT F 128

8 N 090 F6 Q

Aeroflex Circuit
Technology

Memory Type

F = FLASH EEPROM

Memory Depth

Options

Memory Width, Bits

N = None

Memory Speed, ns

Package Type & Size

Surface Mount Packages

Thru-Hole Packages

F6 = .82" x .40" 32 Lead FP Unformed

P4 = 32 Pin DIP

F7 = .82" x .40" 32 Lead FP Formed

C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
M = Military Temp, -55°C to +125°C, Screening

Q = MIL-PRF-38534 Compliant / SMD

Screening

Screened to the individual test methods of MIL-STD-883

Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11830

Telephone: (516) 694-6700
FAX: (516) 694-6715

Toll Free Inquiries: 1-(800) 843-1553

Specifications subject to change without notice.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ACT-F1288N-070P4I

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ACT-F1288N-070P4I