eroflex Circuit Technology - Advanced Multichip Modules SCD1665 REV B 6/29/01
General Description
The ACTF512K32 is a high
speed, 16 megabit CMOS flash
multichip module (MCM)
designed for full temperature
range military, space, or high
reliability applications.
The MCM can be organized
as a 512K x 32bits, 1M x 16bits
or 2M x 8bits device and is input
TTL and output CMOS
compatible. The command
register is written by bringing
WE to a logic low level (V
IL
),
while CE is low and OE is at
logic high level (V
IH
)
. Reading is
accomplished by chip Enable
(CE) and Output Enable (OE)
being logically active, see
Figure 9. Access time grades of
60ns, 70ns, 90ns, 120ns and
150ns maximum are standard.
The ACTF512K32 is
packaged in a hermetically
Features
512Kx8
512Kx8
512Kx8
512Kx8
CE
4
OE
A
0
A
18
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
8
8
8
8
CE
3
WE
4
WE
3
WE
2
WE
1
CE
1
CE
2
Block Diagram PGA Type Package(P3,P7) & CQFP(F5)
Pin Description
I/O
0-31
Data I/O
A
018
Address Inputs
WE
1-4
Write Enables
CE
1-4
Chip Enables
OE
Output Enable
V
CC
Power Supply
GND
Ground
NC
Not Connected
4 Low Power 512K x 8 FLASH Die in One MCM
Package
TTL Compatible Inputs and CMOS Outputs
Access Times of 60, 70, 90, 120 and 150ns
+5V Programing, 5V 10% Supply
100,000 Erase/Program Cycles
Low Standby Current
Page Program Operation and Internal Program
Control Time
Sector Architecture (Each Die)
8 Equal size sectors of 64K bytes each
Any Combination of Sectors can be erased with
one command sequence
Supports full chip erase
Embedded Erase and Program Algorithms
MIL-PRF-38534 Compliant MCMs Available
Industry Standard Pinouts
Packaging Hermetic Ceramic
68 Lead, .88" x .88" x .160" Single-Cavity Small
Outline gull wing, Aeroflex code# "F5"
(Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)
66 Pin, 1.08" x 1.08" x .160" PGA Type, No
Shoulder, Aeroflex code# "P3"
66 Pin, 1.08" x 1.08" x .185" PGA Type, With
Shoulder, Aeroflex code# "P7"
Internal Decoupling Capacitors for Low Noise
Operation
Commercial, Industrial and Military Temperature
Ranges
DESC SMD# 596294612
Released (P3,P7,F5)
ACTF512K32 High Speed
16 Megabit FLASH Multichip Module
CIRCUIT TECHNOLOGY
www.aeroflex.com
A
A
Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
2
sealed co-fired ceramic 66 pin, 1.08"SQ PGA
or a 68 lead, .88"SQ Ceramic Gull Wing CQFP
package for operation over the temperature
range of -55C to +125C and military
environment.
Each flash memory die is organized as
512KX8 bits and is designed to be
programmed in-system with the standard
system 5.0V Vcc supply. A 12.0V V
PP
is not
required for write or erase operations. The
MCM can also be reprogrammed with standard
EPROM programmers (with the proper socket).
The standard ACTF512K32 offers access
times between 60ns and 150ns, allowing
operation of high-speed microprocessors
without wait states. To eliminate bus
contention, the device has separate chip
enable (CE) and write enable (WE). The
ACT-F512K32 is command set compatible with
JEDEC standard 4 Mbit EEPROMs.
Commands are written to the command
register using standard microprocessor write
timings. Register contents serve as input to an
internal state-machine which controls the
erase and programming circuitry. Write cycles
also internally latch addresses and data
needed for the programming and erase
operations.
Reading data out of the device is similar to
reading from 12.0V Flash or EPROM devices.
The ACT-F512K32 is programmed by
executing the program command sequence.
This will invoke the Embedded Program
Algorithm which is an internal algorithm that
automatically times the program pulse widths
and verifies proper cell margin. Typically, each
sector can be programmed and verified in less
than one second. Erase is accomplished by
executing the erase command sequence. This
will invoke the Embedded Erase Algorithm
which is an internal algorithm that
automatically preprograms the array, (if it is not
already programmed) before executing the
erase operation. During erase, the device
automatically times the erase pulse widths and
verifies proper cell margin.
Each die in the module or any individual
sector of the die is typically erased and verified
in 1.5 seconds (if already completely
preprogrammed).
Each die also features a sector erase
architecture. The sector mode allows for 64K
byte blocks of memory to be erased and
reprogrammed without affecting other blocks.
The ACT-F512K32 is erased when shipped
from the factory.
The device features single 5.0V power
supply operation for both read and write
functions. lnternally generated and regulated
voltages are provided for the program and
erase operations. A low V
CC
detector
automatically inhibits write operations on the
loss of power. The end of program or erase is
detected by Data Polling of D7 or by the Toggle
Bit feature on D6. Once the end of a program
or erase cycle has been completed, the device
internally resets to the read mode.
All bits of each die, or all bits within a
sector of a die, are erased via
Fowler-Nordhiem tunneling. Bytes are
programmed one byte at a time by hot electron
injection.
DESC Standard Military Drawing (SMD)
numbers are released.
General Description, Cont'd
,
A
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Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
3
z
Absolute Maximum Ratings
Parameter
Symbol
Range
Units
Case Operating Temperature
T
C
-55 to +125
C
Storage Temperature Range
T
STG
-65 to +150
C
Supply Voltage Range
V
CC
-2.0 to +7.0
V
Signal Voltage Range (Any Pin Except A9) Note 1
V
G
-2.0 to +7.0
V
Maximum Lead Temperature (10 seconds)
-
300
C
Data Retention
-
10
Years
Endurance (Write/Erase cycles)
-
100,000 Minimum
A9 Voltage for sector protect, Note 2
V
ID
-2.0 to +14.0
V
Note 1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot V
SS
to -2.0v for periods of up to
20ns. Maximum DC voltage on input and I/O pins is V
CC
+ 0.5V. During voltage transitions, inputs and I/O pins may overshoot to
V
CC
+ 2.0V for periods up to 20 ns.
Note 2. Minimum DC input voltage on A9 is -0.5V. During voltage transitions, A9 may undershoot V
SS
to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns.
Normal Operating Conditions
Symbol
Parameter
Minimum
Maximum
Units
V
CC
Power Supply Voltage
+4.5
+5.5
V
V
IH
Input High Voltage
+2.0
V
CC
+ 0.5
V
V
IL
Input Low Voltage
-0.5
+0.8
V
T
A
Operating Temperature (Military)
-55
+125
C
V
ID
A9 Voltage for sector protect
11.5
12.5
V
Capacitance
(V
IN
= 0V, f = 1MHz, Tc = 25C)
Symbol
Parameter
Maximum
Units
C
AD
A
0
A
16
Capacitance
50
pF
C
OE
OE Capacitance
50
pF
C
WE
Write Enable Capacitance
CQFP(F5) Package
20
pF
PGA(P3,P7) Package
20
pF
C
CE
Chip Enable Capacitance
20
pF
C
I
/
O
I/O0 I/O31 Capacitance
20
pF
Parameters Guaranteed but not tested
DC Characteristics CMOS Compatible
(Vcc = 5.0V, Vss = 0V, T
C
= -55C to +125C, unless otherwise indicated)
Parameter
Sym
Conditions
Speeds 60, 70, 90, 120 & 150ns
Minimum
Maximum
Units
Input Leakage Current
I
LI
V
CC
= 5.5V, Vi
N
= GND to V
CC
10
A
Output Leakage Current
I
LOX
32 V
CC
= 5.5V, Vi
N
= GND to V
CC
10
A
Active Operating Supply Current for Read (1)
I
CC
1
CE = V
IL
,
OE = V
IH
, f = 5MHz
190
mA
Active Operating Supply Current for Program or Erase (2)
I
CC
2
CE = V
IL
,
OE = V
IH
240
mA
Standby Supply Current
I
CC
4
V
CC
= 5.5V, CE = V
IH
, f = 5MHz
6.5
mA
Static Supply Current (4)
I
CC
3
V
CC
= 5.5V, CE = V
IH
0.6
mA
Output Low Voltage
V
OL
I
OL
= +8.0 mA, V
CC
= 4.5V
0.45
V
Output High Voltage
V
OH
I
OH
= 2.5 mA, V
CC
= 4.5V
0.85 x V
CC
V
Low Power Supply Lock-Out Voltage (4)
V
LKO
3.2
4.2
V
Note 1. The Icc current listed includes both the DC operating current and the frequency dependent component (At 5 MHz). The frequency
component typically is less than 2 mA/MHz, with OE at V
IN
.
Note 2. Icc active while Embedded Algorithm (Program or Erase) is in progress.
Note 3. DC Test conditions: V
IL
= 0.3V, V
IH
= V
CC
- 0.3V, unless otherwise indicated
Note 4. Parameter Guaranteed but not tested.
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Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
4
AC Characteristics Read Only Operations
(Vcc = 5.0V, Vss = 0V, T
C
= -55C to +125C)
Parameter
Symbol
JEDEC Stand'd
60
Min Max
70
Min Max
90
Min Max
120
Min Max
150
Min Max
Units
Read Cycle Time
t
AVAV
t
RC
60
70
90
120
150
ns
Address Access Time
t
AVQV
t
ACC
60
70
90
120
150
ns
Chip Enable Access Time
t
ELQV
t
CE
60
70
90
120
150
ns
Output Enable to Output Valid
t
GLQV
t
OE
30
35
35
50
55
ns
Chip Enable to Output High Z (1)
t
EHQZ
t
DF
20
20
20
30
35
ns
Output Enable High to Output High Z (1)
t
GHQZ
t
DF
20
20
20
30
35
ns
Output Hold from Address, CE or OE Change, Whichever is First
t
AXQX
t
OH
0
0
0
0
0
ns
Note 1. Guaranteed by design, but not tested.
AC Characteristics Write/Erase/Program Operations, WE Controlled
(Vcc = 5.0V, Vss = 0V, T
C
= -55C to +125C)
Parameter
Symbol
JEDEC Stand'd
60
Min Max
70
Min Max
90
Min Max
120
Min Max
150
Min Max
Units
Write Cycle Time
t
AVAC
t
WC
60
70
90
120
150
ns
Chip Enable Setup Time
t
ELWL
t
CE
0
0
0
0
0
ns
Write Enable Pulse Width
t
WLWH
t
WP
40
45
45
50
50
ns
Address Setup Time
t
AVWL
t
AS
0
0
0
0
0
ns
Data Setup Time
t
DVWH
t
DS
40
45
45
50
50
ns
Data Hold Time
t
WHDX
t
DH
0
0
0
0
0
ns
Address Hold Time
t
WLAX
t
AH
45
45
45
50
50
ns
Write Enable Pulse Width High
t
WHWL
t
WPH
20
20
20
20
20
ns
Duration of Byte Programming
t
WHWH
1
14
TYP
14
TYP
14
TYP
14
TYP
14
TYP
s
Sector Erase Time
t
WHWH
2
30
30
30
30
30
Sec
Chip Erase Time
t
WHWH
3
120
120
120
120
120
Sec
Read Recovery Time before Write (2)
t
GHWL
0
0
0
0
0
s
Vcc Setup Time (2)
t
VCE
50
50
50
50
50
s
Chip Programming Time
50
50
50
50
50
Sec
Output Enable Setup Time (2)
t
OES
0
0
0
0
0
ns
Output Enable Hold Time (1) (2)
t
OEH
10
10
10
10
10
ns
Notes: 1. For Toggle and Data Polling. 2. Guaranteed by design, but not tested.
AC Characteristics Write/Erase/Program Operations, CE Controlled
(Vcc = 5.0V, Vss = 0V, T
C
= -55C to +125C)
Parameter
Symbol
JEDEC Stand'd
60
Min Max
70
Min Max
90
Min Max
120
Min Max
150
Min Max
Units
Write Cycle Time
t
AVAC
t
WC
60
70
90
120
150
ns
Write Enable Setup Time
t
WLE
L
t
WS
0
0
0
0
0
ns
Chip Enable Pulse Width
t
ELEH
t
CP
40
45
45
50
50
ns
Address Setup Time
t
AVEL
t
AS
0
0
0
0
0
ns
Data Setup Time
t
DVEH
t
DS
40
45
45
50
50
ns
Data Hold Time
t
EHDX
t
DH
0
0
0
0
0
ns
Address Hold Time
t
ELAX
t
AH
45
45
45
50
50
ns
Chip Enable Pulse Width High
t
EHEL
t
CPH
20
20
20
20
20
ns
Duration of Byte Programming Operation
t
WHWH
1
14
TYP
14
TYP
14
TYP
14
TYP
14
TYP
s
Sector Erase Time
t
WHWH
2
30
30
30
30
30
Sec
Chip Erase Time
t
WHWH
3
120
120
120
120
120
Sec
Read Recovery Time Before Write (1)
t
GHEL
0
0
0
0
0
s
Chip Programming Time
50
50
50
50
50
Sec
1. Guaranteed by design, but not tested.
A
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Aeroflex Circuit Technology
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
5
Device Operation
The ACT-F512K32 MCM is composed of four, four
megabit Flash chips. The following description is for the
individual flash device, is applicable to each of the four
memory chips inside the MCM. Chip 1 is distinguished by
CE
1
and I/O
1-7
, Chip 2 by CE
2
and I/0
8-15
, Chip 3 by CE
3
and I/0
16-23
, and Chip 4 by CE
4
and I/0
24-31
.
Programming of the ACT-F512K32 is accomplished by
executing the program command sequence. The
program algorithm, which is an internal algorithm,
automatically times the program pulse widths and verifies
proper cell status. Sectors can be programed and
verified in less than one second. Erase is accomplished
by executing the erase command sequence. The erase
algorithm, which is internal, automatically preprograms
the array if it is not already programed before executing
the erase operation. During erase, the device
automatically times the erase pulse widths and verifies
proper cell status. The entire memory is typically erased
and verified in 1.5 seconds (if pre-programmed). The
sector mode allows for 64K byte blocks of memory to be
erased and reprogrammed without affecting other blocks.
Bus Operation
READ
The ACT-F512K32 has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output-Enable (OE)
is the output control and should be used to gate data to
the output pins of the chip selected. Figure 7 illustrates
AC read timing waveforms.
OUTPUT DISABLE
With Output-Enable at a logic high level (V
IH
), output from
the device is disabled. Output pins are placed in a high
impedance state.
STANDBY MODE
The ACT-F512K32 standby mode consumes less than
6.5 mA. In the standby mode the outputs are in a high
impedance state, independent of the OE input.
If the device is deselected during erasure or
programming, the device will draw active current until the
operation is completed.
WRITE
Device erasure and programming are accomplished via
the command register. The contents of the register serve
as input to the internal state machine. The state machine
outputs dictate the function of the device.
The command register itself does not occupy an
addressable memory location. The register is a latch
used to store the command, along with address and data
information needed to execute the command. The
command register is written by bringing WE to a logic low
level (V
IL
), while CE is low and OE is at V
IH
. Addresses
are latched on the falling edge of WE or CE, whichever
happens later. Data is latched on the rising edge of the
WE or CE whichever occurs first. Standard
microprocessor write timings are used. Refer to AC
Program Characteristics and Waveforms, Figures 3,
8 and 13.
Command Definitions
Device operations are selected by writing specific
address and data sequences into the command register.
Table 3 defines these register command sequences.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command
register. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for reads
until the command register contents are altered.
The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will
retrieve array data. The device will automatically
power-up in the read/reset state. In this case, a
command sequence is not required to read data.
Standard Microprocessor read cycles will retrieve array
data. This default value ensures that no spurious
alteration of the memory content occurs during the power
transition. Refer to the AC Read Characteristics and
Figure 7 for the specific timing parameters.
Table 1 Bus Operations
Operation
CE OE WE A0 A1 A6 A9
I/O
READ
L
L
H
A
0
A
1
A
6
A
9
DOUT
STANDBY
H
X
X
X
X
X
X
HIGH Z
OUTPUT DISABLE
L
H
H
X
X
X
X
HIGH Z
WRITE
L
H
L
A
0
A
1
A
6
A
9
D
IN
ENABLE SECTOR
PROTECT
L
V
ID
L
X
X
X
V
ID
X
VERIFY SECTOR
PROTECT
L
L
H
L
H
L
V
ID
Code
Table 2 Sector Addresses Table
A18 A17
A16
Address Range
SA0
0
0
0
00000h 0FFFFh
SA1
0
0
1
10000h 1FFFFh
SA2
0
1
0
20000h 2FFFFh
SA3
0
1
1
30000h 3FFFFh
SA4
1
0
0
40000h 4FFFFh
SA5
1
0
1
50000h 5FFFFh
SA6
1
1
0
60000h 6FFFFh
SA7
1
1
1
70000h 7FFFFh
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