Data Sheet
April 2001
Quad Differential Receivers
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Features
s
Pin equivalent to the general-trade 26LS32 device,
with improved speed, reduced power consumption,
and significantly lower levels of EMI
s
High input impedance approximately 8 k
s
Four line receivers per package
s
400 Mbits/s maximum data rate when used with
Agere Systems Inc. data transmission drivers
s
Meets enhanced small device interface (ESDI)
standards
s
4.0 ns maximum propagation delay
s
<0.20 V input sensitivity
s
-
1.2 V to
+
7.2 V common-mode range
s
-
40
C to
+
125
C ambient operating temperature
range (wider than the 41 Series)
s
Single 5.0 V
10% supply
s
Output defaults to logic 1 when inputs are left
open*
s
Available in four package types
s
Lower power requirement than the 41 Series
Description
These quad differential receivers accept digital data
over balanced transmission lines. They translate
differential input logic levels to TTL output logic
levels. All devices in this family have four receivers
with a common enable control. These receivers are
pin equivalent to the general-trade 26LS32, but offer
increased speed and decreased power consumption.
They replace the Agere 41 Series receivers.
* This feature is available on BRF1A and BRF2A.
The BRF1A device is the generic receiver in this
family and requires the user to supply external
resistors on the circuit board for impedance
matching.
The BRF2A is identical to the BRF1A, but has an
electrostatic discharge (ESD) protection circuit
added to significantly improve the ESD human-body
model (HBM) characteristics on the differential input
terminals.
The BRS2B is identical to the BRF2A, but has a
preferred state feature that places the output in the
high state when the inputs are open, shorted to
ground, or shorted to the power supply.
The BRR1A is equivalent to the BRF1A, but has a
110
resistor connected across the differential
inputs. This eliminates the need for an external
resistor when terminating a 100
impedance line.
This device is designed to work with the DP1A or
PNPA in point-to-point applications.
The BRT1A is equivalent to the BRF1A; however, it
is provided with a Y-type resistor network across the
differential inputs and terminated to ground. The
Y-type termination provides the best EMI results.
This device is not recommended for applications
where the differences in ground voltage between the
driver and the receiver exceed 1 V. This device is
designed to work with the DG1A or PNGA in point-to-
point applications.
The powerdown loading characteristics of the
receiver input circuit are approximately 8 k
relative
to the power supplies; hence, they will not load the
transmission line when the circuit is powered down.
For those circuits with termination resistors, the line
will remain impedance matched when the circuit is
powered down.
The packaging options that are available for these
quad differential line drivers include a 16-pin DIP; a
16-pin, J-lead SOJ; a 16-pin, gull-wing small-outline
integrated circuit (SOIC); and a 16-pin, narrow-body,
gull-wing SOIC.
2
Agere Systems Inc.
Data Sheet
April 2001
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Quad Differential Receivers
Pin Information
12-2281.a(F)
Figure 1. Quad Differential Receiver Logic Diagrams
Table 1. Enable Truth Table
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.
Electrical Characteristics
For electrical characteristics over the temperature range, see Figure 7 through Figure 10.
Table 2. Power Supply Current Characteristics
See Figure 7 for variation in I
CC
over the temperature range. T
A
= 40 C to +125 C, V
CC
= 5 V
0.5 V.
E1
E2
Condition
0
0
Active
1
0
Active
0
1
Disabled
1
1
Active
Parameter
Symbol
Min
Max
Unit
Power Supply Voltage
V
CC
--
6.5
V
Ambient Operating Temperature
T
A
-
40
125
C
Storage Temperature
T
stg
-
40
150
C
Parameter
Symbol
Min
Typ
Max
Unit
Power Supply Current (V
CC
= 5.5 V):
All Outputs Disabled
All Outputs Enabled
I
CC
I
CC
30
20
45
32
mA
mA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
E1
16
15
14
13
12
11
10
9
AI
AI
AO
BO
BI
BI
GND
DO
V
CC
DI
DI
E2
CO
CI
CI
E1
AI
AI
AO
BO
BI
BI
GND
DO
V
CC
DI
DI
E2
CO
CI
CI
A
D
B
C
A
D
B
C
BRR1A
BRT1A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
E1
AI
AI
AO
BO
BI
BI
GND
DO
V
CC
DI
DI
E2
CO
CI
CI
A
D
B
C
BRF1A
BRF2A
BRS2B
Agere Systems Inc.
3
Data Sheet
April 2001
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Quad Differential Receivers
Electrical Characteristics
(continued)
Table 3. Voltage and Current Characteristics
For variation in minimum V
OH
and maximum V
OL
over the temperature range, see Figure 8. T
A
= 40 C to +125 C.
12-2819.a(F)
Figure 2. BRT1A Terminating Resistor Configuration
Parameter
Sym
Min
Typ
Max
Unit
Output Voltages, V
CC
= 4.5 V:
Low, I
OL
= 8.0 mA
V
OL
--
--
0.5
V
High, I
OH
=
-
400 A
V
OH
2.4
--
--
V
Enable Input Voltages:
Low, V
CC
= 5.5 V
V
IL
1
1. The input levels and difference voltage provide zero noise immunity and should be tested only in a static, noise-free environment.
--
--
0.7
V
High, V
CC
= 5.5 V
V
IH
1
2.0
--
--
V
Clamp, V
CC
= 4.5 V, I
I
= 5.0 mA
V
IK
--
--
1.0
V
Differential Input Voltages, V
IH
V
IL
:
2
2. Outputs of unused receivers assume a logic 1 level when the inputs are left open. (It is recommended that all unused positive inputs
be tied to the positive power supply. No external series resistor is required.)
-
0.80 V < V
IH
< 7.2 V,
-
1.2 V < V
IL
< 6.8 V
V
TH
1
--
0.1
0.20
V
Input Offset Voltage
V
OFF
0.02
0.05
V
Input Offset Voltage BRS2B
V
OFF
0.1
0.15
V
Output Currents, V
CC
= 5.5 V:
Off-state (high Z), V
O
= 0.4 V
I
OZL
--
--
20
A
Off-state (high Z), V
O
= 2.4 V
I
OZH
--
--
20
A
Short Circuit
I
OS
3
3. Test must be performed one lead at a time to prevent damage to the device.
25
--
100
mA
Enable Currents, V
CC
= 5.5 V:
Low, V
IN
= 0.4 V
I
IL
--
--
400
A
High, V
IN
= 2.7 V
I
IH
--
--
20
A
Reverse, V
IN
= 5.5 V
I
IH
--
--
100
A
Differential Input Currents, V
CC
= 5.5 V:
Low, V
IN
= 1.2 V
I
IL
--
--
-
1.0
mA
High, V
IN
= 7.2 V
I
IH
--
--
1.0
mA
Differential Input Impedance (BRR1A):
Connected Between RI and RI
R
O
--
110
--
Differential Input Impedance (BRT1A)
4
4. See Figure 2.
R
1
--
60
--
R
2
--
90
--
RI
R1
R1
R2
RI
4
Agere Systems Inc.
Data Sheet
April 2001
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Quad Differential Receivers
Timing Characteristics
Table 4. Timing Characteristics (See Figure 4 and Figure 5.)
For propagation delays (t
PLH
and t
PHL
) over the temperature range, see Figure 9 and Figure 10.
Propagation delay test circuit connected to output is shown in Figure 6.
T
A
= 40 C to +125 C, V
CC
= 5 V
0.5 V.
12-3462(F)
Note: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the
delay due to the external capacitance and the intrinsic delay of the device.
Figure 3. Typical Extrinsic Propagation Delay vs. Load Capacitance at 25 C
Parameter
Symbol
Min
Typ
Max
Unit
Propagation Delay:
Input to Output High
t
PLH
1.5
2.5
4.0
ns
Input to Output Low
t
PHL
1.5
2.5
4.0
ns
Disable Time, C
L
= 5 pF:
High-to-high Impedance
t
PHZ
--
5
12
ns
Low-to-high Impedance
t
PLZ
--
5
12
ns
Pulse Width Distortion, ltpHL
-
tpLHI:
Load Capacitance (C
L
) = 15 pF
tskew1
--
--
0.7
ns
Load Capacitance (C
L
) = 150 pF
tskew1
--
--
4.0
ns
Output Waveform Skews:
Part-to-Part Skew, T
A
= 75 C
tskew1p-p
--
0.8
1.4
ns
Part-to-Part Skew, T
A
= 40 C to +125 C
tskew1p-p
--
--
1.5
ns
Same Part Skew
tskew
--
--
0.3
ns
Enable Time:
High Impedance to High
t
PZH
--
8
12
ns
High Impedance to Low
t
PZL
--
8
12
ns
Rise Time (20%--80%)
t
tLH
--
--
3.0
ns
Fall Time (80%--20%)
t
tHL
--
--
3.0
ns
25
50
75
100
125
150
0
LOAD CAPACITANCE, C
L
(pF)
2
1
3
7
175
200
0
4
5
6
E
X
TRINSIC
P
R
OPA
G
ATI
O
N DELA
Y,
t
P
(ns)
t
PHL
(TYP)
t
PLH
(TYP)
Agere Systems Inc.
5
Data Sheet
April 2001
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Quad Differential Receivers
Timing Characteristics
(continued)
12-2251.b(F)
Figure 4. Receiver Propagation Delay Timing
12-253.b(F)
* E2 = 1 while E1 changes state.
E1 = 0 while E2 changes state.
Figure 5. Receiver Enable and Disable Timing
Test Conditions
Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data
transmission driver devices are measured with the following output load circuits.
12-2249(F)
* Includes probe and jig capacitances.
Note: All 458E, IN4148, or equivalent diodes.
Figure 6. Receiver Propagation Delay Test Circuit
INPUT
OUTPUT
INPUT
80%
20%
3.7 V
3.2 V
2.7 V
V
OH
1.5 V
V
OL
80%
20%
t
PHL
t
tHL
t
PLH
t
tLH
V = 0.5 V
V = 0.5 V
V = 0.5 V
V = 0.5 V
E1*
OUTPUT
t
PHZ
t
PZH
3 V
1.5 V
0 V
E2
3 V
1.5 V
0 V
V
OH
V
OL
t
PZL
t
PLZ
TO OUTPUT OF
DEVICE UNDER
TEST
C
L
15 pF*
5 k
2 k
5 V
6
6
Agere Systems Inc.
Data Sheet
April 2001
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Quad Differential Receivers
Temperature Characteristics
12-3463.a(F)
Figure 7. Typical and Maximum I
CC
vs. Temperature
12-3464.a(F)
Figure 8. Minimum V
OH
and Maximum V
OL
vs.
Temperature at V
CC
= 4.5 V
12-3465(F)
Figure 9. Propagation Delay for a High Output (t
PLH
)
vs. Temperature at V
CC
= 5.0 V
12-3466(F)
Figure 10. Propagation Delay for a Low Output
(t
PHL
) vs. Temperature at V
CC
= 5.0 V
25
0
25
50
75
100
18
26
TEMPERATURE (
C)
22
20
24
32
125
150
28
I
CC
(m
A)
50
30
I
CC
MAX
V
CC
= 5.5
I
CC
TYP
V
CC
= 5.0
25
0
25
50
75
100
0.0
1.6
TEMPERATURE (
C)
0.8
0.4
1.2
2.8
125
150
2.0
VO
LT
AG
E (V
)
50
2.4
I
OH
MIN
I
OL
MAX
3.2
3.6
3.8
25
0
25
50
75
100
1.00
3.00
TEMPERATURE (
C)
2.00
1.50
2.50
4.00
125
150
3.50
MAX
TYP
MIN
PR
O
PA
G
AT
I
O
N DE
LAY
(
ns
)
50
25
0
25
50
75
1.00
1.50
2.00
4.00
125
150
50
2.50
3.00
3.50
MAX
TYP
MIN
PR
O
P
A
G
AT
ION
D
E
L
A
Y (n
s
)
TEMPERATURE (
C)
100
Handling Precautions
CAUTION: This device is susceptible to damage as a result of ESD. Take proper precautions during both
handling and testing. Follow guidelines such as JEDEC Publication No. 108-A (Dec. 1988).
When handling and mounting line driver products, proper precautions should be taken to avoid exposure to ESD.
The user should adhere to the following basic rules for ESD control:
1. Assume that all electronic components are sensitive to ESD damage.
2. Never touch a sensitive component unless properly grounded.
3. Never transport, store, or handle sensitive components except in a static-safe environment.
Agere Systems Inc.
7
Data Sheet
April 2001
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Quad Differential Receivers
ESD Failure Models
Agere employs two models for ESD events that can
cause device damage or failure:
1. An HBM that is used by most of the industry for
ESD-susceptibility testing and protection-design
evaluation. ESD voltage thresholds are dependent
on the critical parameters used to define the model.
A standard HBM (resistance = 1500
,
capacitance = 100 pF) is widely used and, therefore,
can be used for comparison purposes.
2. A charged-device model (CDM), which many
believe is the better simulator of electronics
manufacturing exposure.
Table 5 and Table 6 illustrates the role these two
models play in the overall prevention of ESD damage.
HBM ESD testing is intended to simulate an ESD event
from a charged person. The CDM ESD testing
simulates charging and discharging events that occur in
production equipment and processes, e.g., an
integrated circuit sliding down a shipping tube.
The HBM ESD threshold voltage presented here was
obtained by using the following circuit parameters:
Table 5. Typical ESD Thresholds for Data
Transmission Receivers
Table 6. ESD Damage Protection
Device
HBM Threshold
CDM
Threshold
Differential
Inputs
Others
BRF1A, BRR1A,
BRT1A
>
800
>
2000
>
1000
BRF2A, BRS2B
>
2000
>
2000
>
2000
ESD Threat Controls
Personnel
Processes
Control
Wrist straps.
ESD shoes.
Antistatic flooring.
Static-dissipative
materials.
Air ionization.
Model
Human body
model (HBM).
Charged-device
model (CDM).
Latch Up
Latch-up evaluation has been performed on the data transmission receivers. Latch-up testing determines if power-
supply current exceeds the specified maximum due to the application of a stress to the device under test. A device
is considered susceptible to latch up if the power supply current exceeds the maximum level and remains at that
level after the stress is removed.
Agere performs latch up testing per an internal test method that is consistent with JEDEC Standard No. 17
(previously JC-40.2)
CMOS Latch Up Standardized Test Procedure
.
Latch up evaluation involves three separate stresses to evaluate latch up susceptibility levels:
1. dc current stressing of input and output pins.
2. Power supply slew rate.
3. Power supply overvoltage.
Table 7. Latch Up Test Criteria and Test Results
Based on the results in Table 7, the data transmission receivers pass the Agere latch-up esting requirements and
are considered not susceptible to latch up.
dc Current Stress
of I/O Pins
Power Supply
Slew Rate
Power Supply
Overvoltage
Data Transmission
Receiver ICs
Minimum Criteria
150 mA
1
s
1.75 x Vmax
Test Results
250 mA
100 ns
2.25 x Vmax
8
8
Agere Systems Inc.
Data Sheet
April 2001
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Quad Differential Receivers
Power Dissipation
System designers incorporating Agere data
transmission drivers in their applications should be
aware of package and thermal information associated
with these components.
Proper thermal management is essential to the long-
term reliability of any plastic encapsulated integrated
circuit. Thermal management is especially important
for surface-mount devices, given the increasing circuit
pack density and resulting higher thermal density. A
key aspect of thermal management involves the
junction temperature (silicon temperature) of the
integrated circuit.
Several factors contribute to the resulting junction
temperature of an integrated circuit:
s
Ambient use temperature
s
Device power dissipation
s
Component placement on the board
s
Thermal properties of the board
s
Thermal impedance of the package
Thermal impedance of the package is referred to as
ja
and is measured in C rise in junction temperature
per watt of power dissipation. Thermal impedance is
also a function of airflow present in system application.
The following equation can be used to estimate the
junction temperature of any device:
T
j
= T
A
+
P
D
ja
where:
T
j
is device junction temperature (C).
T
A
is ambient temperature (C).
P
D
is power dissipation (W).
ja
is package thermal impedance (junction to
ambient
--
C/W).
The power dissipation estimate is derived from two
factors:
s
Internal device power
s
Power associated with output terminations
Multiplying I
CC
times V
CC
provides an estimate of
internal power dissipation.
The power dissipated in the output is a function of the:
s
Termination scheme on the outputs
s
Termination resistors
s
Duty cycle of the output
Package thermal impedance depends on:
s
Airflow
s
Package type (e.g., DIP, SOIC, SOIC/NB)
The junction temperature can be calculated using the
previous equation, after power dissipation levels and
package thermal impedances are known.
Figure 11 illustrates the thermal impedance estimates
for the various package types as a function of airflow.
This figure shows that package thermal impedance is
higher for the narrow-body SOIC package. Particular
attention should, therefore, be paid to the thermal
management issues when using this package type.
In general, system designers should attempt to
maintain junction temperature below 125 C. The
following factors should be used to determine if specific
data transmission drivers in particular package types
meet the system reliability objectives:
s
System ambient temperature
s
Power dissipation
s
Package type
s
Airflow
12-2753(F)
Figure 11. Power Dissipation
DIP
SOIC/NB
J-LEAD SOIC/GULL WING
AIRFLOW (ft./min.)
200
400
600
800
1000
1200
0
40
50
60
70
80
90
100
110
120
130
140
THE
R
MAL RESI
ST
ANCE
ja
(
C/
W
)
Agere Systems Inc.
9
Data Sheet
April 2001
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Quad Differential Receivers
Outline Diagrams
16-Pin DIP
Dimensions are in millimeters.
5-4410(F)
Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts,
please contact your Agere Systems sales representative.
Package
Description
Number of
Pins
(N)
Package Dimensions
Maximum Length
(L)
Maximum Width
Without Leads
(B)
Maximum Width
Including Leads
(W)
Maximum Height
Above Board
(H)
Plastic Dual
In-Line Package
(PDIP3)
16
20.57
6.48
7.87
5.08
W
H
0.58 MAX
2.54 TYP
0.38 MIN
SEATING PLANE
N
1
PIN #1 IDENTIFIER ZONE
L
B
10
Agere Systems Inc.
Data Sheet
April 2001
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Quad Differential Receivers
Outline Diagrams
(continued)
16-Pin SOIC (SONB/SOG)
Dimensions are in millimeters.
5-4414(F)
Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts,
please contact your Agere Systems sales representative.
Package
Description
Number of
Pins
(N)
Package Dimensions
Maximum Length
(L)
Maximum Width
Without Leads
(B)
Maximum Width
Including Leads
(W)
Maximum Height
Above Board
(H)
Small-Outline,
Narrow Body
(SONB)
16
10.11
4.01
6.17
1.73
Small-Outline,
Gull-Wing
(SOG)
16
10.49
7.62
10.64
2.67
W
0.61
0.51 MAX
H
0.28 MAX
0.10
SEATING PLANE
1.27 TYP
N
L
B
1
PIN #1 IDENTIFIER ZONE
Agere Systems Inc.
11
Data Sheet
April 2001
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Quad Differential Receivers
Outline Diagrams
(continued)
16-Pin SOIC (SOJ)
Dimensions are in millimeters.
5-4413(F)
Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts,
please contact your Agere Systems sales representative.
Package
Description
Number of
Pins
(N)
Package Dimensions
Maximum Length
(L)
Maximum Width
Without Leads
(B)
Maximum Width
Including Leads
(W)
Maximum Height
Above Board
(H)
Small-Outline,
J-Lead (SOJ)
16
10.41
7.62
8.81
3.18
N
1
PIN #1 IDENTIFIER ZONE
0.51 MAX
0.79 MAX
0.10
SEATING PLANE
1.27 TYP
H
W
B
L
Data Sheet
April 2001
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Quad Differential Receivers
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright 2001 Agere Systems Inc.
All Rights Reserved
Printed in U.S.A.
April 2001
DS01-069ANET-1 (Replaces DS01-069ANET)
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
http://www.agere.com
E-MAIL:
docmaster@micro.lucent.com
N. AMERICA:
Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
CHINA:
Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC
Tel. (86) 21 50471212, FAX (86) 21 50472266
JAPAN:
Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
EUROPE:
Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Technical Inquiries:GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),
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Ordering Information
Part Number
Package Type
Comcode
Former Pkg. Type
Former Part Number
BRF1A16E
16-pin, Plastic SOJ
107949927
1041
LF, MF, LS
BRF1A16E-TR
Tape & Reel SOJ
107949935
1041
LF, MF, LS
BRF1A16G
16-pin, Plastic SOIC
107950297
1141
LF, MF, LS
BRF1A16G-TR
Tape & Reel SOIC
107950305
1141
LF, MF, LS
BRF1A16NB
16-pin, Plastic SOIC/NB
107949968
1241
LF, MF, LS
BRF1A16NB-TR
Tape & Reel SOIC/NB
107949976
1241
LF, MF, LS
BRF1A16P
16-pin, Plastic DIP
107949984
41
LF, MF, LS
BRF2A16E
16-pin, Plastic SOJ
107949992
1041
LF2, MF2
BRF2A16E-TR
Tape & Reel SOJ
107950008
1041
LF2, MF2
BRF2A16G
16-pin, Plastic SOIC
107950016
1141
LF2, MF2
BRF2A16G-TR
Tape & Reel SOIC
107950024
1141
LF2, MF2
BRF2A16NB
16-pin, Plastic SOIC/NB
107950032
1241
LF2, MF2
BRF2A16NB-TR
Tape & Reel SOIC/NB
107950040
1241
LF2, MF2
BRF2A16P
16-pin, Plastic DIP
107950057
41
LF2, MF2
BRR1A16E
16-pin, Plastic SOJ
107950065
1041
LR, MR
BRR1A16E-TR
Tape & Reel SOJ
107950073
1041
LR, MR
BRR1A16G
16-pin, Plastic SOIC
107950081
1141
LR, MR
BRR1A16G-TR
Tape & Reel SOIC
107950099
1141
LR, MR
BRR1A16NB
16-pin, Plastic SOIC/NB
107950107
1241
LR, MR
BRR1A16NB-TR
Tape & Reel SOIC/NB
107950115
1241
LR, MR
BRR1A16P
16-pin, Plastic DIP
107950123
41
LR, MR
BRS2B16E
16-pin, Plastic SOJ
108888470
1041
MF, MF2, LS
BRS2B16E-TR
Tape & Reel SOJ
108888488
1041
MF, MF2, LS
BRS2B16G
16-pin, Plastic SOIC
108699133
1141
MF, MF2, LS
BRS2B16G-TR
Tape & Reel SOIC
108699125
1141
MF, MF2, LS
BRS2B16P
16-pin, Plastic DIP
108888447
41
MF, MF2, LS
BRS2B16NB
16-pin, Plastic SOIC/NB
108888454
1241
MF, MF2, LS
BRS2B16NB-TR
Tape & Reel SOIC/NB
108888462
1241
MF, MF2, LS
BRT1A16E
16-pin, Plastic SOJ
107950131
1041
LT, MT
BRT1A16E-TR
Tape & Reel SOJ
107950149
1041
LT, MT
BRT1A16G
16-pin, Plastic SOIC
107950156
1141
LT, MT
BRT1A16G-TR
Tape & Reel SOIC
107950164
1141
LT, MT
BRT1A16NB
16-pin, Plastic SOIC/NB
107950313
1241
LT, MT
BRT1A16NB-TR
Tape & Reel SOIC/NB
107950321
1241
LT, MT
BRT1A16P
16-pin, Plastic DIP
107950339
41
LT, MT
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