Data Sheet

March 2001

Dual Differential Transceiver BTF1A
With Idle Bus Indicator

Features

Driver Features

Produces a logic zero in third state

400 mV difference voltage in third state

Two line drivers per package

Logic to convert TTL input logic levels to differen-
tial, pseudo-emmiter coupled logic (ECL) output
logic levels

No line loading when V

= 0 V

High output driver for 50

loads

200 mA short-circuit current (typical)

2.0 ns maximum propagation delay

<0.2 ns output skew (typical)

Receiver Features

Two line receivers per package

High input impedance

8 k

Logic that converts differential input logic levels to
TTL output logic levels

4.0 ns maximum propagation delay

<0.20 V input sensitivity (typical)

1.2 V to

7.2 V common-mode range

Common Device Features

Common enable for each driver/receiver pair

Operating temperature range: 40

C to +125

(wider than the 41 Series)

Single 5.0 V

5% supply

400 Mbits/s maximum data rate

Meets enhanced small device interface (ESDI)
standards

Electrostatic discharge (ESD) performance better
than the 41 Series

Lower power requirement than the 41 Series

Description

The BTF1A device is a dual differential transceiver
circuit that transmits and receives digital data over
balanced transmission lines and is compatible with
Lucent Technologies Microelectronics Group differ-
ential drivers and receivers. It is designed to provide
a strong logic zero when in the third state. The mini-
mum difference voltage in the third state is 400 mV. It
is designed specifically for bus applications where a
well-defined logic state is needed when the bus is
idle. The driver puts out a logic zero when in the third
state mode, which is easily overriden by an active
buffer on the bus. When all the buffers on the bus are
inactive (third state), the signal on the bus is a zero
indicating that the bus is idle.

The dual drivers translate input TTL logic levels to dif-
ferential pseudo-ECL output levels. The dual receiver
converts differential input logic levels to TTL output
levels. Each driver/receiver pair has its own common
enable control allowing serial data and a control clock
to be transmitted and received on a single integrated
circuit. The BTF1A transceiver requires the customer
to supply termination resistors on the circuit board.

The powerdown loading characteristics of the
receiver input circuit are approximately 8 k

relative

to the power supplies; hence, it will not load the
transmission line when the circuit is powered down.
For those circuits with termination resistors, the line
will remain impedance matched when the circuit is
powered down. The driver does not load the line
when it is powered down.

Agere Systems Inc.

Data Sheet

March 2001

With Idle Bus Indicator

Dual Differential Transceiver BTF1A

Pin Information

12-2747.a(F)

Figure 1. Differential Transceiver Logic Diagram

Table 1. Enable Truth Table

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.

Table 2. Absolute Maximum Ratings

Active

Disabled

Active

Disabled

Parameter

Symbol

Min

Max

Unit

Power Supply Voltage

6.5

Ambient Operating Temperature

125

°C

Storage Temperature

stg

150

°C

RO1

DI1

GND

DI2

RO2

DO1

RI1

DO1

DO2

RI2

BTF1A

Agere Systems Inc.

Data Sheet
March 2001

With Idle Bus Indicator

Dual Differential Transceiver BTF1A

Electrical Characteristics

For variations in electrical characteristics over the temperature range, see Figure 10 through Figure 12.

Table 3. Power Supply Current Characteristics

40 °C to +125 °C, V

= 5 V

0.25 V.

Third State

The BTF1A driver produces pseudo-ECL levels, and has a third-state mode, which is different than a conventional
TTL device. When a driver is placed in the third state, the base of the output transistors are pulled low, bringing the
outputs below the active-low level. The BTF1A is unique because it provides a logic zero at its output when in the
third state. If all the buffers on the bus are in the third state, the BTF1A is designed to deliver a logic zero to the bus
to act as an indicator that the bus is idle. The guaranteed zero level, Vdo Vdo, is 0.4 V.

Parameter

Symbol

Min

Typ

Max

Unit

Power Supply Current (V

= 5.5 V)

All Outputs Disabled
All Outputs Enabled

--
--

40
20

65
35

mA
mA

Agere Systems Inc.

Data Sheet

March 2001

With Idle Bus Indicator

Dual Differential Transceiver BTF1A

Electrical Characteristics

(continued)

Table 4. Driver Voltage and Current Characteristics

For variations in output voltage over the temperature range, see Figure 10 and Figure 11. T

40 °C to +125 °C.

Parameter

Symbol

Min

Typ

Max

Unit

Output Voltages:

Low

1. Values are with terminations as per Figure 7.

1.4

1.1

0.65

High

1.8

0.8

Differential Voltage (V

)

DIFF

0.65

1.1

1.4

Output Voltage Third State:

Difference Voltage Vdo - Vdo

DIFZ

0.4

0.6

Third State, I

= 1.0 mA, V

= 4.75 V

0.2

Output Voltages (T

= 0 °C to 85 °C):

Low

1.4

1.1

0.8

High

1.5

0.8

Differential Voltage (V

)

DIFF

0.8

1.1

1.4

Input Voltages:

Low, V

= 5.25 V:

2. The input levels and difference voltage provide zero noise immunity and should be tested only in a static, noise-free environment.

0.8

Data Input

3. Test must be performed one lead at a time to prevent damage to the device.

0.8

Enable Input

0.7

High, V

= 4.75 V

2.0

Clamp, V

= 4.75 V, I

= 5.0 mA

1.0

Short-circuit Output Current, V

= 5.25 V

100

Input Currents, V

= 5.25 V:

Low, V

= 0.4 V

400

µA

High, V

= 2.7 V

µA

Reverse, V

= 5.25 V

100

µA

Agere Systems Inc.

Data Sheet
March 2001

With Idle Bus Indicator

Dual Differential Transceiver BTF1A

Electrical Characteristics

(continued)

Table 5. Receiver Voltage and Current Characteristics

For variation in minimum V

and maximum V

over the temperature range, see Figure 10. T

= 40 °C to +125 °C.

Parameter

Symbol

Min

Typ

Max

Unit

Output Voltages V

= 4.75 V:

Low, I

= 8.0 mA

1. The input levels and difference voltage provide zero noise immunity and should be tested only in a static, noise-free environment.

0.5

High, I

400 µA

2.4

Enable Input Voltages:

Low, V

= 5.25 V

0.7

High, V

= 4.75 V

2.0

Clamp, V

= 4.75 V, I

= 5.0 mA

1.0

Minimum Differential Input Voltages, V

2. Outputs of unused receivers assume a logic 1 level when the inputs are left open. (It is recommended that all unused positive inputs

be tied to the positive power supply. No external series resistor is required.)

0.80 V < V

< 7.2 V,

1.2 V < V

< 6.8 V

0.1

0.20

Input Offset Voltage

OFF

0.03

0.05

Output Currents, V

= 5.25 V:

Off-state (high Z), V

= 0.4 V

OZL

µA

Off-state (high Z), V

= 2.4 V

OZH

µA

Short Circuit

3. Test must be performed one lead at a time to prevent damage to the device.

100

Enable Input Currents, V

= 5.25 V:

Low, V

= 0.4 V

400

µA

High, V

= 2.7 V

µA

Reverse, V

= 5.5 V

100

µA

Differential Input Currents:

Low, V

= 1.2 V

1.0

High, V

= 7.2 V

1.0

Agere Systems Inc.

Data Sheet

March 2001

With Idle Bus Indicator

Dual Differential Transceiver BTF1A

Timing Characteristics

Table 6. Driver Timing Characteristics (See Figure 3 and Figure 4.)

For t

and t

propagation delays over the temperature range, see Figure 13. Propagation delay test circuit con-

nected to output is shown in Figure 7. T

40 °C to +125 °C, V

= 5 V

0.25 V.

Table 7. Receiver Timing Characteristics (See Figure 5 and Figure 6.)

For propagation delays (t

PLH

and t

PHL

) over the temperature range, see Figure 14 and Figure 15. Propagation delay

test circuit connected to output is shown in Figure 8. T

40 °C to +125 °C, V

= 5 V

0.25 V.

Parameter

Symbol

Min

Typ

Max

Unit

Propagation Delay:

Input High to Output

1. CL = 5 pF. Capacitor is connected from each output to ground.

2. tP1 and tP2 are measured from the 1.5 V point of the input to the crossover point of the outputs (see Figure 3).

0.8

1.2

2.0

Input Low to Output

0.8

1.2

2.0

Capacitive Delay

0.02

0.03

ns/pF

Disable Time (either E1 or E2):

High-to-High Impedance

PHZ

Low-to-High Impedance

PLZ

Enable Time (either E1 or E2):

High Impedance to High

PZH

High Impedance to Low

PZL

Output Skew:

skew1

0.1

0.3

PHH

PHL

|, |t

PLH

PLL

skew2

0.2

0.5

Difference Between Drivers

skew

0.3

Rise Time (20%--80%)

tLH

0.7

Fall Time (80%--20%)

tHL

0.7

Parameter

Symbol

Min

Typ

Max

Unit

Propagation Delay:

Input to Output High

PLH

1.5

2.5

4.0

Input to Output Low

PHL

1.5

2.5

4.0

Pulse Width Distortion, ltpHL-tpLHI:

Load Capacitance (C

) = 15 pF

tskew1

0.7

Load Capacitance (C

) = 150 pF

tskew1

4.0

Output Waveform Skews:

Part-to-Part Skew, T

= 75 °C

tskew1p-p

0.8

1.4

Part-to-Part Skew, T

= 40 °C to +125 °C

tskew1p-p

1.5

Same Part Skew

tskew

0.3

Disable Time, C

= 5 pF:

High-to-high Impedance

PHZ

Low-to-high Impedance

PLZ

Enable Time:

High Impedance to High

PZH

High Impedance to Low

PZL

Rise Time (20%--80%)

tLH

3.0

Fall Time (80%--20%)

tHL

3.0

Agere Systems Inc.

Data Sheet
March 2001

With Idle Bus Indicator

Dual Differential Transceiver BTF1A

Timing Characteristics

(continued)

12-3462(F)

Note: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the

delay due to the external capacitance and the intrinsic delay of the device.

Figure 2. Typical Extrinsic Propagation Delay Versus Load Capacitance at 25 °C

12-2677(F)

Figure 3. Driver Propagation Delay Timing

100

125

150

LOAD CAPACITANCE, C

(pF)

175

200

I
C

ATI

,

t

(ns)

PHL

(TYP)

PLH

(TYP)

INPUT

TRANSITION

OUTPUTS

OUTPUT

tLH

PHL

tHL

PLH

PHH

PLL

20%

80%

20%

80%

2.4 V

1.5 V

0.4 V

+ V

)/2

+ V

)/2

Agere Systems Inc.

Data Sheet

March 2001

With Idle Bus Indicator

Dual Differential Transceiver BTF1A

Timing Characteristics

(continued)

12-2268.d(F)

Note: In the third state, OUTPUT is 0.4 V more negative than OUTPUT.

Figure 4. Driver Enable and Disable Timing

12-2251.b(F)

Figure 5. Receiver Propagation Delay Timing

OUTPUT

PHZ

PZH

PLZ

PZL

3.0 V

1.5 V

0.0 V

+ 0.2 V

0.1 V

OUTPUT 0.4 V

INPUT

OUTPUT

INPUT

80%

20%

3.7 V

3.2 V

2.7 V

1.5 V

80%

20%

PHL

tHL

PLH

tLH

Data Sheet
March 2001

Agere Systems Inc.

With Idle Bus Indicator

Dual Differential Transceiver BTF1A

Timing Characteristics

(continued)

12-2538.b(F)

* E2 = 1 while E1 changes state.
E1 = 0 while E2 changes state.

Figure 6. Receiver Enable and Disable Timing

V = 0.5 V

E1*

OUTPUT

PHZ

PZH

3 V

1.5 V

0 V

3 V

1.5 V

0 V

PZL

PLZ

Test Conditions

Parametric values specified under the Electrical Char-
acteristics and Timing Characteristics sections for the
data transmission driver devices are measured with the
following output load circuits.

12-2271.a(F)

Figure 7. Driver Propagation Delay Test Circuit

12-2249(F)

* Includes probe and jig capacitances.

Note: All 458E, IN4148, or equivalent diodes.

Figure 8. Receiver Propagation Delay Test Circuit

200

100

TO OUTPUT OF

DEVICE UNDER

TEST

15 pF*

5 k

2 k

+5 V

Agere Systems Inc.

Data Sheet

March 2001

With Idle Bus Indicator

Dual Differential Transceiver BTF1A

Output Characteristics

Figure 9 illustrates typical driver output characteristics.
Included are load lines for two typical termination con-
figurations.

12-2269(F)

A. Output Current vs. Output Voltage for Loads

Shown in B and C

12-2270(F)

B. Y Load

12-2271.a(F)

Load

Figure 9. Driver Output Current vs. Voltage

Characteristics

Temperature Characteristics

2-3467(F)

Figure 10. V

and V

Extremes for Drivers vs.

Temperature for 100

Load

12-3468(F)

Figure 11. Differential Voltage (V

 V

) for

Drivers vs. Temperature

Y LOAD

LOAD

OUTPUT VOLTAGE (V)

OUTPU

CURRE

NT (m

2 V

1 V

200

100

2.5

TEMPERATURE (°C)

2.0

125 150

0.5

1.0

1.5

OUTP

UT V

LTA

RELA

MAX

MIN

MAX

MIN

100

TEMPERATURE (°C)

0.4

1.2

125 150

1.0

0.8

0.6

ENT

I
A

LTA

(V)

TYP

MIN

Agere Systems Inc.

Data Sheet
March 2001

With Idle Bus Indicator

Dual Differential Transceiver BTF1A

Temperature Characteristics

(continued)

12-3464.a(F)

Figure 12. Minimum V

and Maximum V

vs.

Temperature at V

= 4.5 V for the

Receiver

12-3469.a(F)

Figure 13. Min and Max for t

and t

Propagation

Delays vs. Temperature for the Driver

12-3465(F)

Figure 14. Propagation Delay for a High Output

PLH

) vs. Temperature at V

= 5.0 V for

the Receivers

12-3466(F)

Figure 15. Propagation Delay for a Low Output

PHL

) vs. Temperature at V

= 5.0 V for

the Receivers

100

0.0

1.6

TEMPERATURE (

0.8

0.4

1.2

2.8

125

150

2.0

)

2.4

MIN

MAX

3.2

3.6

3.8

100

0.5

TEMPERATURE (°C)

0.7

1.7

125 150

2.1

2.3

N DELA

Y (ns)

1.5

1.3

1.1

0.9

1.9

0.3

RANGE FOR t

AND t

MAX

MIN

100

1.00

3.00

TEMPERATURE (

2.00

1.50

2.50

4.00

125

150

3.50

MAX

TYP

MIN

PRO

N DEL

AY (ns)

1.00

1.50

2.00

4.00

125

150

2.50

3.00

3.50

MAX

TYP

MIN

I
O

LAY

TEMPERATURE (

100

Agere Systems Inc.

Data Sheet

March 2001

With Idle Bus Indicator

Dual Differential Transceiver BTF1A

Handling Precautions

CAUTION: This device is susceptible to damage as a result of ESD. Take proper precautions during both

handling and testing. Follow guidelines such as JEDEC Publication No. 108-A (Dec. 1988).

When handling and mounting line driver products, proper precautions should be taken to avoid exposure to ESD.
The user should adhere to the following basic rules for ESD control:

1. Assume that all electronic components are sensitive to ESD damage.

2. Never touch a sensitive component unless properly grounded.

3. Never transport, store, or handle sensitive components except in a static-safe environment.

ESD Failure Models

Lucent employs two models for ESD events that can cause device damage or failure:

1. A human body model (HBM) that is used by most of the industry for ESD-susceptibility testing and protection-

design evaluation. ESD voltage thresholds are dependent on the critical parameters used to define the model.
A standard HBM (resistance = 1500

, capacitance = 100 pF) is widely used and, therefore, can be used for

comparison purposes.

2. A charged-device model (CDM), which many believe is the better simulator of electronics manufacturing expo-

sure.

Table 8 and Table 9 illustrate the role these two models play in the overall prevention of ESD damage. HBM ESD
testing is intended to simulate an ESD event from a charged person. The CDM ESD testing simulates charging and
discharging events that occur in production equipment and processes, e.g., an integrated circuit sliding down a
shipping tube.

The HBM ESD threshold voltage presented here was obtained by using these circuit parameters.

Table 8. Typical ESD Thresholds for Data Transmission Transceivers

Table 9. ESD Damage Protection

Device

HBM Threshold

CDM Threshold

Differential Inputs

800

1000

All Other Pins

2000

1000

ESD Threat Controls

Personnel

Processes

Control

Wrist straps

ESD shoes

Antistatic flooring

Static-dissipative materials

Air ionization

Model

Human body model (HBM)

Charged-device model (CDM)

Agere Systems Inc.

Data Sheet
March 2001

With Idle Bus Indicator

Dual Differential Transceiver BTF1A

Latch Up

Latch up evaluation has been performed on the data transmission receivers. Latch up testing determines if the
power-supply current exceeds the specified maximum due to the application of a stress to the device under test. A
device is considered susceptible to latch up if the power supply current exceeds the maximum level and remains at
that level after the stress is removed.

Lucent performs latch up testing per an internal test method which is consistent with JEDEC Standard No. 17 (pre-
viously JC-40.2)

CMOS Latch Up Standardized Test Procedure

Latch up evaluation involves three separate stresses to evaluate latch up susceptibility levels:

1. dc current stressing of input and output pins.

2. Power supply slew rate.

3. Power supply overvoltage.

Table 10. Latch Up Test Criteria and Test Results

dc Current Stress

of I/O Pins

Power Supply

Slew Rate

Power Supply

Overvoltage

Data Transmission

Receiver ICs

Minimum Criteria

150 mA

µs

1.75 x Vmax

Test Results

250 mA

100 ns

2.25 x Vmax

Agere Systems Inc.

Data Sheet

March 2001

With Idle Bus Indicator

Dual Differential Transceiver BTF1A

Outline Diagrams

16-Pin SOIC (SONB/SOG)

Dimensions are in millimeters.

5-4414(F)

Note: The dimensions in this oultine diagram are intended for informational purposes only. For detailed schematics to assist your design efforts,

please contact your Lucent Technologies sales representative.

Package

Description

Number of

Pins

(N)

Package Dimensions

Maximum Length

(L)

Maximum Width

Without Leads

(B)

Maximum Width

Including Leads

(W)

Maximum Height

Above Board

(H)

Small-Outline,

Gull-Wing

(SOG)

10.49

7.62

10.64

2.67

0.61

0.51 MAX

0.28 MAX

0.10

SEATING PLANE

1.27 TYP

PIN #1 IDENTIFIER ZONE

Agere Systems Inc.

Data Sheet
March 2001

With Idle Bus Indicator

Dual Differential Transceiver BTF1A

Power Dissipation

System designers incorporating Lucent data transmis-
sion drivers in their applications should be aware of
package and thermal information associated with these
components.

Proper thermal management is essential to the long-
term reliability of any plastic encapsulated integrated
circuit. Thermal management is especially important
for surface-mount devices, given the increasing circuit
pack density and resulting higher thermal density. A
key aspect of thermal management involves the junc-
tion temperature (silicon temperature) of the integrated
circuit.

Several factors contribute to the resulting junction tem-
perature of an integrated circuit:

Ambient use temperature

Device power dissipation

Component placement on the board

Thermal properties of the board

Thermal impedance of the package

Thermal impedance of the package is referred to as

and is measured in °C rise in junction temperature

per watt of power dissipation. Thermal impedance is
also a function of airflow present in system application.

The following equation can be used to estimate the
junction temperature of any device:

= T

where:

is device junction temperature (°C).

is ambient temperature (°C).

is power dissipation (W).

is package thermal impedance (junction to

ambient

°C/W).

The power dissipation estimate is derived from two fac-
tors:

Internal device power

Power associated with output terminations

Multiplying I

times V

provides an estimate of

internal power dissipation.

The power dissipated in the output is a function of the:

Termination scheme on the outputs

Termination resistors

Duty cycle of the output

Package thermal impedance depends on:

Airflow

Package type (e.g., DIP, SOIC, SOIC/NB)

The junction temperature can be calculated using the
previous equation, after power dissipation levels and
package thermal impedances are known.

Figure 16 illustrates the thermal impedance estimates
for the various package types as a function of airflow.
This figure shows that package thermal impedance is
higher for the narrow-body SOIC package. Particular
attention should, therefore, be paid to the thermal man-
agement issues when using this package type.

In general, system designers should attempt to main-
tain junction temperature below 125 °C. The following
factors should be used to determine if specific data
transmission drivers in particular package types meet
the system reliability objectives:

System ambient temperature

Power dissipation

Package type

Airflow

12-2753(F)

Figure 16. Power Dissipation

DIP

SOIC/NB

J-LEAD SOIC/GULL WING

AIRFLOW (ft/min)

200

400

600

800

1000

1200

100

110

120

130

140

ERM

L RESI

ANCE

(

)

Data Sheet

March 2001

With Idle Bus Indicator

Dual Differential Transceiver BTF1A

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

March 2001
DS01-068ANET-1 (Replaces DS01-068ANET)

For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:

http://www.agere.com

E-MAIL:

docmaster@micro.lucent.com

N. AMERICA:

Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256

Tel. (65) 778 8833, FAX (65) 777 7495

CHINA:

Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC
Tel. (86) 21 50471212, FAX (86) 21 50472266

JAPAN:

Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700

EUROPE:

Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Technical Inquiries:GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),

FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)

Ordering Information

Part Number

Driver

Terminating

1. Indicates on-chip output terminating resistors from each driver output to ground.

Receiver

Terminating

2. Indicates on-chip input terminations across receiver inputs.

Package Type

Comcode

BTF1A16G

None

16-pin, Plastic SOIC

108648861

BTF1A16G-TR

None

Tape and Reel SOIC

108698887

Document Outline

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Document Outline

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