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December 2001
DSP1611/17/18/27/28/29
DIGITAL SIGNAL PROCESSOR
Information Manual
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright 2001 Agere Systems Inc.
All Rights Reserved
December 2001
MN02-016AUTO (Replaces MN97-030WDSP)
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
http://www.agere.com
E-MAIL:
docmaster@agere.com
N. AMERICA: Agere Systems Inc., Lehigh Valley Cental Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA:
Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
Tel. (852) 3129-2000, FAX (852) 3129-2020
CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen)
JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)
EUROPE:
Tel. (44) 7000 624624, FAX (44) 1344 488 045
A Word About Trademarks . . .
The following Agere Systems Inc. trademark is used in this manual:
Tapdance
The following trademarks, owned by entities other than Agere Systems Inc., are used in this manual:
IEEE
is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Intel
and
Intellec
are registered trademarks of Intel Corporation.
MC6800
is a trademark and
Motorola
is a registered trademark of Motorola, Inc.
MS-DOS
and
Windows
are registered trademarks of Microsoft Corporation.
Sun
,
Sun Microsystems
, the Sun logo,
SUNOS
, and
Solaris
are trademarks or registered trademarks of Sun Micro-
systems, Inc. in the United States and other countries.
TI
is a registered trademark of Texas Instruments, Inc.
UNIX
is a registered trademark licensed exclusively through X/Open Company Ltd.
X-Windows
is a trademark of Massachusetts Institute of Technology.
Agere Systems, Inc.
iii
Foreword
This manual contains detailed information on the design and application of the DSP1611/17/18/27/28/29
Digital Signal Processor family. The DSP1611-ST, DSP1618-ST, DSP1617-ST, DSP1627-ST,
DSP1628-ST, and DSP1629-ST support software libraries, the DSP1600-HDS Development System, and
numerous DSP1611/17/18/27/28/29-specific hardware support tools are also available to aid in developing
software and integrating the devices into systems.
Additional information on the digital signal processor product line is available in the form of manuals, data
sheets, and application notes.
Conventions Used in this Manual
In general, all registers writable or readable by DSP instructions are lower case. Device flags, I/O pins, and
nonprogram-accessible registers are generally upper case. For clarity, register names and DSP instruc-
tions are printed in boldface when used in written descriptions. Variable names that are to be replaced by
specific names are italicized, such as
filename
. Instruction set notation conventions are defined in Chapter
4.
DSP1611/17/18/27/28/29 Digital Signal Processor
INFORMATION MANUAL
CONTENTS
iv Agere Systems Inc.
1 Introduction ...........................................................................................................................1-1
1.1 General Description....................................................................................................1-2
1.1.1 Architecture .................................................................................................1-2
1.1.2 Instruction Set .............................................................................................1-3
1.2 Typical Applications....................................................................................................1-3
1.3 Application Support ....................................................................................................1-4
1.3.1 Support Software Library .............................................................................1-4
1.3.2 Hardware Development System ..................................................................1-4
1.4 Manual Organization ..................................................................................................1-6
1.4.1 Applicable Documentation ...........................................................................1-7
2 Hardware Architecture ..........................................................................................................2-1
2.1 Device Architecture Overview ....................................................................................2-1
2.1.1 Harvard Architecture ...................................................................................2-1
2.1.2 Concurrent Operations ................................................................................2-2
2.1.3 Device Architecture .....................................................................................2-4
2.1.4 Memory Space and Bank Switching ..........................................................2-12
2.1.5 Internal Instruction Pipeline .......................................................................2-13
2.2 Core Architecture Overview .....................................................................................2-16
2.2.1 Data Arithmetic Unit ..................................................................................2-16
2.2.2 Y Space Address Arithmetic Unit (YAAU) .................................................2-17
2.2.3 X Space Address Arithmetic Unit (XAAU) .................................................2-18
2.2.4 Cache ........................................................................................................2-18
2.2.5 Control .......................................................................................................2-18
2.3 Internal Memories.....................................................................................................2-19
2.4 External Memory Interface (EMI) .............................................................................2-19
2.5 Bit Manipulation Unit (BMU) .....................................................................................2-20
2.6 Serial Input/Output (SIO) Units.................................................................................2-20
2.7 Parallel Input/Output (PIO) (DSP1617 Only)............................................................2-21
2.8 Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only) ...................................2-21
2.9 Bit Input/Output (BIO)...............................................................................................2-22
2.10
JTAG ........................................................................................................................2-22
2.11
Timer ........................................................................................................................2-22
2.12
Hardware Development System (HDS) Module.......................................................2-23
2.13
Clock Synthesis (DSP1627/28/29 Only)...................................................................2-23
2.14
Power Management .................................................................................................2-23
3 Software Architecture ...........................................................................................................3-1
3.1 Register View of the DSP1611/17/18/27/28/29..........................................................3-1
3.1.1 Types of Registers ......................................................................................3-1
3.1.2 Register Length Definition ...........................................................................3-5
3.1.3 Register Reset Values .................................................................................3-6
3.1.4 Flags ............................................................................................................3-7
3.2 Memory Space and Addressing .................................................................................3-8
3.2.1 Y-Memory Space .........................................................................................3-8
3.2.2 X-Memory Space .......................................................................................3-10
3.3 Arithmetic and Precision...........................................................................................3-21
3.4 Interrupts ..................................................................................................................3-27
3.4.1 Introduction ................................................................................................3-27
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3.4.2 Interrupt Sources .......................................................................................3-29
3.4.3 Outputs of Interrupts ..................................................................................3-31
3.4.4 Interrupt Operation ....................................................................................3-32
3.4.5 Trap Description ........................................................................................3-38
3.4.6 Powerdown with the AWAIT State ............................................................3-40
3.4.7 Interrupts in DSP16A-Compatible Mode (DSP1617 Only) ........................3-42
3.4.8 Timing Examples, DSP16A-Compatible Mode (DSP1617 Only) ..............3-44
3.5 Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only) ...................................3-47
3.5.1 PLL Control Signals ...................................................................................3-48
3.5.2 PLL Programming Examples .....................................................................3-50
3.5.3 Latency ......................................................................................................3-50
3.6 Power Management .................................................................................................3-52
3.6.1
powerc
Control Register Bits ....................................................................3-52
3.6.2 STOP Pin ..................................................................................................3-56
3.6.3 The
pllc
Register Bits (DSP1627/28/29 Only) ..........................................3-56
3.6.4 AWAIT Bit of the
alf
Register ....................................................................3-56
3.6.5 Power Management Sequencing ..............................................................3-57
3.6.6 Power Management Examples .................................................................3-58
4 Instruction Set.......................................................................................................................4-1
4.1 Notation ......................................................................................................................4-2
4.2 Instruction Cycle Timing .............................................................................................4-3
4.3 Addressing Modes......................................................................................................4-3
4.3.1 Register Indirect Addressing .......................................................................4-3
4.3.2 Compound Addressing ................................................................................4-5
4.3.3 Direct Data Addressing ...............................................................................4-7
4.4 Processor Flags .........................................................................................................4-9
4.5 Instruction Set ..........................................................................................................4-11
4.5.1 Control Instructions ...................................................................................4-12
4.5.2 Cache Instructions .....................................................................................4-14
4.5.3 Data Move Instructions ..............................................................................4-15
4.5.4 Special Function Group .............................................................................4-19
4.5.5 Multiply/ALU Group ...................................................................................4-22
4.5.6 F3 ALU Instructions ...................................................................................4-29
4.5.7 BMU Instructions .......................................................................................4-30
4.5.8 Assembler Ambiguities ..............................................................................4-35
5 Core Architecture..................................................................................................................5-1
5.1 Data Arithmetic Unit ...................................................................................................5-1
5.1.1 Inputs and Outputs ......................................................................................5-2
5.1.2 Multiplier Functions .....................................................................................5-2
5.1.3 ALU .............................................................................................................5-2
5.1.4 Accumulators ...............................................................................................5-3
5.1.5 Counters ......................................................................................................5-4
5.1.6 DAU Pseudorandom Sequence Generator (PSG) ......................................5-7
5.1.7 Control Registers .........................................................................................5-9
5.2 X Address Arithmetic Unit (XAAU) ...........................................................................5-11
5.2.1 Inputs and Outputs ....................................................................................5-11
5.2.2 X-Memory Space Segment Selection .......................................................5-11
5.2.3 Register Descriptions ................................................................................5-12
5.3 Y Address Arithmetic Unit (YAAU) ...........................................................................5-13
5.3.1 Inputs and Outputs ....................................................................................5-13
5.3.2 Y-Memory Space .......................................................................................5-14
5.3.3 Register Descriptions ................................................................................5-14
5.3.4 Addressing Modes .....................................................................................5-14
5.4 Cache and Control ...................................................................................................5-17
5.4.1 Cache ........................................................................................................5-17
5.4.2 Control .......................................................................................................5-19
vi Agere Systems Inc.
6 External Memory Interface....................................................................................................6-1
6.1 EMI Function ..............................................................................................................6-1
6.2 Programmable Features...........................................................................................6-13
6.3 Functional Timing .....................................................................................................6-14
6.3.1 Timing Action with Wait-States ..................................................................6-15
6.4 Timing Examples......................................................................................................6-17
6.4.1 CKO Timing ...............................................................................................6-17
6.4.2 Write, Read, Read, W = 0 .........................................................................6-18
6.4.3 Read, Write, Write, W = 0 ..........................................................................6-19
6.4.4 Read, Write, W = 0, Compound Address ..................................................6-20
6.4.5 Read W = 1, Read W = 2 ..........................................................................6-21
6.4.6 Write W = 1 ................................................................................................6-22
6.4.7 Read, Read with Delayed Enable .............................................................6-23
6.4.8 Write, Read, with Delayed Enable .............................................................6-24
6.5 Boot-Up from External ROM ....................................................................................6-25
6.6 Memory Sequencer ..................................................................................................6-26
6.7 Downloading Code into External Program Memory .................................................6-28
7 Serial I/O...............................................................................................................................7-1
7.1 SIO Operation ............................................................................................................7-2
7.1.1 Active Clock Generator ...............................................................................7-2
7.1.2 Input Section ...............................................................................................7-4
7.1.3 Output Section .............................................................................................7-6
7.2 User-Controlled Features ...........................................................................................7-9
7.2.1 The
sioc
Register ........................................................................................7-9
7.2.2 Loopback Control ......................................................................................7-11
7.2.3 Power Management ..................................................................................7-11
7.3 Serial I/O Pin Descriptions .......................................................................................7-12
7.4 Codec Interface ........................................................................................................7-13
7.5 Serial I/O Programming Example.............................................................................7-14
7.5.1 Program Segment .....................................................................................7-14
7.6 Multiprocessor Mode Description .............................................................................7-15
7.6.1 Multiprocessor Mode Overview .................................................................7-15
7.6.2 Detailed Multiprocessor Mode Description ................................................7-17
7.6.3 Suggested Multiprocessor Configuration ..................................................7-24
7.6.4 Multiprocessor Mode Initialization .............................................................7-25
7.7 Serial Interface #2 ....................................................................................................7-26
7.7.1 SIO2 Features ...........................................................................................7-26
7.7.2 Programmable Features ............................................................................7-27
7.7.3 Instructions Using the SIO2 .......................................................................7-27
8 Parallel I/O (DSP1617 Only).................................................................................................8-1
8.1 PIO Operation ............................................................................................................8-2
8.1.1 Active Mode .................................................................................................8-2
8.1.2 PIO Interaccess Timing ...............................................................................8-5
8.1.3 Passive Mode ..............................................................................................8-6
8.1.4 Peripheral Mode (Host Interface) ................................................................8-9
8.2 Programmer Interface ..............................................................................................8-14
8.2.1
pioc
Register Settings ...............................................................................8-16
8.2.2 Latent Reads .............................................................................................8-17
8.2.3 Power Management ..................................................................................8-19
8.3 Interrupts and the PIO ..............................................................................................8-19
8.4 PIO Signals ..............................................................................................................8-21
8.4.1 PIO Pin Multiplexing ..................................................................................8-22
8.5 PIO Loopback Test Mode.........................................................................................8-22
9 Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only)................................................9-1
9.1 PHIF Operation ..........................................................................................................9-2
9.1.1
Intel
Mode, 16-Bit Read ...............................................................................9-3
9.1.2
Intel
Mode, 16-Bit Write ...............................................................................9-4
9.1.3
Motorola
Mode, 16-Bit Read .......................................................................9-5
Agere Systems Inc. vii
9.1.4
Motorola
Mode, 16-Bit Write ........................................................................9-6
9.1.5 8-Bit Transfers .............................................................................................9-7
9.1.6 Accessing the PSTAT Register ...................................................................9-7
9.2 Programmer Interface ................................................................................................9-8
9.2.1
phifc
Register Settings ...............................................................................9-8
9.2.2 Power Management ..................................................................................9-10
9.3 Interrupts and the PHIF ............................................................................................9-10
9.4 PHIF Pin Multiplexing ...............................................................................................9-11
9.5 Overall Functional Timing.........................................................................................9-12
10 Bit I/O Unit ..........................................................................................................................10-1
10.1
BIO Hardware Function ............................................................................................10-1
10.1.1 BIO Configured as Inputs ..........................................................................10-2
10.1.2 BIO Configured as Outputs .......................................................................10-2
10.1.3 Pin Descriptions ........................................................................................10-3
10.1.4 BIO Pin Multiplexing ..................................................................................10-4
10.2
Software View ..........................................................................................................10-4
10.2.1 Registers ...................................................................................................10-5
10.2.2 Flags ..........................................................................................................10-6
10.2.3 Instructions ................................................................................................10-6
10.2.4 Examples ...................................................................................................10-6
11 The JTAG Test Access Port ...............................................................................................11-1
11.1
Overview of the JTAG Architecture ..........................................................................11-1
11.2
Overview of the JTAG Instructions ...........................................................................11-3
11.3
Elements of the JTAG Test Logic.............................................................................11-4
11.3.1 The Test Access Port (TAP) ......................................................................11-4
11.3.2 The TAP Controller ....................................................................................11-5
11.3.3 The Instruction Register--JIR ...................................................................11-7
11.3.4 The Boundary-Scan Register--JBSR .......................................................11-8
11.3.5 The Bypass Register--JBPR ..................................................................11-16
11.3.6 The Device Identification Register--JIDR ...............................................11-16
11.3.7 The JTAG Data Register--
jtag
...............................................................11-19
11.3.8 The JTAG Control Register--JCON ........................................................11-19
11.3.9 The JTAG Output Stage--JOUT .............................................................11-19
11.4
The JTAG Instruction Set .......................................................................................11-19
11.4.1 The EXTEST Instruction ..........................................................................11-19
11.4.2 The INTEST Instruction ...........................................................................11-19
11.4.3 The SAMPLE Instruction .........................................................................11-20
11.4.4 The BYPASS Instruction .........................................................................11-20
11.4.5 The IDCODE Instruction ..........................................................................11-20
12 Timer...................................................................................................................................12-1
12.1
Hardware View .........................................................................................................12-1
12.2
Programmable Features and Operation ...................................................................12-2
12.2.1
timerc
Register Encoding .........................................................................12-2
12.2.2
timer0
Register .........................................................................................12-3
12.2.3 The
inc
Register ........................................................................................12-3
12.2.4 Initialization Conditions ..............................................................................12-3
12.3
Program Example.....................................................................................................12-4
12.4
Timing.......................................................................................................................12-5
13 Bit Manipulation Unit (BMU) ...............................................................................................13-1
13.1
Hardware View .........................................................................................................13-1
13.2
Software View ..........................................................................................................13-2
13.2.1 Instruction Set ...........................................................................................13-2
13.2.2 Shifting Operations ....................................................................................13-2
13.2.3 Normalization ............................................................................................13-4
13.2.4 Extraction ..................................................................................................13-5
13.2.5 Insertion .....................................................................................................13-6
13.2.6 Shuffle Accumulators ................................................................................13-8
13.2.7 Instruction Encoding ..................................................................................13-9
viii Agere Systems Inc.
13.2.8 Software Example ...................................................................................13-10
14 Error Correction Coprocessor (DSP1618/28 Only).............................................................14-1
14.1
System Description ..................................................................................................14-1
14.2
Hardware Architecture..............................................................................................14-3
14.2.1 Branch Metric Unit .....................................................................................14-3
14.2.2 Update Unit ...............................................................................................14-4
14.2.3 Traceback Unit ..........................................................................................14-4
14.2.4 Interrupts and Flags ..................................................................................14-5
14.2.5 Traceback RAM .........................................................................................14-5
14.3
DSP Decoding Operation Sequence........................................................................14-6
14.4
Operation of the ECCP.............................................................................................14-7
14.5
Software Architecture ...............................................................................................14-8
14.5.1 R-Field Registers .......................................................................................14-8
14.5.2 ECCP Internal Memory-Mapped Registers .............................................14-10
14.5.3 ECCP Interrupts and Flags .....................................................................14-17
14.5.4 Traceback RAM .......................................................................................14-17
14.6
ECCP Instruction Timing ........................................................................................14-19
14.6.1 ResetECCP Instruction ...........................................................................14-19
14.6.2 UpdateMLSE Instruction with Soft Decision ............................................14-19
14.6.3 UpdateMLSE Instruction with Hard Decision ..........................................14-21
14.6.4 UpdateConv Instruction with Soft Decisions ...........................................14-22
14.6.5 UpdateConv Instruction with Hard Decision ............................................14-23
14.6.6 TraceBack Instruction ..............................................................................14-23
15 Interface Guide ...................................................................................................................15-1
15.1
Pin Information .........................................................................................................15-1
15.2
Signal Descriptions...................................................................................................15-5
15.2.1 System Interface .......................................................................................15-5
15.2.2 External Memory Interface ........................................................................15-6
15.2.3 Serial Interface #1 .....................................................................................15-7
15.2.4 PIO/PHIF or Serial Interface #2 and Control I/O Interface ........................15-9
15.2.5 Control I/O Interface ................................................................................15-11
15.2.6 JTAG Test Interface ................................................................................15-11
15.3
Resetting DSP161X and DSP162X Devices..........................................................15-12
15.3.1 Powerup Reset ........................................................................................15-12
15.3.2 Using the TAP to Reset the TAP Controller ............................................15-12
15.3.3 RSTB Pin Reset ......................................................................................15-13
15.4
Mask-Programmable Options.................................................................................15-14
15.4.1 Input Clock Options .................................................................................15-14
15.4.2 ROM Security Options (DSP1617/18/27/28/29 Only) .............................15-14
15.5
Additional Electrical Characteristics and Requirements for Crystal .......................15-15
A Instruction Encoding ............................................................................................................ A-1
A.1 Instruction Encoding Formats.................................................................................... A-1
A.2 Field Descriptions...................................................................................................... A-4
B Instruction Set Summary ..................................................................................................... B-1
goto JA................................................................................................................................ B-1
goto B ................................................................................................................................. B-2
if CON goto/call/return ........................................................................................................ B-3
call JA ................................................................................................................................. B-4
icall...................................................................................................................................... B-5
do K { .................................................................................................................................. B-6
redo K ................................................................................................................................. B-7
R = IM16 ............................................................................................................................. B-8
SR = IM9........................................................................................................................... B-10
R = aS[l] ............................................................................................................................ B-11
aT[l] = R ............................................................................................................................ B-12
R = Y................................................................................................................................. B-13
Y = R................................................................................................................................. B-14
Z : R .................................................................................................................................. B-15
Agere Systems Inc. ix
DR = *(OFFSET)............................................................................................................... B-16
*(OFFSET) = DR............................................................................................................... B-17
if CON F2.......................................................................................................................... B-18
ifc CON F2 ........................................................................................................................ B-19
F1 Y................................................................................................................................ B-20
F1 Y = a0[l]..................................................................................................................... B-22
F1 Y = a1[l]..................................................................................................................... B-22
F1 x = Y.......................................................................................................................... B-24
F1 y[l] = Y ....................................................................................................................... B-26
F1 y = Y x = *pt++[i]..................................................................................................... B-28
F1 y = a0 x = *pt++[i] ................................................................................................... B-30
F1 y = a1 x = *pt++[i] ................................................................................................... B-30
F1 aT[l] = Y..................................................................................................................... B-32
F1 Y = y[l] ....................................................................................................................... B-34
F1 Z : y[l] ........................................................................................................................ B-36
F1 Z : aT[l]...................................................................................................................... B-38
F1 Z : y x = *pt++[i] ...................................................................................................... B-40
aD = aS OP aT ................................................................................................................. B-42
aD = aS OP p.................................................................................................................... B-43
aD = aS<h,l> OP IM16...................................................................................................... B-44
aD = a SHIFT aS ............................................................................................................ B-46
aD = aS SHIFT arM .......................................................................................................... B-47
aD = aS SHIFT IM16 ........................................................................................................ B-48
aD = exp (aS).................................................................................................................... B-49
aD = norm (aS, arM) ......................................................................................................... B-50
aD = extracts (aS, arM)..................................................................................................... B-51
aD = extractz (aS, arM)..................................................................................................... B-51
aD = extracts (aS, IM16)................................................................................................... B-52
aD = extractz (aS, IM16)................................................................................................... B-52
aD = insert (aS, arM) ........................................................................................................ B-53
aD = insert (aS, IM16)....................................................................................................... B-54
aD = aS : aaT.................................................................................................................... B-55
S
Chapter 1
Introduction
CHAPTER 1. INTRODUCTION
CONTENTS
1
Introduction ...........................................................................................................................1-1
1.1
General Description....................................................................................................1-2
1.1.1
Architecture .................................................................................................1-2
1.1.2
Instruction Set .............................................................................................1-3
1.2
Typical Applications....................................................................................................1-3
1.3
Application Support ....................................................................................................1-4
1.3.1
Support Software Library .............................................................................1-4
1.3.2
Hardware Development System ..................................................................1-4
1.4
Manual Organization ..................................................................................................1-6
1.4.1
Applicable Documentation ...........................................................................1-7
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001
Agere Systems Inc.
DRAFT COPY
1-1
1 Introduction
Designed specifically for applications requiring low-power dissipation in digital cellular systems, the DSP1611,
DSP1617, DSP1618, DSP1618x24
1
, DSP1627, DSP1627x32
2
, DSP1628x08
3
, DSP1628x16
3
, DSP1629x10
4
, and
DSP1629x16
4
are signal coding devices that can be programmed to perform a wide variety of fixed-point signal
processing functions. The devices are based on the DSP1600 core with a bit manipulation unit for enhanced signal
coding efficiency. The DSP1611/17/18/27/28/29 include a mix of peripherals specifically intended to support pro-
cessing-intensive, but cost-sensitive, applications in the area of digital mobile communications. The features of the
DSP1611/17/18/27/28/29 are as follows:
*
Optimized for digital cellular applications with a bit manipulation unit for higher signal coding efficiency
*
Multiple speed and operating voltage options
*
Low power consumption
*
Flexible power management modes
-- Standard sleep
-- Sleep with slow internal clock
-- Hardware STOP pin halts DSP
*
Multiple packaging options available including low-profile TQFP and BQFP packaging
*
Multiple mask-programmable clock options
*
Single-cycle squaring
*
16 x 16-bit multiplication and 36-bit accumulation in one instruction cycle
*
Instruction cache for high-speed, program-efficient, zero-overhead looping
*
Memory sequencer for single-instruction access to both X and Y external memory space
*
Two external vectored interrupts and trap
*
Flexible internal ROM and internal dual-port RAM configurations
*
Dual serial I/O ports with multiprocessor capability--16-bit data channel, 8-bit protocol channel
*
8-bit parallel interface
*
8-bit control I/O interface
*
256 memory-mapped I/O ports, one internally decoded for glueless device interfacing
*
Interrupt timer
*
CMOS I/O levels
*
IEEE
P1149.1 test port (JTAG with boundary-scan)
*
Full-speed in-circuit emulation hardware development system on-chip
*
Supported by DSP1611/17/18/27/28/29 software and hardware development tools
*
Each device also includes specific features for specialized applications
-- Error correction coprocessor (ECCP) in DSP1618/28
-- On-chip phase-lock loop (PLL) in DSP1627/28/29
-- Bootstrap ROM in DSP1611
This manual is a user's reference guide for the DSP1611/17/18/27/28/29.
1.The DSP1618x24 is basically the same as the DSP1618. They differ in the amount of internal ROM memory and X-memory mapping (see
Table 3-11, Section 3.2.2, X-Memory Space). Discussion of the DSP1618 also refers to the DSP1618x24 except if noted otherwise.
2.The DSP1627x32 is basically the same as the DSP1627. They differ in the amount of internal ROM memory and X-memory mapping (see
Table 3-12, Section 3.2.2, X-Memory Space). Discussion of the DSP1627 also refers to the DSP1627x32 except if noted otherwise.
3.The DSP1628x08 and DSP1628x16 differ only in the size of internal dual-port RAM. Discussion of the DSP1628 refers to both the
DSP1628x08 and DSP1628x16 except if noted otherwise.
4.The DSP1629x10 and DSP1629x16 differ only in the size of internal dual-port RAM. Discussion of the DSP1629 refers to both the
DSP1629x10 and DSP1629x16 except if noted otherwise.
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1.1 General Description
1.1.1 Architecture
The DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629 are made up of the DSP1600 core pro-
cessor, a dual-port RAM, ROM, and several peripheral blocks. The core contains the data arithmetic unit, the
memory addressing units, the cache, and the control section.
The data arithmetic unit (DAU) is the main computational execution unit of the processor. It supports a 16-bit x
16-bit multiply, a 36-bit ALU operation, and two 16-bit data fetches from memory in a single instruction cycle. The
DAU is made up of two input data registers, the multiplier, two accumulators, the ALU, and various control registers.
The product from the multiplier can be accumulated in one of the two 36-bit accumulators. The data in these accu-
mulators can be directly loaded from or stored to memory in 16-bit words. The ALU supports a full set of arithmetic
and logic operations on either 16- or 32-bit data. Because a standard set of ALU conditions can be tested to per-
form conditional branches and subroutine calls, the processor functions as a powerful 16-bit or 32-bit microproces-
sor for logical and control applications.
A bit manipulation unit (BMU) is provided to accelerate signal coding algorithms. It performs full 36-bit barrel shift-
ing, normalization, and bit field extraction or insertion of data in the accumulators. Two alternate accumulators pro-
vide storage for 36-bit data.
An on-chip cache memory can selectively store repetitive operations like those found in an FIR or IIR filter section.
The code in the cache can repeat up to 127 times with no looping overhead. In addition, operations in the cache
that require an X-memory data access (for example, reading fixed coefficients) execute at twice the normal rate.
The cache greatly reduces the need for writing in-line repetitive code and, therefore, reduces program memory size
requirements. In addition, power consumption is reduced because use of the cache eliminates a memory access
for instruction fetches.
Two addressing units support high-speed, register-indirect memory addressing with postincrementing of the regis-
ter. Four address pointer registers can be used for either read or write addresses to the RAM. One address regis-
ter is dedicated to the instruction/coefficient memory space for table look-up. Direct data addressing is supported
for 16 key registers. A unique compound addressing mode that swaps data between a register and memory in only
two instruction cycles is available. Immediate addressing can be done by using a 9-bit address in a one-cycle
instruction or a 16-bit address in a two-cycle instruction.
The DSP1611/17/18/27/28/29 on-chip memory includes both ROM and dual-port RAM. The RAM has separate
ports to the instruction/coefficient bus and the data bus, and it can write either bus. A program can be downloaded
from slow off-chip memory into the RAM and then executed at full-speed without wait-states. The RAM can also be
downloaded through the JTAG interface for full-speed, remote, in-circuit emulation or for self-test.
The external memory interface (EMI) connects either the instruction/coefficient buses or the data buses to the
external memory buses. The bit input/output (BIO) unit has eight pins that can be individually selected as inputs or
outputs. The timer provides programmable periodic interrupts. The JTAG interface is a four-wire standard test port
defined by
IEEE
P1149.1. On-chip hardware development system (HDS) circuitry performs instruction break-
pointing and branch tracing in support of full-speed, in-circuit emulation with only the low-speed serial JTAG inter-
face required off-chip.
The DSP1611/17/18/27/28/29 have both a parallel I/O port (PIO or PHIF) and two serial I/O ports (SIO). The serial
I/O units are double-buffered and easily interface to other DSP1600 family devices, commercially available codecs,
and time-division multiplexed (TDM) channels with few, if any, additional components. Both ports connect as many
as eight DSPs in multiprocessor operation. The parallel I/O unit is capable of interfacing to an 8-bit bus containing
other DSP1600 family devices, microprocessors, microprocessor peripherals, or other I/O devices.
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Introduction
Agere Systems Inc.
DRAFT COPY
1-3
1.1 General Description
(continued)
1.1.1 Architecture
(continued)
Many applications, such as portable cellular terminals, require programmable sleep modes for power management.
There are three different control mechanisms for achieving low-power operation: the
powerc
control register
,
the
STOP pin, and the AWAIT bit in the
alf
register. The
powerc
register configures various power-saving modes by
controlling internal clocks and peripheral I/O units. The STOP pin controls the internal processor clock. The
AWAIT bit in the
alf
register allows the processor to go into a power-saving standby mode until an interrupt occurs.
The external interrupts asynchronously restart the processor from a deep sleep power-saving mode, and program
execution continues without any loss of state. The various power management options are chosen based on
power consumption, wake-up latency, or both requirements.
The DSP1611/17/18/27/28/29 are implemented in low-power CMOS technology and are offered in a variety of
packaging options. For optimal matching to system requirements, several options for low-voltage power supply and
clock speeds are available. See the latest data sheet for the current offerings.
1.1.2 Instruction Set
The DSP1611/17/18/27/28/29 instructions fall into seven categories: multiply/ALU, special function, control, data
move, F3 ALU, BMU, and cache. All instructions are 16 bits wide and have a C-like assembler syntax. Instructions
typically execute in one or sometimes two cycles, and data-path latency effects have been eliminated. Very high
performance is achieved by the use of concurrent instructions in the DAU.
1.2 Typical Applications
The devices in the DSP16XX
1
family of digital signal processors are used in many different application areas
including telecommunications, speech processing, image processing, graphics, array processors, robotics, studio
electronics, instrumentation, and military applications. Some of the possible applications follow:
TELECOMMUNICATIONS
1.XX denotes the last two digits of the device name, e.g., XX = 11 for the DSP1611.
*
Mobile Communications Speech coding, modulation/demodulation, channel coding/decoding
*
Modems Echo cancellation, filtering, error correction and detection
*
PBX Tone detection, tone generation, MF, DTMF
*
Switches Tone detection, tone generation, line testing
*
Transmission Multipulse LPC, ADPCM, transmultiplexing, encryption, DS0, DS1
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Introduction December 2001
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1.2 Typical Applications
(continued)
SPEECH
CONSUMER
Many of these applications can use standard algorithms that have been designed to reduce computational and
data transfer requirements for these DSPs. These algorithms have been coded in DSP1600 assembly language
and are available to registered users via Agere's DSP tech support web page at
http://www.agere.com/micro/w am/tse.
1.3 Application Support
The use of the DSP1611/17/18/27/28/29-ST Support Tools and the DSP1600-HDS Hardware Development Sys-
tem aids application development.
1.3.1 Support Software Library
Software development tools to help create, test, and debug DSP1611/17/18/27/28/29 application programs are
available from the Agere Systems' appropriate support software library for the particular device. Each sup-
port software library consists of an assembler, linker, and software simulator that run on
Sun-4
,
UNIX
, or
MS-
DOS
operating systems. The software includes a menu driven,
Windows
based, graphical user interface.
The assembler transforms DSP1611/17/18/27/28/29 source code into object code in a standard format (COFF)
that is then processed by the linker. The assembler contains a preprocessor similar to the C preprocessor and pro-
vides the features of a full macro assembler. The linker creates load modules for the simulator by combining object
files, performing relocation, resolving external references, and supporting symbol table information for symbolic
testing. The DSP1611/17/18/27/28/29 software simulator provides access to all registers and memory and allows
program breakpointing. The simulator also provides the user interface to the DSP1600 Hardware Development
System.
1.3.2 Hardware Development System
The DSP1600 JTAG communication system (JCS) supports application system hardware development and soft-
ware testing.
*
Recognition Feature extraction, spectrum analysis, pattern matching
*
Synthesis LPC, format synthesis
*
Coding CELP, VSELP, ADPCM, LPC, multipulse LPC, vector quantization
*
Studio Electronics Digital audio
*
Answering Machines Speech coding/decoding, system control
*
Entertainment Speech coding/decoding
*
Educational --
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Introduction
Agere Systems Inc.
DRAFT COPY
1-5
1.3 Application Support
(continued)
1.3.2 Hardware Development System (continued)
Figure 1-1 shows the components of the DSP1600 hardware development system for in-circuit emulation. The PC
is an
MS-DOS 386, 486-based, or better machine. The enhanced system controller card (ESCC) plugs into an
8-bit slot on the PC ISA I/O bus and connects to the enhanced target interface box (ETIB). The ETIB provides a
JTAG interface to the target DSP1611/17/18/27/28/29 device using a 9-pin connector cable. With this configura-
tion, a program can be downloaded into the DSP on the user's board and executed at full speed. The emulation is
performed with the actual DSP located on the user's board, and not one separated from it by a performance-
limiting cable. Program development with breakpointing, single-stepping, and branch tracing is available with the
simulator; it is aided by the hardware development system module on the DSP1611/17/18/27/28/29.
Figure 1-1. In-Circuit Emulation with the DSP1600--JCS
Another development tool available is the demonstration board (DSP1611/17/18/27/28/29-DEMO). The demon-
stration board replaces the customer board in Figure 1-1 and provides a development platform with external mem-
ory (static RAM or PROM), a DSP1611/17/18/27/28/29 device, and access many DSP signals.
ESCC
ETIB
TARGET BOARD
9-PIN CABLE
37-PIN CABLE
ESCC ENHANCED SYSTEM CONTROLLER CARD
ETIB ENHANCED TARGET INTERFACE BOX
(JTAG INTERFACE)
POWER CABLE
TARGET BOARD
POWER
SUPPLY
ac SUPPLY
(12.0 V--15.0 V)
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1.4 Manual Organization
This document is a reference guide for the DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629. It
describes the architecture, instruction set, and interfacing requirements of the device. The remaining chapters of
this manual are outlined below:
Chapter 2. Hardware Architecture: An overall description of the device including separate sections describ-
ing the major elements of the architecture and how they function.
Chapter 3. Software Architecture: A description of the topics associated with the software of the device.
Included are a register view of the chip, arithmetic and precision of data, memory space descrip-
tion, and the interrupt structure.
Chapter 4. Instruction Set: This section describes the general characteristics of the groups of instructions.
Notation and addressing modes are also discussed in detail. Appendix B lists the complete
instruction set and provides a description of each instruction including restrictions and normal
uses.
Chapter 5. Core Architecture: A detailed description of the DSP1600 core architecture.
Chapter 6. External Memory Interface: A description of the EMI port including functional timing.
Chapter 7. Serial I/O: A detailed analysis of the operation of the serial I/O ports including active and passive
clocking, interrupts, and multiprocessor operation.
Chapter 8. Parallel I/O (DSP1617 Only): A detailed analysis of the operation of this parallel I/O port including
interrupt information.
Chapter 9. Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only): A functional description of the oper-
ation of this port, including interrupt information.
Chapter 10. Bit I/O Unit: A functional description of the operation and programming of this port.
Chapter 11. JTAG Test Access Port: Functional description of the JTAG port.
Chapter 12. Timer: Operation and programming.
Chapter 13. Bit Manipulation Unit: A detailed description of the bit manipulation unit.
Chapter 14. Error Correction Coprocessor (DSP1618/28 Only): A detailed description of this coprocessor.
Chapter 15. Interface Guide: A functional description of each category of pins with tables describing pins.
Appendix A. Instruction Encoding: Lists the hardware-level encoding of the instruction set.
Appendix B. Instruction Set Summary: Each instruction is described in detail.
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Introduction
Agere Systems Inc.
DRAFT COPY
1-7
1.4 Manual Organization
(continued)
1.4.1 Applicable Documentation
A variety of documents exists to provide specific information on various members of the DSP1600 product family.
Contact your Agere Systems Account Manager for the latest issue of any of the following documents. The
back cover lists contact numbers for customer assistance.
DSP1611/17/18/27/28/29 Digital Signal Processor Information Manual (this manual) is a reference guide for the
DSP1611/17/18/27/28/29. It describes the architecture, instruction set, and interfacing requirements.
DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629 Digital Signal Processor data sheets provide
up-to-date timing requirements and specifications, electrical characteristics, and a summary of the instruction set
and device architecture for each device.
DSP1600 Support Tools Manual is an online document shipped with DSP1611/17/18/27/28/29 software tools. It
includes the appropriate DSP1611/17/18/27/28/29 supplement that provides the information necessary to install
and use the DSP1611/17/18/27/28/29 support software. The support tools manual is also required if working with
the DSP1600 Hardware Development System because the support software provides an interface between the
host computer and the development system. Each hardware development tool is packed with a user manual and
schematics.
Chapter 2
Hardware Architecture
CHAPTER 2. HARDWARE ARCHITECTURE
CONTENTS
2
Hardware Architecture ..........................................................................................................2-1
2.1
Device Architecture Overview ....................................................................................2-1
2.1.1
Harvard Architecture ...................................................................................2-1
2.1.2
Concurrent Operations ................................................................................2-2
2.1.3
Device Architecture .....................................................................................2-4
2.1.4
Memory Space and Bank Switching ..........................................................2-12
2.1.5
Internal Instruction Pipeline .......................................................................2-13
2.2
Core Architecture Overview .....................................................................................2-16
2.2.1
Data Arithmetic Unit ..................................................................................2-16
2.2.2
Y Space Address Arithmetic Unit (YAAU) .................................................2-17
2.2.3
X Space Address Arithmetic Unit (XAAU) .................................................2-18
2.2.4
Cache ........................................................................................................2-18
2.2.5
Control .......................................................................................................2-18
2.3
Internal Memories.....................................................................................................2-19
2.4
External Memory Interface (EMI) .............................................................................2-19
2.5
Bit Manipulation Unit (BMU) .....................................................................................2-20
2.6
Serial Input/Output (SIO) Units.................................................................................2-20
2.7
Parallel Input/Output (PIO) (DSP1617 Only)............................................................2-21
2.8
Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only) ...................................2-21
2.9
Bit Input/Output (BIO)...............................................................................................2-22
2.10
JTAG ........................................................................................................................2-22
2.11
Timer ........................................................................................................................2-22
2.12
Hardware Development System (HDS) Module.......................................................2-23
2.13
Clock Synthesis (DSP1627/28/29 Only)...................................................................2-23
2.14
Power Management .................................................................................................2-23
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Hardware Architecture
Agere Systems Inc.
DRAFT COPY
2-1
2 Hardware Architecture
This chapter presents an overview of the hardware in the DSP1611, DSP1617, DSP1618, DSP1627, DSP1628,
and DSP1629. First, an overall view of the architecture is discussed; then, each major functional block is
described. The following chapters give full details on each block.
2.1 Device Architecture Overview
2.1.1 Harvard Architecture
Figure 2-1 shows a view of a simple operation in the DSP1611/17/18/27/28/29 architecture to demonstrate funda-
mentally how an instruction is processed. The architecture is a Harvard architecture defined as having two sepa-
rate memory spaces. The first is the instruction/coefficient space or program space that is referred to in this
manual as the X-memory space. The second is the data memory space that is referred to as the Y-memory
space. Each memory space has a corresponding address arithmetic unit. In the instruction/coefficient memory
space, the program addressing unit (XAAU) places addresses on the program address bus (XAB). In this example,
these addresses go to the internal ROM that, then, places instructions on the program data bus (XDB). The
instructions are decoded in the control block that, in turn, provides control signals to all of the processor sections.
The control signals respond to instructions that, in this example, call for arithmetic operations on data residing in
the RAM. The data addressing unit (YAAU) addresses the RAM over the data address bus (YAB), and data is
transferred between the RAM and data arithmetic unit (DAU) over the data bus (YDB). The power of the architec-
ture lies in the parallel operations that are possible. In this case, instruction processing, data transfer, and arith-
metic operations can all be done simultaneously.
5-4140
Figure 2-1. Harvard Architecture
ROM
CONTROL
PROGRAM
ADDRESS
UNIT
RAM
DATA
ARITHMETIC
UNIT
DATA
ADDRESS
UNIT
INSTRUCTIONS
PROG. COUNTER
XAB
YAB
YDB
XDB
16
16
16
16
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2.1 Device Architecture Overview
(continued)
2.1.2 Concurrent Operations
Figure 2-2 shows the hardware view of an example of concurrent operations in the device. It also demonstrates
the flexibility of the memory spaces. In this example, the program is executing from the instruction cache. Instruc-
tions are fed directly to the control section freeing the XAB. The program addressing unit (XAAU) is now address-
ing one bank of the dual-port RAM (Bank 1) to transfer variable coefficients between the RAM and the DAU. It
could alternatively have been addressing the ROM to transfer fixed coefficients to the DAU. The data addressing
unit (YAAU) is addressing another bank of the dual-port RAM (Bank 4) to transfer data between the RAM and the
DAU. Thus, in one instruction cycle, two words of data can be transferred to the DAU simultaneously during inter-
nal calculations in the DAU. In the DAU, a multiplication can occur at the same time as an accumulation of a previ-
ous product. In fact, a multiplication can occur in parallel with a variety of ALU operations.
5-4141.a
Figure 2-2. Concurrent Operations in the DSP1611/17/18/27/28/29
CACHE
CONTROL
DUAL-PORT
RAM
BANK 4
DUAL-PORT
RAM
BANK 1
INTERNAL
BUS
YAB XAB
YDB XDB
DAU
INSTRUCTIONS
DATA
VARIABLE
COEFFICIENTS
x REGISTER
y REGISTER
MULTIPLIER
ACCUMULATOR
XAAU
YAAU
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Hardware Architecture
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2-3
2.1 Device Architecture Overview
(continued)
2.1.2 Concurrent Operations
(continued)
Table 2-1 shows the sequence of instructions whose operations are described in the previous example. The pipe-
lining of functional operations and data transfers is illustrated. The interpretation of the instructions is as follows:
y
= Y means place the contents of memory space Y in register
y
. In the actual instruction, Y could be replaced by
*
rM
++. *
rM
++ denotes the memory location pointed to by the address in register
rM
(M = <0--3>) and postincre-
ment the address. Similarly,
x
= X means place the contents of memory space X in register
x
. In the actual
instruction, X could be replaced by *
pt
++. *
pt
++ denotes the memory location pointed to by the address in the
pt
register and postincrement the address.
p
=
x
*
y
means multiply the data in registers
x
and
y
and put the result in
register
p
.
a0
=
a0
+
p
means add the value in
p
to the previous value in accumulator
a0
. The subscripts are
attached to indicate the order of the operation and to demonstrate the flow of the results of operations on
y
and
x
.
In this example, an accumulation takes place during every instruction cycle but there is a delay of three instructions
from the data into the
x
and
y
registers to the final accumulation.
The most efficient programs use the parallelism as described above to the fullest extent. The instructions that
allow concurrent operations are the multiply/ALU instructions with their associated data transfers and are described
in detail in Chapter 4, Instruction Set.
Table 2-1. Pipeline Flow for Concurrent Operations
Instruction # Accumulator Multiplier Registers
(1) a0
0
= a0
1
+ p
0
p
1
= x
1
* y
1
y
2
= Y
2
, x
2
= X
2
(2) a0
1
= a0
0
+ p
1
p
2
= x
2
* y
2
y
3
= Y
3
, x
3
= X
3
(3) a0
2
= a0
1
+ p
2
p
3
= x
3
* y
3
y
4
= Y
4
, x
4
= X
4
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2.1 Device Architecture Overview
(continued)
2.1.3 Device Architecture
Figures 2-3, 2-4, 2-5, 2-6, 2-7, and 2-8 show the block diagrams for DSP1611, DSP1617, DSP1618, DSP1627,
DSP1628, and DSP1629 processors. The major blocks are the DSP1600 processor core, the memories, the bit
manipulation unit, the external memory interface, the serial input(s)/output(s), the parallel input/output, the bit I/O,
the JTAG, and the timer.
These registers are accessible through external pins only.
5-4142.a
Figure 2-3. DSP1611 Block Diagram
TDO
TCK
TMS
M
U
X
DSP1600 CORE
RWN EXM DSEL EROM ERAMHI
AB[15:0]
DB[15:0] I/O
VEC[3:0] OR IOBIT[7:4]
DO2 OR PSEL1
OLD2 OR PODS
OCK2 OR PSEL2
OBE2 OR POBE
SYNC2 OR PSEL0
ICK2 OR PB0
ILD2 OR PIDS
DI2 OR PB1
IBF2 OR PIBF
DOEN2 OR PB2
SADD2 OR PB3
IOBIT[3:0] OR PB[7:4]
CKI
CKI2
CKO
RSTB
STOP
TRAP
INT[1:0]
IACK
DI1
ICK1
ILD1
IBF1
DO1
OCK1
OLD1
OBE1
SYNC1
SADD1
DOEN1
EXTERNAL MEMORY INTERFACE & EMUX
ioc
DUAL-PORT
RAM
12K x 16
ROM
1K x 16
ERAMLO
YAB YDB
XDB XAB BMU
aa0
aa1
ar0
ar1
ar2
ar3
IDB
PHIF
phifc
PSTAT
pdx0(IN)
pdx0(OUT)
BIO
sbit
cbit
SIO2
sdx2(OUT)
srta2
tdms2
sdx2(IN)
sioc2
saddx2
SIO1
sdx(OUT)
srta
tdms
sdx(IN)
sioc
saddx
TIMER
timerc
timer0
HDS
BREAKPOINT
JTAG
BOUNDARY-SCAN
jtag
JCON
ID
BYPASS
TRACE
powerc
TDI
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December 2001 Hardware Architecture
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DRAFT COPY
2-5
2.1 Device Architecture Overview
(continued)
2.1.3 Device Architecture
(continued)
These registers are accessible through external pins only.
5-4142.b
Figure 2-4. DSP1617 Block Diagram
TDO
TDI
TCK
TMS
M
U
X
DSP1600 CORE
VEC[3:0] OR IOBIT[7:4]
DO2 OR PSEL1
OLD2 OR PODS
OCK2 OR PSEL2
OBE2 OR POBE
SYNC2 OR PSEL0
ICK2 OR PB0
ILD2 OR PIDS
DI2 OR PB1
IBF2 OR PIBF
DOEN2 OR PB2
SADD2 OR PB3
IOBIT[3:0] OR PB[7:4]
CKI
CKI2
CKO
RSTB
STOP
TRAP
INT[1:0]
IACK
DI1
ICK1
ILD1
IBF1
DO1
OCK1
OLD1
OBE1
SYNC1
SADD1
DOEN1
EXTERNAL MEMORY INTERFACE & EMUX
ioc
DUAL-PORT
RAM
4K x 16
ROM
24K x 16
YAB YDB
XDB XAB BMU
aa0
aa1
ar0
ar1
ar2
ar3
IDB
PIO
pioc
PSTAT
pdx<0--7>(IN)
pdx<0--7>(OUT)
BIO
sbit
cbit
SIO2
sdx2(OUT)
srta2
tdms2
sdx2(IN)
sioc2
saddx2
SIO1
sdx(OUT)
srta
tdms
sdx(IN)
sioc
saddx
TIMER
timerc
timer0
HDS
BREAKPOINT
JTAG
BOUNDARY-SCAN
jtag
JCON
ID
BYPASS
TRACE
powerc
RWN
EXM DSEL EROM
ERAMHI
AB[15:0]
DB[15:0] I/O ERAMLO
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2.1 Device Architecture Overview
(continued)
2.1.3 Device Architecture
(continued)
These registers are accessible through external pins only.
DSP1618x24 contains 24K x 16 ROM.
5-4142.c
Figure 2-5. DSP1618 Block Diagram
TDO
TDI
TCK
TMS
M
U
X
DSP1600 CORE
RWN EXM DSEL EROM ERAMHI
AB[15:0]
DB[15:0] I/O
VEC[3:0] OR IOBIT[7:4]
DO2 OR PSEL1
OLD2 OR PODS
OCK2 OR PSEL2
OBE2 OR POBE
SYNC2 OR PSEL0
ICK2 OR PB0
ILD2 OR PIDS
DI2 OR PB1
IBF2 OR PIBF
DOEN2 OR PB2
SADD2 OR PB3
IOBIT[3:0] OR PB[7:4]
CKI
CKI2
CKO
RSTB
STOP
TRAP
INT[1:0]
IACK
DI1
ICK1
ILD1
IBF1
DO1
OCK1
OLD1
OBE1
SYNC1
SADD1
DOEN1
EXTERNAL MEMORY INTERFACE & EMUX
ioc
RAM[3:1]
3K x 16
RAM4
1K x 16
ERAMLO
YAB YDB XDB XAB BMU
aa0
aa1
ar0
ar1
ar2
ar3
IDB
PHIF
phifc
PSTAT
pdx0(IN)
pdx0(OUT)
BIO
sbit
cbit
SIO2
sdx2(OUT)
srta2
tdms2
sdx2(IN)
sioc2
saddx2
SIO1
sdx(OUT)
srta
tdms
sdx(IN)
sioc
saddx
TIMER
timerc
timer0
HDS
BREAKPOINT
JTAG
BOUNDARY-SCAN
jtag
JCON
ID
BYPASS
TRACE
powerc
DUAL-PORT
ROM
16K x 16
ECCP
eir
ear
edr
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December 2001 Hardware Architecture
Agere Systems Inc.
DRAFT COPY
2-7
2.1 Device Architecture Overview
(continued)
2.1.3 Device Architecture
(continued)
These registers are accessible through external pins only.
DSP1627x32 contains 32K x 16 internal ROM.
5-4142.d
Figure 2-6. DSP1627 Block Diagram
TDO
TCK
TMS
M
U
X
DSP1600 CORE
RWN EXM EROM ERAMHI
AB[15:0]
DB[15:0] I/O
VEC[3:0] OR IOBIT[7:4]
DO2 OR PSEL1
OLD2 OR PODS
OCK2 OR PSEL2
OBE2 OR POBE
SYNC2 OR PSEL0
ICK2 OR PB0
ILD2 OR PIDS
DI2 OR PB1
IBF2 OR PIBF
DOEN2 OR PB2
SADD2 OR PB3
IOBIT[3:0] OR PB[7:4]
CKI
CKI2
CKO
RSTB
STOP
TRAP
INT[1:0]
IACK
DI1
ICK1
ILD1
IBF1
DO1
OCK1
OLD1
OBE1
SYNC1
SADD1
DOEN1
EXTERNAL MEMORY INTERFACE & EMUX
ioc
DUAL-PORT
RAM
6K x 16
ROM
36K x 16
ERAMLO
YAB YDB
XDB XAB BMU
aa0
aa1
ar0
ar1
ar2
ar3
IDB
PHIF
phifc
PSTAT
pdx0(IN)
pdx0(OUT)
BIO
sbit
cbit
SIO2
sdx2(OUT)
srta2
tdms2
sdx2(IN)
sioc2
saddx2
SIO1
sdx(OUT)
srta
tdms
sdx(IN)
sioc
saddx
TIMER
timerc
timer0
HDS
BREAKPOINT
JTAG
BOUNDARY-SCAN
jtag
JCON
ID
BYPASS
TRACE
powerc
TDI
CLOCK
SYNTHESIZER
pllc
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Hardware Architecture December 2001
2-8
DRAFT COPY
Agere Systems Inc.
2.1 Device Architecture Overview
(continued)
2.1.3 Device Architecture (continued)
These registers are accessible through external pins only.
DSP1628x16 contains a total of 16K x 16 internal RAM, and DSP1628x08 contains a total of 8K x 16 internal RAM.
Figure 2-7. DSP1628 Block Diagram
TDO
TDI
TCK
TMS
M
U
X
DSP1600 CORE
RWN EXM DSEL EROM ERAMHI
AB[15:0]
DB[15:0] I/O
VEC[3:0] OR IOBIT[7:4]
DO2 OR PSTAT
OLD2 OR PODS
OCK2 OR PCSN
OBE2 OR POBE
SYNC2 OR PBSEL
ICK2 OR PB0
ILD2 OR PIDS
DI2 OR PB1
IBF2 OR PIBF
DOEN2 OR PB2
SADD2 OR PB3
IOBIT[3:0] OR PB[7:4]
CKI
CKI2
CKO
RSTB
STOP
TRAP
INT[1:0]
IACK
DI1
ICK1
ILD1
IBF1
DO1
OCK1
OLD1
OBE1
SYNC1
SADD1
DOEN1
EXTERNAL MEMORY INTERFACE & EMUX
ioc
RAM4
1K x 16
ERAMLO
XAB XDB YAB YDB BMU
aa0
aa1
ar0
ar1
ar2
ar3
IDB
PHIF
phifc
PSTAT
pdx0(IN)
pdx0(OUT)
BIO
sbit
cbit
SIO2
sdx2(OUT)
srta2
tdms2
sdx2(IN)
sioc2
saddx2
SIO1
sdx(OUT)
srta
tdms
sdx(IN)
sioc
saddx
TIMER
timerc
timer0
HDS
BREAKPOINT
JTAG
BOUNDARY-SCAN
jtag
JCON
ID
BYPASS
TRACE
powerc
DUAL-PORT
ROM
48K x 16
ECCP
eir
ear
edr
RAM
15/7K x 16
TRST
CLOCK
SYNTHESIZER
pllc
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Hardware Architecture
Agere Systems Inc.
DRAFT COPY
2-9
2.1 Device Architecture Overview
(continued)
2.1.3 Device Architecture (continued)
These registers are accessible through external pins only.
DSP1629x16 contains 16K x 16 internal RAM, and DSP1629x10 contains 16K x 10 internal RAM.
Figure 2-8. DSP1629 Block Diagram
TDO
TCK
TMS
M
U
X
DSP1600 CORE
RWN EXM EROM ERAMHI
AB[15:0]
DB[15:0] I/O
VEC[3:0] OR IOBIT[7:4]
DO2 OR PSTAT
OLD2 OR PODS
OCK2 OR PCSN
OBE2 OR POBE
SYNC2 OR PBSEL
ICK2 OR PB0
ILD2 OR PIDS
DI2 OR PB1
IBF2 OR PIBF
DOEN2 OR PB2
SADD2 OR PB3
IOBIT[3:0] OR PB[7:4]
CKI
CKI2
CKO
RSTB
STOP
TRAP
INT[1:0]
IACK
DI1
ICK1
ILD1
IBF1
DO1
OCK1
OLD1
OBE1
SYNC1
SADD1
DOEN1
EXTERNAL MEMORY INTERFACE & EMUX
ioc
DUAL-PORT
RAM
16K/10K x 16
ROM
48K x 16
ERAMLO
YAB YDB
XDB XAB BMU
aa0
aa1
ar0
ar1
ar2
ar3
IDB
PHIF
phifc
PSTAT
pdx0(IN)
pdx0(OUT)
BIO
sbit
cbit
SIO2
sdx2(OUT)
srta2
tdms2
sdx2(IN)
sioc2
saddx2
SIO1
sdx(OUT)
srta
tdms
sdx(IN)
sioc
saddx
TIMER
timerc
timer0
HDS
BREAKPOINT
JTAG
BOUNDARY-SCAN
jtag
JCON
ID
BYPASS
TRACE
powerc
TDI
CLOCK
SYNTHESIZER
pllc
TRST
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Hardware Architecture December 2001
2-10
DRAFT COPY
Agere Systems Inc.
2.1 Device Architecture Overview
(continued)
2.1.3 Device Architecture (continued)
Table 2-2. Symbols Used in the Block Diagrams
Symbol Name/Description
aa0--aa1 Alternate Accumulators
ar0--ar3 Auxiliary BMU Registers
BIO Bit Input/Output Unit
BMU Bit Manipulation Unit
BREAKPOINT Four Instruction Breakpoint Registers
BYPASS JTAG Bypass Register
cbit Control Register for BIO
ECCP Error Correction Coprocessor (DSP1618 and DSP1628 only)
ear ECCP Address Register (DSP1618 and DSP1628 only)
edr ECCP Data Register (DSP1618 and DSP1628 only)
eir ECCP Instruction Register (DSP1618 and DSP1628 only)
EMUX External Memory Multiplexor
HDS Hardware Development System
ID JTAG Device Identification Register
IDB Internal Data Bus
ioc I/O Configuration Register
JCON JTAG Configuration Register
JTAG Standardized Test Port Defined in
IEEE P1149.1
jtag 16-bit Serial/Parallel Register
pdx0--pdx7(IN) Parallel I/O Data Transmit Input Registers <0--7>
pdx0--pdx7(OUT)
Parallel I/O Data Transmit Output Registers <0--7>
PHIF Parallel Host Interface (DSP1611/18/27/28/29 only)
phifc Parallel Host Interface Control Register (DSP1611/18/27/28/29 only)
pllc Phase-lock Loop Control Register (DSP1627/28/29 only)
PIO Parallel Input/Output Unit (DSP1617 only)
pioc Parallel I/O Control Register (DSP1617 only)
powerc Power Control Register
PSTAT Parallel I/O Status Register
ROM Internal ROM (1 Kword for DSP1611, 24 Kwords for DSP1617, 16 Kwords
for DSP1618, 24 Kwords for DSP1618x24, 36 Kwords for DSP1627,
32 Kwords for DSP1627x32, 48 Kwords for DSP1628 and DSP1629)
saddx Multiprocessor Protocol Register
sbit Status Register for BIO
sdx(IN) Serial Data Transmit Input Register
sdx2(IN) Serial Data Transmit Input Register for SIO2
sdx(OUT) Serial Data Transmit Output Register
sdx2(OUT) Serial Data Transmit Output Register for SIO2
SIO1 Serial Input/Output Unit #1
SIO2 Serial Input/Output Unit #2
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Hardware Architecture
Agere Systems Inc.
DRAFT COPY
2-11
2.1 Device Architecture Overview
(continued)
2.1.3 Device Architecture (continued)
sioc Serial I/O Control Register
sioc2 Serial I/O Control Register for SIO2
srta<1, 2> Serial Receive/Transmit Address Registers
tdms<1, 2> Serial I/O Time-division Multiplex Signal Control Registers
TIMER Programmable Timer
timer0 Time Running Count Register
timerc Timer Control Register
TRACE Program Discontinuity
XAB Program Space Address Bus
XDB Program Space Data Bus
YAB Data Space Address Bus
YDB Data Space Data Bus
DUAL-PORT RAM Internal dual-port RAM (12 Kwords for DSP1611, 4 Kwords for DSP1617
and DSP1618, 6 Kwords for DSP1627, 8 Kwords for DSP1628x08,
16 Kwords for DSP1628x16, 10 Kwords for DSP1629x10, and 16 Kwords
for DSP1629x16)
Table 2-2. Symbols Used in the Block Diagrams (continued)
Symbol Name/Description
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Hardware Architecture December 2001
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DRAFT COPY
Agere Systems Inc.
2.1 Device Architecture Overview
(continued)
2.1.4 Memory Space and Bank Switching
Table 2-3 describes the two memory spaces.
There are two memory spaces with separate addressing units, address buses, and data buses. The actual memo-
ries associated with the spaces are enabled automatically based on the address. For the data memory space,
either internal dual-port RAM or external memory is used. The external memory is divided into three segments.
The internal dual-port RAM is divided into multiple 1K word banks for DSP1611/17/18/27/28/29. For the program
memory space, either internal ROM, internal dual-port RAM, or external ROM can be addressed. There are
2
16
= 65,536 addresses in each of the two memory spaces; the total address space for each is divided into seg-
ments, and each segment is associated with a physical memory. The arrangement of the segments is called the
memory map. There is one map for the data memory space, and there are four possible memory maps for the pro-
gram space. Memory maps are discussed in Section 3.2, Memory Space and Addressing and Section 6.1, EMI
Function.
x = 4 for DSP1617 and DSP1618.
x = 6 for DSP1627.
x = 8 for DSP1628x08.
x = 10 for DSP1629x10.
x = 12 for DSP1611.
x = 16 for DSP1628x16 and DSP1629x16.
Table 2-3. Memory Space
Terminology Address
Source
Address
Bus
Memory Segments
Accessed
Data Bus
Data (Y) memory space (see
Section 3.2.1).
YAAU YAB RAM[1:x]
YDB
IO
ERAMLO
ERAMHI
Program or instruction/coefficient (X)
memory space (see Section 3.2.2).
XAAU XAB [RAM1:x]
XDB
IROM
EROM
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December 2001 Hardware Architecture
Agere Systems Inc.
DRAFT COPY
2-13
2.1 Device Architecture Overview
(continued)
2.1.4 Memory Space and Bank Switching (continued)
The internal dual-port RAM can be accessed in both the Y space and the X space. This RAM is arranged in multi-
ple 1 Kword banks; and as long as the banks accessed are different, simultaneous data and instruction accesses
can be made. If the same bank is accessed from both memory spaces simultaneously, an extra instruction cycle
(one wait-state) is automatically initiated to carry out the transfer. The data transfer is performed first.
It is important to note that the selection of physical memory within a memory space is automatic because it only
depends on choice of address, and no extra time is involved to switch banks except in the case of accessing the
same bank of internal RAM just described.
2.1.5 Internal Instruction Pipeline
The internal pipeline of fetch, decode, and execute is hidden from the user. The latencies involved are automati-
cally controlled without external intervention. The following is provided for information only. The relevant hardware
is shown in Figure 2-9.
5-4143
Figure 2-9. Hardware Block Diagram for Internal Pipeline
CONTROL
RAM
DAU
YAAU
INSTRUCTIONS
PC
XAB
YAB
YDB
XDB
XAAU
X SPACE MEM.
DAU
DECODE
AAU
DECODE
16
16
16
16
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Hardware Architecture December 2001
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DRAFT COPY
Agere Systems Inc.
2.1 Device Architecture Overview
(continued)
2.1.5 Internal Instruction Pipeline (continued)
Table 2-4 illustrates the internal pipeline for single-cycle instructions such as a multiply-ALU instruction involving a
read from RAM to the DAU. Each instruction cycle corresponds to one cycle of the non-wait-stated CKO. The
instructions shown on the XAB bus will appear one phase (1/2 an instruction cycle) later on the external memory
address bus.
The following describes the actions associated with each of the steps shown in bold in Table 2-4.
Table 2-4. Single-Cycle Instruction Internal Pipeline
Instruction
Cycle
CKO
Level
XAB XDB AAU
DECODE
DAU
DECODE
YAB YDB
1
1
xaddr
1
instr
0
-- instr
1
yaddr
1
--
1 0 -- -- instr
0
instr
1
-- data
2
2 1 xaddr
2
instr
1
-- instr
0
yaddr
0
--
2
0
--
--
instr
1
instr
0
-- data
1
3 1 xaddr
3
instr
2
-- instr
1
yaddr
1
--
3 0 -- -- instr
2
instr
1
-- data
0
4 1 xaddr
4
instr
3
-- instr
2
yaddr
2
--
4 0 -- -- instr
3
instr
2
-- data
1
Instruction
Cycle
CKO
Level
Process Description
1 1 The program counter (PC) places xaddr
1
on the address bus XAB to program memory
(X space memory).
1 0 The program memory is accessed.
2 1 The program memory responds by placing instr
1
on the instruction data bus (XDB).
2 0 The AAU decoder decodes the instruction and sets up the YAAU to address the RAM.
3 1 The YAAU places yaddr
1
on the address bus YAB to the RAM. Also, the DAU
decoder decodes instr
1
.
3 0 The decoders direct a RAM read of data
1
to the DAU.
4 1 The RAM is being accessed.
4 0 The RAM places the data on the YDB, and it is loaded into the DAU.
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Hardware Architecture
Agere Systems Inc.
DRAFT COPY
2-15
2.1 Device Architecture Overview
(continued)
2.1.5 Internal Instruction Pipeline (continued)
Table 2-5 illustrates the internal pipeline for a two-cycle fetch from X-memory space by using the pt register and a
concurrent compound read/write of the Y-memory space by using the multiply/ALU instruction: Z : y x = *pt++.
The following describes the actions associated with each of the steps shown in bold in Table 2-5.
Table 2-5. Two-Cycle Fetch Internal Pipeline
Instruction
Cycle
CKO
Level
XAB XDB AAU
DECODE
DAU
DECODE
YAB YDB
1
1
xaddr
1
instr
0
-- instr
1
yaddr
1
--
1 0 -- -- instr
0
instr
1
-- data
2
2 1 xaddr
2
instr
1
-- instr
0
yaddr
0
--
2
0
--
--
instr
1
instr
0
-- data
1
3
1
ptaddr instr
2
-- instr
1
yaddr
1r
--
3
0
--
--
instr
1
instr
1
-- data0
4 1 xaddr
3
coeff -- instr
1
yaddr
1w
data
1w
4 0 -- -- instr
2
instr
1
-- data
1r
5 1 xaddr
4
instr
3
-- instr
2
yaddr
2
--
Instruction
Cycle
CKO
Level
Process Description
1 1 The program counter (PC) places xaddr
1
on the address bus XAB to program memory
(X space memory).
1 0 The program memory is accessed.
2 1 The program memory responds by placing instr
1
on the instruction data bus (XDB).
2 0 The AAU decoder decodes the instruction, and sets up the YAAU to address the RAM
and the XAAU to place the contents of the pt register on the XAB. The control section
recognizes a two-cycle instruction.
3 1 The YAAU places yaddr
1r
on the address bus YAB to the RAM. Also, the DAU
decoder decodes instr
1
. The contents of the pt register (ptaddr) are placed on the
XAB.
3 0 The decoder directs a RAM read of data
1r
to the DAU. The RAM is accessed.
4 1 The data, coeff, from the X memory is transferred to the x register. The data
1w
is
transferred to the RAM from the y register.
4 0 The data
1r
is transferred from the RAM to the y register. The RAM is written with
data
1w
.
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DRAFT COPY
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2.2 Core Architecture Overview
2.2.1 Data Arithmetic Unit
The data arithmetic unit (DAU) is the main execution unit for signal processing algorithms. The DAU consists of a
16-bit by 16-bit multiplier, a 36-bit ALU, and two 36-bit accumulators: a0 and a1. The DAU performs two's comple-
ment, fixed-point arithmetic and is usable as a multiply/accumulate or ALU structure. The DAU multiplier and adder
operate in parallel requiring, together, one instruction cycle for their execution. Microprocessor-like instructions are
executed by the ALU.
5-1741.a
Figure 2-10. DSP1600 Core Functions
psw (16)
auc (16)
CONTROL
CACHE
cloop (7)
inc (16)
ins (16)
alf (16)
mwait (16)
SYS
XDB
XAB
IDB
YAB
YDB
r0 (16)
r1 (16)
r2 (16)
r3 (16)
j (16)
k (16)
re (16)
YAAU
rb (16)
ADDER
MUX
CMP
ybase (16)
pc (16)
pt (16)
pi (16)
i (16)
ADDER
XAAU
EXTRACT/SAT
x (16)
yh (16) yl (16)
16 x 16 MPY
p (32)
SHIFT (2, 0, 1, 2)
c0 (8)
c2 (8)
c1 (8)
16
ALU/SHIFT
a0 (36)
a1 (36)
36
32
MUX
DAU
MUX
1, 0, 1, 2
BRIDGE
MUX
1
pr (16)
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Hardware Architecture
Agere Systems Inc.
DRAFT COPY
2-17
2.2 Core Architecture Overview
(continued)
2.2.1 Data Arithmetic Unit (continued)
The multiplier executes a 16-bit by 16-bit multiply and stores the 32-bit product in the product register (p) in one
instruction cycle. Data for the multiplier's inputs comes from the 16-bit x register and the upper 16 bits (high half) of
the 32-bit y register.
For multiply/ALU instructions, the x register can be loaded with coefficients from X-memory space or data from Y-
memory space. The high half of the y register can be loaded from Y-memory space or the high or low half of an
accumulator. If the single-cycle square mode is set in the auc register, an instruction that loads the y register also
loads the x register with the same data. A multiply instruction then performs a squaring function.
x, y, yl, p, pl, a0, a0l, a1, and a1l are also included in the general set of registers used for data move instructions.
If the 32-bit registers are used in 16-bit instructions, the l suffix identifies the low half of the register and no suffix
identifies the upper half. For example, a0 means bits 31--16 of a0 and a0l means bits 15--0.
In addition to being used as an adder in the multiply/accumulate instructions, the 36-bit ALU provides the capability
to implement functions and algorithms in the DSP1611/17/18/27/28/29 device that conventionally are executed in a
microcomputer or a microprocessor. Operands to the ALU can be data in y, p, a0, or a1, or they can be immedi-
ates. The ALU sign-extends 32-bit operands from y or p to 36 bits, and it produces a 36-bit output (32 data bits
and 4 guard bits) in one instruction cycle. Either accumulator can receive the 36-bit result. The ALU supports
dyadic (two-operand) functions including addition, subtraction, and logical AND, OR, and XOR. It also supports
monadic (single-operand) functions including rounding, two's complement negation, incrementing, and left and
right shifts of 1, 4, 8, or 16 bits. More general shifting is available with the bit manipulation unit (see Section 2.5, Bit
Manipulation Unit (BMU)).
The auc (arithmetic unit control) register has five functions. It selects or deselects clearing of the lower 16-bit word
of the y register and accumulators when the upper word is written. It selects or deselects saturation on overflow for
the accumulators. It selects one of four alignments of data in the p register. It controls whether the pseudorandom
sequence generator is reset if the pi register is written (see Section 5.1.6, DAU Pseudorandom Sequence Genera-
tor (PSG)). It selects the single-cycle squaring mode (See Section 5.1.2, Multiplier Functions). The auc register is
reset to all zeros at chip reset. The psw (processor status word) register contains flags from ALU operations and
provides access to the guard bits in the accumulators. The c<0--2> counters are 8 (signed) bits wide and can be
used to count events such as the number of times the program has executed a sequence of code. They are con-
trolled by the conditional instructions and provide a convenient method of program looping.
2.2.2 Y Space Address Arithmetic Unit (YAAU)
The YAAU supports high-speed, register-indirect data memory addressing with postmodification of the address
register. Four general-purpose 16-bit registers r<0--3> store read or write addresses for on-chip or off-chip RAM.
Two 16-bit registers rb and re allow zero-overhead modulo addressing of data for efficient filter implementations.
Two signed registers j and k are used to hold user-defined postincrements. Fixed increments of +1, 1, and +2 are
also available, but the +2 increment is only available with compound addressing. Four compound-addressing
modes are provided to make read/write operations more efficient.
The YAAU allows direct addressing of data memory. During direct addressing, the base register (ybase) stores the
11 most significant bits of the address. The direct address instruction contains 5 bits that are concatenated with
the 11 bits in ybase to form a complete 16-bit address. The instruction also specifies one register (DR) of 16 pos-
sible registers. A data move then takes place between the memory location specified by the 16-bit address and the
register selected by the DR field.
The YAAU decodes the 16-bit data memory address and provides individual enables for each 1 Kword bank of on-
chip dual-port RAM and three external data memory segments (ERAMHI, ERAMLO, and IO). One individual
address in the IO memory segment also has an individually decoded output DSEL
1
facilitating glueless memory-
mapped I/O.
1. Not available in the DSP1627/28/29.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
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DRAFT COPY
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2.2 Core Architecture Overview
(continued)
2.2.3 X Space Address Arithmetic Unit (XAAU)
The XAAU contains registers and an adder that control the sequencing of instructions in the processor. The pro-
gram counter (PC) automatically increments through the instruction space and specifies addresses for instruction
fetches. The interrupt return register (pi) and the subroutine return register (pr) are automatically loaded with
return addresses that direct the return to main program execution from interrupt service routines and subroutines.
High-speed, register-indirect instruction/coefficient memory addressing with postincrementing is done by using the
pt register. The signed register i is used to hold a user-defined postincrement, or a fixed postincrement of +1 is
available.
The XAAU of the DSP1600 decodes the 16-bit instruction/coefficient address and produces enable signals for the
appropriate X-memory segment. The possible X segments are internal ROM, each 1 Kword bank of dual-port
RAM, and external ROM. The locations of these memory segments depend on which of the four memory maps is
selected (see Section 3.2, Memory Space and Addressing).
A core security mode can be selected by mask option
1
. This prevents reading out the contents of on-chip memo-
ries from off-chip.
2.2.4 Cache
Under user control, the on-chip cache memory can store instructions for repetitive operations to increase the
throughput and the coding efficiency of the device. The cache can store up to 15 instructions at a time and can
repeatedly cycle through those instructions up to 127 times without using user defined loop, test, and conditional
branch instructions. The set of instructions is executed as it is loaded into the cache, so zero-overhead looping is
achieved. The cache iterative count can be specified either as an immediate value at assembly time or can be
determined by the use of the cloop register. Instructions previously stored in the cache can be re-executed without
reloading the cache.
Note: Instructions in a cache loop are noninterruptible.
Cache instructions eliminate the overhead if repeating a block of instructions. Therefore, the cache reduces the
need to implement in-line coding in order to maximize the throughput. A routine using the cache uses fewer ROM
locations than an in-line coding of the same routine.
For two-operand multiply/arithmetic logic unit (ALU) instructions that do not require a write to memory, executing
from the cache decreases the execution time from two instruction cycles to one instruction cycle resulting in an
increase in throughput.
2.2.5 Control
The control block provides overall DSP1611/17/18/27/28/29 system coordination. Inputs are provided to the con-
trol block over the program data bus (XDB). The instructions are decoded by hardware in the control block. The
execution of the phases of an instruction is controlled by hardware throughout the DSP1611/17/18/27/28/29
device. The hardware sequences instructions through the pipeline and controls the I/O, the processing, the mem-
ory accesses, and the timing necessary to perform each operation.
1. The internal ROM memory of the DSP1611 is only available with a standard boot routine. DSP1611 devices do not offer the secure mask
option.
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Hardware Architecture
Agere Systems Inc.
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2-19
2.3 Internal Memories
All memory (internal and external) is 16 bits wide. The DSP1611 ROM contains 1K words and is preprogrammed
with a variety of boot routines that make it easy for systems to download programs and data to the DSP1611's
large internal RAM space. The DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629 all feature large, mask-
programmable internal ROM memories that can be encoded with programs, fixed data, or both. The DSP1617
ROM contains 24 Kwords, the DSP1618 ROM contains 16 Kwords, the DSP1618x24 ROM contains 24 Kwords,
the DSP1627 ROM contains 36 Kwords, the DSP1627x32 ROM contains 32 Kwords, the DSP1628 contains
48 Kwords, and the DSP1629 contains 48 Kwords. The internal ROM of the code to support the hardware devel-
opment system is included in ROMless devices supplied by Agere Systems and should be included in cus-
tomer-created ROM programs.
The internal dual-port RAM contains multiple banks of zero-wait-state memory. Each bank consists of 1K of 16-bit
words and has separate ports to the instruction/coefficient buses and data buses. A program can reference the
memory from either port at any time transparently and without restriction. The DSP1600 core automatically per-
forms the multiplexing. In the event that references to both ports of a single bank are made simultaneously, the
DSP1600 core automatically performs the data port access and then inserts a wait-state followed by the instruc-
tion/coefficient port access.
A program can be downloaded from slow off-chip memory into the dual-port RAM and then executed with-
out wait-states
. Dual-port RAM is also useful for improving the performance of convolution in cases where the
coefficients are adaptive. Full-speed, remote, in-circuit emulation is possible because the dual-port RAM can be
downloaded through the JTAG port. This download capability is also useful for self-test.
2.4 External Memory Interface (EMI)
The DSP1611/17/18/27/28/29 provides a 16-bit external address bus (AB[15:0]) and a 16-bit, external, bidirectional
data bus (DB[15:0]). These buses are multiplexed between the internal instruction/coefficient memory buses (X
space) and the data memory buses (Y space). The multiplexing is automatically controlled by the core that deter-
mines the memory space to be accessed from the instruction, the memory map, and the address.
Because only Y space or X space can be accessed at one time through the EMI, a sequencer automatically han-
dles the case when a program calls for simultaneous access of X space and Y space. For example, if a program is
being executed from external ROM and an instruction calls for a read from external RAM, the sequencer first
accesses the X space external ROM and then reads the data from external RAM. One extra instruction cycle is
required, in addition to any external wait-states that are present if external memory is used, compared to internal
operation.
Four external memory enables (ERAMLO, IO, ERAMHI, and EROM) are outputs that control the selection of exter-
nal memory segments. One of the IO addresses is individually decoded to provide an enable (DSEL
1
) for memory-
mapped I/O peripherals.
Each of the five enables can be programmed individually to delay their assertion one-half of a free-running CKO
period from the beginning of the external cycle. This allows a mix of high- and low-speed devices without bus con-
flicts or expensive glue logic. The DSEL
1
enable is normally active-low, but it can be programmed to be active-
high. The ERAMLO, ERAMHI, EROM, and IO signals are active-low.
Each of the memory segments can have a different number of wait-states associated with it where a wait-state is
an extra instruction cycle inserted in the read or write cycle to allow for slower memories. The number of wait-
states is programmable from 0 to 15 by setting bits in the mwait register.
1. Not available in the DSP1627/28/29.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Hardware Architecture December 2001
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Agere Systems Inc.
2.4 External Memory Interface (EMI)
(continued)
The DSP1611/17/18/27/28/29 allows writing to external program (X) memory. Bit 11 (WEROM) and bit 14
(EXTROM) of the ioc register enable the DSP to write the external X-memory space, which is normally read-only.
If WEROM is set high, a write to or read from ERAMLO, IO, or ERAMHI memory space asserts the EROM strobe
instead of the ERAM or IO strobes, thereby allowing access to X memory. If the EXTROM bit is set in conjunction
with the WEROM bit, an entire 64K of EROM can be accessed. This feature is used by the hardware development
software, and it can be used in system applications to download a program into the external program memory
space.
If external data (Y) memory is written, the RWN signal goes low for an external cycle. The CKO output pin can pro-
vide a reference for external I/O timing. Either a free-running CKO or a wait-stated CKO can be selected. The flex-
ibility provided by the programmable options of the external memory interface allows the DSP1611/17/18/27/28/29
to interface gluelessly with a variety of commercial memory chips. A full description of the EMI is found in
Chapter 6, External Memory Interface.
2.5 Bit Manipulation Unit (BMU)
The BMU adds extensions to the DSP1600 core instruction set that execute in one or two cycles for more efficient
bit operations on accumulators. The BMU contains logic for barrel shifting, normalization, and bit-field insertion or
extraction. The unit also contains a set of 36-bit alternate accumulators that can be shuffled with the working set.
Flags returned by the BMU mesh seamlessly with the conditional instructions. The BMU contains four 16-bit auxil-
iary registers ar<0--3> that contain input or output operands. The BMU is fully described in Chapter 13, Bit Manip-
ulation Unit.
The following barrel shift operations are available: arithmetic or logical shifts and left or right shifts. The shift
amount is from immediate data in the second word of the instruction, from data in ar<0--3>, or from data in an
accumulator. The normalization function is done on the accumulators by finding the exponent that is the number
of redundant sign bits of a two's complement number. The calculated exponent is placed in one of the ar
registers. The original accumulator value is shifted or normalized with respect to bit 31. In bit extraction, a contigu-
ous field of bits is moved from the source accumulator to the lowest-order bits of the destination accumulator. In bit
insertion, a contiguous field of bits in the lowest-order position of the source accumulator replaces bits at an offset
position in the destination accumulator. The other bits in the destination accumulator are filled from the corre-
sponding bits in the second source accumulator. The two alternate accumulators are used to shuffle data with one
or two working accumulators. With the shuffle instruction, data is moved from a source accumulator to an alternate
accumulator and the old data in the alternate accumulator is moved to a destination accumulator. Only one instruc-
tion cycle is required for swapping all 36 bits.
2.6 Serial Input/Output (SIO) Units
SIO1 and SIO2 are asynchronous, full-duplex, double-buffered channels that easily interface with other DSP16XX
1
devices in a multiple-processor environment. Commercially available codecs and time-division multiplex (TDM)
channels can be interfaced to the SIO with few, if any, additional components. The SIO units are fully described in
Chapter 7, Serial I/O.
An 8-bit serial protocol channel is also available in the multiprocessor mode. This feature uses the SADD pin and
saddx register to transmit an 8-bit software-definable field in addition to the address of the called processor. This
feature is useful for transmitting the source address of the data, high-level framing information, or bits for error
detection and correction.
1. XX denotes the last two digits of the device name, e.g., XX = 11 for the DSP1611.
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Hardware Architecture
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2.6 Serial Input/Output (SIO) Units
(continued)
The following are some of the features of the SIO units:
*
Strobes and clocks are either active or passive (driven by the DSP or from off-chip) to provide interface flexibility.
*
Four selectable active clock speeds allow a variety of throughput rates.
*
8- or 16-bit data is supported.
*
Input and output can be independently chosen to shift either MSB or LSB first.
*
Input and output are independently configured.
2.7 Parallel Input/Output (PIO) (DSP1617 Only)
The DSP1617 has an 8-bit parallel I/O interface for rapid transfer of data with external devices such as other DSPs,
microprocessors, or peripheral I/O devices. Minimal or no additional logic is required to interface with peripheral
devices, and data rates of up to 20 Mbytes/s are obtained at an instruction cycle of 25 ns. Two maskable interrupts
are associated with the PIO unit. Although there is only one physical PIO port, there are eight logical PIO ports
pdx<0--7>. One of the eight logical ports is signaled by the state of the peripheral select pins (PSEL[2:0]). The
PIO is fully described in Chapter 8, Parallel I/O (DSP1617 Only).
The data path of the PIO contains the 8-bit input buffer pdxin and the 8-bit output buffer pdxout. In passive mode,
there are two pins that indicate the state of these buffers: the parallel input buffer full (PIBF) and the parallel output
buffer empty (POBE). The pdxin register is shadowed in some modes to allow the PIO to accept data on an inter-
rupt without disrupting its normal operation. In addition, there are two registers used to control and monitor the
PIO's operation: the parallel I/O control (pioc) register and the PIO status (PSTAT) register. The PSTAT register
can only be read by an external device, and it reflects the condition of the PIO. The pioc contains information
about interrupts and can be used to set the PIO in a variety of modes. Strobe widths are programmable through
the strobe field in the pioc. The PIO is accessed in two basic modes, active or passive. Input or output can be
configured in either of these modes independently. In active mode, the DSP is in control and provides the strobes.
In passive mode, the external device provides the strobes.
2.8 Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only)
The PHIF is a passive 8-bit parallel port that can interface to an 8-bit bus containing other Agere DSPs, micropro-
cessors, or peripheral I/O devices. The PHIF port supports
Motorola
or
Intel
protocols and 8- or 16-bit transfers
configured in software. The port data rate depends on the instruction cycle rate. A 25 ns instruction cycle allows
the PHIF to support data rates up to 16 Mbytes/s assuming the external host device can transfer 1 byte of data in
25 ns.
The PHIF is accessed in two basic modes, 8- and 16-bit modes. In 16-bit mode, the host determines an access of
the high or low byte. In 8-bit mode, only the low byte is accessed. Software-programmable features provide a
glueless host interface to microprocessors. The PHIF is fully described in Chapter 9, Parallel Host Interface (PHIF)
(DSP1611/18/27/28/29 Only).
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
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Agere Systems Inc.
2.9 Bit Input/Output (BIO)
The BIO provides convenient and efficient monitor and control of eight individually configurable pins. A control reg-
ister individually controls the directions of eight bidirectional control I/O pins (IOBIT[7:0]). If a pin is configured as
an output, it can be individually set, cleared, or toggled. If a pin is configured as an input, it can be read, tested, or
both. Flags returned by the BIO mesh seamlessly with the DSP1600 conditional instructions. The sbit and cbit
registers are used to configure the BIO and transfer data to or from the DSP. The BIO pins are multiplexed with
other device pins and are selected in the ioc register. The BIO is fully described in Chapter 10, Bit I/O Unit.
2.10 JTAG
The DSP1611/17/18/27/28/29 incorporates extensive logic for a standard 4-pin test access port defined by the
IEEE P1149.1 standard known as JTAG. The test port fully conforms to the standard's requirements and is further
augmented by a number of custom features for self-test and on-chip emulation. The JTAG block contains instruc-
tion registers, data registers, and control logic and has its own set of instructions. It is controlled externally by a
JTAG bus master. The 4-pin port is designed to provide board-level test capability in which all of the chips on a
board would be connected in a serial path with test access to each chip. The following capabilities are provided by
the JTAG block:
1. A set of instructions can be downloaded through the JTAG port into the DSP dual-port RAM and executed pro-
viding self-test capability. The results of a block of tests can be read out by scanning one of the data registers in
the JTAG.
2. Boundary-scan can be done. All of the chip pins can be configured into a serial shift register that can be read or
written serially through the JTAG. If data is serially shifted into the JTAG scan register, it can be used to replace
the real chip inputs and outputs. Alternatively, the real chip data on the pins can be parallel-loaded into the scan
register and shifted out.
3. The JTAG can be used to access and control the on-chip hardware development system.
The JTAG block is fully described in Chapter 11, JTAG Test Access Port.
2.11 Timer
The timer can interrupt after a programmed interval or can provide repetitive interrupts at a programmed interval. It
provides more than nine orders of magnitude in the range interval selection.
The interrupt timer is composed of these blocks: the prescaler, the timer itself, the timer control register, the timer0
register, and the period holding register.
The prescaler divides the free-running CKO clock by one of 16 possible divisors from 2 to 65,536. This will provide
a wide range of interrupt delay periods depending on the device instruction cycle and clock divisor chosen.
The timer is a 16-bit down counter that can be loaded with an arbitrary number from software. It then counts down
to 0 at the clock rate provided by the prescaler. Upon reaching 0 count, an interrupt is issued to the DSP through a
vectored interrupt (bit 8 of inc and ins registers). At the discretion of the user, the timer will then either wait in a
quiescent state for another command from software or will automatically repeat the last interrupting period.
The timer control register (timerc) contains three fields affecting the timer. The RELOAD bit determines if the inter-
rupt cycle will be repeated or if it is just a one-time event. The TOEN bit enables the clock to the timer so that it
either counts or holds the old value. The PRESCALE field holds the value for the prescaler.
The timer0 register provides the interface for reading or writing the timer. A write to timer0 is used to set an initial
value in the timer and in the period holding register. The value in the timer can be read on-the-fly by a data move
from timer0. The value written to timer0 is also stored in the period register and held as the count that the timer
will return to if in the repeating mode.
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Hardware Architecture
Agere Systems Inc.
DRAFT COPY
2-23
2.11 Timer
(continued)
The timer interrupt can be individually enabled or disabled through the inc register. The timer can be stopped and
started by software and can be reloaded with a new delay at any time. The timer is fully described in Chapter 12,
Timer.
2.12 Hardware Development System (HDS) Module
The on-chip HDS performs instruction breakpointing and branch tracing at full speed. Through the JTAG port,
breakpointing is set up and the trace history is read back remotely. The JTAG port works in conjunction with HDS
code in the on-chip ROM and software in a remote computer.
Four hardware breakpoints can be set on instruction addresses. A counter can be preset with the number of
breakpoints to be received before trapping the core. Breakpoints can be set in interrupt service routines. Alter-
nately, the counter can be preset with the number of cache instructions to execute before trapping the core.
Every time the program branches instead of executing the next sequential instruction, the pair of addresses from
before and after the branch are caught in circular memory. The memory contains the last four pairs of program dis-
continuities for hardware tracing.
A multiprocessor feature can be configured, so all processors are trapped if one processor gets a breakpoint.
The Hardware Development System (HDS) is described in the
DSP1600 Support Tools Manual and
DSP1611/17/18/27/28/29 supplements.
2.13 Clock Synthesis (DSP1627/28/29 Only)
The DSP1627/28/29 includes an on-chip clock synthesizer that can be used to generate the system clock for the
DSP. The clock will run at a programmable frequency multiple of the input clock (CKI). The 1X CKI input clock, the
output of the synthesizer, or a slow internal ring oscillator can be used as the source for the internal DSP clock.
On powerup, CKI is selected as the clock source for the DSP. Setting the appropriate bits in the pllc control regis-
ter will enable the clock synthesizer to become the clock source. The powerc register can override the selection to
stop clocks or force the use of the slow ring oscillator clock for low-power operation.
If not being used, the clock synthesizer can be powered down by clearing the PLLEN bit of the pllc register. Clock
synthesis is fully described in Section 3.5, Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only)
2.14 Power Management
Many applications, such as portable cellular terminals, require programmable sleep modes for power management.
There are three different control mechanisms for achieving low-power operation: the powerc control register, the
STOP pin, and the AWAIT bit in the alf register. The AWAIT bit in the alf register allows the processor to go into a
power-saving standby mode until an interrupt occurs. The powerc register configures various power-saving
modes by controlling internal clocks and peripheral I/O units. The STOP pin controls the internal processor clock.
The various power management options can be chosen based on power consumption, wake-up latency require-
ments, or both. Power management is fully described in Section 3.6, Power Management.
Chapter 3
Software Architecture
CHAPTER 3. SOFTWARE ARCHITECTURE
CONTENTS
3
Software Architecture ...........................................................................................................3-1
3.1
Register View of the DSP1611/17/18/27/28/29..........................................................3-1
3.1.1
Types of Registers ......................................................................................3-1
3.1.2
Register Length Definition ...........................................................................3-5
3.1.3
Register Reset Values .................................................................................3-6
3.1.4
Flags ............................................................................................................3-7
3.2
Memory Space and Addressing .................................................................................3-8
3.2.1
Y-Memory Space .........................................................................................3-8
3.2.2
X-Memory Space .......................................................................................3-10
3.3
Arithmetic and Precision...........................................................................................3-21
3.4
Interrupts ..................................................................................................................3-27
3.4.1
Introduction ................................................................................................3-27
3.4.2
Interrupt Sources .......................................................................................3-29
3.4.3
Outputs of Interrupts ..................................................................................3-31
3.4.4
Interrupt Operation ....................................................................................3-32
3.4.5
Trap Description ........................................................................................3-38
3.4.6
Powerdown with the AWAIT State ............................................................3-40
3.4.7
Interrupts in DSP16A-Compatible Mode (DSP1617 Only) ........................3-42
3.4.8
Timing Examples, DSP16A-Compatible Mode (DSP1617 Only) ..............3-44
3.5
Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only)...................................3-47
3.5.1
PLL Control Signals ...................................................................................3-48
3.5.2
PLL Programming Examples .....................................................................3-50
3.5.3
Latency ......................................................................................................3-50
3.6
Power Management .................................................................................................3-52
3.6.1
powerc
Control Register Bits ....................................................................3-52
3.6.2
STOP Pin ..................................................................................................3-56
3.6.3
The
pllc
Register Bits (DSP1627/28/29 Only) ..........................................3-56
3.6.4
AWAIT Bit of the
alf
Register ....................................................................3-56
3.6.5
Power Management Sequencing ..............................................................3-57
3.6.6
Power Management Examples .................................................................3-58
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Software Architecture
Agere Systems Inc.
DRAFT COPY
3-1
3 Software Architecture
This
chapter contains a variety of topics on the software and programming of the device. First, the registers and
their properties are listed in Section 3.1, Register View of the DSP1611/17/18/27/28/29. Next, the memory space
and addressing modes are described Section 3.2, Memory Space and Addressing. Then, the arithmetic and preci-
sion for calculations in the DAU are described in Section 3.3, Arithmetic and Precision. Section 3.4, Interrupts, dis-
cusses both the vectored interrupts and the DSP16A compatible interrupts. (The DSP16A compatible interrupts
are available on the DSP1617 only.) Section 3.5, Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only),
describes the DSP1627/28/29's phase-lock loop based clock synthesizer. And finally, the flexible power manage-
ment features are discussed in Section 3.6, Power Management.
3.1 Register View of the DSP1611/17/18/27/28/29
3.1.1 Types of Registers
Registers are either accessible by the program or through the DSP1611/17/18/27/28/29 pins. Accessible by pro-
gram means they can be selected in data move instructions. The program-accessible registers are denoted by
lower-case names; the pin-accessible registers are denoted by upper-case names. The registers are generally of
three types:
Data
--used for storing data that, in turn, become operands for the functional operators.
Control and status
--used for setting different configurations of the machine (control) or indicating the configura-
tion of the machine (status).
Addressing
--used for storing information that points to a memory location. In some cases, addressing registers
can be used as general-purpose data registers accessible by data move instructions.
A very important register not directly accessible to the programmer or through external pins is the PC (program
counter register). The machine automatically controls the PC to properly sequence the instructions.
Table 3-1 lists the general set of program-accessible registers sorted by function. Table 3-2 sorts them alphabeti-
cally and includes their type and location. Table 3-3 lists the pin-accessible registers. Figure 3-1 depicts the pro-
gram-accessible registers in a block diagram of the whole chip.
Table 3-1. Program-Accessible Registers by Function
Register Name Function
r0, r1, r2, r3, j, k, rb, re, ybase YAAU addressing
pt, pr, pi, i XAAU addressing
p, pl, x, y, yl, a0, a0l, a1, a1l, aa0, aa1 DAU data
auc, psw DAU control
c0, c1, c2 Counters
sdx, sdx2 SIO data
srta, srta2, tdms, tdms2, saddx, saddx2, sioc, sioc2 SIO control
pdx<0--7> (pdx0 only for DSP1611/18/27/28/29) PIO or PHIF data
phifc (DSP1611/18/27/28/29 only) PHIF control
pioc (DSP1617 only) PIO control
eir, ear, edr (DSP1618/28 only) ECCP instruction, address, and data registers
pllc (DSP1627/28/29 only) Control register for clock synthesizer
cbit, sbit BIO data and control
Note: Registers
sioc
,
sioc2
,
srta
,
srta2
,
tdms
, and
tdms2
are not readable. Alternate accumulators
aa0
and
aa1
are only acces-
sible with the BMU swap instruction.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Software Architecture December 2001
3-2
DRAFT COPY
Agere Systems Inc.
3.1 Register View of the DSP1611/17/18/27/28/29
(continued)
3.1.1 Types of Registers
(continued)
Notation for 32-bit registers: No suffix denotes the upper 16 bits; the
l
suffix denotes the lower 16 bits, e.g.,
a0
,
a0l
(see Section 3.1.2, Register Length Definition for more details).
ioc SIO, CKO, PIO, EMI control
timerc, timer0 Timer control and data
ar0, ar1, ar2, ar3 BMU data
inc, ins Interrupt control and status
cloop Cache control
mwait Wait-states control
jtag Test interface data (reserved)
powerc Power control
alf Standby mode, memory map, flag status
Table 3-2. Program-Accessible Registers by Type, Listed Alphabetically
Register Name Description Type Section
aa0, aa1 Alternate accumulators, 36-bit data BMU
a0, a0l, a1, a1l Accumulators 0 and 1, 36-bit data DAU
alf Await, lowpr, flags c & s Control
ar0, ar1, ar2, ar3 Auxiliary BMU registers data BMU
auc Arithmetic unit control c & s DAU
c0, c1, c2 Counters data DAU
cbit Control register for BIO c & s/data BIO
cloop Cache loop count data Cache
i Pointer postincrement address XAAU
inc Interrupt control control Control
ins Interrupt status status Control
ioc I/O configuration register c & s EMI, SIO, PIO
j Pointer postincrement
address YAAU
jtag 16-bit parallel/serial register data JTAG
k Pointer postincrement address YAAU
mwait Wait-states for EMI control EMI
p, pl 32-bit product, p is bits [31:16], pl is bits [15:0] data DAU
pdx<0--7> PIO/PHIF I/O registers (pdx0 only for
DSP1611/18/27/28/29)
data PIO/PHIF
phifc PHIF control register (DSP1611/18/27/28/29) c & s PHIF
pi Program interrupt return address XAAU
Note: Registers
sioc
,
sioc2
,
srta
,
srta2
,
tdms
, and
tdms2
are not readable. Alternate accumulators
aa0
and
aa1
are only accessible with the
BMU swap instruction.
Table 3-1. Program-Accessible Registers by Function
(continued)
Register Name Function
Note: Registers
sioc
,
sioc2
,
srta
,
srta2
,
tdms
, and
tdms2
are not readable. Alternate accumulators
aa0
and
aa1
are only acces-
sible with the BMU swap instruction.
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Software Architecture
Agere Systems Inc.
DRAFT COPY
3-3
3.1 Register View of the DSP1611/17/18/27/28/29
(continued)
3.1.1 Types of Registers
(continued)
pioc PIO control register (DSP1617 only) c & s PIO
pllc Control registers for clock synthesizer
(DSP1627/28/29 only)
control Clock
Synthesizer
powerc Power control
control Chip
pr Program return
address XAAU
psw Program status word c & s, data DAU
pt X address space table pointer address XAAU
r0, r1, r2, r3 Y address space pointers address YAAU
rb Modulo addressing, begin address address YAAU
re Modulo addressing, end address address YAAU
saddx<1, 2> Multiprocessor protocol register address/data SIO
sbit Status register for BIO c & s/data BIO
sdx<1, 2> SIO 16-bit I/O registers data SIO
sioc<1, 2> SIO control registers c & s SIO
srta<1, 2> Multiprocessing serial receive/transmit address regis-
ters
address SIO
tdms<1, 2> Time-division multiplex signal control registers c & s SIO
timer0 Timer running count register data Timer
timerc Timer control register c & s Timer
x Multiplier input
data DAU
y, yl Multiplier input, 32-bit, y is bits [31:16], yl is bits [15:0] data DAU
ybase Direct addressing
address YAAU
Table 3-2. Program-Accessible Registers by Type, Listed Alphabetically
(continued)
Register Name Description Type Section
Note: Registers
sioc
,
sioc2
,
srta
,
srta2
,
tdms
, and
tdms2
are not readable. Alternate accumulators
aa0
and
aa1
are only accessible with the
BMU swap instruction.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Software Architecture December 2001
3-4
DRAFT COPY
Agere Systems Inc.
3.1 Register View of the DSP1611/17/18/27/28/29
(continued)
3.1.1 Types of Registers
(continued)
5-4145.c
Figure 3-1. Program-Accessible Registers, DSP1611/17/18/27/28/29
ioc
mwait
jtag
JTAG BIO
BMU
DAU
PIO
CACHE &
CONTROL
YAAU XAAU
inc
ins
cloop
alf
pdx<0--7>(IN)
pioc
x
y
p
a0
a1
auc
psw
c0
c1
c2
SIO
sdx
saddx
srta
tdms
sioc
TIMER
timerc
pdx<0--7>(OUT)
CONTROL &
STATUS
ADDRESS DATA
SIO2
sdx2
saddx2
srta2
tdm2
sioc2
EMI
cbit
sbit
r0
r1
r2
r3
j
k
rb
re
ybase
i
pi
pr
pt
ar0
ar1
ar2
ar3
aa0
aa1
timer0
powerc
pllc
CLOCK SYNTHESIZER
ECCP (DSP1618/28 ONLY)
eir
ear
edr
(DSP1627/28/29 ONLY)
PHIF
pdx0(IN)
phifc
pdx0(OUT)
(DSP1617 ONLY)
(DSP1611/18/27/28/29 ONLY)
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Software Architecture
Agere Systems Inc.
DRAFT COPY
3-5
3.1 Register View of the DSP1611/17/18/27/28/29
(continued)
3.1.1 Types of Registers
(continued)
Registers not directly observable by the programmer (denoted by upper case), listed alphabetically:
3.1.2 Register Length Definition
The accumulators are 36 bits long, and the
y
and
p
registers are 32 bits long. The letter name
y
(or
p
) can mean
either the upper 16 bits of
y
(or
p
) or all 32 bits of
y
(or
p
) depending on the instruction. The table below defines
when the upper 16 bits are meant and when the full 32 bits are meant.
Table 3-3. Registers Nonaccessible by Program, Accessible Through Pins
Name Description Type Section
BREAKPOINT Four instruction breakpoint registers address HDS
BYPASS Bypass the boundary-scan register, 1 bit data JTAG
ID Identification register, 32 bits data JTAG
ISR Input shift register data
SIO
JCON JTAG configuration register, 17 bits c & s JTAG
OSR Output shift register data SIO
PSTAT PHIF/PIO status register c & s PHIF/PIO
TRACE Program discontinuity trace buffer address HDS
Note: The program counter register (PC) is not directly accessible to be read or written by instruction or external pins.
Table 3-4. Register Length Definition
Register When Used in Transfers In Functional Operators
a0, a1,
aa0, aa1
16-bit, except 36-bit between accumulators and in aD = y 36-bit, except 16-bit in aDh = aSh+1
and aD = aS<h, l> OP IM16
p 16-bit, except 32-bit to accumulators in multiply/ALU instruction 32-bit
y 16-bit, except 32-bit to accumulators in special function instruction 32-bit, except 16-bit in p = x * y
Note: The user must specify h or l in the ALU immediate, e.g.,
aD
=
aS
<h,l> OP IM16.
p
or
y
is sign-extended to 36 bits for operations with
accumulators.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Software Architecture December 2001
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DRAFT COPY
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3.1 Register View of the DSP1611/17/18/27/28/29
(continued)
3.1.3 Register Reset Values
Table 3-5 lists the values of the general set of registers after reset. A
indicates unknown on powerup reset and
unaffected on subsequent reset. An S means the register shadows the PC. P indicates the value of the bit on the
corresponding input pin.
DSP1617 only.
DSP1617 value is
0111010011000010.
If EXM is high and INT1 is low and RSTB goes high,
mwait
will contain all ones instead of all zeros.
DSP1627/28/29 only.
DSP1618/28 only.
DSP1611/18/27/28/29 only.
Table 3-5. Register Reset Values
Register Bits [15:0] Register Bits [15:0]
a0
pioc
0000000000001000
a0l
pl
a1
powerc
0000000000000000
a1l
pr
alf
00000000
psw
00
ar0
pt
ar1
r0
ar2
r1
ar3
r2
auc
0000000000000000
r3
c0
rb
0000000000000000
c1
re
0000000000000000
c2
saddx
cbit
saddx2
cloop
000000000
sbit
00000000PPPPPPPP
i
sdx
inc
0000000000000000
sdx2
ins
0000010000000110
sioc
0000000000
ioc
0000000000000000
sioc2
0000000000
j
srta
jtag
srta2
k
tdms
0000000000
mwait
0000000000000000
tdms2
0000000000
p
timer0
0000000000000000
pdx0
00000000
timerc
00000000
pdx1
00000000
x
pdx2
00000000
y
pdx3
00000000
ybase
pdx4
00000000
yl
pdx5
00000000
pllc
0000000000000000
pdx6
00000000
ear
0000000000000000
pdx7
00000000
eir
0000000000001111
phifc
0000000000000000
edr
pi
SSSSSSSSSSSSSSSS
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Software Architecture
Agere Systems Inc.
DRAFT COPY
3-7
3.1 Register View of the DSP1611/17/18/27/28/29
(continued)
3.1.4 Flags
For reference purposes, the definitions of the flags are included in Table 3-6 and Chapter 4, Instruction Set.
Testing each of these conditions increments the respective counter being tested.
The heads or tails condition is determined by a randomly set or a cleared bit. The bit is randomly set with probability of 0.5.
The random bit is generated by a 10-stage pseudorandom sequence generator (PSG) that is updated after either a heads or
tails test. (See Section 5.1.6, DAU Pseudorandom Sequence Generator (PSG) for more details.)
These flags are only set after an appropriate write to the BIO port (cbit register).
Table 3-6. Flag Definitions
Test Meaning Test Meaning
pl Result is nonnegative (not LMI) (
0). mi Result is negative (LMI) (< 0).
eq Result is equal to 0 (LEQ) (= 0). ne Result is not equal to 0 (not LEQ) (
0).
gt Result is greater than 0 (not LMI and
not LEQ) (> 0).
le Result is less than or equal to 0 (LMI or
LEQ) (
0).
lvs Logical overflow set (LLV). lvc Logical overflow clear (not LLV).
mvs Mathematical overflow set (LMV). mvc Mathematical overflow clear (not LMV).
c0ge
Counter 0 greater than or equal to 0. c0lt
Counter 0 less than 0.
c1ge
Counter 1 greater than or equal to 0. c1lt
Counter 1 less than 0.
heads
Pseudorandom sequence bit set. tails
Pseudorandom sequence bit clear.
true The condition is always satisfied in an
if instruction.
false The condition is never satisfied in an if
instruction.
allt
All true--all BIO input bits tested com-
pared successfully.
allf
All false--no BIO input bits tested com-
pared successfully.
somet
Some true--some BIO input bits
tested compared successfully.
somef
Some false--some BIO input bits
tested did not compare successfully.
oddp Odd parity from BMU operation. evenp Even parity from BMU operation.
mns1 Minus 1 result of BMU operation. nmns1 Not minus 1 result of BMU operation.
npint Not PINT used by Hardware Develop-
ment System.
njint Not JINT used by Hardware Develop-
ment System.
lock The PLL has achieved lock and is sta-
ble (DSP1627/28/29 only).
ebusy ECCP busy indicates error correction
coprocessor activity (DSP1618/28
only).
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Software Architecture December 2001
3-8
DRAFT COPY
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3.2 Memory Space and Addressing
The DSP1611/17/18/27/28/29 has two memory spaces: the X-memory space and the Y-memory space. They are
differentiated by which addressing unit they use and not by the physical memory they use. The dual-port RAM is in
the Y space and the X space, but it can be at different addresses. The Y addressing arithmetic unit (YAAU), unique
to the Y-memory space, is particularly suited for addressing memory that contains data or operands for the pro-
cessing units. The X addressing arithmetic unit (XAAU), unique to the X-memory space, is particularly suited for
program control and addressing memory that contains the instructions and coefficients as operands.
The internal dual-port RAM can be accessed in both the Y space and the X space. This RAM has multiple 1 Kword
banks, and, as long as the banks accessed are different, simultaneous data and instruction accesses can be
made. If the same bank is accessed from both memory spaces simultaneously, an extra instruction cycle (one
wait-state) is added to carry out the transfer and the Y space transfer is performed before the X space transfer.
3.2.1 Y-Memory Space
The Y-memory space is shown in Figure 3-2. Associated with the Y space are the Y addressing arithmetic unit
(YAAU), the Y address bus (YAB), the Y data bus (YDB), and the external memory interface (EMI). The 64K mem-
ory space is divided into four segments (RAM, IO, ERAMLO, and ERAMHI), as shown in Table 3-7. The selection
of a segment is automatic corresponding to the address in the YAAU. The segment for the internal RAM is further
divided into multiple 1K banks. The addresses are decoded in the YAAU, and an enable wire is provided for each
of the three external segments and for each of the internal RAM banks.
5-4110
Figure 3-2. Data (Y) Memory Space
INTERNAL
DUAL-PORT
RAM
YAAU
EXTERNAL
ERAMHI
EXTERNAL
ERAMLO
EXTERNAL
IO
YDB DATA BUS
YAB
EXTERNAL MEMORY DATA BUS
OFF-CHIP
EXTERNAL MEMORY ADDRESS BUS
ENAB
LES
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Software Architecture
Agere Systems Inc.
DRAFT COPY
3-9
3.2 Memory Space and Addressing
(continued)
3.2.1 Y-Memory Space (continued)
Table 3-7. Data Memory Map (Y-Memory Space)
Decimal
Address
Hexadecimal Address
in r0, r1, r2, r3
DSP1611 DSP1617/1618 DSP1627
DSP1628
x08
DSP1628
x16
DSP1629
x10
DSP1629
x16
0 0x0000
0x03FF
RAM1 RAM1 RAM1 RAM1 RAM1 RAM1 RAM1
1024 0x0400
0x07FF
RAM2 RAM2 RAM2 RAM2 RAM2 RAM2 RAM2
2048 0x0800
0x0BFF
RAM3 RAM3 RAM3 RAM3 RAM3 RAM3 RAM3
3072 0x0C00
0x0FFF
RAM4 RAM4 RAM4 RAM4 RAM4 RAM4 RAM4
4096 0x1000
0x13FF
RAM5 Reserved RAM5 RAM5 RAM5 RAM5 RAM5
5120 0x1400
0x17FF
RAM6 RAM6 RAM6 RAM6 RAM6 RAM6
6144 0x1800
0x1BFF
RAM7 Reserved RAM7 RAM7 RAM7 RAM7
7168 0x1C00
0x1FFF
RAM8 RAM8 RAM8 RAM8 RAM8
8192 0x2000
0x23FF
RAM9 Reserved RAM9 RAM9 RAM9
9216 0x2400
0x27FF
RAM10 RAM10 RAM10 RAM10
10240 0x2800
0x2BFF
RAM11 RAM11 Reserved RAM11
11264 0x2C00
0x2FFF
RAM12 RAM12 RAM12
12288 0x3000
0x33FF
Reserved RAM13 RAM13
13312 0x3400
0x37FF
RAM14 RAM14
14336 0x3800
0x3BFF
RAM15 RAM15
15360 0x3C00
0x3FFF
RAM16 RAM16
16384 0x4000
0x40FF
IO IO IO IO IO IO IO
16640 0x4100
0x7FFF
ERAMLO ERAMLO ERAMLO ERAMLO ERAMLO ERAMLO ERAMLO
32768
65535
0x8000
0xFFFF
ERAMHI ERAMHI ERAMHI ERAMHI ERAMHI ERAMHI ERAMHI
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Software Architecture December 2001
3-10
DRAFT COPY
Agere Systems Inc.
3.2 Memory Space and Addressing
(continued)
3.2.2 X-Memory Space
X-memory space (Figure 3-3) is instruction/coefficient or program memory. Associated with the X space are the X
addressing arithmetic unit (XAAU), the X address bus (XAB), the X data bus (XDB), and three possible physical
memories. The selection of the three memories is automatic corresponding to the address in the XAAU and the
memory map selected. Each physical memory device has a corresponding address space, but, unlike the YAAU,
the relationship between the memories and their corresponding address space can be changed. As shown in
Tables 3-8 through 3-12, there are four different arrangements of the memories in the memory map. The selection
of MAP 1--4 corresponds to the value of EXM and LOWPR.
5-4111
Figure 3-3. Instruction/Coefficient (X) Memory Space
XAB ADDRESS BUS
INTERNAL
ROM
INTERNAL
DUAL-PORT
RAM
EXTERNAL
EROM
XDB DATA BUS
XAAU
EXTERNAL MEMORY
ADDRESS BUS
EXTERNAL MEMORY
DATA BUS
ENABLE
OFF-CHIP
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Software Architecture
Agere Systems Inc.
DRAFT COPY
3-11
3.2 Memory Space and Addressing
(continued)
3.2.2 X-Memory Space (continued)
MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine.
LOWPR is an alf register bit. The Agere Systems development system tools can independently set the memory map.
Table 3-8. DSP1611 Instruction/Coefficient Memory Map (X-Memory Space)
Decimal
Address
Address in
pc, pt, pi, pr
MAP1
(EXM = 0
LOWPR
= 0)
MAP2 (EXM = 1
LOWPR = 0)
MAP3 (EXM = 0
LOWPR = 1)
MAP4 (EXM = 1
LOWPR = 1)
0 0x0000
0x03FF
IROM
(1K)
EROM
(48K)
RAM<1--12>
(12K)
RAM<1--12>
(12K)
1024 0x0400
0x2FFF
Reserved
(15K)
12288 0x3000
0x3FFF
Reserved
(4K)
Reserved
(4K)
16384 0x4000
0x43FF
EROM
(32K)
IROM
(1K)
EROM
(48K)
17408 0x4400
0x7FFF
Reserved
(15K)
32768 0x8000
0xBFFF
EROM
(32K)
49152 0xC000
0xDFFF
RAM<1--12>
(12K)
RAM<1--12>
(12K)
61439
65535
0xF000
0xFFFF
Reserved
(4K)
Reserved
(4K)
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Software Architecture December 2001
3-12
DRAFT COPY
Agere Systems Inc.
3.2 Memory Space and Addressing
(continued)
3.2.2 X-Memory Space (continued)
MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine.
LOWPR is an alf register bit. The Agere Systems development system tools can independently set the memory map.
MAP3 is not available if the secure mask-programmable option is selected.
MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine.
LOWPR is an alf register bit. The Agere Systems development system tools can independently set the memory map.
MAP3 is not available if the secure mask-programmable option is selected.
Table 3-9. DSP1617 Instruction/Coefficient Memory Map (X-Memory Space)
Decimal
Address
Address in
pc, pt, pi, pr
MAP1
(EXM = 0
LOWPR
= 0)
MAP2 (EXM = 1
LOWPR = 0)
MAP3
(EXM = 0
LOWPR = 1)
MAP4 (EXM = 1
LOWPR = 1)
0 0x0000
0x0FFF
IROM
(24K)
EROM
(48K)
RAM<1--4>
(4K)
RAM<1--4>
(4K)
4096 0x1000
0x3FFF
Reserved
(12K)
Reserved
(12K)
16384 0x4000
0x5FFF
IROM
(24K)
EROM
(48K)
24576 0x6000
0x7FFF
Reserved
(8K)
32768 0x8000
0x9FFF
EROM
(16K)
40960 0xA000
0xBFFF
Reserved
(8K)
49152 0xC000
0xCFFF
RAM<1--4>
(4K)
RAM<1--4>
(4K)
EROM
(16K)
53248
65535
0xD000
0xFFFF
Reserved
(12K)
Reserved
(12K)
Table 3-10. DSP1618 Instruction/Coefficient Memory Map (X-Memory Space)
Decimal
Address
Address in
pc, pt, pi, pr
MAP1
(EXM = 0
LOWPR
= 0)
MAP2 (EXM = 1
LOWPR = 0)
MAP3
(EXM = 0
LOWPR = 1)
MAP4 (EXM = 1
LOWPR = 1)
0 0x0000
0x0FFF
IROM
(16K)
EROM
(48K)
RAM<1--4>
(4K)
RAM<1--4>
(4K)
4096 0x1000
0x3FFF
Reserved
(12K)
Reserved
(12K)
16384 0x4000
0x7FFF
EROM
(32K)
IROM
(16K)
EROM
(48K)
32768 0x8000
0xBFFF
EROM
(32K)
49152 0xC000
0xCFFF
RAM<1--4>
(4K)
RAM<1--4>
(4K)
53248
65535
0xD000
0xFFFF
Reserved
(12K)
Reserved
(12K)
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Software Architecture
Agere Systems Inc.
DRAFT COPY
3-13
3.2 Memory Space and Addressing
(continued)
3.2.2 X-Memory Space (continued)
MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine.
LOWPR is an alf register bit. The Agere Systems development system tools can independently set the memory map.
MAP3 is not available if the secure mask-programmable option is selected.
Table 3-11. DSP1618x24 Instruction/Coefficient Memory Map (X-Memory Space)
Decimal
Address
Address in
pc, pt, pi, pr
MAP1
(EXM = 0
LOWPR
= 0)
MAP2 (EXM = 1
LOWPR = 0)
MAP3
(EXM = 0
LOWPR = 1)
MAP4 (EXM = 1
LOWPR = 1)
0 0x0000
0x0FFF
IROM
(24K)
EROM
(48K)
RAM<1--4>
(4K)
RAM<1--4>
(4K)
4096 0x1000
0x1FFF
Reserved
(12K)
Reserved
(12K)
8192 0x2000
0x3FFF
16384 0x4000
0x5FFF
IROM
(24K)
EROM
(48K)
24576 0x6000
0x7FFF
Reserved
(8K)
32768 0x8000
0x9fff
EROM
(16K)
40960 0xA000
0xBFFF
Reserved
(8K)
49152 0xC000
0xCFFF
RAM<1--4>
(4K)
RAM<1--4>
(4K)
EROM
(16K)
53248 0xD000
0xDFFF
Reserved
(12K)
Reserved
(12K)
57344
65535
0xE000
0xFFFF
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Software Architecture December 2001
3-14
DRAFT COPY
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3.2 Memory Space and Addressing
(continued)
3.2.2 X-Memory Space (continued)
MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine.
LOWPR is an alf register bit. The Agere Systems development system tools can independently set the memory map.
MAP3 is not available if secure mask-programmable option is selected.
Table 3-12. DSP1627 Instruction/Coefficient Memory Map (X-Memory Space)
Decimal
Address
Address in
pc, pt, pi, pr
MAP1
(EXM = 0
LOWPR
= 0)
MAP2 (EXM = 1
LOWPR = 0)
MAP3
(EXM = 0
LOWPR = 1)
MAP4 (EXM = 1
LOWPR = 1)
0 0x0000
0x0FFF
IROM
(36K)
EROM
(48K)
RAM<1--6>
(6K)
RAM<1--6>
(6K)
4096 0x1000
0x17FF
6144 0x1800
0x1FFF
Reserved
(10K)
Reserved
(10K)
8192 0x2000
0x2FFF
12288 0x3000
0x3FFF
16384 0x4000
0x4FFF
IROM
(36K)
EROM
(48K)
20480 0x5000
0x5FFF
24576 0x6000
0x6FFF
28672 0x7000
0x7FFF
32768 0x8000
0x8FFF
36864 0x9000
0x9FFF
Reserved
(12K)
40960 0xA000
0xAFFF
45056 0xB000
0xBFFF
49152 0xC000
0xCFFF
RAM<1--6>
(6K)
RAM<1--6>
(6K)
53248 0xD000
0xD7FF
Reserved
(12K)
55296 0xD800
0xDFFF
Reserved
(10K)
Reserved
(10K)
57344 0xE000
0xEFFF
61440
65535
0xF000
0xFFFF
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Software Architecture
Agere Systems Inc.
DRAFT COPY
3-15
3.2 Memory Space and Addressing
(continued)
3.2.2 X-Memory Space (continued)
MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine.
LOWPR is an alf register bit. The Agere Systems development system tools can independently set the memory map.
MAP3 is not available if secure mask-programmable option is selected.
Table 3-13. DSP1627x32 Instruction/Coefficient Memory Map (X-Memory Space)
Decimal
Address
Address in
pc, pt, pi, pr
MAP1
(EXM = 0
LOWPR
= 0)
MAP2 (EXM = 1
LOWPR = 0)
MAP3
(EXM = 0
LOWPR = 1)
MAP4 (EXM = 1
LOWPR = 1)
0 0x0000
0x0FFF
IROM
(32K)
EROM
(48K)
RAM<1--6>
(6K)
RAM<1--6>
(6K)
4096 0x1000
0x17FF
6144 0x1800
0x2FFF
Reserved
(10K)
Reserved
(10K)
12288 0x3000
0x3FFF
16384 0x4000
0x4FFF
IROM
(32K)
EROM
(48K)
20480 0x5000
0x5FFF
24576 0x6000
0x6FFF
28672 0x7000
0x7FFF
32768 0x8000
0x8FFF
EROM
(16K)
36864 0x9000
0x9FFF
40960 0xA000
0xAFFF
45056 0xB000
0xBFFF
49152 0xC000
0xCFFF
RAM<1--6>
(6K)
RAM<1--6>
(6K)
EROM
(16K)
53248 0xD000
0xD7FF
55296 0xD800
0xDFFF
Reserved
(10K)
Reserved
(10K)
57344 0xE000
0xEFFF
61440
65535
0xF000
0xFFFF
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Software Architecture December 2001
3-16
DRAFT COPY
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3.2 Memory Space and Addressing
(continued)
3.2.2 X-Memory Space (continued)
MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine.
LOWPR is an alf register bit. The Agere Systems development system tools can independently set the memory map.
MAP3 is not available if secure mask-programmable option is selected.
Table 3-14. DSP1628x08 Instruction/Coefficient Memory Map (X-Memory Space)
Decimal
Address
Address in
pc, pt, pi, pr
MAP1
(EXM = 0
LOWPR
= 0)
MAP2 (EXM = 1
LOWPR = 0)
MAP3
(EXM = 0
LOWPR = 1)
MAP4 (EXM = 1
LOWPR = 1)
0 0x0000
0x0FFF
IROM
(48K)
EROM
(48K)
DPRAM
(8K)
DPRAM
(8K)
4096 0x1000
0x17FF
6144 0x1800
0x1FFF
8192 0x2000
0x3FFF
Reserved
(8K)
Reserved
(8K)
16384 0x4000
0x4FFF
IROM
(48K)
EROM
(48K)
20480 0x5000
0x5FFF
24576 0x6000
0x6FFF
28672 0x7000
0x7FFF
32768 0x8000
0x8FFF
36864 0x9000
0x9FFF
40960 0xA000
0xAFFF
45056 0xB000
0xBFFF
49152 0xC000
0xCFFF
DPRAM
(8K)
DPRAM
(8K)
53248 0xD000
0xDFFF
57344 0xE000
0xEFFF
Reserved
(8K)
Reserved
(8K)
61440
65535
0xF000
0xFFFF
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Software Architecture
Agere Systems Inc.
DRAFT COPY
3-17
3.2 Memory Space and Addressing
(continued)
3.2.2 X-Memory Space (continued)
MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine.
LOWPR is an alf register bit. The Agere Systems development system tools can independently set the memory map.
MAP3 is not available if secure mask-programmable option is selected.
Table 3-15. DSP1628x16 Instruction/Coefficient Memory Map (X-Memory Space)
Decimal
Address
Address in
pc, pt, pi, pr
MAP1
(EXM = 0
LOWPR
= 0)
MAP2 (EXM = 1
LOWPR = 0)
MAP3
(EXM = 0
LOWPR = 1)
MAP4 (EXM = 1
LOWPR = 1)
0 0x0000
0x0FFF
IROM
(48K)
EROM
(48K)
DPRAM
(16K)
DPRAM
(16K)
4096 0x1000
0x17FF
6144 0x1800
0x2FFF
12288 0x3000
0x3FFF
16384 0x4000
0x4FFF
IROM
(48K)
EROM
(48K)
20480 0x5000
0x5FFF
24576 0x6000
0x6FFF
28672 0x7000
0x7FFF
32768 0x8000
0x8FFF
36864 0x9000
0x9FFF
40960 0xA000
0xAFFF
45056 0xB000
0xBFFF
49152 0xC000
0xCFFF
DPRAM
(16K)
DPRAM
(16K)
53248 0xD000
0xDFFF
57344 0xE000
0xEFFF
61440
65535
0xF000
0xFFFF
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Software Architecture December 2001
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DRAFT COPY
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3.2 Memory Space and Addressing
(continued)
3.2.2 X-Memory Space (continued)
MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine.
LOWPR is an alf register bit. The Agere Systems development system tools can independently set the memory map.
MAP3 is not available if secure mask-programmable option is selected.
Table 3-16. DSP1629x10 Instruction/Coefficient Memory Map (X-Memory Space)
Decimal
Address
Address in
pc, pt, pi, pr
MAP1
(EXM = 0
LOWPR
= 0)
MAP2 (EXM = 1
LOWPR = 0)
MAP3
(EXM = 0
LOWPR = 1)
MAP4 (EXM = 1
LOWPR = 1)
0 0x0000
0x0FFF
IROM
(48K)
EROM
(48K)
DPRAM
(10K)
DPRAM
(10K)
4096 0x1000
0x27FF
10240 0x2800
0x2FFF
Reserved
(6K)
Reserved
(6K)
12288 0x3000
0x3FFF
16384 0x4000
0x4FFF
IROM
(48K)
EROM
(48K)
20480 0x5000
0x5FFF
24576 0x6000
0x6FFF
28672 0x7000
0x7FFF
32768 0x8000
0x8FFF
36864 0x9000
0x9FFF
40960 0xA000
0xAFFF
45056 0xB000
0xBFFF
49152 0xC000
0xCFFF
DPRAM
(10K)
DPRAM
(10K)
53248 0xD000
0xDFFF
57344 0xE000
0xE7FF
59392 0xE800
0xEFFF
Reserved
(6K)
Reserved
(6K)
61440
65535
0xF000
0xFFFF
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Software Architecture
Agere Systems Inc.
DRAFT COPY
3-19
3.2 Memory Space and Addressing
(continued)
3.2.2 X-Memory Space (continued)
MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine.
LOWPR is an alf register bit. The Agere Systems development system tools can independently set the memory map.
MAP3 is not available if secure mask-programmable option is selected.
Table 3-17. DSP1629x16 Instruction/Coefficient Memory Map (X-Memory Space)
Decimal
Address
Address in
pc, pt, pi, pr
MAP1
(EXM = 0
LOWPR
= 0)
MAP2 (EXM = 1
LOWPR = 0)
MAP3
(EXM = 0
LOWPR = 1)
MAP4 (EXM = 1
LOWPR = 1)
0 0x0000
0x0FFF
IROM
(48K)
EROM
(48K)
DPRAM
(16K)
DPRAM
(16K)
4096 0x1000
0x17FF
6144 0x1800
0x2FFF
12288 0x3000
0x3FFF
16384 0x4000
0x4FFF
IROM
(48K)
EROM
(48K)
20480 0x5000
0x5FFF
24576 0x6000
0x6FFF
28672 0x7000
0x7FFF
32768 0x8000
0x8FFF
36864 0x9000
0x9FFF
40960 0xA000
0xAFFF
45056 0xB000
0xBFFF
49152 0xC000
0xCFFF
DPRAM
(16K)
DPRAM
(16K)
53248 0xD000
0xDFFF
57344 0xE000
0xEFFF
61440
65535
0xF000
0xFFFF
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DRAFT COPY
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3.2 Memory Space and Addressing
(continued)
3.2.2 X-Memory Space (continued)
Interrupt Vectors in X Space
If interrupts are being used, the lower addresses of the X-memory space must be reserved for the interrupt vectors.
These addresses can be in IROM, EROM, or RAM depending on the memory map in force. Table 3-18 shows the
vectors assigned to interrupts in the X-memory space.
DSP1617 only.
The icall instruction is reserved for use by the hardware development system.
DSP1618/28 only.
Table 3-18. Interrupts in X-Memory Space
Vector Description Vector Address
Reset vector 0x0
IBF, OBE, PIDS, or PODS enabled from pioc
;
INT0
0x1
Software interrupt, from instruction icall
0x2
TRAP from HDS 0x3
INT1 0x4
TIMEOUT 0x10
IBF2 0x14
OBE2 0x18
Reserved 0x1c
EREADY
0x20
EOVF
0x24
Reserved 0x28
IBF 0x2c
OBE 0x30
PIBF/PIDS 0x34
POBE/PODS 0x38
JINT 0x42
TRAP from user 0x46
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
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Agere Systems Inc.
DRAFT COPY
3-21
3.3 Arithmetic and Precision
Fixed-point, two's complement arithmetic is used throughout the DSP1611/17/18/27/28/29 device. In the DAU,
16-bit data in the x register and in the high half of the y register can be multiplied together and the 32-bit result is
stored in the p register. The data in the y or p registers or both accumulators can be operated on by the ALU; the
result is stored in either of the 36-bit accumulators. The 32-bit data from the y or p register is sign-extended to
36 bits if operated on by the ALU. The four guard bits in the accumulators reduce the need for scaling data.
Sometimes the 36-bit accumulators can be thought of as having an implied binary point to the right of bit 16, for
example, if multiplying a fraction with 16 bits to the right of the decimal (Q16 format) times an integer. Bits
15--0 are then the fractional part (which is referred to as aMI, where aM
= a0 or a1), and bits 35--16 are the inte-
ger part. The ALU operates on all 36 bits of the accumulators. The CLR field of the auc register (see Table 3-10)
controls automatic clearing of the low half while loading a0, a1, or y registers. This makes it easy to perform 16-bit
integer operations in the ALU by automatically clearing the low half of the register when the high half is loaded.
The operands for the DAU can have many different formats. To make it easier to handle these different formats, the
DSP has four options for scaling data as it is transferred from the p register to the accumulators: no shift, a 2-bit left
shift, 1-bit left shift, or a 2-bit right shift. Table 3-10 illustrates how 2 bits in the auc register (auc[1, 0]) determine
the bit alignment of the data in p with respect to the data in the accumulators. The connection of the data bus to
the p register, the RAM, the accumulators, and the remaining registers in the DSP device is fixed, i.e., no other
automatic shifts of data occur with data move or multiply/ALU instructions (although effectively a 16-bit right shift
occurs in transferring the high half of a 32-bit register to a 16-bit register).
The SAT field of the auc register (bits 3, 2) selects or deselects saturation mode. This is the manner in which data
is transferred from the accumulators after an overflow has been detected. Overflow occurs whenever bit 31 of an
accumulator is different from any of its guard bits.
If saturation is enabled, the data transferred out of the accumulator is the largest positive or negative number (as
defined by bit 35 of the accumulator) that can be represented with 32 bits.
Note: The data in the accumulator does not change, only the value that is transferred changes.
2
31
1 = 0x7FFFFFFF largest positive number
2
31
= 0x80000000 largest negative number
In nonsaturation mode, the actual value in the accumulator will be written.
For further information about overflow, refer to the psw register in Section 5.1.7, Control Registers.
The X=Y= field of the auc register (bit 7) controls the loading of the x register. If this bit is set to zero, there is no
change in the loading of the x register; i.e., instructions that load the x register operate as expected, and instruc-
tions that do not load the x register do not affect the contents of the x register. If this bit is set to one, all instruc-
tions that load the high half of the y register cause the same data that is loaded into y to be loaded into x. The
purpose of this bit is to allow a single-cycle squaring operation. For example:
a0=0
auc=0x80 /* enable X=Y=
*/
r1=table
y=*r1++ /* square, and load both y and x
*/
do 100 {
a0=a0+p
p=x*y
y=*r1++ /* accumulate, square, and load both y */
/* and x */
auc=0 /* disable X=Y= */
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DRAFT COPY
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3.3 Arithmetic and Precision
(continued)
The RAND field of the auc register (bit 8) selects or deselects inhibiting the on-chip pseudorandom sequence gen-
erator (PSG) whenever the pi register is written. If RAND is set to zero, the PSG is reset whenever the pi register
is written with any value except during execution of an interrupt service routine (ISR). If RAND is set to one, reset-
ting of the PSG is inhibited. For more details on the PSG, see Section 5.1.6, DAU Pseudorandom Sequence Gen-
erator (PSG).
Table 3-19. Arithmetic Unit Control (auc) Register
Bit 8 7 6--4 3--2 1--0
Field RAND X=Y= CLR SAT ALIGN
Field Value Description
RAND 0
1
Pseudorandom sequence generator (PSG) is reset by writing the pi register only
outside an interrupt service routine.
PSG never reset by writing the pi register.
X=Y= 0
1
Normal operation.
y = Y transfer statements load both the x and the y registers allowing single-
cycle squaring with p = x * y.
CLR 1xx Clearing yl is disabled (enabled if 0).
x1x Clearing a1l is disabled (enabled if 0).
xx1 Clearing a0l is disabled (enabled if 0).
SAT 1x a1 saturation on overflow is disabled (enabled if 0).
x1 a0 saturation on overflow is disabled (enabled if 0).
ALIGN 00 a0, a1
p.
01 a0, a1
p/4.
10 a0, a1
p x 4 (and zeros written to the two LSBs).
11 a0, a1
p x 2 (and zeros written to the LSB).
The auc is a 16-bit register of which 9 bits [8:0] are used for control. The unused upper 7 bits [15:9] are always zero when read and should
always be written with zeros to make the program compatible with future chip versions. The auc register is cleared at reset.
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
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Agere Systems Inc.
DRAFT COPY
3-23
3.3 Arithmetic and Precision
(continued)
No Shift (Figure 3-4)
If the auc[1:0] bits are 00, the data in the p register is not shifted with respect to the bits in the accumulator before
product bits 31--0 are transferred into bits 31--0 of the accumulator. In the accumulator, the sign bit from the p
register is extended into the guard bits 35--32. This mode is most often used if both x and y operands are 16-bit
integers.
5-4112
Figure 3-4. p Register to Accumulator Bit Alignment, auc[1:0] = 00
x(16)
15 0
31 16 15
y(32)
p(32)
a0, a1(36)
0
31
31
0
32
35
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DRAFT COPY
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3.3 Arithmetic and Precision
(continued)
Shift Right 2 Bits (Figure 3-5)
If the auc[1:0] bits are 01, the data in the p register is shifted 2 bits to the right with respect to the bits in the accu-
mulator as product bits 31--2 are transferred into bits 29--0 of the accumulator. Bits p[1:0] are lost. The sign of
p (bit 31) is extended by 6 bits into bits 35--30 of the accumulator. This setting is most useful if avoiding overflow
is a primary consideration and the loss of the two LSBs of the product can be tolerated.
5-4113
Figure 3-5. p Register to Accumulator Bit Alignment, auc[1:0] = 01
x(16)
15 0
31 16 15
y(32)
p(32)
a0, a1(36)
0
31
0
35
2
30 29
1
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Software Architecture
Agere Systems Inc.
DRAFT COPY
3-25
3.3 Arithmetic and Precision
(continued)
Shift Left 2 Bits (Figure 3-6)
If the auc[1:0] bits are 10, the data in the p register is shifted 2 bits to the left with respect to the bits in the accumu-
lator as product bits 31--0 are transferred into bits 33--2 of the accumulator. Bits 1 and 0 of the accumulator are
cleared by the load of the accumulator with the data in p. The sign of p is extended by 2 bits into bits 35 and 34 of
the accumulator. This mode is often used in filtering applications where coefficients in the x register are in Q14 for-
mat (2 magnitude bits, 14 fractional bits), and state variables in the y register are 16-bit integers. If the p register is
not shifted prior to accumulation, the accumulated result would have 4 guard bits, 18 magnitude bits, and 14 frac-
tional bits. Because it is often desirable to have the implied binary point to the right of bit 16 (16 fractional bits), the
setting auc[1:0] = 10 automatically shifts the result 2 bit locations to the left generating an accumulated result with
4 guard bits, 16 magnitude bits, and 16 fractional bits.
Note: The top 2 magnitude bits are shifted into overflow bits 33 and 32 that can only be read via the psw register,
and saturation can be detected if enabled in the auc register.
5-4114
Figure 3-6. p Register to Accumulator Bit Alignment, auc[1:0] = 10
x(16)
15 0
31 16 15
y(32)
p(32)
a0, a1(36)
0
31
35
2
33 1 0
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3.3 Arithmetic and Precision
(continued)
Shift Left 1 Bit (Figure 3-7)
If the auc[1:0] bits are 11, the data in the p register is shifted 1 bit to the left with respect to the bits in the accumu-
lator as product bits 31--0 are transferred into bits 32--1 of the accumulator. Bit 0 of the accumulator is cleared by
the load of the accumulator with the data in p. The sign of p is extended by 3 bits into bits 35 through 33 of the
accumulator. This mode is often used in filtering applications where coefficients in the x register are in Q15 format
(1 magnitude bit, 15 fractional bits), and state variables in the y register are 16-bit integers. If the p register is not
shifted prior to accumulation, the accumulated result would have 4 guard bits, 17 magnitude bits, and 15 fractional
bits. Because it is often desirable to have the implied binary point to the right of bit 16 (16 fractional bits), the set-
ting auc[1:0] = 11 automatically shifts the result 1 bit location to the left generating an accumulated result with
4 guard bits, 16 magnitude bits, and 16 fractional bits.
Note: The top magnitude bit is shifted into overflow bit 32 that can only be read via the psw register, and saturation
can be detected if enabled in the auc register.
5-4114.a
Figure 3-7. Register to Accumulator Bit Alignment, auc[1:0] = 11
x(16)
15 0
31 16 15
y(32)
p(32)
a0, a1(36)
0
31
35
32 1 0
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
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Agere Systems Inc.
DRAFT COPY
3-27
3.4 Interrupts
3.4.1 Introduction
If an interrupt condition arises (e.g., an I/O request like assertion of PIDS), a sequence of actions is taken by the
interrupt control logic to suspend normal program execution and branch to the interrupt service routine. The inter-
rupt service routine is executed before returning to the normal instruction.
Vectored interrupts allow multiple interrupt sources to be differentiated by assigning each to a unique interrupt
branching location. If more than one interrupt is asserted at the same time, they will be serviced sequentially
according to their assigned priorities. If an interrupt is being serviced and the same interrupt is requested again
before service of the first is completed, the interrupt must remain asserted until the next rising edge of IACK. The
interrupt structure of the DSP1611/17/27/29 provides a total of 11 interrupts and two traps, and the interrupt struc-
ture of the DSP1618/28 provides a total of 13 interrupts and two traps (see Table 3-20).
Interrupt service routines cannot be interrupted. Branch instructions, conditional branch instructions, postdecre-
ments of Y address registers, and cache loops are also not interruptible. A vectored interrupt that occurs during a
noninterruptible instruction is not serviced until after the next interruptible instruction has been executed.
A trap is similar to an interrupt except it gains control of the processor by branching to the trap service routine even
if the current instruction is noninterruptible. However, it might not be possible to return to the normal instruction
from the trap service routine because the state of the machine might not have been saved. The trap mechanism is
intended for two purposes. It can be used by an application to gain control of the processor rapidly for asynchro-
nous time-critical event handling (typically for catastrophic error recovery). It is also used by the hardware develop-
ment system (HDS) to gain control of the processor.
In the DSP1617, a set of interrupts have been retained to maintain compatibility with the DSP16A. Four I/O inter-
rupts and the hardware interrupt pin (INT0) from DSP16A can be used in a DSP16A-compatible mode (see
Section 3.4.7, Interrupts in DSP16A-Compatible Mode (DSP1617 Only)).
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
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3.4 Interrupts
(continued)
3.4.1 Introduction (continued)
Figure 3-8 is a functional block diagram of the interrupt hardware.
5-4115b
Figure 3-8. Interrupt Operation
JINT
OBE2
IBF2
TIME
INT[1:0] OFF-CHIP
PIDS/PIBF
PODS/POBE
OBE
IBF
IACK
VEC[3:0]
TRAP
icall
HDS trap
OFF-CHIP
CLEAR BITS
4--8,11
ONLY
13 13
13
13
INTERRUPT
PROCESSING
INC REGISTER
MASKS
INS REGISTER
CLEARS
16
16
IDB
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3-29
3.4 Interrupts
(continued)
3.4.2 Interrupt Sources
There are 11 sources
1
of interrupts and two sources of traps. The interrupt sources are described in the following
list; Table 3-20 has more detail for each interrupt vector's source, its vector address, its priority, its output encoding,
and its cause.
*
Software interrupt--An interrupt request issued by the instruction icall. The priority is 1 (lowest), and it is
nonmaskable. The icall instruction is reserved for use by the hardware development system.
*
IBF[2]
2
--Input buffer full indicates that an external device has written data into the SIO<1, 2> (serial input buffer).
IBF can be enabled from either pioc
3
or inc (IBF2 can only be enabled from inc). Interrupts enabled from pioc
3
are compatible with DSP16A, and their priority is lower than the vectored interrupts enabled from inc.
*
OBE[2]--Output buffer empty indicates that an external device has read data from the SIO<1, 2> (serial output
buffer). OBE can be enabled from either pioc
3
or inc (OBE2 can only be enabled from inc).
*
PIDS--Parallel input data strobe indicates that an external device has written data into the parallel input
register. PIDS can be enabled from either pioc
3
or inc.
*
PODS--Parallel output data strobe indicates that an external device has read the data from the parallel output
register. PODS can be enabled from either pioc
3
or inc.
*
PIBF--Parallel input buffer full flag indicates that data has been written to the parallel input data register. PIBF
can be enabled from inc.
*
POBE--Parallel output buffer empty flag indicates that the parallel output data register has been read by an
external device. POBE can be enabled from inc.
*
INT[1:0]--Interrupt by an external device indicates an external device has requested service by asserting the
INT[1:0] pin. INT0 can be enabled from either pioc
3
or inc.
*
JINT--JTAG interrupt request indicates that the jtag register has been written. JINT is reserved for the hardware
development system.
*
TIMEOUT--Interrupt request by timer indicates that the timer has reached zero count.
*
EREADY
4
--Interrupt indicates ECCP is ready.
*
EOVF
4
--Interrupt indicates an ECCP overflow condition.
The interrupt sources can be classified in several different ways:
*
On- or off-chip: The INT[1:0], PIDS (passive), PODS (passive), and trap signals are externally generated; the
other interrupts are internally generated.
*
Hardware or software: The icall instruction generates a software interrupt; the rest are generated by hardware.
*
DSP16A--Compatible (DSP1617 only) or not: Four of the interrupt sources (PIDS, PODS, OBE, and IBF) have
a different effect depending on whether they are enabled from the pioc
3
(DSP16A compatibility mode) or
enabled from the inc register. If they are enabled from the pioc
3
register, program control will jump to location
0x1. If they are enabled from the inc register, program control jumps to a different vector location for each. If
they are enabled from both the inc and the pioc
3
registers, they are serviced as if enabled from the inc. Also,
the INT0 is compatible with the INT of DSP16A because it vectors to location 0x1. Figure 3-9 shows the logical
function of the DSP16A-compatible interrupts, and Table 3-20 describes them.
1. 13 for DSP1618/28.
2. The label in [ ] is optional; IBF[2] means IBF or IBF2.
3. DSP1617 only.
4. DSP1618/28 only.
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3.4 Interrupts
(continued)
3.4.2 Interrupt Sources (continued)
5-4146
Figure 3-9. DSP16A-Compatible Interrupts (DSP1617 Only)
PIDS
PODS
OBE
IBF
INTERRUPT
PROCESSING
IACK
IDB
MASKS
16
INT0
pioc
INTERRUPTS
ENABLED
FROM CHIP PIN
TO CHIP PIN
icall
0
4
9
5
5
5
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3-31
3.4 Interrupts
(continued)
3.4.2 Interrupt Sources (continued)
3.4.3 Outputs of Interrupts
The status bits in the ins register show if an interrupt has been recognized (defined as when the interrupt is latched
into the register). An interrupt, however, might be recognized but not serviced (acted on by executing the associ-
ated service routine) depending on the state of the machine (i.e., other interrupt in progress, uninterruptible instruc-
tion, etc.). An interrupt will not be serviced if not enabled. The VEC[3:0] outputs show the interrupt being serviced
(see the encoding in Table 3-20). If no interrupt or trap is being serviced, the VEC[3:0] output pins are all zero.
Another output (IACK) goes high if any interrupt or trap is being serviced and goes low when the service routine
ends (see the functional timing diagrams for IACK timing).
Pins VEC[3:0] are multiplexed with pins IOBIT[7:4]. Bit 12 of the ioc register must be cleared to enable VEC[3:0].
The icall instruction is reserved for use by the hardware development system.
Available on DSP1617 only.
DSP1618/28 only.
Table 3-20. Vector Table
Source Vector Priority VEC[3:0]
Issued by Cleared By
No interrupt --
-- 0x0 -- --
Software interrupt 0x2 1 lowest 0x1 icall
ireturn
IBF enabled by pioc
0x1 1 0x1 SIO in read of sdx
OBE enabled by pioc
0x1 1 0x1 SIO out write to sdx
PIDS enabled by pioc
0x1 1 0x1 PIO in read of pdx<0--7>
PODS enabled by pioc
0x1 1 0x1 PIO out write to pdx<0--7>
INT0
0x1 2 0x2 pin ireturn or write to ins
JINT 0x42 3 0x8 jtag in read of jtag
INT1 0x4 4 0x9 pin ireturn or write to ins
TIMEOUT 0x10 7 0xc timer ireturn or write to ins
IBF2 0x14 8 0xd SIO2 in read of sdx2
OBE2 0x18 9 0xe SIO2 out write to sdx2
Reserved 0x1c 10 -- -- --
EREADY
0x20 11 0x1 ECCP ready ireturn or write to ins
EOVF
0x24 12 0x2 ECCP overflow ireturn or write to ins
Reserved 0x28 13 -- -- --
IBF enabled by inc 0x2c 14 0x3 SIO in read of sdx
OBE enabled by inc 0x30 15 0x4 SIO out write to sdx
PIDS/PIBF enabled by
inc
0x34 16 0x5 PHIF/PIO in read of pdx0
PODS/POBE enabled by
inc
0x38 17 0x6 PHIF/PIO out write to pdx0
TRAP from HDS 0x3 18 -- breakpoint, jtag, or pin ireturn
TRAP from user 0x46 19 highest 0x7 pin ireturn
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3.4 Interrupts
(continued)
3.4.4 Interrupt Operation
Figure 3-10, on page 3-33 shows the timing of a simple interrupt. Also shown is the code segment that is being
executed along with the interrupt service routine. In the timing diagram prior to time frame A, an external interrupt
occurs on INT1. The DSP at this time is executing a sequence of single cycle interruptible instructions (nops). In
time frame A, the interrupt is synchronized and latched in an interrupt-pending latch during the current instruction
cycle (A). During time frame B, the interrupt decoder decodes the vector address of the pending interrupt. In the
following cycle during time frame C, the interrupt is acknowledged on the VEC and IACK pins. The PC register is
loaded with the next instruction address of the INT1 interrupt service routine. The return address of the interrupted
instruction is saved in the pi register. At time frame D, the first instruction of the interrupt service routine (a0 = *r0)
is executed causing the ERAMHI strobe to go low immediately. Three cycles later (E), the ireturn instruction exe-
cutes, signaling the end of the interrupt service routine. The IACK and VEC pins are cleared and the contents of
the pi register is loaded into the PC register. At time frame F, the next instruction begins.
Code Fragment
INT1 Interrupt Service Routine
int1_isr:
a0=0x0 a0=*r0 //r0 points to ERAMHI
mwait=0x0 2*nop
r0=ERAM_HI ireturn
inc=0x20
nop

}
Single cycle interruptible instructions
nop
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3-33
3.4 Interrupts
(continued)
3.4.4 Interrupt Operation
(continued)
CKO is a zero-wait-stated clock.
Notes:
A. INT1 pin is synchronized and latched in interrupt pending latch.
B. Executing an interruptible instruction.
C. Branch to interrupt routine.
D. Start executing instructions in interrupt service routine.
E. ireturn instruction is executed; end of interrupt service routine.
F. Next instruction.
Figure 3-10. Timing Diagram of a Simple Interrupt (Asserted During an Interruptible Instruction and No
Other Pending Interrupts)
CKO
INT1
IACK
VEC[3:0]
A
B
C
D
E
F
ERAMHI
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3.4 Interrupts
(continued)
3.4.4 Interrupt Operation (continued)
In the following cases, extra delays (excluding wait-states) are required to service the interrupt:
1. The interrupt is always taken on instruction boundaries. If the instruction is a two-cycle instruction, the interrupt
will allow it to complete execution.
2. The higher-priority interrupts are serviced before the lower-priority interrupts. Therefore, extra delay is more
likely to occur to interrupts with low priority.
3. Interrupt service routines and trap service routines cannot be interrupted.
4. Branch instructions, conditional branch instructions and cache loops are not interruptible.
5. Postdecrement of the RAM address register (*rM--, M = one of 0, 1, 2, or 3) is not interruptible. (This is used by
the pop instruction for control of stacks.)
ins and inc Registers
All of the vectored interrupts are maskable through the inc register. A one in any bit of inc enables the associated
interrupt. If the bit is zero, the interrupt is masked. An interrupt that comes in while masked is latched (or recog-
nized) and will cause an interrupt after being enabled. The status of the interrupt sources that have been recog-
nized are readable in the ins register. Any of these interrupts that have been enabled in the inc register will cause
a vectored interrupt, possibly with some delay, as described previously. Table 3-22 through Table 3-24 show the
inc and ins registers.
Clearing of Interrupts
The PIO/PHIF and SIO<1, 2>interrupts are cleared by reading or writing pdx and sdx. Reading pdx clears
PIDS/PIBF; writing to pdx clears PODS/POBE. Reading sdx clears IBF; writing to sdx clears OBE (see
Section 8.3, Interrupts and the PIO, for more detail). The JTAG interrupt is cleared by reading the jtag register. If
the vectored interrupts TIME and INT[1:0] are being serviced, they will be cleared when the ireturn instruction is
issued. These vectored interrupts can also be cleared by writing to the ins register. If bits 8--4 in the ins register
are written to with a one, the corresponding interrupt condition is cleared and the bit becomes a zero. Writing a
zero to the ins register does nothing.
A zero in any bit of the inc register disables the corresponding interrupt, and a one in any bit enables the corresponding interrupt.
JINT is a JTAG interrupt and is controlled by the HDS. It can be made unmaskable by the Agere Systems development system tools.
A zero in any bit of the ins register disables the corresponding interrupt, and a one in any bit enables the corresponding interrupt.
JINT is a JTAG interrupt and is controlled by the HDS. It can be made unmaskable by the Agere Systems development system tools.
A zero in any bit of the inc register disables the corresponding interrupt, and a one in any bit enables the corresponding interrupt.
JINT is a JTAG interrupt and is controlled by the HDS. It can be made unmaskable by the Agere Systems development system tools.
Table 3-21. Interrupt Control (inc
) Register (All Except DSP1618/28)
Bit 15 14--11 10 9 8 7--6 5--4 3 2 1 0
Field JINT
Rsvd OBE2 IBF2 TIMEOUT Rsvd INT[1:0] PIDS/PIBF PODS/POBE OBE IBF
Table 3-22. Interrupt Status (ins
) Register (All Except DSP1618/28)
Bit 15 14--11 10 9 8 7--6 5--4 3 2 1 0
Field JINT
Rsvd OBE2 IBF2 TIMEOUT Rsvd INT[1:0] PIDS/PIBF PODS/POBE OBE IBF
Table 3-23. Interrupt Control (inc
) Register (DSP1618/28)
Bit 15 14 13 12 11 10 9 8 7--6 5--4 3 2 1 0
Field JINT
Rsvd EOVF EREADY Rsvd OBE2 IBF2 TIMEOUT Rsvd INT[1:0] PIBF POBE OBE IBF
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3-35
3.4 Interrupts
(continued)
3.4.4 Interrupt Operation (continued)
Interrupt Disable Latency
Interrupts are latched on the falling edge of CKO and are taken at the end of the next interruptible instruction. Inter-
rupts are enabled or disabled with a write to the inc register. The enabled/disabled condition becomes effective
just prior to the fetch of the instruction following the write of the inc register. To illustrate this, the following code
fragment demonstrates the interrupt disable latency. Interrupt disable latency is the delay from writing to the inc
register for disabling certain interrupts to the time the interrupt is actually disabled. The number of nop instructions
is not important; six nops were used in this example.
inc=0x10 /* enable the INT0 interrupt pin */
6*nop /* 6 nops */
inc=0 /* disable the INT0 interrupt pin */
6*nop /* 6 nops */
Figure 3-11 shows the functional timing for this example with the INT0 interrupt applied at varying times to deter-
mine if the interrupt is taken or not taken. The reference is the time at which instruction words are fetched on the
XDB (program data bus).
5-4117
Figure 3-11. Interrupt Disable Latency
The interrupt pins are latched on the falling edge of CKO. The transition region from accepting the interrupt to not
accepting it occurs at the falling edge of CKO during the fetch of the immediate word for the inc = 0 instruction. If
the interrupt is taken, the program will branch to location 1 at time slot 6. If the interrupt is not taken, a nop occurs
at time slot 6. One additional instruction, in this case a nop, will be executed before the interrupt service routine
begins to be executed.
If the user wishes to include a block of code that cannot be interrupted, the block of code could follow the nop after
the imm(0) (immediate equal to zero) in Figure 3-11.
A zero in any bit of the ins register disables the corresponding interrupt, and a one in any bit enables the corresponding interrupt.
JINT is a JTAG interrupt and is controlled by the HDS. It can be made unmaskable by the Agere Systems development system tools.
Table 3-24. Interrupt Status (ins
) Register (DSP1618/28)
Bit 15 14 13 12 11 10 9 8 7--6 5--4 3 2 1 0
Field JINT
Rsvd EOVF EREADY Rsvd OBE2 IBF2 TIMEOUT Rsvd INT[1:0] PIBF POBE OBE IBF
CKO
XDB
INT0
inc = 0 goto 1
INTERRUPT
IS TAKEN
INTERRUPT IS
NOT TAKEN
nop
nop
2
1
3
4
5
6
imm(0)
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3.4 Interrupts
(continued)
3.4.4 Interrupt Operation (continued)
Concurrent Interrupts
If using DSP16A-compatible interrupts in the DSP1617 device, concurrent interrupts must be handled with extra
care in order to guarantee that all interrupts will be serviced (details are described in Section 4.2.6 of the
DSP16A
Information Manual). It is much simpler to handle concurrent interrupts if they are enabled from the inc register in
DSP1611/17/18/27/28/29. Interrupts are serviced according to the following rules:
If interrupt requests (internal or external) occur at the same time or pending interrupts are enabled at the same time
and the device is not servicing any of the pending requests, all the interrupts will be serviced sequentially according
to their priority. The corresponding interrupt status bit is cleared after that interrupt is serviced and ireturn is
issued. The interrupt service status pins (VEC[3:0]) and IACK pin indicate which interrupt is currently being ser-
viced. Figure 3-12 shows a typical circuit that is used to assert an interrupt by an external device. This circuit
removes the interrupt request signal when it begins to service that interrupt.
5-4147
Figure 3-12. Interrupt Request Circuit Diagram
DSP1611/17/18/27/28/29
INT1
INT0
VEC0
VEC1
VEC2
VEC3
A0
A1
A2
A3
IACK
1-OF-16
DECODER
Q0
Q8
Q9
Q15
INT1ACK
Q
D
CK
CL
V
DD
ENABLE
INT1 INTERRUPT REQUEST
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3.4 Interrupts
(continued)
3.4.4 Interrupt Operation (continued)
If the device is servicing a particular interrupt or that interrupt is already pending and it is desired to have the same
interrupt requested again, the interrupt must remain asserted until the next rising edge of IACK. Figure 3-13 is the
timing diagram of the concurrent interrupt in which the same interrupt is asserted again while the first interrupt
request is being serviced.
5-4118
CKO is a zero-wait-stated clock.
Notes:
A. INT1 pin is synchronized and latched in interrupt pending latch.
B. Executing an interruptible instruction.
C. Branch to interrupt routine.
D. Start executing instructions in interrupt service routine.
E. ireturn instruction is executed; end of interrupt service routine.
F. Next interruptible instruction.
G. Branch to interrupt service routine caused by second INT1.
H. Start executing instructions in interrupt service routine.
Figure 3-13. Timing Diagram of Concurrent Interrupts (Interrupt Is Asserted During the Service of the
Same Interrupt.)
CKO
INT1
IACK
VEC[3:0]
A
B
C
D
E
F
G
H
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3.4 Interrupts
(continued)
3.4.4 Interrupt Operation
(continued)
Polling for Interrupt
The interrupts that are masked will not be serviced by an interrupt service routine. However, the interrupt condi-
tions can be determined by polling the ins register. If the interrupt source is examined in a polling routine, certain
action is taken to clear that status bit in the ins register. The SIO[2] and PIO/PHIF interrupt conditions can be
cleared by reading or writing the I/O registers. JINT can be cleared by reading the jtag register. The interrupts
TIME and INT[1:0] are cleared by an ireturn instruction or by writing the corresponding bits of the ins register with
ones. Interrupts that can be cleared by an ireturn instruction are latched on the rising edge of the IACK signal. For
this reason, these interrupts cannot be polled while programs are executing from the interrupt level.
In the following example, the code continuously polls the ins register to determine if the condition TIMEOUT is true.
When the timer reaches zero count, the serial input data is read into RAM and the TIMEOUT status of the ins reg-
ister is cleared.
sioc=0x0 /* passive SIO */
inc=0x0 /* mask vectored interrupts */
wait: a0=ins /* check ins register for TIMEOUT */
a0h&0x0100 /* look only at bit 8 */
if eq goto wait /* if no TIMEOUT, wait. */
ins=0x0100 /* if TIMEOUT, clear interrupt by setting bit 8 to 1 */
*r0=sdx /* move serial input data into RAM */
Note: pioc bits 9, 8 = 0 to disable ibf and obe interrupts in DSP16A-compatible mode (DSP1617 only).
3.4.5 Trap Description
The maximum interrupt latency in a program can be as long as thousands of cycles if a cache loop uses a large
repeat count. For some time-critical events, the long interrupt response time is too slow to gain control of the pro-
cessor and remove the exception condition. Therefore, programming techniques such as breaking long cache
loops into several short ones, using short interrupt service routines, etc. are often used to improve the response
time. Alternatively, the trap mechanism causes the processor to branch to a trap service routine with less than four
cycles of latency without restrictions from the current instruction. If in a trap service routine, another trap will be
ignored. Also, the trap feature is used by the hardware development system for breakpointing and gaining control
of the processor. Table 3-20 shows the vector address, priority, and trap status encoding (VEC[3:0]) of the user
trap and HDS trap.
The user trap (vector 0x46) is caused by asserting the TRAP pin of the DSP. Because a trap is not maskable and
the user trap has the highest priority, at most two instructions (four cycles maximum) will execute from the time the
trap is received at the pin to when it gains control (see Figure 3-14). An instruction that is executing when the trap
occurs will be allowed to complete before the trap is taken (note that the instruction could be lengthened by wait-
states). If the instruction is a two-cycle instruction (not counting wait-states), the pi register contains the address of
the next instruction. If the instruction was a one-cycle instruction, the pi register will contain the address after the
next instruction. If the program is in an interrupt service routine at the time the trap was taken, the return address
in the pi register is overwritten if a user trap is taken. It is not possible to return to an interrupt service routine from
a user trap service routine. Continuing program execution if a trap occurs during a cache loop is also not possible.
A trap by the hardware development system does not affect the IACK or VEC[3:0] pins. Instead, they show the
interrupt state or interrupt source of the DSP when the TRAP occurs.
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3-39
3.4 Interrupts
(continued)
3.4.5 Trap Description (continued)
5-4119.a
CKO is a zero-wait-stated clock.
Notes:
A. TRAP pin is synchronized and latched in interrupt pending latch.
B. A constant two-cycle delay to allow a two-cycle instruction to complete before entering into the trap service routine.
C. Branch to trap service routine.
D. Start executing instructions in trap service routine.
E. ireturn instruction is executed; end of trap service routine.
F. Next interruptible instruction.
Figure 3-14. Timing Diagram of User Trap
CKO
IACK
VEC[3:0]
A
B
C
D
E
F
USER TRAP
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3.4 Interrupts
(continued)
3.4.6 Powerdown with the AWAIT State
These DSPs have a power-saving standby mode in which the internal clock is stretched indefinitely until an inter-
rupt/trap request is received. A minimum amount of circuitry on the chip, including the PIO/PHIF and SIO, will con-
tinue to run in order to process the incoming interrupt. The processor enters the powerdown mode by the user
setting the AWAIT bit (bit 15) of the alf register. After the AWAIT bit is set, one more instruction cycle is executed
before entering the standby powerdown mode. After an interrupt request wakes up the processor, one more
instruction cycle is executed before being interrupted. The timing of entering and exiting the sleep mode is illus-
trated in Figure 3-15.
5-4120
CKO is a free-running clock (ioc = 0x0000).
CKO is a wait-stated clock (ioc = 0x0080).
Notes:
A. Setting AWAIT bit of the alf register.
B. Executing one more instruction (nop) after AWAIT is set.
C. Stretching the clock for powerdown mode.
D. Executing one more instruction (nop) after coming out of sleep mode.
E. Branching to interrupt service routine.
F. Start executing instructions in interrupt service routine.
Figure 3-15. Timing Diagram of Entering and Exiting Powerdown Mode
CKO
IACK
VEC[3:0]
A
B
C
D
E
F
INT1
CKO
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3-41
3.4 Interrupts
(continued)
3.4.6 Powerdown with the AWAIT State (continued)
Code Example for Sleep Mode (assuming execution from internal RAM)
sleep:
alf=0x8000 /* set bit 15 of alf register */
nop /* one more instruction executed */
/* sleep here */
/* external interrupt occurs */
nop /* one more instruction executed */
/* branch here */
/* return here */
main code:
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3.4 Interrupts
(continued)
3.4.7 Interrupts in DSP16A-Compatible Mode (DSP1617 Only)
One external interrupt (INT0) and four internal interrupts (IBF, OBE, PIDS, and PODS) can be compatible with the
corresponding DSP16A interrupts in the DSP1617. If these interrupts are enabled in the pioc register, program
control jumps to address 0x0001 upon receiving an interrupt just as in the DSP16A. If operating in DSP16A-com-
patible mode, no vectored interrupts should be enabled
1
, i.e., inc = 0x0 for software compatibility with the DSP16A
source code. However, detailed timing specifications and interrupt latency differ between the DSP16A and the
DSP1617. The most important distinction is that, in DSP16A-compatible mode, ireturn does not clear the pending
external interrupt if the interrupt is actually caused by an internal interrupt. The pending INT0 can be cleared by
writing 0x10 to the ins register before issuing ireturn. One notable timing difference is the IACK signal that is
asserted at the rising edge of the CKO clock in the DSP1617 instead of the falling edge of CKO as in DSP16A.
However, ORing VEC0 and VEC1 in the DSP16A-compatible mode generates a signal equivalent to the DSP16A
IACK signal.
The software interrupt (icall, branching to location 0x2) in DSP1611/17/18/27/28/29 works the same way as in
DSP16A. The icall instruction is reserved for use by the hardware development system.
Concurrent Interrupts in DSP16A-Compatible Mode (DSP1617 Only)
The complexity of servicing concurrent interrupts in the DSP16A-compatible interrupt mode is described below.
The following discussion uses an example to illustrate the problem. For concurrent internal and external interrupts,
any interrupts recognized more than one clock cycle before IACK are displayed by the status bits of the pioc
register. They can be serviced in an interrupt handler as demonstrated in the example.
EXAMPLE
/******************************************************************/
/* Interrupts in DSP16A compatible mode (DSP1617). */
/* Concurrent internal (IBF) and external (INT0) interrupt */
/* enabled from the pioc register. */
/******************************************************************/
goto start
intrpt: /* interrupt service routine */
a0=pioc /* move pioc register to a0 */
y=0x1 /* load mask 0x1 to y */
a0&y /* examine bit 0 (INT0) of pioc */
if eq goto sioint /* if no INT0, then service IBF */
/* service external interrupt */
r0=0x11 /* DUMMY CODE */
a1=r0 /* DUMMY CODE */
pdx1=a1 /* DUMMY CODE */
ins=0x10 /* clear INT0 before ireturn */
ireturn
1. If interrupts are enabled in the inc and pioc registers, the vectored interrupts are serviced.
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3-43
3.4 Interrupts
(continued)
3.4.7 Interrupts in DSP16A-Compatible Mode (DSP1617 Only) (continued)
sioint: /* service internal (IBF) interrupt */
a1=sdx /* reading sdx clears IBF */
pdx0=a1 /* DUMMY CODE */
ireturn
start:
pioc=0x1a20 /* enable IBF and INT0 interrupts */
/* active pio */
sioc=0x0 /* passive sio port */
srta=0x0
auc=0x0
40*nop
stop: goto stop
If the external interrupt is recognized while servicing an internal interrupt (less than one cycle between IACK and
INT0 being latched), the INT0 interrupt is pending and is serviced at the next interruptible instruction after the cur-
rent interrupt service routine has finished. In this case, unlike the DSP16A, there is no need to hold the INT0 signal
until the next rising edge of IACK. If the IBF interrupt is recognized while servicing the external interrupt, it is ser-
viced at the next interruptible instruction as in the previous case.
Therefore, given the interrupt service routine in the EXAMPLE, asserting INT0 with a pulse width of two clock peri-
ods guarantees the service of the concurrent internal and external interrupts under all conditions.
For concurrent external interrupts and if the external interrupt is being serviced as indicated by IACK and VEC1
high and if another external interrupt is requested again, the INT0 signal must be asserted until the next rising edge
of IACK (or VEC1).
For applications that need both concurrent internal and external interrupts, the INT0 pin can be asserted by a pulse
of two CKO periods if no other INT0 is pending or in progress; otherwise, INT0 must remain asserted in order to be
serviced again.
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3.4 Interrupts
(continued)
3.4.8 Timing Examples, DSP16A-Compatible Mode (DSP1617 Only)
Concurrent Internal and External Interrupts--Figure 3-16 shows the timing sequence of concurrent IBF and
INT0 interrupts with both interrupt signals synchronized to the falling edge of the CKO clock. Four cases are given
for different INT0 signals asserted at the same time as, or after, the IBF signal.
*
Case 1--INT0 is asserted the same time as IBF. They are latched internally at point A, and an interrupt is
caused by INT0 with both status bits in pioc set. INT0 in the pioc register is cleared when IACK goes low. IBF is
cleared upon reading of sdx.
*
Case 2--INT0 is asserted one clock cycle after IBF and latched internally at point B. Interrupt is caused by IBF
with both status bits in pioc set. ireturn does not clear INT0. In DSP16A, ireturn does clear INT0 in this case.
*
Case 3--INT0 is asserted two clock cycles after IBF and latched internally at point C. Interrupt is caused by IBF
with only IBF status bit set in the pioc register. INT0 is pending and is taken at the next interruptible instruction
after ireturn.
*
Case 4--INT0 asserted three clock cycles after IBF. This case is identical to case 3.
5-4121
CKO is a zero-wait-stated clock.
Figure 3-16. Timing Sequence of Concurrent Internal and External Interrupts, DSP16A-Compatible Mode
CKO
IACK
A
B
C
D
INT0 CASE 1
INT0 CASE 2
INT0 CASE 3
INT0 CASE 4
IBF
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3.4 Interrupts
(continued)
3.4.8 Timing Examples, DSP16A-Compatible Mode (DSP1617 Only) (continued)
Concurrent Internal and External Interrupts--Figure 3-17 also shows the timing sequence of concurrent IBF
and INT0 interrupts with three cases of IBF asserted after the INT0 signal.
*
Case 1--IBF is asserted one clock cycle after INT0. INT0 is latched at point A and IBF at point B. Interrupt is
caused by INT0 with both status bits in pioc set. INT0 latch is negated when IACK goes high.
*
Case 2--IBF is asserted two clock cycles after INT0 and latched internally at point C. Interrupt is caused by
INT0, and only the INT0 status bit in pioc is set. INT0 latch is negated when IACK goes high. IBF interrupt is
serviced at the next interruptible instruction after ireturn.
*
Case 3--IBF is asserted three clock cycles after INT0. The result is identical to case 2.
5-4122
CKO is a zero-wait-stated clock.
Figure 3-17. Timing Sequences of Concurrent Internal and External Interrupts, DSP16A Compatible Mode
CKO
IACK
A
B
C
D
IBF CASE 1
IBF CASE 2
IBF CASE 3
INT0
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3.4 Interrupts
(continued)
3.4.8 Timing Examples, DSP16A-Compatible Mode (DSP1617 Only) (continued)
Concurrent External Interrupts--Figure 3-18 shows the timing sequence of concurrent INT0 interrupts.
*
Case 1--INT0 signal is negated at point B and asserted again at point C. Because the previous INT0 is still
pending, the new INT0 must be asserted until the second rising edge of IACK.
*
Case 2--INT0 signal is negated at point B and asserted again at point D. In this case, INT0 is asserted if servic-
ing of the previous INT0 is in progress; it must remain asserted until the next rising edge of IACK.
5-4123
CKO is a zero-wait-stated clock.
Figure 3-18. Timing Sequence of Concurrent External Interrupts, DSP16A Compatible Mode
CKO
IACK
A
B
C
D
INT0 CASE 1
INT0 CASE 2
VEC1
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3.5 Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only)
The DSP1627/28/29 provides an on-chip programmable clock synthesizer that can be driven by an external clock
at a fraction of the desired instruction rate. Figure 3-19 is the clock source diagram. The 1X CKI input clock, the
output of the synthesizer, or a slow internal ring oscillator can be used as the source for the internal DSP clock.
The clock synthesizer is based on a phase-lock loop (PLL). The terms clock synthesizer and PLL are used inter-
changeably.
On powerup, CKI is used as the clock source for the DSP. This clock is used to generate the internal processor
clocks and CKO. Setting the appropriate bits in the pllc control register (see Table 3-26) will enable the clock syn-
thesizer to become the clock source. The powerc register, which is discussed in Section 3.6.1, powerc Control
Register Bits, can be programmed to override the clock selection, to stop clocks, or to force the use of the slow ring
oscillator clock for low-power operation.
Notes:
Signals shown in bold are control bits from the pllc register or the powerc register.
If PLLSEL = 0, DSP runs from the 1X version of CKI input clock.
Other signals from the powerc register also control the clock source.
Figure 3-19. Clock Source Block Diagram
LOCK
PLL/SYNTHESIZER
pllc
powerc
f
CKI
Nbits[2:0]
Mbits[4:0] LF[3:0]
M
N
PHASE
DETECTOR
LOOP
FILTER
CHARGE
PUMP
VCO
(FLAG TO INDICATE LOCK
CONDITION OF PLL)
VCO CLOCK
INTERNAL
PROCESSOR
CLOCK
PLLSEL
PLLEN
SLOWCKI
CKI INPUT CLOCK
2
f
SLOW CLOCK
RING
OSCILLATOR
f
CKI
M
U
X
f
INTERNAL CLOCK
f
VCO
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DRAFT COPY
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3.5 Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only)
(continued)
3.5.1 PLL Control Signals
The input to the PLL comes from the input clock CKI. The PLL cannot operate without this external input clock.
To use the PLL, the PLL must first be allowed to stabilize and lock to the programmed frequency. After the PLL has
locked, the LOCK flag is set and the lock detect circuitry is disabled. The synthesizer can then be selected and
used as the clock source. Setting the PLLSEL bit in the pllc register will switch sources from f
CKI
to f
VCO
/2 without
glitching. It is important to note that the setting of the pllc register must be maintained and should not be changed
unless the PLL is deselected as the clock source. Every time the pllc register is written, the LOCK flag is reset.
The LOCK flag is not accessible through any register; its status is tested by the conditional control instruction
if LOCK. (See Section 4.5.1, Control Instructions.)
The frequency of the PLL output clock (f
VCO
) is determined by the values loaded into the 3-bit N divider and the
5-bit M divider. If the PLL is selected and locked, the frequency of the initial processor clock is related to the fre-
quency of CKI by the following equations:
f
VCO
= f
CKI
* M/N
f
INTERNAL CLOCK
= f
CKO
= f
VCO
/2
The frequency of the VCO (f
VCO
) must fall within the range defined in the data sheet.
Note: f
VCO
must be at least twice f
CKI
.
The coding of the Mbits and Nbits is described as follows:
Mbits=M-2
if (N==1)
Nbits=0x7
else
Nbits=N-2
where N ranges from 1 to 8 and M ranges from 2 to 20.
Program the loop filter bits (LF[3:0]) according to Table 3-27.
Two other bits in the pllc register (PLLEN and PLLSEL) provide control functions of the PLL. Clearing the PLLEN
bit powers down the PLL. Setting the PLLEN bit powers up the PLL. Clearing the PLLSEL bit deselects the PLL
causing the DSP to be clocked by the 1X CKI input. The PLL can be deselected and powered down in the same
instruction by clearing bits PLLEN and PLLSEL of the pllc register; all remaining pllc bits must remain unchanged.
Setting the PLLSEL bit selects the PLL-generated clock for the source of the DSP internal processor clock. The
pllc register is cleared on reset and powerup; therefore, the DSP comes out of reset with the PLL deselected and
powered down. M and N should be changed only if the PLL is deselected.
The PLL provides a user flag (LOCK) to indicate if the loop has locked. If this flag is not asserted, the PLL output is
unstable. The DSP should not be switched to the PLL-based clock without first checking that the LOCK flag is set.
The LOCK flag is cleared by writing to the pllc register. If the PLL is deselected, it is necessary to wait for the PLL
to relock before the DSP can be switched to the PLL-based clock. Before the input clock (CKI) is stopped, the PLL
should be powered down. Otherwise, the LOCK flag is not reset, and there might be no way to determine if the
PLL is stable when the input clock is applied again.
The lock-in time depends on the operating frequency and the values programmed for M and N (see Table 3-27).
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Software Architecture
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DRAFT COPY
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3.5 Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only)
(continued)
3.5.1 PLL Control Signals (continued)
The following rules govern proper programming and use of the PLL:
*
Choose the M and N counter values in the pllc register by selecting the lowest value for N and the appropriate
value of M required to obtain the desired frequency of the internal clock. The values for M are in Table 3-27.
*
The frequency of the PLL output clock (VCO) must fall within the range defined in the data sheet. The VCO fre-
quency must also be at least 2x f
CKI
.
*
Change the bits in the pllc register only if the PLL is not providing the internal clock source.
*
To select the PLL as the internal clock:
1. Program all bits in the pllc register to the desired setting except for PLLSEL, which should be cleared. Setting
the pllc register should be performed if the PLL is deselected.
2. Wait for the LOCK flag to be set.
3. Select the PLL by setting the PLLSEL bit.
*
To deselect the PLL, clear only the PLLSEL without changing any other bits in the pllc register.
*
The PLL is powered down by clearing the PLLEN bit in the pllc register. The PLL should not be powered down if
it is selected. The PLL can be deselected and powered down in the same instruction by clearing bits PLLEN and
PLLSEL of the pllc register; all remaining pllc bits must remain unchanged.
*
Do not remove the input clock (CKI) before the PLL is powered down.
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3.5 Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only)
(continued)
3.5.2 PLL Programming Examples
The following section of code illustrates how the PLL is initialized on powerup assuming the following operating
conditions:
*
V
DD
= 3 V
*
CKI input frequency = 10 MHz
*
Internal clock and CKO frequency = 50 MHz
*
VCO frequency = 100 MHz
*
Input divide down count N = 2 (Set Nbits[2:0] = 000 to get N = 2, as Table 3-26 describes.)
*
Feedback down count M = 20 (Set Mbits[4:0] = 10010 to get M = 18 + 2 = 20, as Table 3-26 describes.)
The device comes out of reset with the PLL powered down and deselected.
pllinit: pllc=0xA912 /* Running CKI input clock at 10 MHz, set up counters */
/* in PLL, Power on PLL, but PLL remains deselected */
call pllwait /* Loop to check for LOCK flag assertion */
pllc=0xE912 /* Select high-speed, PLL clock */
2*nop /* Switch to PLL latency */
goto start /* User's code, now running at 50 MHz */
pllwait: if lock return
goto pllwait
Section 3.6.6, Power Management Examples lists programming examples that illustrate how to use the PLL with
the various power management modes.
3.5.3 Latency
The switch between the CKI-based clock and the PLL-based clock is synchronous. This method results in the
actual switch taking place several cycles after the PLLSEL bit is changed. During this time, actual code can be
executed at the precedent clock rate. Table 3-25 shows the latency times for switching between CKI-based and
PLL-based clocks. The PLL cannot be disabled until the switch back to CKI has been completed. In the example
given, the delay to switch to the PLL source is 1--4 CKO cycles and to switch back is 11--31 CKO cycles.
Table 3-25. Latency Times for Switching Between CKI and PLL-Based Clocks
Minimum
Latency (cycles)
Maximum
Latency (cycles)
Switch to PLL-based clock 1 N + 2
Switch from PLL-based clock M/N + 1 M + M/N + 1
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December 2001 Software Architecture
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DRAFT COPY
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3.5 Clock Synthesis (DSP1627, DSP1628, and DSP1629 Only)
(continued)
3.5.3 Latency (continued)
Table 3-26. Phase-Locked Loop Control (pllc) Register
Bit 15 14 13 12 11--8 7--5 4--0
Field PLLEN PLLSEL ICP SEL5V
LF[3:0] Nbits[2:0] Mbits[4:0]
Field Value Description
PLLEN 0
1
PLL powered down.
PLL powered up.
PLLSEL 0
1
DSP internal clock taken directly from CKI.
DSP internal clock taken from PLL.
ICP -- Charge Pump Current Selection (see Table 3-27 for proper value).
SEL5V
0
1
3 V operation (see Table 3-27 for proper value).
5 V operation (see Table 3-27 for proper value).
LF[3:0] -- Loop filter setting (see Table 3-27 for proper value).
Nbits[2:0] -- Encodes N, 1
N
8; where N = Nbits[2:0] + 2, unless Nbits[2:0] = 111 then N = 1.
Mbits[4:0] -- Encodes M, 2
M
24; where M = Mbits[4:0] + 2 & f
INTERNAL CLOCK
= f
CKI
x (M/(2N)).
Not available on the DSP1628 or DSP1629.
Table 3-27. PLL Electrical Specifications and pllc Register Settings
M
V
DD
pllc13
(ICP)
pllc12
(SEL5V)
pllc[11:8]
(LF[3:0])
Typical Lock-in Time (
s)
(See Note 2)
23--24 2.7 V--3.6 V 1 0 1011 30
21--22 2.7 V--3.6 V 1 0 1010 30
19--20 2.7 V--3.6 V 1 0 1001 30
16--18 2.7 V--3.6 V 1 0 1000 30
12--15 2.7 V--3.6 V 1 0 0111 30
8--11 2.7 V--3.6 V 1 0 0110 30
2--7 2.7 V--3.6 V 1 0 0100 30
19--20 5 V
5% 1 1 1110 30
17--18 5 V
5% 1 1 1101 30
16 5 V
5% 1 1 1100 30
14--15 5 V
5% 1 1 1011 30
12--13 5 V
5% 1 1 1010 30
10--11 5 V
5% 1 1 1001 30
8--9 5 V
5% 1 1 1000 30
7 5 V
5% 1 1 0111 30
5--6 5 V
5% 1 1 0110 30
2--4 5 V
5% 1 1 0101 30
Notes:
The M and N counter values in the pllc register must be set so that the VCO operates in the appropriate range
(see the data sheet). Choose the lowest value of N and then the appropriate value of M for
f
INTERNAL CLOCK
= f
CKI
x (M/(2N)) = f
VCO
/2.
Lock-in time represents the time following assertion of the PLLEN bit of the pllc register during which the PLL out-
put clock is unstable. The DSP must operate from the 1X CKI input clock or from the slow ring oscillator while the
PLL is locking. Completion of the lock-in interval is indicated by assertion of the LOCK flag.
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3.6 Power Management
There are three different control mechanisms for putting the DSP1611/17/18/27/28/29 into low-power modes: the
powerc
control register, the STOP
pin, and the AWAIT bit in the alf register. See the appropriate device's data
sheet for the typical power consumption in each mode.
3.6.1 powerc Control Register Bits
The powerc register has 9 bits that power down various portions of the chip and select the clock source. The
encoding for the powerc register is in Tables 3-28, 3-29, 3-30, and 3-31. The bits are described as follows:
XTLOFF: Assertion of the XTLOFF bit powers down the crystal oscillator or the small-signal input circuit disabling
the internal processor clock. Assertion of the XTLOFF bit also disables the crystal oscillator if it is used as a nonin-
verting input buffer. Because the oscillator and the small-signal input circuits take many cycles to stabilize, care
must be taken with the turn-on sequence as described in Section 3.6.5, Power Management Sequencing.
SLOWCKI: Assertion of the SLOWCKI bit selects the ring oscillator as the clock source for the internal clock
instead of CKI (or the clock synthesizer on the DSP1627/28/29). If CKI (or the clock synthesizer) is selected, the
ring oscillator is powered down. Switching of the clocks is synchronized so that no partial or short clock pulses
occur. Two nops should follow the instruction that sets or clears SLOWCKI.
NOCK: Assertion of the NOCK bit synchronously turns off the internal processor clock whether its source is pro-
vided by CKI, the clock synthesizer, or the ring oscillator. The NOCK bit can be cleared by either resetting the chip
with the RSTB pin or by asserting the INT0 or INT1 pins. Two nops should follow the instruction that sets NOCK.
INT0EN: This bit allows the INT0 pin to asynchronously clear the NOCK bit, thereby, allowing the device to con-
tinue program execution from where it left off without any loss of state. No chip reset is required. It is recom-
mended that, if INT0EN is to be used, the INT0 interrupt be disabled in the inc register so that an unintended
interrupt does not occur. After the program resumes, the INT0 interrupt in the ins register should be cleared.
INT1EN: This bit enables the INT1 pin to be used as the NOCK clear exactly like INT0EN previously described.
The following control bits power down the peripheral I/O units of the DSP and can be used to further reduce the
power consumption during standard sleep mode.
SIO1DIS: This is a powerdown signal to the SIO1 I/O unit. It disables the clock input to the unit, thus eliminating
any sleep power associated with the SIO1. Because the gating of the clocks might result in incomplete transac-
tions, it is recommended that this option be used in applications where the SIO1 is not used or if reset might be
used to reenable the SIO1 unit. Otherwise, the first transaction after reenabling the unit might be corrupted.
SIO2DIS: This bit powers down the SIO2 in the same way SIO1DIS powers down the SIO1.
PIODIS (DSP1617 only): This is a powerdown signal to the PIO I/O unit. It disables the clock input to the unit
eliminating any sleep power associated with the PIO. Because the gating of the clocks can result in incomplete
transactions, it is recommended that this option be used in applications where the PIO is not used or if reset can be
used to reenable the PIO unit. Otherwise, the first transaction after reenabling the unit might be corrupted. If the
DSP16A-compatible interrupts are being used, the PIO must remain powered up because the pioc register is
needed.
PHIFDIS (DSP1611/18/27/28/29 only): This is a powerdown signal to the PHIF I/O unit. It disables the clock input
to the unit eliminating any sleep power associated with the PIO. Because the gating of the clocks can result in
incomplete transactions, it is recommended that this option be used in applications where the PHIF is not used or if
reset might be used to reenable the PHIF unit. Otherwise, the first transaction after reenabling the unit might be
corrupted.
TIMERDIS: This is a timer disable signal that disables the clock input to the timer unit. Its function is identical to
the DISABLE field of the timerc control register. Writing a 0 to the TIMERDIS field continues the timer operation.
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
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3.6 Power Management
(continued)
3.6.1 powerc Control Register Bits (continued)
ECCPDIS (DSP1618/28 only): This is a powerdown signal to the error correction coprocessor. It disables the
clock input to the ECCP eliminating any sleep power associated with the coprocessor. Because the gating of the
clocks can result in incomplete transactions, it is recommended that this option be used in applications where the
ECCP is not used or if reset might be used to reenable the ECCP. Otherwise, the first transaction after reenabling
the unit can be corrupted.
Figures 3-20 and 3-21 demonstrate a functional view of the effect of the bits of the powerc register on the clock cir-
cuitry. They illustrate only the high-level operation of each bit. Not shown are the bits that power down the periph-
eral units.
Table 3-28. powerc Fields (DSP1617)
Bit 15 14 13 12 11 10 9--8 7 6 5 4 3--0
Field XTLOFF SLOWCKI NOCK INTOEN rsvd INT1EN rsvd SIO1DIS SIO2DIS PIODIS TIMERDIS
rsvd
Table 3-29. powerc Fields (DSP1611, DSP1627, and DSP1629)
Bit 15 14 13 12 11 10 9--8 7 6 5 4 3--0
Field XTLOFF SLOWCKI NOCK INTOEN rsvd INT1EN rsvd SIO1DIS SIO2DIS PHIFDIS TIMERDIS
rsvd
Table 3-30. powerc Fields (DSP1618 and DSP1628)
Bit 15 14 13 12 11 10 9--8 7 6 5 4 3--1 0
Field XTLOFF SLOWCKI NOCK INTOEN rsvd INT1EN rsvd SIO1DIS SIO2DIS PHIFDIS TIMERDIS rsvd ECCPDIS
Table 3-31. powerc Control Register Fields Description
Field Description
XTLOFF 1 = power down crystal oscillator or small-signal clock input.
SLOWCKI 1 = select ring oscillator clock.
NOCK 1 = disable internal processor clock.
INT0EN 1 = INT0 clears NOCK field.
INT1EN 1 = INT1 clears NOCK field.
SIO1DIS 1 = disable SIO1.
SIO2DIS 1 = disable SIO2.
PIODIS 1 = disable PIO (DSP1617 only).
PHIFDIS 1 = disable PHIF (DSP1611/18/27/28/29 only)
TIMERDIS 1 = disable timer.
ECCPDIS 1 = disable ECCP (DSP1618/28 only)
Note: The reserved (rsrvd) bits should always be written with zeros to make the program compatible with
future chip versions
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3.6 Power Management
(continued)
3.6.1 powerc Control Register Bits (continued)
5-4124
Notes:
The functions in the shaded ovals are bits in the powerc control register.
Bits used to power down the peripheral units and the ECCP (DSP1618 only) are not shown.
Deep sleep is the state arrived at by a hardware or software stop of the internal processor clock.
The switching of the multiplexers and the synchronous gate is designed to be clean in the sense that no partial clocks occur.
If the deep sleep state is entered with the ring oscillator selected, the internal processor clock is turned off before the ring oscillator is powered
down.
Figure 3-20. Power Management Using the powerc Register (DSP1611/17/18 Only)
CKI2
CRYSTAL
OSCILLATOR,
OR
SMALL SIGNAL
CLOCK
RING
OSCILLATOR
STOP
XTLOFF
MASK
OPTION
SELECTION
OFF
CKI
TTL
INPUT
CLOCK
RSTB
CMOS
INPUT
CLOCK
SYNC.
GATE
NOCK
SLOWCKI
SYNC.
MUX
INTERNAL
PROCESSOR
CLOCK
DEEP
SLEEP
CLEAR
NOCK
DISABLE
INT0
INT0EN
ON
INT1
INT1EN
DEEP
SLEEP
HW STOP
SW STOP
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3.6 Power Management
(continued)
3.6.1 powerc Control Register Bits (continued)
5-4124.a
Notes:
The functions in the shaded ovals are bits in the powerc control register. The functions in the nonshaded ovals are bits in the pllc control regis-
ter. Bits used to power down peripheral units and the ECCP (DSP1628) are not shown.
Deep sleep is the state arrived at by a hardware or software stop of the internal processor clock.
The switching of the multiplexers and the synchronous gate is designed to be clean in the sense that no partial clocks occur.
If the deep sleep state is entered with the ring oscillator selected, the internal processor clock is turned off before the ring oscillator is powered
down.
PLL select is the PLLSEL bit of pllc; PLL powerdown is the PLLEN bit of pllc.
Figure 3-21. Power Management Using the powerc Register (DSP1627/28/29 Only)
CKI2
CRYSTAL
OSCILLATOR,
OR
SMALL SIGNAL
CLOCK
RING
OSCILLATOR
STOP
XTLOFF
MASK-PROGRAMMABLE
OPTION
OFF
CKI
RSTB
CMOS
INPUT
CLOCK
SYNC.
GATE
NOCK
SLOWCKI
SYNC.
MUX
INTERNAL
PROCESSOR
CLOCK
DEEP
SLEEP
CLEAR NOCK
DISABLE
INT0
INT0EN
ON
INT1
INT1EN
DEEP
SLEEP
HW STOP
SW STOP
PLLEN
PLL
PLLSEL
f
CKI
f
VCO
/2
f
slow clock
f
internal clock
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3.6 Power Management
(continued)
3.6.2 STOP Pin
Assertion (active-low) of the STOP pin has the same effect as setting the NOCK bit in the powerc register. The
internal processor clock is synchronously disabled until the STOP pin is returned high. If the STOP pin is returned
high, program execution continues from where it left off without any loss of state. No chip reset is required. For the
DSP1627/28/29, the PLL remains running, if enabled, during STOP assertion.
3.6.3 The pllc Register Bits (DSP1627/28/29 Only)
The PLLEN bit of the pllc register can be used to power down the clock synthesizer circuitry. Before shutting down
the clock synthesizer circuitry, the system clock should be switched to either CKI by using the PLLSEL bit of pllc or
to the ring oscillator by using the SLOWCKI bit of powerc.
3.6.4 AWAIT Bit of the alf Register
Setting the AWAIT bit of the alf register causes the processor to go into the standard sleep state or power-saving
standby mode. Operation of the AWAIT bit is unchanged from the DSP1610. In this mode, only the minimum cir-
cuitry required to process an incoming interrupt remains active. An interrupt returns the processor to the previous
state, and program execution continues. The action resulting from setting the AWAIT bit and the action resulting
from setting bits in the powerc register are mostly independent. As long as the processor is receiving a clock,
whether slow or fast, the DSP can be put into standard sleep mode with the AWAIT bit. If the AWAIT bit is set, the
STOP pin can be used to stop and later restart the processor clock returning to the standard sleep state. If the pro-
cessor clock is not running, however, the AWAIT bit cannot be set. If executing code with two or more wait-states,
it is recommended that the alf register be set from within the cache to prevent any pending interrupt from being ser-
viced until after the DSP enters the AWAIT state.
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3.6 Power Management
(continued)
3.6.5 Power Management Sequencing
There are important considerations for sequencing the power management modes. Both the crystal oscillator and
the small-signal clock input circuits have start-up delays that must be taken into account. Also, the chip might or
might not need to be reset following a return from a low-power state.
Devices with the crystal oscillator or small-signal input clocking option can use the XTLOFF bit in the powerc reg-
ister to power down the on-chip oscillator or the small-signal circuitry, thereby, reducing the power dissipation.
When reenabling the oscillator or the small-signal circuitry, it is important to bear in mind that a start-up interval
exists during which time the clocks are not stable. Two scenarios exist here:
1. Immediate Turn-Off--Turn-On with RSTB: This scenario applies to situations where the target device is not
required to execute any code while the crystal oscillator or small-signal input circuit is powered down and where
restart from a reset state can be tolerated. In this case, the processor clock derived from either the oscillator or
the small-signal input is running if XTLOFF is asserted. This effectively stops the internal processor clock. If the
system chooses to reenable the oscillator or small-signal input, a reset of the device is required. The reset pulse
must be of sufficient duration for the oscillator start-up interval to be satisfied. A similar interval is required for
the small-signal input circuit to reach its dc operating point. A minimum reset pulse of 20 ms is adequate. The
falling edge of the reset signal (RSTB) asynchronously clears the XTLOFF field, thus, reenabling the power to
the oscillator or small-signal circuitry. The target DSP then starts execution from a reset state following the rising
edge of RSTB.
2. Running from Slow Clock While XTLOFF Active: This second scenario applies to situations where the device
needs to continue execution of its target code if the crystal oscillator or small-signal input is powered down. In
this case, the device switches to the slow ring oscillator clock first by enabling the SLOWCKI field before writing
a 1 to the XTLOFF field. Two nops are needed in between the two write operations to the powerc register. The
target device then continues execution of its code at slow speed while the crystal oscillator or small-signal input
clock is turned off. Switching from the slow clock back to the high-speed crystal oscillator clock is then accom-
plished in three user steps. First, XTLOFF is cleared. Then, a user-programmed routine sets the internal timer
to a delay to wait for the crystal's oscillations to become stable. When the timer counts down to zero, the high-
speed clock is selected by clearing the SLOWCKI field either in the timer's interrupt service routine or following a
timer polling loop.
For devices with the PLL and slow clock ring oscillator option, the use of the internal ring oscillator (slow clock) is
required if entering the low-power state. For reliable operation in all environments, the ring oscillator must be
selected as the clock source before the PLL is turned off.
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3.6 Power Management
(continued)
3.6.6 Power Management Examples
The following examples illustrate the more significant options for reducing the power dissipation.
Standard Sleep Mode. This is the standard sleep mode. The alf register's AWAIT bit is set while the processor is
clocked with a high-speed clock (CKI). Peripheral units can be turned off to further reduce the sleep power.
powerc=0x00F0 /* Turn off all peripheral units, core running with CKI */
sleep: a0=0x8000 /* Preload a0 with alf setting */
do 1 { /* Use cache to make instructions noninterruptible */
alf=a0 /* Stop internal DSP clock. Interrupt circuits active */
nop /* Needed for bedtime execution */
}
nop /* Only sleep power consumed here until */
/* interrupt wakes up the device */
next: . . . /* User code executes here */
powerc=0x0 /* Turn peripheral units back on */
Sleep with Slow Internal Clock
1
. In this case, the ring oscillator is selected to clock the processor before the
device is put to sleep. This will reduce the power dissipation while waiting for an interrupt to continue program
execution.
powerc=0x40F0 /* Turn off all peripheral units and select slow clock */
2*nop /* Wait for it to take effect */
sleep: a0=0x8000 /* Preload a0 with alf setting */
do 1 { /* Use cache to make instructions noninterruptible */
alf=a0 /* Stop internal DSP clock. Interrupt circuits active */
nop /* Needed for bed-time execution */
}
nop /* Only sleep power consumed here until */
/* interrupt wakes up the device */
next: . . . /* User code executes here */
powerc=0x00F0 /* Select high-speed clock */
2*nop /* Wait for it to take effect */
powerc=0x0000 /* Turn peripheral units back on */
1. In this case, the wake-up latency is determined by the period of the ring oscillator clock.
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3.6 Power Management
(continued)
3.6.6 Power Management Examples (continued)
Sleep with Slow Internal Clock and Crystal Oscillator/Small-Signal Disabled
1
. If the target device contains
the crystal oscillator or the small-signal clock option, the clock input circuitry can be powered down to further
reduce power. In this case, the slow clock must be selected first.
powerc=0x40F0 /* Turn off all peripheral units and select slow clock */
2*nop /* Wait for it to take effect */
powerc=0xC0F0 /* Turn off the crystal oscillator */
sleep: a0=0x8000 /* Preload a0 with alf setting */
do 1 { /* active */
alf=a0 /* Stop internal DSP clock. Interrupt circuits active */
nop /* Needed for bedtime execution */
}
nop /* Only sleep power consumed here until */
/* interrupt wakes up the device */
powerc=0x40F0 /* Clear XTLOFF, reenable oscillator/small-signal */
call xtlwait /* Wait until oscillator/small-signal is stable */
next: powerc=0x00F0 /* Select high-speed clock */
2*nop /* Wait for it to take effect */
powerc=0x0000 /* Turn peripheral units back on */
Software Stop. In this case, all internal clocking is disabled. INT0, INT1, or RSTB can be used to reenable the
clocks. If the device uses the crystal oscillator or small-signal clock option, the power management must be done
in correct sequence.
powerc=0x4000 /* SLOWCKI asserted */
2*nop /* Wait for it to take effect */
powerc=0xD000 /* XTLOFF asserted if applicable and INT0EN asserted */
inc=NOINT0 /* Disable the INT0 interrupt */
sopor: powerc=0xF000 /* NOCK asserted, all clocks stop */
/* Minimum switching power consumed here */
3*nop /* Some nops will be needed */
/* INT0 pin clears the NOCK field, clocking resumes */
next: powerc=0x4000 /* INT0EN cleared and XTLOFF cleared, if applicable */
call xtlwait /* Wait for the crystal oscillator/small-signal to */
/* stabilize, if applicable */
powerc=0x0 /* Clear SLOWCKI field, back to high speed */
2*nop /* Wait for it to take effect */
ins=0x0010 /* Clear the INT0 status bit */
1. In this case, the wake-up latency is dominated by the crystal oscillator or small-signal start-up period. xltwait is a called subroutine that waits
for stabilization.
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3.6 Power Management
(continued)
3.6.6 Power Management Examples (continued)
In this case also, the wake-up latency is dominated by the crystal oscillator or small-signal start-up period. The
previous examples do not provide an exhaustive list of options available to the user. These options depend on:
1. The clock source to the processor.
2. Whether the user chooses to power down the peripheral units.
3. The operational state of the crystal oscillator/small-signal clock input either powered or unpowered.
4. Whether the internal processor clock is disabled through hardware or software.
5. The combination of power management modes the user chooses.
6. Whether or not the PLL is enabled.
Power Management Examples with the PLL (DSP1627/28/29 Only)
The following examples show the more significant options for reducing power dissipation if operation with the PLL
clock synthesizer is desired.
Standard Sleep Mode, PLL Running. This mode is entered in the same manner as without the PLL. While the
input to the clock synthesizer (CKI) remains running, the alf register's AWAIT bit is set. The PLL continues to run
and dissipate power. Peripheral units can be turned off to further reduce the sleep power.
powerc=0x00F0 /* Turn off peripherals, core running with PLL */
sleep: a0=0x8000 /* Set alf register in cache loop if running from */
do 1 { /* external memory with >1 wait-state */
alf=a0 /* Stop internal processor clock, interrupt circuits */
nop /* active */
}
nop /* Needed for bedtime execution. Only sleep power plus PLL */
nop /* power consumed here... Interrupt wakes up the device. */
next: . . . /* User code executes here */
powerc=0x0000 /* Turn peripheral units back on */
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3-61
3.6 Power Management
(continued)
3.6.6 Power Management Examples (continued)
Sleep with Slow Internal Clock, PLL Running. In this case, the ring oscillator is selected to clock the processor
before the device is put to sleep. This reduces power dissipation while waiting for an interrupt to continue program
execution.
powerc=0x40F0 /* Turn off peripherals and select slow clock */
2*nop /* Wait for slow clock to take effect */
sleep: a0=0x8000 /* Set alf register in cache loop if running from */
do 1 { /* external memory with >1 wait-state */
alf=a0 /* Stop internal processor clock, interrupt circuits */
nop /* active */
}
nop /* Needed for bedtime execution. Only sleep power plus PLL */
nop /* power consumed here... Interrupt wakes up the device. */
next: . . . /* User code executes here */
powerc=0x00F0 /* Select high-speed PLL based clock */
2*nop /* Wait for it to take effect */
powerc=0x0000 /* Turn the peripheral units back on */
Sleep with Slow Internal Clock and Crystal Oscillator/Small-Signal Disabled, PLL Disabled. If the target
device contains the crystal oscillator or the small-signal clock option, the clock input circuitry can be powered down
to further reduce power. In this case, the slow clock must be selected first and then the PLL must be disabled
because the PLL cannot run without the clock input circuitry being active.
powerc=0x40F0 /* Turn off peripherals and select slow clock */
2*nop /* Wait for slow clock to take effect */
pllc=0x29F2 /* Disable PLL (assume N=1, M=20, LF=1001) */
powerc=0xC0F0 /* Disable crystal oscillator */
sleep: a0=0x8000 /* Set alf register in cache loop if running from */
do 1 { /* external memory with >1 wait-state */
alf=a0 /* Stop internal processor clock, interrupt circuits */
nop /* active */
}
nop /* Needed for bedtime execution. Only sleep power plus PLL */
nop /* power consumed here... Interrupt wakes up the device. */
powerc=0X40F0 /* Clear XTLOFF, leave PLL disabled */
call xtlwait /* Wait until crystal oscillator/small-signal is stable */
pllc=0xE9F2 /* Enable PLL, continue to run off slow clock */
call pllwait /* Loop to check for LOCK flag assertion */
next: powerc=0x00F0 /* Select high-speed PLL based clock */
2*nop /* Wait for it to take effect */
powerc=0x0000 /* Turn the peripheral units back on */
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3.6 Power Management
(continued)
3.6.6 Power Management Examples (continued)
Software Stop, PLL Disabled. In this case, all internal clocking is disabled. INT0, INT1, or RSTB can be used to
reenable the clocks. If the device uses the crystal oscillator or small-signal clock option, the power management
must be done in the correct sequence with the PLL being disabled before shutting down the clock input buffer.
powerc=0x40F0 /* Turn off peripherals and select slow clock */
2*nop /* Wait for slow clock to take effect */
pllc=0x29F2 /* Disable PLL (assume N=1, M=20, LF=1001) */
powerc=0xD000 /* XTLOFF asserted, if applicable and INT0EN asserted */
sopor: powerc=0xF000 /* NOCK asserted, all clocks stop */
/* Minimum switching power consumed here */
3*nop /* Some nops will be needed */
/* INT0 pin clears NOCK field, clocking resumes */
cont: powerc=0x4000 /* INTOEN cleared and XTLOFF cleared, if applicable */
call xtlwait /* Wait until crystal oscillator/small-signal is */
/* stable if applicable */
pllc=0xE9F2 /* Enable PLL, continue to run off slow clock */
call pllwait /* Loop to check for LOCK flag assertion */
powerc=0x0000 /* Select high-speed PLL based clock */
2*nop /* Wait for it to take effect */
ins=0x0010 /* Clear the INT0 status bit */
An example subroutine for xtlwait follows:
xtlwait:
timer0=0x2710 /* Load a count of 10,000 into the timer */
timerc=0x0010 /* Start the timer with a PRESCALE of two */
inc=0x0000 /* Disable the interrupts */
loop1: a0=ins /* Poll the ins register */
a0=a0 & 0x0100 /* Check bit 8 (TIME) of the ins register */
if eq goto loop1 /* Loop if the bit is not set */
ins=0x0100 /* Clear the TIME interrupt bit */
return /* Return to the main program */
An example subroutine for pllwait follows:
pllwait: if lock return /* wait for lock flag to be set */
goto pllwait
Chapter 4
Instruction Set
CHAPTER 4. INSTRUCTION SET
CONTENTS
4
Instruction Set.......................................................................................................................4-1
4.1
Notation ......................................................................................................................4-2
4.2
Instruction Cycle Timing .............................................................................................4-3
4.3
Addressing Modes......................................................................................................4-3
4.3.1
Register Indirect Addressing .......................................................................4-3
4.3.2
Compound Addressing ................................................................................4-5
4.3.3
Direct Data Addressing ...............................................................................4-7
4.4
Processor Flags .........................................................................................................4-9
4.5
Instruction Set ..........................................................................................................4-11
4.5.1
Control Instructions ...................................................................................4-12
4.5.2
Cache Instructions .....................................................................................4-14
4.5.3
Data Move Instructions ..............................................................................4-15
4.5.4
Special Function Group .............................................................................4-19
4.5.5
Multiply/ALU Group ...................................................................................4-22
4.5.6
F3 ALU Instructions ...................................................................................4-29
4.5.7
BMU Instructions .......................................................................................4-30
4.5.8
Assembler Ambiguities ..............................................................................4-35
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4-1
4 Instruction Set
All DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and DSP1629 instructions are 16 bits wide and resemble
C code. The instructions are grouped into seven categories:
*
Control instructions direct program flow and can be conditionally executed on the basis of the state of internal
flags.
*
Cache instructions implement low-overhead loops by loading a set of instructions into a cache memory and
repetitively executing them (up to 127 times).
*
Data move instructions transfer data between registers, memory, and accumulators. Immediate loads of regis-
ters and accumulators are also possible.
*
Special function instructions perform accumulator operations such as incrementing, rounding, negation, logical
left shifts, and arithmetic right shifts. Special function instructions also permit a single-cycle 32-bit load of an
accumulator from either the
p
or
y
register. These special function instructions can be conditionally executed on
the basis of the state of internal flags.
*
Multiply/ALU instructions are the primary instructions for signal-processing programs that perform multiply/accu-
mulate, logical, and other ALU functions. They also transfer data between memory and registers in the data arith-
metic unit. Flags are set based on accumulator results.
*
ALU instructions perform operations between two accumulators, between an accumulator and the product regis-
ter, or between an accumulator and an immediate data word. The operations are add, subtract, AND, OR, and
exclusive OR. Flags are set based on accumulator results.
*
BMU instructions perform full barrel shifting, extraction of an exponent, normalization, and extraction or insertion
of an arbitrary field of bits on the accumulators. An instruction shuffles data between the accumulators and one
of the alternate accumulators. Flags are set based on results.
Note:
The only instruction groups that set flags are the multiply/ALU, special function, ALU, and BMU groups.
Also, certain flags are set by the BIO.
The following sections describe the notation, the instruction cycle timing, the addressing modes, the internal flags
used by conditional instructions, and the seven groups of instructions. Appendix B describes each instruction indi-
vidually.
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4.1 Notation
These operators are used to describe the instruction set:
For all instructions listed in this chapter, the following are true:
*
Brackets, [ ], are
not
part of the instruction syntax but indicate that the enclosed item is optional.
*
Parentheses, ( ), and braces, { },
are
part of the instruction syntax and
must
appear where shown in the instruc-
tion.
*
Arrow brackets, < >, are
not
part of the instruction syntax but indicate that one of the enclosed items or a proper
statement
must
be included to form a valid instruction.
*
Upper-case characters in instructions denote a replacement character that is to be replaced by a specific value.
For example, consider the pointer register
rM
, where M is replaced by 0, 1, 2, or 3.
F Titles
F1, F2, F3, and F4 are terms used to differentiate classes of instructions or statements.
They are defined as follows:
F1: Multiply/ALU operator statements
F2: Operator statements for special function instructions (if CON F2)
F3: ALU instructions
F4: BMU instructions
The valid instruction groups for the DSP device are represented in Tables 4-1 to 4-17. The items in these tables
that are written in lower-case letters are proper statements and must appear where shown in the instruction. The
items with capital letters are not proper statements and are replaced with immediate data, a register name, or a
condition. For example,
aD
would be either
a0
or
a1
. The valid replacement values for upper-case items are listed
in the replacement tables.
The ALU performs 36-bit operations, but the operands can be 16, 32, or 36 bits.
Operator Meaning
* 16 x 16 32-bit multiplication
(Denotes register-indirect addressing if used as a prefix to an address register.)
+ 36-bit addition
36-bit subtraction
++ Register postincrement
Register postdecrement
>> Arithmetic right shift
<< Arithmetic left shift
>>> Logical right shift
<<< Logical left shift
& 36-bit bitwise AND
| 36-bit bitwise OR
^ 36-bit bitwise EXCLUSIVE OR
: Compound addressing
~ One's complement
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4-3
4.2 Instruction Cycle Timing
For the DSP1611/17/18/27/28/29, the instruction cycle is defined as the execution time of a single-cycle instruction
in the absence of wait-states. For a 60 MHz 2x CKI or a 30 MHz 1x CKI, the instruction cycle is 33 ns. For the
DSP1627/28/29, an instruction cycle is based on the frequency of the clock source that is selected (ring oscillator,
CKI, or clock synthesizer). Instructions are all one or two 16-bit words and, typically, execute in one or two instruc-
tion cycles.
4.3 Addressing Modes
There are three different locations for data in the DSP: in a register, in memory, or in an instruction. In this section,
addressing refers to the way the location of the data is specified in an instruction. The DSP1611/17/18/27/28/29
instructions use the following modes of addressing:
1.
Register-direct:
Data is already in a register and can be used directly in a command (e.g.,
p = x * y
). The reg-
ister is specified in the instruction.
2.
Register-indirect:
Data is located in memory and is pointed to by an addressing register defined in the instruc-
tion.
3.
Immediate:
Data is located in part of a single-word instruction (short-immediate) or is the second word of a two-
word instruction (long-immediate). For a short immediate instruction, 9 bits of data can only be transferred to
one of the registers in the YAAU (except for
ybase
) and no other action occurs. For a long immediate instruc-
tion, two locations of program space are required so that 16 bits of data from the second word of the instruction
can be transferred to one of the general set of registers.
4.
Compound addressing:
A combination of the above cases 1 and 2 in which the data is in both a register and in
memory. A single instruction can call for a swap of the data. This is compound
addressing; one addressing reg-
ister points to a memory location (or locations) for a read followed by a write. The instruction also specifies a
register for the swap, and the addressing register can be postmodified.
5.
Direct-data addressing:
A combination of case 1, 2, and 3 in which 5 bits from the instruction are concatenated
with 11 bits previously stored in the
ybase
register to form an address to Y-memory space. The instruction also
selects one of 16 registers to be the source or destination of data exchange with the Y memory.
6.
Virtual-shift (modulo) addressing:
A special case of register-indirect addressing in which an implicit circular
shift register is established for zero-overhead virtual-shift addressing. This mode enables the creation of an arbi-
trarily sized portion of contiguous RAM locations to behave as if it were a physical delay or shift register without
actually moving data within RAM. The virtual-shift buffer is implemented in memory by storing the data at fixed
locations and incrementing the memory pointer in a modular fashion. Virtual-shift addressing is described in
detail in Section 5.3.4, Addressing Modes.
4.3.1 Register Indirect Addressing
Indirect addressing allows a register to be used as a pointer to a memory location. The following instructions are
examples of register indirect addressing.
x=*pt++
*r0=y
The first instruction says to perform a memory read from the memory location pointed to by the
pt
register, put that
data in the
x
register, and increment the address in
pt
by one. The second instruction says to look at the address
in the
r0
register and write the data from the
y
register (upper half) to the memory location in
r0
. In both cases, the
register
r0
or
pt
is said to point to the data in memory because the register contains a 16-bit address for a memory
read or write.
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4.3 Addressing Modes
(continued)
4.3.1 Register Indirect Addressing
(continued)
Mnemonics have been defined for indirect addressing. X represents data in the X-memory space, and Y repre-
sents data in the Y-memory space. They can have the following replacement values:
X = *pt++ or *pt++i
Y = one of *rM, *rM++, *rM , or *rM++j
Note:
M = one of 0, 1, 2, 3
i = postincrement or postdecrement register
j = postincrement or postdecrement register
The asterisk preceding the Y or X address register stands for the data pointed to by the address in the register.
The mnemonics have the following meaning:
*
*rM.
This statement means the data pointed to by the address in the register
rM
. The contents of the register
are not altered by the operation.
*
*rM++, *pt++.
The
++
following the address register indicates a postincrement of the address register. This
example means the data pointed to by the address in the register; add 1 to the contents of the register after the
operation is complete.
*
*rM .
The
following the address register indicates a postdecrement of the address register. This example
means the data pointed to by the address of the register: subtract 1 from the contents of the register after the
operation is complete.
*
*rM++j.
The
++j
following the address register indicates a postincrement of the address register. This example
means the data pointed to by the address in the register and add the value of register
j
to the contents of the
address register after the operation is complete. Negative values of
j
yield a postdecrement.
*
*pt++i.
The
++i
following the address register indicates a postincrement of the address register. This example
means the data pointed to by the address in the register and add the value of register
i
to the contents of the
address register after the operation is complete. Negative values of
i
yield a postdecrement.
Modulo (virtual shift) addressing uses indirect addressing to form the equivalent of a cyclic shift register within the
RAM. Addresses loaded into registers
rb
and
re
define the first and last physical addresses of the cyclic shift reg-
ister respectively. If a register is used as a memory pointer, its value is compared with
re
. If its value is equal to the
contents of
re
and the postincrement is +1, the value in
rb
is copied into the register after the memory access is
complete.
Note:
Whenever
re
contains a value not equal to zero, modulo addressing is active. On reset, the value of
re
is
zero. Whenever modulo addressing is not used, this register should contain zero and should not be used to
store any number other than the address of the end of a modulo. Modulo addressing works only with
*rM++
,
*rMpz
, and
*rMzp
. Section 5.3, Y Address Arithmetic Unit (YAAU) has more detail on modulo addressing.
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4-5
4.3 Addressing Modes
(continued)
4.3.2 Compound Addressing
Compound addressing is a memory read/write operation using only one pointer register. The term Z specifies a
source and a destination for a compound RAM read followed by a write sequence. The mnemonics for Z are a
shorthand notation for the compound addressing functions explained below and shown in Table 4-1. The term
temp used in the descriptions is a hypothetical register used for illustration only. Note that postincrementation can
occur after either Step 2 or Step 3 in Table 4-1.
Note: M can be 0, 1, 2, or 3. R can be one of the general set of registers in Table 4-9. R and rM must not be the
same register (e.g., r1pz : r1). The two alphanumerics in mnemonics zp, pz, m2, and jk stand for the postin-
crements after Step 2 and Step 3. z is zero, p is plus 1, m is minus 1, 2 is plus 2, and j and k are increments
from the j and k registers.
Table 4-1. Compound Addressing Instructions
Instruction Operations
Z : R Step 1 Step 2 Step 3
*rMzp : R TEMP = R R = *rM *rM++ = TEMP
*rMpz : R TEMP = R R = *rM++ *rM = TEMP
*rMm2 : R TEMP = R R = *rM *rM++2 = TEMP
*rMjk : R TEMP = R R = *rM++j *rM++k = TEMP
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4.3 Addressing Modes
(continued)
4.3.2 Compound Addressing (continued)
Figure 4-1 shows the four compound address instructions pictorially.
5-4148
j or k can be positive or negative.
Figure 4-1. Compound Addressing
*rMzp : R
INITIAL ADDRESS IN rM
FINAL ADDRESS IN rM
Y MEMORY
Y ADDRESSING
REGISTER
*rMpz : R
INITIAL ADDRESS IN rM
FINAL ADDRESS IN rM
*rMm2 : R
INITIAL ADDRESS IN rM
FINAL ADDRESS IN rM
*rMjk : R
INITIAL ADDRESS IN rM
FINAL ADDRESS IN rM
R
R
R
R
j
k
NEXT ADDRESS IN rM
*rM
*(rM + 1)
TEMP
*rM
*(rM + 1)
*(rM 1)
*rM
*((rM 1) + 2)
NEXT ADDRESS IN rM
...
...
*rM
*(rM + j)
*((rM + j) + k)
TEMP
TEMP
TEMP
2
2
2
2
1
3
1
1
1
3
3
3
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4-7
4.3 Addressing Modes
(continued)
4.3.2 Compound Addressing (continued)
As with other instructions that use the y, a0, and a1 registers, the following rules apply if using the compound
addressing mode:
*
If clearing of the low half of the register is enabled (according to the CLR field of the auc register), the low half of
the register is cleared when the high half is loaded.
*
If saturation on overflow is enabled (according to the SAT field of the auc register), the value of data transferred
from the accumulator is limited. (See Section 5.1, Data Arithmetic Unit.)
Virtual-shift addressing can be used with compound addressing. The contents of the address register are com-
pared with the contents of register re during both the read and write cycles. If the contents of the address register
are equal to the contents of re during the read cycle and the *rMpz mode is specified, rM is loaded with the con-
tents of rb. If the contents of the address register are equal to the contents of re during the write cycle and the
*rMzp mode is specified, rM is loaded with the contents of rb. Two of the compound addressing formats (*rMm2
and *rMjk) do not work with modulo addressing.
4.3.3 Direct Data Addressing
Figure 4-2 shows the operation of direct data addressing used in two instructions: DR = *(OFFSET) and
*(OFFSET) = DR. The contents of register DR are read from or written to the RAM memory location at the direct
address. The ybase register holds the base address used for the direct address. It can be loaded with any 16-bit
value, but only the upper 11 bits are used for the address. The ybase register can be thought of as specifying one
of 2048 32-word pages. The OFFSET is a 5-bit address (OFFSET from the ybase register) and is specified in the
opcode. The upper 11 bits of ybase are concatenated with the OFFSET to form the direct address.
The register DR, specified in the opcode by bits 6--9, can be one of a set of 16. They are listed as follows.
Table 4-2. Direct Data Addressing
Register DR Field Register DR Field
r0 0000 y 1000
r1 0001 yl 1001
r2 0010 p 1010
r3 0011 pl 1011
a0 0100 x 1100
a0l 0101 pt 1101
a1 0110 pr 1110
a1l 0111 psw 1111
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4.3 Addressing Modes
(continued)
4.3.3 Direct Data Addressing (continued)
5-4149
Figure 4-2. Direct Data Addressing
Example of *(OFFSET) = DR
a0=0xface /* Initialize value in accumulator. */
ybase=0x1232 /* Store the upper 11 bits of 0x1232 into ybase as follows: */
/* Place (0001 0010 001) into the upper 11 bits of ybase */
*(0x15)=a0 /* Offset=0x15; Store (1 0101) into lower 5 bits of ybase */
/* Address in ybase is 0x1215, demonstrated below: */
/* 0001 0010 001 = upper 11 bits */
/* 1 0101 = lower 5 bits */
/* 0001 0010 0011 0101 = address=0x1235 */
/* Store 0xface (contents of a0) into location 0x1235. */
11
5
5
RAM
REGISTER DR
BASE
ybase
REGISTER
IN YAAU
CONTROL
T-FIELD DR SPECIFIED
1
OFFSET
16
16
0
4
5
15
15 10 9 5 4 0
6
YAB
YDB
16
OFFSET
XDB
INSTRUCTION
IN X-MEMORY
SPACE
DR = *(OFFSET)
or
*(OFFSET) = DR
16
5
11
R/W
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4-9
4.4 Processor Flags
Control and special function instructions can be conditionally executed on the basis of internal flags set by the fol-
lowing conditions:
*
A previous ALU operation
*
A previous BMU operation
*
A previous special function instruction
*
The condition of one of the counters
*
The value of a randomly set bit
*
A test by the BIO port
*
An interrupt from the JTAG port
Functional operations on the accumulators set the flags as described above. Loading the accumulators with data
move instructions or multiply/ALU transfer statements does not set flags.
Four of the basic processor flags are defined below. They can be set by either ALU or BMU operations. These
flags and their meanings are given below:
LMI Logical Minus--A logical minus is determined by the state of bit 35 of the accumulator after the last DAU or
BMU operation result. If bit 35 = 1, the result is a negative number and LMI is true.
LEQ Logical Equal--A logical equal is determined by testing bits 35--0 of the last DAU or BMU operation
result. If these bits are all zero, the result is zero and LEQ is true.
LLV Logical Overflow (36-bit Overflow)--LLV is true if the sign of the result of an operation cannot be repre-
sented in a 36-bit accumulator.
LMV Mathematical Overflow (32-bit Overflow)--LMV is true if bit 31 of the accumulator differs from any of the
guard bits (32--35) after the last DAU or BMU operation. This indicates a number not representable in
32 bits.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Instruction Set December 2001
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DRAFT COPY
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4.4 Processor Flags
(continued)
Table 4-3 shows the complete set of flags that can be used in conditional instructions and their meanings. The
state of the four internal flags (defined above) that causes the condition to be true is enclosed in parentheses after
the description. For example, if testing the condition le, the result is true if either the logical minus (LMI) or logical
equal (LEQ) flags are true.
Availability of flags: The BIO and four of the BMU flags (oddp, evenp, nmns1, and mns1) can be read from the alf
register. The LMI, LEQ, LLV, and LMV can be read from the psw register.
Testing each of these conditions increments the respective counter being tested.
The heads or tails condition is determined by a randomly set or cleared bit respectively. The bit is randomly set with probability of
0.5. The random bit is generated by a 10-stage pseudorandom sequence generator (PSG) that is updated after either a heads or
tails test. The pseudorandom sequence can be reset by writing any value to the pi register except during an interrupt service rou-
tine. While in an interrupt service routine, writing to the pi register will update the register and not reset the PSG. If not in an inter-
rupt service routine, writing to the pi register will reset the PSG. (The pi register will be updated but will be written with the
contents of the PC on the next instruction.) Interrupts must be disabled when writing to the pi register. If an interrupt is taken
after the pi write--before pi is updated with the PC value, the ireturn instruction will not return to the correct location. If the RAND
bit in the auc register is set, however, writing the pi register will never reset the PSG. A random rounding function can be imple-
mented with either heads or tails. (For further information, see Section 5.1.6, DAU Pseudorandom Sequence Generator (PSG).)
These flags are only set after an appropriate write to the BIO port (cbit register).
DSP1627/28/29 only.
DSP1618/28 only.
Table 4-3. Flags (Conditional Mnemonics)
Test Meaning Test Meaning
pl Result is nonnegative (not LMI) (
0). mi Result is negative (LMI) (< 0).
eq Result is equal to 0 (LEQ) (= 0). ne Result is not equal to 0 (not LEQ) (
0).
gt Result is greater than 0 (not LMI and
not LEQ) (> 0).
le Result is less than or equal to 0 (LMI or
LEQ) (
0).
lvs Logical overflow set (LLV). lvc Logical overflow clear (not LLV).
mvs Mathematical overflow set (LMV). mvc Mathematical overflow clear (not LMV).
c0ge
Counter 0 greater than or equal to 0. c0lt
Counter 0 less than 0.
c1ge
Counter 1 greater than or equal to 0. c1lt
Counter 1 less than 0.
heads
Pseudorandom sequence bit set. tails
Pseudorandom sequence bit clear.
true The condition is always satisfied in an if
instruction.
false The condition is never satisfied in an if
instruction.
allt
All true--all BIO input bits tested com-
pared successfully.
allf
All false--no BIO input bits tested com-
pared successfully.
somet
Some true--some BIO input bits tested
compared successfully.
somef
Some false--some BIO input bits
tested did not compare successfully.
oddp Odd parity from BMU operation. evenp Even parity from BMU operation.
mns1 Minus 1 result of BMU operation. nmns1 Not minus 1 result of BMU operation.
npint Not PINT used by hardware develop-
ment system.
njint Not JINT used by hardware develop-
ment system.
lock
The PLL has achieved lock and is sta-
ble.
ebusy
ECCP busy indicates error correction
coprocessor activity.
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Instruction Set
Agere Systems Inc.
DRAFT COPY
4-11
4.5 Instruction Set
Control
goto JA
goto B
if CON
goto/call/return
call JA
icall
Cache
do K {
instr1
.
.
instrN
}
redo K
Data Move
R = IM16
SR = IM9
R = aS[l]
aT[l] = R
R = Y
Y = R
Z : R
DR = *(OFFSET)
*(OFFSET) = DR
push(*rM) = R
R = pop(*rM)
Special Function
if CON F2
ifc CON F2
Multiply/ALU
F1 Y
F1 Y = a0[l]
F1 Y = a1[l]
F1 x = Y
F1 y[l] = Y
F1 y = Y
F1 y = a0
F1 y = a1
F1 aT[l] = Y
F1 Y = y[l]
F1 Z : y[l]
F1 Z : aT[l]
F1 Z : y
F3 ALU
aD = aS OP aT
aD = aS OP p
aD = aS<h, l> OP IM16
aS aT
aS p
aS <h, l> IM16
aS & aT
aS & p
aS < h, l> & IM16
BMU
aD = aT SHIFT aS
aD = aS SHIFT arM
aD = aS SHIFT IM16
aD = exp (aS)
aD = norm (aS, arM)
aD = extracts (aS, arM)
aD = extractz (aS, arM)
aD = extracts (aS, IM16)
aD = extractz (aS, IM16)
aD = insert (aS, arM)
aD = insert (aS, IM16)
aD = aS : aaT
x = *pt++[i]
x = *pt++[i]
x = *pt++[i]
x = *pt++[i]
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Instruction Set December 2001
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DRAFT COPY
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4.5 Instruction Set
(continued)
4.5.1 Control Instructions
Control instructions implement goto, call, and return commands. There is no latency when branching, i.e., the
instruction executed following the control instruction has the address specified in the PC after execution of the con-
trol instruction. Control instructions are executed either conditionally or unconditionally. Both the condition and its
complement are available for use in control instructions. Control instructions can not be executed in the cache.
Control instructions can be conditioned on the basis of the DSP flags defined in Table 4-3. The result of the most
recent accumulator operation prior to the control instruction establishes the state of the flags for the conditions
associated with logical or mathematical functions. Table 4-4 lists the control instructions along with a description of
how each instruction is encoded, the number of instruction cycles required to execute each instruction, and the
number of memory locations (in words) required for the encoding of each instruction. Table 4-5 describes the
replacements for the upper-case fields shown in Table 4-4.
Control instructions cannot be used in the cache. Table 4-5 lists replacements for the upper-case fields shown in this table.
The goto JA and call JA instructions should not be placed in the last or next-to-last instruction before the boundary of a 4 Kword
page. If the goto or call is placed there, the program counter increments to the next page and the jump is to the next page rather than
the desired current page.
If PC, pt, or pr point to external memory, add programmed wait-states to the number of cycles.
The icall instruction is reserved for use by the hardware development system.
DSP1627/28/29 only.
DSP1618/28 only.
Table 4-4. Control Instructions
Control Instruction
Equivalent Instruction
(if applicable)
Encoded As
Number of
Cycles
Number of
Words
goto JA
goto pt
call JA
call pt
return
goto pr goto JA
goto B
call JA
goto B
goto B
2
1
if CON goto JA
if CON goto pt
if CON call JA
if CON call pt
if CON return
if CON goto pr if CON goto JA
if CON goto B
if CON call JA
if CON goto B
if CON goto B
3
2
ireturn goto pi goto B 2 1
icall
icall 3 1
Table 4-5. Replacement Table for Control Function Instructions
Replace Value Meaning
CON mi, pl, eq, ne, gt, le, lvs, mvs, mvc, c0ge, c0lt,
c1ge, c1lt, heads, tails, true, false, npint, njint,
lock
, ebusy
See Table 4-3 for definitions of processor flags.
JA 12-bit value Least significant 12 bits of an absolute address
within the same 4 Kword memory section.
B 3-bit value in B-field instruction B selects one of
return (same as goto pr)
ireturn (same as goto pi)
goto pt
call pt
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Instruction Set
Agere Systems Inc.
DRAFT COPY
4-13
4.5 Instruction Set
(continued)
4.5.1 Control Instructions (continued)
Control Statements
*
goto JA. The goto JA instruction moves the immediate value JA into the lower 12 bits of the program counter
(PC). The upper 4 bits of PC remain unchanged. The instruction at address JA is the next instruction executed.
The goto JA instruction does not affect the program return (pr) register and can be used in a subroutine without
losing the return address of the subroutine. The goto JA instruction should not be placed in the last or next-to-
last instruction before the boundary of a 4 Kword page. If the goto is placed there, the program counter will have
incremented to the next page and the jump will be to the next page rather than to the desired current page.
*
call JA. The call JA instruction moves the contents of the PC into the pr register and the immediate data JA into
the lower 12 bits of the PC. The upper 4 bits of PC remain unchanged. The pr register holds the return address
of the subroutine, i.e., the address of the instruction following call JA; for example, if call JA is located at
address N, the pr register is loaded with address N + 1. The instruction at address JA is the next instruction
executed. The call JA instruction should not be placed in the last or next-to-last instruction before the boundary
of a 4 Kword page. If the call is placed there, the program counter will have incremented to the next page and
the jump will be to the next page rather than to the desired current page.
*
goto pt. The goto pt instruction moves the contents of pt into the PC. The instruction with address equal to the
contents of pt is the next instruction executed. Because pt is a 16-bit register, goto pt allows branches to any
location in the 64 Kword program space. The goto pt instruction does not affect the program return register.
*
call pt. The call pt instruction moves the contents of the PC into the pr register and the contents in pt into the
PC. The pr register holds the return address of the subroutine, i.e., the address of the instruction following call
pt
; for example, if the call pt is located at address N, the pr register is loaded with the value N + 1. The instruc-
tion with address equal to the contents of pt is the next instruction executed.
*
icall. The icall instruction moves the contents of the PC into the program interrupt (pi) register and interrupt vec-
tor address 0x0002 into the PC. The pi register holds the return address of the interrupt routine, i.e., the address
following the icall instruction; for example, if the icall instruction is located at address N, the pi register is loaded
with the value N + 1. The icall instruction is reserved for use by the hardware development system.
*
return/goto pr. The return instruction moves the contents of the pr register into the PC. The pr register holds
the return address of the subroutine. Execution of the instruction with address equal to the contents of pr follows
the execution of the return instruction. The goto pr instruction works identically to the return instruction.
*
ireturn/goto pi. The ireturn instruction moves the contents of the pi register into the PC. The pi register holds
the interrupt return address. Outside of an interrupt service routine, the value of the PC is regularly written into
the pi register. Execution of the instruction with address equal to the contents of pi follows the execution of the
ireturn instruction. The goto pi instruction works identically to the ireturn instruction. If the goto pi or ireturn
instructions are executed outside of an interrupt service routine, the instruction that immediately precedes the
goto pi (or ireturn) must be a load of the pi register; otherwise, the goto pi (or ireturn) instruction will not exe-
cute properly.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Instruction Set December 2001
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4.5 Instruction Set
(continued)
4.5.2 Cache Instructions
Cache instructions implement low-overhead loops. The use of cache loops conserves program memory, speeds
execution time, and reduces power dissipation. The do instruction treats the specified N instructions as a loop to
be executed K times. The redo instruction treats the previous N instructions as another loop to be executed K
times. Both cache instructions use one program memory location. The do instruction executes in one instruction
cycle, but the redo instruction executes in two instruction cycles.
The value of K can also be written to the cloop register to specify the number of iterations at run time. The value in
cloop is used if K is specified as zero in the instruction encoding. The value in cloop decrements every cache loop
and is decremented to zero at the end of the do or redo instruction. (The cloop register will also contain the cache
count from a do K or redo K instruction, K = 1 to 127).
For multiply/ALU instructions that require two reads of dual-port RAM, executing from the cache decreases the
execution time from two instruction cycles to one instruction cycle resulting in an additional increase in throughput.
The assembly-language statements (do cloop and redo cloop) are used to specify that the number of iterations is to be
taken from the cloop register. K is set to 0 in the instruction encoding to select cloop.
Table 4-6. Example of Execution of Cache Instruction
Cache Instructions
do K { redo K
instruction1
instruction2
.
.
instructionN
}
Table 4-7. Replacement Table for Cache Instructions
Replace Value Meaning
K cloop
Take the number of times the instructions are to be executed from
bits 0 through 6 of the cloop register.
1 to 127 Number of times the instructions are to be executed, encoded in
instruction.
N 1 to 15 1 to 15 instructions can be included.
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Instruction Set
Agere Systems Inc.
DRAFT COPY
4-15
4.5 Instruction Set
(continued)
4.5.2 Cache Instructions (continued)
Cache Statements
When the cache is used to repeat a block of N instructions, the cycle timing of the instructions are as follows:
1. The first pass does not affect cycle timing except for the last instruction in the block of N instructions. This
instruction always executes in two cycles, whether it is a one- or a two-cycle instruction.
2. During pass 2 through pass K 1, each instruction is executed in the cache.
3. During the last (Kth) pass, the block of instructions executes inside the cache except for the last instruction that
executes outside the cache.
The instructions remain in the cache memory and can be reexecuted by using the redo command without the need
to reload the cache.
*
redo K. When the redo K instruction is used, the DSP executes the N instructions currently in the cache's mem-
ory K times. On the last iteration, the last instruction is executed outside the cache.
Control group instructions and instructions with 16-bit immediates cannot be executed from within the cache.
16-bit immediates can be found in data move, F3, and F4 instruction groups. The instruction set summary
(Appendix B) tells whether each instruction is cachable.
Note: Instructions in a cache loop are noninterruptible.
4.5.3 Data Move Instructions
Data move instructions perform three basic operations: moving immediate data to a register, moving data between
a register and an accumulator, and moving data between a register and Y-memory space. All data move instruc-
tions use one program location except for the long immediate instructions that use a second program memory word
for their immediate data. All execute in two instruction cycles except for the short immediate that executes in one
instruction cycle.
Note: If reading signed registers less than 16 bits wide, their contents are sign-extended to 16 bits. If reading
unsigned registers less then 16 bits wide, their contents are zero-extended to 16 bits. If short immediate
addressing is used to write to YAAU registers in the DSP, unsigned registers are zero-extended from 9 bits to
16 bits. Signed registers j and k are sign-extended from 9 bits to 16 bits.
Table 4-8. Data Move Instruction Summary
Statement Description
Instruction
Cycles
Program
Locations
R = IM16
SR = IM9
Loads 16-bit immediate data (IM16) into a register (R).
Loads 9-bit immediate data (IM9) into a YAAU register (SR).
2
1
2
2
R = aS[l]
aT[l] = R
Loads contents of half of accumulator (aS[l] into a register (R).
Loads contents of register (R) into half of accumulator (aS[l]).
2
2
1
1
R = Y
Y = R
Z : R
DR = *(OFFSET)
*(OFFSET) = DR
Loads contents of memory location (Y) into a register (R).
Stores contents of register (R) into a memory location (Y).
Loads contents of memory location (Z) into a register (R), and
stores old contents of register (R) into memory location (Z).
Loads contents of memory location (*(OFFSET)) into a register
(DR).
Stores contents of a register (DR) into a memory location
(*(OFFSET)).
2
2
2
2
2
1
1
1
1
1
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Instruction Set December 2001
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DRAFT COPY
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4.5 Instruction Set
(continued)
4.5.3 Data Move Instructions (continued)
Table 4-9. Replacement Table for Data Move Instructions
(Registers are 16 bits unless otherwise stated.)
Replace Value Meaning
R
x
y
yl
p
pl
auc
c0
c1
c2
DAU register--signed.
DAU register--signed
.
DAU register--unsigned.
DAU product register--signed.
DAU product register, lower half--unsigned.
DAU control register--unsigned, 7 bits.
DAU counter 0--signed, 8 bits.
DAU counter 1--signed, 8 bits.
DAU counter 2--signed, 8 bits.
r0
r1
r2
r3
rb
re
j
k
ybase
YAAU pointer register--unsigned.
YAAU pointer register--unsigned.
YAAU pointer register--unsigned.
YAAU pointer register--unsigned.
YAAU modulo address register--unsigned.
YAAU modulo address register--unsigned.
YAAU incrementing register--signed.
YAAU incrementing register--signed.
YAAU direct data register--unsigned.
pt
pr
pi
i
XAAU pointer register--unsigned.
XAAU program return register--unsigned.
XAAU program interrupt register--unsigned
.
XAAU increment register--signed.
psw Processor status word.
sioc
sdx
tdms
srta
Serial I/O control register
.
Serial I/O data register.
Serial I/O tdms control register
.
Serial receive/transmit address
.
saddx
sioc2
sdx2
tdms2
Serial protocol register.
Serial I/O control register, port 2
.
Serial I/O control register, port 2.
Serial I/O tdms control register, port 2
.
srta2 Serial receive/transmit address, port 2
.
saddx2
pioc
pdx<0--7>
Serial protocol register, port 2.
Parallel I/O control register (DSP1617 only).
Parallel I/O data registers (pdx0 only in DSP1611/18/27/28/29).
Data moves to y, a0, or a1 load the high half (bits 31--16) of the register. If clearing of the destination is enabled according to the CLR field
of the auc register, the low half of the destination register is cleared (0) when the high half is loaded.
The pi register acts as a shadow of the PC. Each time the PC changes, its new value is loaded into pi. Shadowing is disabled when execut-
ing an interrupt service routine, and pi saves the contents of PC prior to the interrupt. Writes to pi do not alter its contents for less than one
instruction cycle after shadowing resumes except during interrupt service routines.
sioc, sioc2, tdms, tdms2, srta, and srta2 registers are not readable.
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Instruction Set
Agere Systems Inc.
DRAFT COPY
4-17
4.5 Instruction Set
(continued)
4.5.3 Data Move Instructions (continued)
R inc
ins
cloop
Interrupt control register.
Interrupt status register.
Cache loop count register.
cbit
sbit
BIO control register.
BIO status register.
ioc
mwait
IO control register--EMI, CKO, PIO, and SIO control.
wait-state control register.
jtag JTAG data register--unsigned.
a0, a1, a0l, a1l High and low halves of accumulators.
ar<0--3> Auxiliary BMU registers.
alf Await, lowpr, flags status & control.
timer0
timerc
Timer initial count.
Timer control register.
powerc Power control register.
eir
ear
edr
ECCP instruction register (DSP1618/28 only).
ECCP address register (DSP1618/28 only).
ECCP data register (DSP1618/28 only).
pllc Clock SYNTHESIZER control register (DSP1627/28/29 only).
phifc PHIF control register (DSP1611/18/27/28/29 only).
DR rM, a0[l], a1[l], y[l],
p, pl, x, pt, pr, psw
Subset of registers accessible with direct addressing.
SR r<0--3>, rb, re, j, k Subset of registers for short immediate.
aS, aT a0, a1 High half of accumulator
(bits 31--16).
aSl, aTl
a0l, a1l
Low half of accumulator (bits 15--0).
Y
*rM,*rM++,
*rM--,*rM++j
Same as in multiply/ALU instructions.
Z
*rMzp,*rMpz,
*rMm2,*rMjk
Same as in multiply/ALU instructions.
IM16 16-bit value Immediate data.
IM9 9-bit value Immediate data for YAAU registers.
*(OFFSET) 5-bit value Immediate address for direct data addressing.
Table 4-9. Replacement Table for Data Move Instructions (continued)
(Registers are 16 bits unless otherwise stated.)
Replace Value Meaning
Data moves to y, a0, or a1 load the high half (bits 31--16) of the register. If clearing of the destination is enabled according to the CLR field
of the auc register, the low half of the destination register is cleared (0) when the high half is loaded.
The pi register acts as a shadow of the PC. Each time the PC changes, its new value is loaded into pi. Shadowing is disabled when execut-
ing an interrupt service routine, and pi saves the contents of PC prior to the interrupt. Writes to pi do not alter its contents for less than one
instruction cycle after shadowing resumes except during interrupt service routines.
sioc, sioc2, tdms, tdms2, srta, and srta2 registers are not readable.
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Instruction Set December 2001
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DRAFT COPY
Agere Systems Inc.
4.5 Instruction Set
(continued)
4.5.3 Data Move Instructions (continued)
Data Move Instruction Examples
Data move instructions must be written in the exact format shown. If the instructions are written in any other way
(for example, R : Z instead of Z : R), the assembler produces an error message. All data move instructions can
execute in the cache except for the long immediate (R = IM16).
*
R = IM16 loads the 16-bit immediate data value (IM16) into the specified destination register (R). This data move
instruction cannot be executed in the cache.
*
SR = IM9 loads a 9-bit immediate data value (IM9) into one of the YAAU registers (j, k, rb, re, r0, r1, r2, or r3).
The 9 bits are loaded into the LSBs of the register. All registers are then zero-extended except for j and k which
are sign-extended. This special-case immediate instruction is often referred to as a short immediate or register
set instruction. Short immediate instructions require one word of program memory, execute in one cycle, and
can be executed inside the cache. The DSP1600 Assembler defaults to the long immediate if the value IM9 is
greater than 9 bits or if a label is used. The short immediate can be forced with the set mnemonic (if the value
IM9 is greater than 9 bits, it is truncated to 9 bits). For example, set r0 = 0xf00d will load r0 with 0x00d.
*
R = Y loads the data contained in the specified Y source into the specified destination register (R).
*
R = aS[l] loads the data contained in bits 31--16 (or 15--0 if aSl is specified) of the specified accumulator (aS)
into the specified destination register (R). If saturation on overflow is enabled (according to the SAT field of the
auc register), the transferred accumulator value is limited (see Section 5.1, Data Arithmetic Unit).
*
Y = R loads the data contained in the specified source register (R) into the specified Y destination.
*
aT[l] = R loads the data contained in the specified source register (R) into bits 31--16 (or 15--0 if aTl is speci-
fied) of the specified accumulator. If clearing of aTl is enabled (according to the CLR field of the auc register),
then aTl is cleared (0) when the high half is loaded. The guard bits are loaded with the value of bit 31.
*
Z : R loads contents of memory location (Z) into a register (R), and stores old contents of register (R) into mem-
ory location (Z). (See Section 4.3.2, Compound Addressing for an explanation of this data transfer mode).
*
DR = *(OFFSET) loads from a direct address. Five bits in the instruction are concatenated with 11 bits in the
ybase register to form a 16-bit address to Y memory. Data at that address is written to register DR.
*
*(OFFSET) = DR stores to a direct address. Data from register DR is written to the Y memory location specified
by the direct address.
*
push(*rM) = R is an optional assembly-language form of the statement *rM++ = R and is used for stack
operations. Data is written from register R to the memory location pointed to by the address in rM, and the
address is incremented.
*
R = pop(*rM) is an optional assembly-language statement that creates two DSP instructions: *rM-- followed by
R = *rM. This combination is used for stack operations. The pointer register rM is decremented, and data is writ-
ten from the new memory location to the register R. The decrement instruction is not interruptible, so interrupts
cannot corrupt the two-instruction pop sequence.
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Instruction Set
Agere Systems Inc.
DRAFT COPY
4-19
4.5 Instruction Set
(continued)
4.5.4 Special Function Group
Instructions from the special function group are always executed in one instruction cycle. They require one word of
program memory. The special function instructions are used to implement a number of algorithms that include the
following nonlinear functions: absolute value, signum, minimum and maximum value finder, A-law and
-law con-
versions, division, half-wave and full-wave rectification, and rounding. Special function instructions are executed
either conditionally or unconditionally. Both the condition and its complement are available for use in special func-
tion instructions. Instructions from this group can be used in the cache.
The special function instructions can be conditioned on the basis of the flags defined in Table 4-3. The result of the
most recent accumulator or BMU operation prior to the special function instruction establishes the state of the flags
for the conditions associated with logical or mathematical functions.
To write a special function instruction unconditionally, write F2 by itself (see Table 4-10). To write the special func-
tion instructions conditionally, write the full form--if CON F2. To use the event counter, write ifc CON F2--mean-
ing:
if CON is true then {
c1=c1+1
F2 instruction
c2=c1
}
else {
c1=c1+1
}
Note: If using the event counter (ifc instruction) and if the condition field CON is c0lt or c0ge, c0 is not incre-
mented. Otherwise, if using the event counter (ifc instruction) and if CON is c1lt or c1ge, c1 is incremented
once after the test. For example, ifc c0lt a0 = a1 first tests to see if c0 is less than zero, then increments
c1. If c0 is less than zero, a0 = a1 is executed and c2 is set to the new value of c1. If c0 is
0, no further
action occurs. Normally, a test of c0, such as if c0lt goto 0x400, increments c0. In the case of the ifc c0lt
F2 instruction, c0 is not incremented.
Special Function Instructions
if CON F2
ifc CON F2
F2
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4.5 Instruction Set
(continued)
4.5.4 Special Function Group (continued)
DSP1627/28/29 only.
DSP1618/28 only.
Table 4-10. Special Function Statements
Statement F2 Description
aD = aS >> 1
aD = aS >> 4
aD = aS >> 8
aD = aS >> 16
Arithmetic right shift (sign preserved) of 36-bit accumulators.
aD = aS
aD = aS
aD = ~aS
36-bit transfer.
Two's complement.
One's complement.
aD = rnd(aS) Round upper 20 bits of accumulator.
aDh = aSh + 1 Increment high half of accumulator (lower half cleared).
aD = aS + 1 Increment accumulator.
aD = y
aD = p
32-bit transfer, sign extend into guard bits 35--32.
aD = aS << 1
aD = aS << 4
aD = aS << 8
aD = aS << 16
Arithmetic left shift (sign-extended from new bit 31) of the least significant.
32 bits of the 36-bit accumulators.
Table 4-11. Replacement Table for Special Function Instructions
Replace Value Meaning
aD, aS a0, a1 One of two DAU accumulators.
CON mi, pl, eq, ne, gt, le, lvc, lvs, mvs, mvc, c0ge, c0lt,
c1ge, c1lt, heads, tails, true, false, allt, allf, somet,
somef, oddp, evenp, mns1, nmns1, npint, njint,
lock
, ebusy
See Table 4-3 for definitions of pro-
cessor flags.
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
December 2001 Instruction Set
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DRAFT COPY
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4.5 Instruction Set
(continued)
4.5.4 Special Function Group (continued)
Special Function Statements
The statements must be written in the exact format shown. If the statements are written in any other way (for
example, aD = 1 + aS instead of aD = aS + 1), the assembler produces an error message.
aD = aS >> 1 The contents of the source accumulator (aS) are divided by 2, and the result is placed in the
destination accumulator (aD). The sign bit is preserved.
aD = aS >> 4 The contents of the source accumulator (aS) are divided by 2
4,
and the result is placed in
the destination accumulator (aD). The sign bit is preserved.
aD = aS >> 8 The contents of the source accumulator (aS) are divided by 2
8,
and the result is placed in
the destination accumulator (aD). The sign bit is preserved.
aD = aS >> 16 The contents of the source accumulator (aS) are divided by 2
16,
and the result is placed in
the destination accumulator (aD). The sign bit is preserved.
aD = aS << 1 The contents of the source accumulator (aS) are shifted 1 bit left, and the result is placed in
the destination accumulator (aD). The sign bit is extended from the new bit 31. The least
significant bit of aD is cleared to zero.
aD = aS << 4 The contents of the source accumulator (aS) are shifted 4 bits left, and the result is placed
in the destination accumulator (aD). The sign bit is extended from the new bit 31. The least
significant 4 bits of aD are cleared to zero.
aD = aS << 8 The contents of the source accumulator (aS) are shifted 8 bits left, and the result is placed
in the destination accumulator (aD). The sign bit is extended from the new bit 31. The least
significant 8 bits of aD are cleared to zero.
aD = aS << 16 The contents of the source accumulator (aS) are shifted 16 bits left, and the result is placed
in the destination accumulator (aD). The sign bit is extended from the new bit 31. The least
significant 16 bits of aD are cleared to zero.
aD = aS The contents of the source accumulator (aS) are placed in the destination accumulator
(aD).
aD = aS The two's complement (or negative of the value) of the contents of the source accumulator
(aS) are placed in the destination accumulator (aD).
aD = rnd(aS) The 36-bit contents of the source accumulator (aS) are rounded to 20 bits, and the result is
placed in aD[35--16] with zeros in aD[15--0].
aDh = aSh + 1 The value 0x00010000 is added to the contents of the source accumulator (aS), and the
result is placed in the destination accumulator (aD). This statement increments the data in
the high half of the source accumulator by one. The low half of aD is cleared.
aD = aS + 1 The value 0x00000001 is added to the contents of the source accumulator (aS), and the
result is placed in the destination accumulator (aD). This statement increments the data in
the source accumulator by one.
aD = y The contents of the y register are written to the destination accumulator (aD).
aD = p The contents of the p register are written to the destination accumulator (aD). The bit align-
ment of the p register is a function of the ALIGN field of the auc register.
aD = ~aS The contents of the source accumulator (aS) are inverted and placed in the destination
accumulator--aD (one's complement).
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4.5 Instruction Set
(continued)
4.5.5 Multiply/ALU Group
The multiply/ALU instructions are the primary instructions used to implement signal-processing algorithms. State-
ments from this group can be combined to generate multiply/accumulate, logical, and other ALU functions and to
simultaneously transfer data between memory and registers in the data arithmetic unit. In the examples presented,
the statements should be read from right to left and top to bottom. Statements within a multiply/ALU instruction are
executed essentially in parallel. The multiply/ALU instructions usually consist of more than one part. Each part of
an instruction is called a statement. The general rule is that valid instructions can be formed by choosing one
statement from each statement column in Table 4-12. If either statement is not required, a single statement from
either column also constitutes a valid instruction. Conversely, valid instructions can be decomposed into separate
statements with each coming from a different column in Table 4-12.
The multiply/ALU instructions consist of two types of statements: a function and a transfer (see Table 4-12). The
statements in the function column can be separated into two more types: those involving the multiplier and those
involving only the ALU in the data arithmetic unit. The multiply/accumulate instructions typically used in signal-pro-
cessing applications are assembled by using statements from the function column that include the multiplication of
the data in x and y bits 31--16. In a full multiply/accumulate instruction, the x and y registers are loaded with the
operands, the product of the previous operands is generated, and the previous product is accumulated in a0 or a1.
The following example shows how a typical multiply/accumulate sequence is implemented.
Example:
In the example presented, the data in the X source is copied into the x register and the data in the Y source into
bits 31--16 of the y register in line 1. In line 2, the product of the data in x and y[31--16] is generated and stored
in p. In line 3, the data in the source accumulator (aS) and the data in p are added and the result is loaded into the
destination accumulator. Note that lines 2 and 3 could also have specified memory transfer operations for later
instructions. Section 2.1.2, Concurrent Operations has more detail on the above pipeline.
The ALU statements perform one of the following:
*
The logical operations of AND, OR, or XOR between an accumulator and the data in the y register.
*
The addition or subtraction of data in the y register or p register with accumulator data.
*
The load of an accumulator with the data in the y register or p register.
The y register or p register must be loaded prior to the ALU operation.
The following example shows how a typical logical operation is implemented.
In this example, the data in the Y source is copied into the y register in line 1. In line 2, the logical AND of the data
in the source accumulator (aS) and the data in y as a result of line 1 are calculated. The result is loaded into the
destination accumulator.
Instruction #
(1) y = Y x = X
(2) p = x * y
(3) aD = aS + p
(1) y = Y
(2) aD = aS & y
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4.5 Instruction Set
(continued)
4.5.5 Multiply/ALU Group (continued)
All multiply/ALU instructions require one word of memory. The number of instruction cycles required to execute an
instruction in the multiply/ALU group is a function of the statement selected from the transfer column in
Table 4-12. Instructions with statements in the transfer column involving a write to RAM are executed in two
instruction cycles whether the instruction is in or out of the cache. Instructions with statements in the transfer col-
umn involving a read from the X space and the Y space simultaneously are executed in two instruction cycles if not
in the cache and one instruction cycle if in the cache. An instruction with no transfer statement executes in one
instruction cycle either in or out of the cache. The remaining instructions are executed in one instruction cycle
either in or out of the cache. Table 4-12 gives the number of instruction cycles for each case.
The no operation (nop) instruction is a special-case encoding of a multiply/ALU instruction and is executed in one
instruction cycle. The assembly-language notation representation of a no operation instruction is either nop or a
single semicolon (;) and is assembled as *r0.
Note that the function statements and transfer statements in Table 4-12 are chosen independently. Any function
statement can be combined with any transfer statement to form a valid multiply/ALU instruction. F1 function state-
ments and transfer statements can also be used alone to form valid instructions.
Note: For transfer statements when loading the upper half of an accumulator, the lower half is cleared if the corresponding
CLR bit in the auc register is zero. auc is cleared by reset.
With a 2X clock selection, an instruction cycle is 2 times the period of the input clock (CKI). With a 1X clock selection, an
instruction cycle is 1 times the period of the input clock (CKI); or for the DSP1627/28/29, the instruction cycle is the fre-
quency of the clock source that is selected. If an external memory access is made in X or Y space and wait-states are
programmed, add the number of wait-states.
Add one cycle if an X space access and a Y space access are made to the same bank of DPRAM in one instruction.
The l in [ ] is an optional argument that specifies the low 16 bits of aT or y.
Table 4-12. Multiply/ALU Instructions
F1 Function Statements Transfer
Statements Cycles (Out/In Cache)
p = x * y y = Y x = X
2/1
aD = p p = x * y y = aT x = X
2/1
aD = aS + p p = x * y y[l] = Y
1/1
aD = aS p p = x * y aT[l] = Y
1/1
aD = p x = Y
1/1
aD = aS + p Y
1/1
aD = aS p Y = y[l]
2/2
aD = y Y = aT[l]
2/2
aD = aS + y Z : y x = X
2/2
aD = aS y Z : y[l]
2/2
aD = aS & y Z : aT[l]
2/2
aD = a S | y
aD = aS ^ y
aS y
aS & y
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4.5 Instruction Set
(continued)
4.5.5 Multiply/ALU Group (continued)
*
Loads of a0, a1, and y clear the lower half of the selected register if the appropriate CLR field bits in the auc reg-
ister are zeroed.
*
Loads of a0l, a1l, and yl do not change the data in the high half of the selected register.
*
The y and p operands are sign-extended through the guard bits[35:32] for operations with the accumulators.
Single-Cycle Square
By setting the X=Y= bit in the auc register, any instruction that loads the upper word of the y register also loads the
x register with the same value. A subsequent instruction to multiply the x register and y register results in the
square of the value being placed in the p register. The instruction a0 = a0+p p = x*y y = *r1++ is executed
from the cache with the X=Y= bit set. It will read the value pointed to by r1, load it to both x and y, square the pre-
viously fetched value, and transfer the previous square to a0. A table of values pointed to by r1 can, thus, be
squared in a pipeline with one instruction cycle per each value. The following sample program demonstrates the
use of the single-cycle square.
a0=a0^a0 /* clear accumulator */
auc=0x80 /* enable X=Y= */
r1=table /* initialize pointer */
y=*r1++ /* load both x and y with first value */
p=x*y y=*r1++ /* square, and load x and y with second*/
/* value */
do 100 { /* set up cache loop of 100 repeats */
a0=a0+p p=x*y y=*r1++ /* accumulate, square, and load both x */
/* and y */
} /* end of cache loop */
auc=0x0 /* turn off single-cycle square mode */
If the X=Y= bit is set and the hardware development system is used, breakpoints or single-stepping will corrupt the
x register. It is best to set the X=Y= bit just before the single-cycle routine is used and clear it just after.
Table 4-13. Replacement Table for Multiply/ALU Instructions
Replace Value Meaning
aD, aS, aT a0, a1 One of two DAU accumulators.
X *pt++
*pt++i
X-space location pointed to by pt. pt is postmodified by +1 and i, respectively.
Y *rM
*rM++
*rM
*rM++j
Y-space location pointed to by rM (M = 0, 1, 2, 3). rM is postmodified by 0, +1,
1, and j, respectively.
Z *rMzp, *rMpz,
*rMm2, *rMjk
Read/write compound addressing in Y space. rM (M = 0, 1, 2, 3) is used
twice. First, postmodified by 0, +1, 1, and j, respectively; and second, post-
modified by +1, 0, + 2, and k, respectively.
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DRAFT COPY
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4.5 Instruction Set
(continued)
4.5.5 Multiply/ALU Group (continued)
Function Statements
In the execution of these statements, the width of the operand is extended to 36 bits as appropriate. This is accom-
plished by sign-extending bit 31 in the p or y register to retain the correct two's complement value. The multiplier
performs a two's complement multiply by using x and the high half of y (bits 31--16).
The statements must be written in the exact format shown. If the statements are written in any other way (for
example, aD = p + aS instead of aD = aS + p), the assembler produces an error message.
*
p = x * y The contents of the x and the y (bits 31--16) registers are multiplied, and the result is placed in the
p register.
*
aD = p p = x * y The contents of the p register are copied into the destination accumulator (aD), then the con-
tents of the x and the y (bits 31--16) registers are multiplied, and the result is placed in the p register. The bit
alignment between p and aD is a function of the ALIGN field of the auc register.
*
aD = aS + p p = x * y The contents of the source accumulator (aS) are added to the contents of the p register,
and the result is placed in the destination accumulator (aD). The bit alignment between p and aS is a function of
the ALIGN field of the auc register. The contents of the x and the y (bits 31--16) registers are multiplied, and the
result is placed in the p register.
*
aD = aS p p = x * y The contents of the p register are subtracted from the contents of the source accumulator
(aS), and the result is placed in the destination accumulator (aD). The bit alignment between p and aS is a func-
tion of the ALIGN field of the auc register. The contents of the x and the y (bits 31--16) registers are multiplied,
and the result is placed in the p register.
*
aD = p The contents of the p register are copied into the destination accumulator (aD). The bit alignment
between p and aD is a function of the ALIGN field of the auc register.
*
aD = aS + p The contents of the source accumulator (aS) are added to the contents of the p register, and the
result is placed in the destination accumulator (aD). The bit alignment between p and aS is a function of the
ALIGN field of the auc register.
*
aD = aS p The contents of the p register are subtracted from the contents of the source accumulator (aS), and
the result is placed in the destination accumulator (aD). The bit alignment between p and aS is a function of the
ALIGN field of the auc register.
*
aD = y The contents of the y register are copied into the destination accumulator (aD).
pt will be incremented, and the value pointed to by pt will be fetched but not loaded into x. Also, any restrictions from reading the same
bank of internal memory or reading from external memory apply as if the x = *pt++[i] was actually implemented.
Table 4-14. Instruction for Loading the x and y Registers into the Squaring Mode
y = IM16 Long immediate data move.
y = aS[l] Data move from an accumulator [low word].
y = *rM Multiply/ALU transfer from Y memory. M = 0, 1, 2, or 3.
y = *rM++
y = *rM
y = *rM++j
F1 y = Y x = *pt++[i] In these, x is loaded with the same data as y but a dummy x access is also
made. The use of these instructions for squaring is not recommended
.
F1 y = aT[l] x = *pt++[i]
F1 Z : y x = *pt++
Z : y Data move with compound addressing.
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4.5 Instruction Set
(continued)
4.5.5 Multiply/ALU Group (continued)
*
aD = aS + y The contents of the source accumulator (aS) are added to the contents of the y register, and the
result is placed in the destination accumulator (aD).
*
aD = aS y The contents of the y register are subtracted from the contents of the source accumulator (aS), and
the result is placed in the destination accumulator (aD).
*
aD = aS & y The contents of the source accumulator (aS) are ANDed with the contents of the y register, and the
result is placed in the destination accumulator (aD).
*
aD = aS | y The contents of the source accumulator (aS) are ORed with the contents of the y register, and the
result is placed in the destination accumulator (aD).
*
aD = aS ^ y The contents of the source accumulator (aS) are XORed with the contents of the y register, and the
result is placed in the destination accumulator (aD).
*
aS y The contents of the y register are subtracted from the contents of the source accumulator (aS). No result
is saved, but the ALU flags are affected by the results of the subtraction.
*
aS & y The contents of the source accumulator (aS) are ANDed to the contents of the y register. No result is
saved, but the ALU flags are affected by the results of the AND function.
Transfer Statements
The transfer statements allow the user to transfer data from memory to the x and y registers and the accumulators,
or from the y register and the accumulators to memory.
*
y = Y x = X The data from the specified Y source is loaded into the high half (bits 31--16) of the y register.
The data from the specified X source is loaded into the x register. If clearing of yl is enabled by using the CLR
field of the auc register, yl is cleared (0) when the high half is loaded.
*
y = aT x = X The data in the high half (bits 31--16) of the specified accumulator is loaded into the high half
(bits 31--16) of the y register. The data from the specified X source is loaded into the x register. If clearing of yl
is enabled by using the CLR field of the auc register, yl is cleared (0) when the high half is loaded.
*
y = Y The data from the specified Y source is loaded into the high half of the y register (bits 31--16). If clearing
of yl is enabled by using the CLR field of the auc register, yl is cleared (0) when the high half is loaded.
*
yl = Y The data from the specified Y source is loaded into the low half of the y register (bits 15--0). The data in
the high half of y is not altered.
*
aT = Y The data from the specified Y source is loaded into the high half (bits 31--16) of the specified
accumulator. The guard bits (35--32) are loaded with the value of bit 31. If clearing of aTl is enabled by using
the CLR field of the auc register, the low half of the accumulator is cleared (0) when the high half is loaded.
*
aTl = Y The data from the specified Y source is loaded into the low half (bits 15--0) of the specified
accumulator. The data in the high half of the accumulator is not altered.
*
x = Y The data from the specified Y source is loaded into the x register.
*
Y No data is transferred. This transfer statement is used to modify the address register specified. If used with-
out postmodification (i.e., *r0), this statement implements a nop.
*
Y = y The data in the high half of the y register (bits 31--16) is loaded into the specified Y destination.
*
Y = yl The data in the low half of the y register (bits 15--0) is loaded into the specified Y destination.
*
Y = aT The data in the high half (bits 31--16) of the specified accumulator is written into the specified Y destina-
tion. If saturation on overflow is selected by using the SAT field of the auc register, the transferred accumulator
value is limited. (See Section 5.1, Data Arithmetic Unit.)
*
Y = aTl The data in the low half (bits 15--0) of the specified accumulator is written into the specified Y destina-
tion. If saturation on overflow is selected by using the SAT field of the auc register, the transferred accumulator
value is limited. (See Section 5.1, Data Arithmetic Unit.)
Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
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DRAFT COPY
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4.5 Instruction Set
(continued)
4.5.5 Multiply/ALU Group (continued)
*
Z : y x = X The data from the specified X source is loaded into the x register. The data from the specified
Z source is loaded into the high half (bits 31--16) of the y register, and the old data from the high half of the
y register is loaded into the Z destination. If clearing of yl is enabled by using the CLR field of the auc register, yl
is cleared (0) when the high half is loaded.
*
Z : y The data from the specified Z source is loaded into the high half (bits 31--16) of the y register, and the old
data from the high half of the y register is loaded into the Z destination. If clearing of yl is enabled by using the
CLR field of the auc register, yl is cleared (0) when the high half is loaded. (See Figure 4-3.)
*
Z : yl The data from the specified Z source is loaded into the low half (bits 15--0) of the y register, and the old
data of the low half of the y register is loaded into the Z destination. Data in the high half of the y register is not
altered. (See Figure 4-3.)
*
Z : aT The data from the specified Z source is loaded into the high half (bits 31--16) of the specified accumula-
tor. If clearing of aTl is enabled by using the CLR field of the auc register, the low half of the accumulator is
cleared (0) when the high half is loaded. The guard bits (35--32) are loaded with the value of bit 31. The old
data from the high half of the accumulator is loaded into the Z destination. If saturation on overflow is enabled by
using the SAT field of the auc register, the transferred accumulator value is limited. (See Section 5.1, Data Arith-
metic Unit and Figure 4-3.)
*
Z : aTl The data from the specified Z source is loaded into the low half (bits 15--0) of the specified accumulator
and the old data from the low half of the accumulator is loaded into the Z destination. The data in the high half of
the accumulator is not altered. (See Figure 4-3.)
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4.5 Instruction Set
(continued)
4.5.5 Multiply/ALU Group (continued)
5-4150
Figure 4-3. Compound Addressing with Accumulators or y Register
Figure 4-3 shows pictorially the transfers associated with compound addressing with an accumulator or the y regis-
ter. Only one of the four possible postmodification conditions is shown: *rMpz. The others are the same as in
Section 4.3.2, Compound Addressing.
Z : aTl *rMpz : aTl
INITIAL ADDRESS IN rM
FINAL ADDRESS IN rM
Y MEMORY
Y ADDRESSING REGISTER
*rMpz : aT
Z : y *rMpz : y
y(h)
Z : yl *rMpz : yl
Z : aT
INITIAL ADDRESS IN rM
FINAL ADDRESS IN rM
INITIAL ADDRESS IN rM
FINAL ADDRESS IN rM
INITIAL ADDRESS IN rM
FINAL ADDRESS IN rM
aT(h)
aT(h) aT(l)
y(l)
y(h) y(l)
*rM
*(rM + 1)
*rM
*rM
*rM
*(rM + 1)
*(rM + 1)
*(rM + 1)
aT(l)
2
1
TEMP 3
0
(IF auc[CLR] = 0)
2
0
(IF auc[CLR] = 0)
TEMP
1
3
TEMP
1
3
2
1
TEMP 3
2
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4.5 Instruction Set
(continued)
4.5.6 F3 ALU Instructions
The F3 ALU instr