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Электронный компонент: DSP16411

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Data Sheet
May 2003
DSP16411 Digital Signal Processor
1 Features
!
Twin DSP16000 dual-MAC cores perform up to
1140 million MACs per second at 285 MHz
!
Low power:
-- 1.2 V internal supply for power efficiency
-- 3.3 V I/O pin supply for compatibility
!
322K x 16 on-chip RAM
!
Centralized direct memory access unit (DMAU):
-- Transparent peripheral-to-memory and mem-
ory-to-memory transfers
-- Better utilization of DSP MIPS
-- Simplifies management of system data flow
!
16-bit parallel interface unit (PIU) with direct mem-
ory access (DMA) provides host access to all DSP
memory
!
Two enhanced serial I/O units (SIU0 and SIU1)
with DMA:
-- Compatible with TDM highways such as T1/E1
and ST-bus
-- Hardware support for
-law and A-law com-
panding
!
Core messaging units (MGU0 and MGU1) for inter-
processor communication
!
On-chip, programmable, PLL clock synthesizer
eliminates need for high-speed clock input
!
Two 7-bit control I/O interfaces (BIOs) for
increased flexibility and lower system costs
!
32-bit system and external memory interface
(SEMI) supports 16-bit or 32-bit synchronous or
asynchronous memories
!
Two IEEE
1149.1 test ports (JTAG boundary
scan)
!
Full-speed, in-circuit emulation hardware for each
core with eight address and two data watchpoint
units for efficient application development
!
Supported by DSP16411 software and hardware
development tools
!
208-ball PBGA package (17 mm x 17 mm; 1.0 mm
ball pitch) for small footprint
2 Description
The DSP16411 is a digital signal processor (DSP)
optimized for communications infrastructure applica-
tions. Large, on-chip memory enables it to be pro-
grammed to perform numerous fixed-point signal
processing functions, including equalization, chan-
nel coding, or speech coding. The DSP16411 fea-
tures twin DSP16000 dual-MAC DSP cores and
enhanced DMA capabilities. Together, these features
deliver the performance required for second- and
third-generation infrastructure equipment.
The DSP16411 extends the performance of the
DSP16410CG with a higher maximum clock rate and
additional on-chip RAM, while maintaining low power
consumption, efficient software code density, and
small physical size. The DSP16411 is pinout and
code compatible with the DSP16410CG to protect
investments in hardware and software development.
Data Sheet
DSP16411 Digital Signal Processor
May 2003
Table of Contents
Contents
Page
2
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
"
1 Features ......................................................................................................................................................... 1
"
2 Description...................................................................................................................................................... 1
"
3 Notation Conventions ................................................................................................................................... 14
"
4 Hardware Architecture .................................................................................................................................. 14
"
4.1 DSP16411 Architectural Overview........................................................................................................ 14
"
4.1.1 DSP16000 Cores ........................................................................................................................ 17
"
4.1.2 Clock Synthesizer (PLL) ............................................................................................................. 17
"
4.1.3 Triport RAMs (TPRAM
0--1
)..................................................................................................... 17
"
4.1.4 Shared Local Memory (SLM) ......................................................................................................17
"
4.1.5 Internal Boot ROMs (IROM
0--1
) ............................................................................................. 17
"
4.1.6 Messaging Units (MGU
0--1
) ................................................................................................... 17
"
4.1.7 System and External Memory Interface (SEMI).......................................................................... 18
"
4.1.8 Bit Input/Output Units (BIO
0--1
) .............................................................................................. 18
"
4.1.9 Timer Units (TIMER0_
0--1
and TIMER1_
0--1
) ................................................................... 18
"
4.1.10 Direct Memory Access Unit (DMAU)........................................................................................... 18
"
4.1.11 Interrupt Multiplexers (IMUX
0--1
)............................................................................................ 18
"
4.1.12 Parallel Interface Unit (PIU) ........................................................................................................ 18
"
4.1.13 Serial Interface Units (SIU
0--1
) ...............................................................................................18
"
4.1.14 Test Access Ports (JTAG
0--1
)................................................................................................. 18
"
4.1.15 Hardware Development Systems (HDS
0--1
) .......................................................................... 18
"
4.2 DSP16000 Core Architectural Overview...............................................................................................19
"
4.2.1 System Control and Cache (SYS) .............................................................................................. 19
"
4.2.2 Data Arithmetic Unit (DAU) ......................................................................................................... 19
"
4.2.3 Y-Memory Space Address Arithmetic Unit (YAAU) .....................................................................20
"
4.2.4 X-Memory Space Address Arithmetic Unit (XAAU).....................................................................20
"
4.2.5 Core Block Diagram .................................................................................................................... 21
"
4.3 Device Reset ........................................................................................................................................ 23
"
4.3.1 Reset After Powerup or Power Interruption ................................................................................ 23
"
4.3.2 RSTN Pin Reset.......................................................................................................................... 23
"
4.3.3 JTAG Controller Reset ................................................................................................................ 24
"
4.4 Interrupts and Traps.............................................................................................................................. 25
"
4.4.1 Hardware Interrupt Logic ............................................................................................................25
"
4.4.2 Hardware Interrupt Multiplexing .................................................................................................. 28
"
4.4.3 Clearing Core Interrupt Requests ...............................................................................................30
"
4.4.4 Host Interrupt Output .................................................................................................................. 30
"
4.4.5 Globally Enabling and Disabling Hardware Interrupts................................................................. 30
"
4.4.6 Individually Enabling, Disabling, and Prioritizing Hardware Interrupts ........................................ 31
"
4.4.7 Hardware Interrupt Status ........................................................................................................... 32
"
4.4.8 Interrupt and Trap Vector Table................................................................................................... 32
"
4.4.9 Software Interrupts...................................................................................................................... 34
"
4.4.10 INT[3:0] and TRAP Pins.............................................................................................................. 34
"
4.4.11 Nesting Interrupts........................................................................................................................ 35
"
4.4.12 Interrupts and Cache Usage ....................................................................................................... 37
"
4.4.13 Interrupt Polling ........................................................................................................................... 37
"
4.5 Interprocessor Communication ............................................................................................................. 38
"
4.5.1 Core-to-Core Interrupts and Traps .............................................................................................. 39
"
4.5.2 Message Buffer Data Exchange ................................................................................................. 39
"
4.5.2.1
Message Buffer Write Protocol ................................................................................... 40
"
4.5.2.2
Message Buffer Read Protocol ................................................................................... 40
"
4.5.3 DMAU Data Transfer...................................................................................................................41
"
4.6 Memory Maps ....................................................................................................................................... 42
Table of Contents
(continued)
Contents
Page
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
3
Use pursuant to Company instructions
"
4.6.1 Private Internal Memory ..............................................................................................................43
"
4.6.2 Shared Internal I/O......................................................................................................................43
"
4.6.3 Shared External I/O and Memory................................................................................................43
"
4.6.4 X-Memory Map ...........................................................................................................................44
"
4.6.5 Y-Memory Maps ..........................................................................................................................45
"
4.6.6 Z-Memory Maps ..........................................................................................................................46
"
4.6.7 Internal I/O Detailed Memory Map ..............................................................................................47
"
4.7 Triport Random-Access Memory (TPRAM) ..........................................................................................48
"
4.8 Shared Local Memory (SLM) ................................................................................................................49
"
4.9 Bit Input/Output Units (BIO
0--1
) .......................................................................................................50
"
4.10 Timer Units (TIMER0_
0--1
and TIMER1_
0--1
) ............................................................................53
"
4.11 Hardware Development System (HDS
0--1
) .....................................................................................56
"
4.12 JTAG Test Port (JTAG
0--1
)...............................................................................................................57
"
4.12.1 Port Identification ........................................................................................................................57
"
4.12.2 Emulation Interface Signals to the DSP16411 ............................................................................58
"
4.12.2.1 TCS 14-Pin Header.....................................................................................................58
"
4.12.2.2 JCS 20-Pin Header .....................................................................................................59
"
4.12.2.3 HDS 9-Pin, D-Type Connector....................................................................................60
"
4.12.3 Multiprocessor JTAG Connections..............................................................................................61
"
4.12.4 Boundary Scan ...........................................................................................................................62
"
4.13 Direct Memory Access Unit (DMAU).....................................................................................................64
"
4.13.1 Overview .....................................................................................................................................64
"
4.13.2 Registers .....................................................................................................................................67
"
4.13.3 Data Structures ...........................................................................................................................83
"
4.13.3.1 One-Dimensional Data Structure (SWT Channels).....................................................83
"
4.13.3.2 Two-Dimensional Data Structure (SWT Channels) .....................................................84
"
4.13.3.3 Memory-to-Memory Block Transfers (MMT Channels) ...............................................86
"
4.13.4 The PIU Addressing Bypass Channel.........................................................................................86
"
4.13.5 Single-Word Transfer Channels (SWT).......................................................................................87
"
4.13.6 Memory-to-Memory Transfer Channels (MMT)...........................................................................90
"
4.13.7 Interrupts and Priority Resolution................................................................................................92
"
4.13.8 Error Reporting and Recovery ....................................................................................................94
"
4.13.9 Programming Examples..............................................................................................................95
"
4.13.9.1 SWT Example 1: A Two-Dimensional Array ...............................................................95
"
4.13.9.2 SWT Example 2: A One-Dimensional Array ...............................................................97
"
4.13.9.3 MMT Example .............................................................................................................99
"
4.14 System and External Memory Interface (SEMI)..................................................................................100
"
4.14.1 External Interface ......................................................................................................................101
"
4.14.1.1 Configuration.............................................................................................................102
"
4.14.1.2 Asynchronous Memory Bus Arbitration.....................................................................103
"
4.14.1.3 Enables and Strobes.................................................................................................104
"
4.14.1.4 External Clock...........................................................................................................105
"
4.14.1.5 Address and Data .....................................................................................................106
"
4.14.2 16-Bit External Bus Accesses ...................................................................................................109
"
4.14.3 32-Bit External Bus Accesses ...................................................................................................109
"
4.14.4 Registers ................................................................................................................................... 110
"
4.14.4.1 ECON0 Register ....................................................................................................... 111
"
4.14.4.2 ECON1 Register ....................................................................................................... 112
"
4.14.4.3 Segment Registers ................................................................................................... 114
"
4.14.5 Asynchronous Memory ............................................................................................................. 116
"
4.14.5.1 Functional Timing...................................................................................................... 116
Table of Contents
(continued)
Contents
Page
4
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
Data Sheet
DSP16411 Digital Signal Processor
May 2003
"
4.14.5.2 Extending Access Time Via the ERDY Pin ............................................................... 120
"
4.14.5.3 Interfacing Examples ................................................................................................ 122
"
4.14.6 Synchronous Memory ............................................................................................................... 124
"
4.14.6.1 Functional Timing...................................................................................................... 124
"
4.14.6.2 Interfacing Examples ................................................................................................ 126
"
4.14.7 Performance ............................................................................................................................. 128
"
4.14.7.1 System Bus............................................................................................................... 128
"
4.14.7.2 External Memory, Asynchronous Interface ............................................................... 129
"
4.14.7.3 External Memory, Synchronous Interface ................................................................. 131
"
4.14.7.4 Summary of Access Times .......................................................................................133
"
4.14.8 Priority ....................................................................................................................................... 134
"
4.15 Parallel Interface Unit (PIU) ................................................................................................................ 135
"
4.15.1 Registers ...................................................................................................................................135
"
4.15.2 Hardware Interface ................................................................................................................... 139
"
4.15.2.1 Enables and Strobes................................................................................................. 140
"
4.15.2.2 Address and Data Pins .............................................................................................141
"
4.15.2.3 Flags, Interrupt, and Ready Pins .............................................................................. 142
"
4.15.3 Host Data Read and Write Cycles ............................................................................................ 143
"
4.15.4 Host Register Read and Write Cycles.......................................................................................145
"
4.15.5 Host Commands .......................................................................................................................147
"
4.15.5.1 Status/Control/Address Register Read Commands.................................................. 148
"
4.15.5.2 Status/Control/Address Register Write Commands .................................................. 148
"
4.15.5.3 Memory Read Commands ........................................................................................ 149
"
4.15.5.4 Flow Control for Memory Read Commands.............................................................. 150
"
4.15.5.5 Memory Write Commands ........................................................................................ 151
"
4.15.5.6 Flow Control for Control/Status/Address Register and Memory Write Commands...151
"
4.15.6 Host Command Examples ........................................................................................................ 152
"
4.15.6.1 Download of Program or Data .................................................................................. 152
"
4.15.6.2 Upload of Data ..........................................................................................................152
"
4.15.7 PIU Interrupts ............................................................................................................................ 153
"
4.16 Serial Interface Unit (SIU) ................................................................................................................... 154
"
4.16.1 Hardware Interface ................................................................................................................... 156
"
4.16.2 Pin Conditioning Logic, Bit Clock Selection Logic, and Frame Sync Selection Logic ............... 157
"
4.16.3 Basic Input Processing ............................................................................................................. 159
"
4.16.4 Basic Output Processing........................................................................................................... 160
"
4.16.5 Clock and Frame Sync Generation ........................................................................................... 161
"
4.16.6 ST-Bus Timing Examples..........................................................................................................166
"
4.16.7 SIU Loopback ........................................................................................................................... 168
"
4.16.8 Basic Frame Structure .............................................................................................................. 168
"
4.16.9 Assigning SIU Logical Channels to DMAU Channels ............................................................... 169
"
4.16.10 Frame Error Detection and Reporting .......................................................................................170
"
4.16.11 Frame Mode.............................................................................................................................. 170
"
4.16.12 Channel Mode--32 Channels or Less in Two Subframes or Less ........................................... 171
"
4.16.13 Channel Mode--Up to 128 Channels in a Maximum of Eight Subframes ................................ 177
"
4.16.14 SIU Examples ........................................................................................................................... 180
"
4.16.14.1 Single-Channel I/O....................................................................................................180
"
4.16.14.2 ST-Bus Interface ....................................................................................................... 181
"
4.16.15 Registers ...................................................................................................................................184
"
4.17 Internal Clock Selection ...................................................................................................................... 200
"
4.18 Clock Synthesis .................................................................................................................................. 201
"
4.18.1 PLL Operating Frequency ......................................................................................................... 201
Table of Contents
(continued)
Contents
Page
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
5
Use pursuant to Company instructions
"
4.18.2 PLL LOCK Flag Generation ......................................................................................................201
"
4.18.3 PLL Registers ...........................................................................................................................202
"
4.18.4 PLL Programming Example ......................................................................................................203
"
4.18.5 Powering Down the PLL ...........................................................................................................203
"
4.18.6 Phase-Lock Loop (PLL) Frequency Accuracy and Jitter...........................................................203
"
4.19 External Clock Selection .....................................................................................................................204
"
4.20 Power Management............................................................................................................................205
"
5 Processor Boot-Up and Memory Download ...............................................................................................208
"
5.1 IROM Boot Routine and Host Download Via PIU ...............................................................................208
"
5.2 EROM Boot Routine and DMAU Download........................................................................................209
"
6 Software Architecture .................................................................................................................................210
"
6.1 Instruction Set Quick Reference .........................................................................................................210
"
6.1.1 Conditions Based on the State of Flags ....................................................................................226
"
6.2 Registers.............................................................................................................................................227
"
6.2.1 Directly Program-Accessible (Register-Mapped) Registers......................................................227
"
6.2.2 Memory-Mapped Registers.......................................................................................................231
"
6.2.3 Register Encodings ...................................................................................................................235
"
6.2.4 Reset States..............................................................................................................................249
"
6.2.5 RB Field Encoding ....................................................................................................................252
"
7 208-Ball PBGA Package Ball Assignments ................................................................................................253
"
8 Signal Descriptions .....................................................................................................................................256
"
8.1 System Interface .................................................................................................................................257
"
8.2 BIO Interface.......................................................................................................................................257
"
8.3 System and External Memory Interface..............................................................................................257
"
8.4 SIU0 Interface .....................................................................................................................................260
"
8.5 SIU1 Interface .....................................................................................................................................261
"
8.6 PIU Interface .......................................................................................................................................262
"
8.7 JTAG0 Test Interface ..........................................................................................................................263
"
8.8 JTAG1 Test Interface ..........................................................................................................................263
"
8.9 Power and Ground..............................................................................................................................264
"
9 Device Characteristics ................................................................................................................................265
"
9.1 Absolute Maximum Ratings ................................................................................................................265
"
9.2 Handling Precautions..........................................................................................................................265
"
9.3 Recommended Operating Conditions.................................................................................................265
"
9.3.1 Package Thermal Considerations .............................................................................................266
"
10 Electrical Characteristics and Requirements ..............................................................................................267
"
10.1 Maintenance of Valid Logic Levels for Bidirectional Signals and Unused Inputs ................................268
"
10.1.1 Maintenance of Valid Logic Levels on the SEMI Interface ........................................................268
"
10.1.2 Maintenance of Valid Logic Levels on the PIU Interface...........................................................270
"
10.2 Analog Power Supply Decoupling.......................................................................................................271
"
10.3 Power Dissipation ...............................................................................................................................272
"
10.3.1 Internal Power Dissipation ........................................................................................................272
"
10.3.2 I/O Power Dissipation................................................................................................................273
"
10.4 Power Supply Sequencing..................................................................................................................275
"
11 Timing Charateristics and Requirements....................................................................................................276
"
11.1 Phase-Lock Loop ................................................................................................................................277
"
11.2 Wake-Up Latency ...............................................................................................................................278
"
11.3 DSP Clock Generation........................................................................................................................279
"
11.4 Reset Circuit .......................................................................................................................................280
"
11.5 Reset Synchronization ........................................................................................................................281
"
11.6 JTAG ...................................................................................................................................................282
Table of Contents
(continued)
Contents
Page
6
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
Data Sheet
DSP16411 Digital Signal Processor
May 2003
"
11.7 Interrupt and Trap ............................................................................................................................... 283
"
11.8 Bit I/O .................................................................................................................................................. 284
"
11.9 System and External Memory Interface.............................................................................................. 285
"
11.9.1 Asynchronous Interface ............................................................................................................ 286
"
11.9.2 Synchronous Interface .............................................................................................................. 289
"
11.9.3 ERDY Interface ......................................................................................................................... 291
"
11.10 PIU ......................................................................................................................................................292
"
11.11 SIU ......................................................................................................................................................296
"
12 Appendix--Naming Inconsistencies ........................................................................................................... 306
"
13 Outline Diagram--208-Ball PBGA .............................................................................................................. 307
"
14 Index ........................................................................................................................................................... 308
List of Figures
Figure
Page
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
7
Use pursuant to Company instructions
"
Figure 1. DSP16411 Block Diagram ..................................................................................................................15
"
Figure 2. DSP16000 Core Block Diagram .........................................................................................................21
"
Figure 3. CORE0 and CORE1 Interrupt Logic Block Diagram...........................................................................26
"
Figure 4. IMUX Block Diagram ..........................................................................................................................29
"
Figure 5. Functional Timing for INT[3:0] and TRAP ...........................................................................................34
"
Figure 6. Interprocessor Communication Logic in MGU0 and MGU1................................................................38
"
Figure 7. X-Memory Map ...................................................................................................................................44
"
Figure 8. Y-Memory Maps .................................................................................................................................45
"
Figure 9. Z-Memory Maps..................................................................................................................................46
"
Figure 10. Internal I/O Memory Map ....................................................................................................................47
"
Figure 11. Interleaved Internal TPRAM ...............................................................................................................48
"
Figure 12. Example Memory Arrangement ..........................................................................................................48
"
Figure 13. Timer Block Diagram ..........................................................................................................................54
"
Figure 14. TCS 14-Pin Connector........................................................................................................................58
"
Figure 15. JCS 20-Pin Connector ........................................................................................................................59
"
Figure 16. HDS 9-Pin Connector .........................................................................................................................60
"
Figure 17. Typical Multiprocessor JTAG Connection with Single Scan Chain.....................................................61
"
Figure 18. DMAU Interconnections and Channels...............................................................................................65
"
Figure 19. DMAU Block Diagram .........................................................................................................................66
"
Figure 20. One-Dimensional Data Structure for Buffering n Channels ................................................................83
"
Figure 21. Two-Dimensional Data Structure for Double-Buffering n Channels....................................................84
"
Figure 22. Memory-to-Memory Block Transfer ....................................................................................................86
"
Figure 23. Example of a Two-Dimensional Double-Buffered Data Structure.......................................................95
"
Figure 24. Example of One-Dimensional Data Structure .....................................................................................97
"
Figure 25. Memory-to-Memory Block Transfer ....................................................................................................99
"
Figure 26. SEMI Interface Block Diagram..........................................................................................................100
"
Figure 27. Asynchronous Memory Cycles .........................................................................................................117
"
Figure 28. Asynchronous Memory Cycles (RSETUP = 1, WSETUP = 1)..........................................................118
"
Figure 29. Asynchronous Memory Cycles (RHOLD = 1, WHOLD = 1)..............................................................119
"
Figure 30. Use of ERDY Pin to Extend Asynchronous Accesses ......................................................................120
"
Figure 31. Example of Using the ERDY Pin ......................................................................................................121
"
Figure 32. 32-Bit External Interface with 16-Bit Asynchronous SRAMs ............................................................123
"
Figure 33. 16-Bit External Interface with 16-Bit Asynchronous SRAMs ............................................................123
"
Figure 34. Synchronous Memory Cycles ...........................................................................................................125
"
Figure 35. 16-Bit External Interface with 16-Bit Pipelined, Synchronous ZBT SRAMs......................................126
"
Figure 36. 32-Bit External Interface with 32-Bit Pipelined, Synchronous ZBT SRAMs......................................127
"
Figure 37. 32-Bit PA Register Host and Core Access........................................................................................138
"
Figure 38. PIU Functional Timing for a Data Read and Write Operation ...........................................................144
"
Figure 39. PIU Functional Timing for a Register Read and Write Operation .....................................................146
"
Figure 40. SIU Block Diagram ...........................................................................................................................155
"
Figure 41. Pin Conditioning Logic, Bit Clock Selection Logic, and Frame Sync Selection Logic.......................158
"
Figure 42. Default Serial Input Functional Timing ..............................................................................................159
"
Figure 43. Default Serial Output Functional Timing ...........................................................................................160
"
Figure 44. Frame Sync to Data Delay Timing ....................................................................................................163
"
Figure 45. Clock and Frame Sync Generation with External Clock and Synchronization
(AGEXT = AGSYNC = IFSA = IFSK = 1 and Timing Requires No Resynchronization) ...................166
"
Figure 46. Clock and Frame Sync Generation with External Clock and Synchronization
(AGEXT = AGSYNC = IFSA = IFSK = 1 and Timing Requires Resynchronization) .........................167
"
Figure 47. Basic Frame Structure ......................................................................................................................168
"
Figure 48. Basic Frame Structure with Idle Time ...............................................................................................169
"
Figure 49. Channel Mode on a 128-Channel Frame .........................................................................................171
List of Figures
(continued)
Data Sheet
DSP16411 Digital Signal Processor
May 2003
Figure
Page
8
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
"
Figure 50. Subframe and Channel Selection in Channel Mode ......................................................................... 176
"
Figure 51. Generating Interrupts on Subframe Boundaries ............................................................................... 178
"
Figure 52. ST-Bus Single-Rate Clock ................................................................................................................ 183
"
Figure 53. ST-Bus Double-Rate Clock............................................................................................................... 183
"
Figure 54. Internal Clock Selection Logic ..........................................................................................................200
"
Figure 55. Clock Synthesizer (PLL) Block Diagram ........................................................................................... 201
"
Figure 56. Power Management and Clock Distribution...................................................................................... 206
"
Figure 57. Interpretation of the Instruction Set Summary Table ........................................................................ 211
"
Figure 58. DSP16411 Program-Accessible Registers for Each Core ................................................................ 228
"
Figure 59. Example Memory-Mapped Registers ............................................................................................... 231
"
Figure 60. 208-Ball PBGA Package Ball Grid Array Assignments (See-Through Top View) ............................ 253
"
Figure 61. DSP16411 Pinout by Interface ......................................................................................................... 256
"
Figure 62. Analog Supply Decoupling................................................................................................................ 271
"
Figure 63. Reference Voltage Level for Timing Characteristics and Requirements for Inputs and Outputs...... 276
"
Figure 64. I/O Clock Timing Diagram.................................................................................................................279
"
Figure 65. Powerup and Device Reset Timing Diagram ................................................................................... 280
"
Figure 66. Reset Synchronization Timing ..........................................................................................................281
"
Figure 67. JTAG I/O Timing Diagram ............................................................................................................... 282
"
Figure 68. Interrupt and Trap Timing Diagram................................................................................................... 283
"
Figure 69. Write Outputs Followed by Read Inputs (cbit = IMMEDIATE; a1 = sbit) Timing Characteristics .... 284
"
Figure 70. Enable and Write Strobe Transition Timing ...................................................................................... 285
"
Figure 71. Timing Diagram for EREQN and EACKN ......................................................................................... 286
"
Figure 72. Asynchronous Read Timing Diagram (RHOLD = 0 and RSETUP = 0) ............................................ 287
"
Figure 73. Asynchronous Write Timing Diagram (WHOLD = 0, WSETUP = 0) ................................................. 288
"
Figure 74. Synchronous Read Timing Diagram (Read-Read-Write Sequence) ................................................289
"
Figure 75. Synchronous Write Timing Diagram ................................................................................................. 290
"
Figure 76. ERDY Pin Timing Diagram ............................................................................................................... 291
"
Figure 77. Host Data Write to PDI Timing Diagram ........................................................................................... 292
"
Figure 78. Host Data Read from PDO Timing Diagram ..................................................................................... 293
"
Figure 79. Host Register Write (PAH, PAL, PCON, or HSCRATCH) Timing Diagram ...................................... 294
"
Figure 80. Host Register Read (PAH, PAL, PCON, or DSCRATCH) Timing Diagram ...................................... 295
"
Figure 81. SIU Passive Frame and Channel Mode Input Timing Diagram ........................................................ 296
"
Figure 82. SIU Passive Frame Mode Output Timing Diagram........................................................................... 297
"
Figure 83. SIU Passive Channel Mode Output Timing Diagram........................................................................ 298
"
Figure 84. SCK External Clock Source Input Timing Diagram ..........................................................................299
"
Figure 85. SIU Active Frame and Channel Mode Input Timing Diagram ........................................................... 300
"
Figure 86. SIU Active Frame Mode Output Timing Diagram ............................................................................. 302
"
Figure 87. SIU Active Channel Mode Output Timing Diagram ..........................................................................303
"
Figure 88. ST-Bus 2x Input Timing Diagram...................................................................................................... 304
"
Figure 89. ST-Bus 2x Output Timing Diagram ................................................................................................... 305
List of Tables
Table
Page
Agere Systems Inc.
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9
Use pursuant to Company instructions
Data Sheet
May 2003
DSP16411 Digital Signal Processor
"
Table 1.
DSP16411 Block Diagram Legend ..................................................................................................16
"
Table 2.
DSP16000 Core Block Diagram Legend..........................................................................................22
"
Table 3.
State of Device Output and Bidirectional Pins During and After Reset ............................................24
"
Table 4.
Hardware Interrupts .........................................................................................................................27
"
Table 5.
imux (Interrupt Multiplex Control) Register ......................................................................................28
"
Table 6.
Global Disabling and Enabling of Hardware Interrupts ....................................................................30
"
Table 7.
inc0 and inc1 (Interrupt Control) Registers 0 and 1 ........................................................................31
"
Table 8.
ins (Interrupt Status) Register..........................................................................................................32
"
Table 9.
Interrupt and Trap Vector Table .......................................................................................................33
"
Table 10.
psw1 (Processor Status Word 1) Register ......................................................................................35
"
Table 11.
signal Register ................................................................................................................................39
"
Table 12.
Full-Duplex Data Transfer Code Through Core-to-Core Message Buffer ........................................40
"
Table 13.
DMAU MMT Channel Interrupts .......................................................................................................41
"
Table 14.
DMA Intracore and Intercore Transfers Example.............................................................................41
"
Table 15.
DSP16411 Memory Components ....................................................................................................42
"
Table 16.
sbit (BIO Status/Control) Register ...................................................................................................50
"
Table 17.
cbit (BIO Control) Register ..............................................................................................................51
"
Table 18.
BIO Operations ................................................................................................................................52
"
Table 19.
BIO Flags .........................................................................................................................................52
"
Table 20.
timer
0,1
c (TIMER
0,1
Control) Register.....................................................................................55
"
Table 21.
timer
0,1
(TIMER
0,1
Running Count) Register ..........................................................................56
"
Table 22.
ID (JTAG Identification) Register .....................................................................................................57
"
Table 23.
TCS 14-Pin Socket Pinout ...............................................................................................................58
"
Table 24.
JCS 20-Pin Socket Pinout ................................................................................................................59
"
Table 25.
HDS 9-Pin, Subminiature, D-Type Plug Pinout ................................................................................60
"
Table 26.
JTAG0 Boundary-Scan Register ......................................................................................................62
"
Table 27.
JTAG1 Boundary-Scan Register ......................................................................................................63
"
Table 28.
DMAU Channel Assignment ............................................................................................................64
"
Table 29.
DMAU Memory-Mapped Registers ..................................................................................................67
"
Table 30.
DSTAT (DMAU Status) Register ......................................................................................................69
"
Table 31.
DMCON0 (DMAU Master Control 0) Register..................................................................................71
"
Table 32.
DMCON1 (DMAU Master Control 1) Register..................................................................................72
"
Table 33.
Collective Designations Used in Table 34........................................................................................73
"
Table 34.
CTL
0--3
(SWT
0--3
Control) Registers .....................................................................................74
"
Table 35.
Collective Designations Used in Table 36........................................................................................76
"
Table 36.
CTL
4--5
(MMT
4--5
Control) Registers .....................................................................................76
"
Table 37.
SADD
0--5
and DADD
0--5
(Channels 0--5 Source and Destination Address) Registers ........77
"
Table 38.
SCNT
0--3
(SWT
0--3
Source Counter) Registers .....................................................................78
"
Table 39.
SCNT
4--5
(MMT
4--5
Source Counter) Registers.....................................................................78
"
Table 40.
DCNT
0--3
(SWT
0--3
Destination Counter) Registers ..............................................................79
"
Table 41.
DCNT
4--5
(MMT
4--5
Destination Counter) Registers ..............................................................79
"
Table 42.
LIM
0--3
(SWT
0--3
Limit) Registers ..........................................................................................80
"
Table 43.
LIM
4--5
(MMT
4--5
Limit) Registers..........................................................................................80
"
Table 44.
SBAS
0--3
(SWT
0--3
Source Base Address) Registers ...........................................................81
"
Table 45.
DBAS
0--3
(SWT
0--3
Destination Base Address) Registers ....................................................81
"
Table 46.
STR
0--3
(SWT
0--3
Stride) Registers .......................................................................................82
"
Table 47.
RI
0--3
(SWT
0--3
Reindex) Registers .......................................................................................82
"
Table 48.
SWT-Specific Memory-Mapped Registers .......................................................................................88
"
Table 49.
MMT-Specific Memory-Mapped Registers .......................................................................................91
"
Table 50.
DMAU Interrupts ..............................................................................................................................92
"
Table 51.
Overview of SEMI Pins ..................................................................................................................101
List of Tables
(continued)
Table
Page
Data Sheet
DSP16411 Digital Signal Processor
May 2003
10
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Agere Systems Inc.
Use pursuant to Company instructions
"
Table 52.
Configuration Pins for the SEMI External Interface........................................................................ 102
"
Table 53.
Asynchronous Memory Bus Arbitration Pins .................................................................................. 103
"
Table 54.
Enable and Strobe Pins for the SEMI External Interface ............................................................... 104
"
Table 55.
ECKO Output Clock Pin Configuration........................................................................................... 105
"
Table 56.
Address and Data Bus Pins for the SEMI External Interface ......................................................... 107
"
Table 57.
16-Bit External Bus Configuration .................................................................................................. 109
"
Table 58.
32-Bit External Bus Configuration .................................................................................................. 109
"
Table 59.
SEMI Memory-Mapped Registers .................................................................................................. 110
"
Table 60.
ECON0 (External Control 0) Register ............................................................................................ 111
"
Table 61.
ECON1 (External Control 1) Register ............................................................................................ 112
"
Table 62.
ECKO Output Clock Pin Configuration........................................................................................... 113
"
Table 63.
EXSEG0 (CORE0 External X Segment Address Extension) Register........................................... 114
"
Table 64.
EXSEG1 (CORE1 External X Segment Address Extension) Register........................................... 114
"
Table 65.
EYSEG0 (CORE0 External Y Segment Address Extension) Register........................................... 115
"
Table 66.
EYSEG1 (CORE1 External Y Segment Address Extension) Register........................................... 115
"
Table 67.
System Bus Minimum Access Times .............................................................................................128
"
Table 68.
Access Time Per SEMI Transaction, Asynchronous Interface, 32-Bit Data Bus ........................... 133
"
Table 69.
Access Time Per SEMI Transaction, Asynchronous Interface, 16-Bit Data Bus ........................... 133
"
Table 70.
Access Time Per SEMI Transaction, Synchronous Interface, 32-Bit Data Bus .............................133
"
Table 71.
Access Time Per SEMI Transaction, Synchronous Interface, 16-Bit Data Bus .............................133
"
Table 72.
Example Average Access Time Per SEMI Transaction, 32-Bit Data Bus ...................................... 134
"
Table 73.
Example Average Access Time Per SEMI Transaction, 16-Bit Data Bus ...................................... 134
"
Table 74.
PIU Registers ................................................................................................................................. 135
"
Table 75.
PCON (PIU Control) Register ........................................................................................................ 136
"
Table 76.
PDI (PIU Data In) Register ............................................................................................................. 137
"
Table 77.
PDO (PIU Data Out) Register ........................................................................................................ 137
"
Table 78.
HSCRATCH (Host Scratch) Register .............................................................................................137
"
Table 79.
DSCRATCH (DSP Scratch) Register .............................................................................................137
"
Table 80.
PA (Parallel Address) Register....................................................................................................... 138
"
Table 81.
PIU External Interface .................................................................................................................... 139
"
Table 82.
Enable and Strobe Pins .................................................................................................................140
"
Table 83.
Address and Data Pins .................................................................................................................. 141
"
Table 84.
Flags, Interrupt, and Ready Pins....................................................................................................142
"
Table 85.
Summary of Host Commands ........................................................................................................ 147
"
Table 86.
Status/Control/Address Register Read Commands ....................................................................... 148
"
Table 87.
Status/Control/Address Register Write Commands ....................................................................... 148
"
Table 88.
Memory Read Commands ............................................................................................................. 149
"
Table 89.
Memory Write Commands ............................................................................................................. 151
"
Table 90.
SIU External Interface .................................................................................................................... 156
"
Table 91.
Control Register Fields for Pin Conditioning, Bit Clock Selection, and Frame Sync Selection ...... 157
"
Table 92.
A Summary of Bit Clock and Frame Sync Control Register Fields ................................................164
"
Table 93.
Examples of Bit Clock and Frame Sync Control Register Fields ................................................... 165
"
Table 94.
Subframe Definition........................................................................................................................ 172
"
Table 95.
Location of Control Fields Used in Channel Mode ......................................................................... 174
"
Table 96.
Description of Control Fields Used in Channel Mode .................................................................... 174
"
Table 97.
Subframe Selection ........................................................................................................................ 175
"
Table 98.
Channel Activation Within a Selected Subframe............................................................................ 175
"
Table 99.
Channel Masking Within a Selected Subframe .............................................................................. 175
"
Table 100. Control Register and Field Configuration for ST-Bus Interface ...................................................... 181
"
Table 101. Control Register and Fields That Are Configured as Required for ST-Bus Interface..................... 182
"
Table 102. SIU Registers ................................................................................................................................. 184
List of Tables
(continued)
Table
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Data Sheet
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DSP16411 Digital Signal Processor
"
Table 103. SCON0 (SIU Input/Output General Control) Register ....................................................................185
"
Table 104. SCON1 (SIU Input Frame Control) Register ..................................................................................186
"
Table 105. SCON2 (SIU Output Frame Control) Register ...............................................................................187
"
Table 106. SCON3 (SIU Input/Output Subframe Control) Register .................................................................188
"
Table 107. SCON4 (SIU Input Even Subframe Valid Vector Control) Register ...............................................189
"
Table 108. SCON5 (SIU Input Odd Subframe Valid Vector Control) Register.................................................189
"
Table 109. SCON6 (SIU Output Even Subframe Valid Vector Control) Register.............................................190
"
Table 110. SCON7 (SIU Output Odd Subframe Valid Vector Control) Register ..............................................190
"
Table 111. SCON8 (SIU Output Even Subframe Mask Vector Control) Register ............................................190
"
Table 112. SCON9 (SIU Output Odd Subframe Mask Vector Control) Register .............................................190
"
Table 113. SCON10 (SIU Input/Output General Control) Register ..................................................................191
"
Table 114. SCON11 (SIU Input/Output Active Clock Control) Register ...........................................................194
"
Table 115. SCON12 (SIU Input/Output Active Frame Sync Control) Register.................................................195
"
Table 116. SIDR (SIU Input Data) Register .....................................................................................................196
"
Table 117. SODR (SIU Output Data) Register.................................................................................................196
"
Table 118. STAT (SIU Input/Output General Status) Register .........................................................................197
"
Table 119. FSTAT (SIU Input/Output Frame Status) Register .........................................................................197
"
Table 120. OCIX
0--1
and ICIX
0--1
(SIU Output and Input Channel Index) Registers .............................198
"
Table 121. OCIX
0--1
(SIU Output Channel Index) Registers ......................................................................198
"
Table 122. ICIX
0--1
(SIU Input Channel Index) Registers ...........................................................................199
"
Table 123. Source Clock Selection ..................................................................................................................200
"
Table 124. pllcon (Phase-Lock Loop Control) Register ..................................................................................202
"
Table 125. pllfrq (Phase-Lock Loop Frequency Control) Register ..................................................................202
"
Table 126. pllfrq1 (Phase-Lock Loop Frequency Control 1) Register .............................................................202
"
Table 127. plldly (Phase-Lock Loop Delay Control) Register .........................................................................202
"
Table 128. ECKO Output Clock Pin Configuration...........................................................................................204
"
Table 129. Wake-Up Latency and Power Consumption for Low-Power Standby Mode ..................................207
"
Table 130. Core Boot-Up After Reset ..............................................................................................................208
"
Table 131. Contents of IROM0 and IROM1 Boot ROMs .................................................................................208
"
Table 132. DSP16411 Instruction Groups .......................................................................................................210
"
Table 133. Instruction Set Summary ................................................................................................................212
"
Table 134. Notation Conventions for Instruction Set Descriptions ...................................................................218
"
Table 135. Overall Replacement Table............................................................................................................219
"
Table 136. F1 Instruction Syntax .....................................................................................................................222
"
Table 137. F1E Function Statement Syntax ....................................................................................................224
"
Table 138. DSP16411 Conditional Mnemonics ...............................................................................................226
"
Table 139. Program-Accessible (Register-Mapped) Registers by Type, Listed Alphabetically .......................229
"
Table 140. DMAU Memory-Mapped Registers ................................................................................................232
"
Table 141. SEMI Memory-Mapped Registers ..................................................................................................233
"
Table 142. PIU Registers .................................................................................................................................234
"
Table 143. SIU Memory-Mapped Registers .....................................................................................................234
"
Table 144. alf (AWAIT Low-Power and Flag) Register ....................................................................................235
"
Table 145. auc0 (Arithmetic Unit Control 0) Register ......................................................................................236
"
Table 146. auc1 (Arithmetic Unit Control 1) Register ......................................................................................237
"
Table 147. cbit (BIO Control) Register ............................................................................................................238
"
Table 148. cloop (Cache Loop) Register ........................................................................................................239
"
Table 149. csave (Cache Save) Register ........................................................................................................239
"
Table 150. cstate (Cache State) Register .......................................................................................................239
"
Table 151. imux (Interrupt Multiplex Control) Register ....................................................................................240
"
Table 152. ID (JTAG
0--1
Identification) Registers .......................................................................................241
"
Table 153. inc0 and inc1 (Interrupt Control) Registers 0 and 1 ......................................................................241
List of Tables
(continued)
Table
Page
Data Sheet
DSP16411 Digital Signal Processor
May 2003
12
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Agere Systems Inc.
Use pursuant to Company instructions
"
Table 154. ins (Interrupt Status) Register........................................................................................................ 242
"
Table 155. mgi (Core-to-Core Message Input) Register ................................................................................. 242
"
Table 156. mgo (Core-to-Core Message Output) Register ............................................................................. 242
"
Table 157. pid (Processor Identification) Register........................................................................................... 242
"
Table 158. pllcon (Phase-Lock Loop Control) Register .................................................................................. 243
"
Table 159. pllfrq (Phase-Lock Loop Frequency Control) Register .................................................................. 243
"
Table 160. pllfrq1 (Phase-Lock Loop Frequency Control 1) Register .............................................................243
"
Table 161. plldly (Phase-Lock Loop Delay Control) Register ......................................................................... 243
"
Table 162. psw0 (Processor Status Word 0) Register .................................................................................... 244
"
Table 163. psw1 (Processor Status Word 1) Register .................................................................................... 245
"
Table 164. sbit (BIO Status/Control) Register ................................................................................................. 246
"
Table 165. signal (Core-to-Core Signal) Register ........................................................................................... 246
"
Table 166. timer0c and timer1c (TIMER
0,1
Control) Registers .................................................................. 247
"
Table 167. timer0 and timer1 (TIMER
0,1
Running Count) Registers .......................................................... 248
"
Table 168. vsw (Viterbi Support Word) Register .............................................................................................248
"
Table 169. Core Register States After Reset--40-Bit Registers...................................................................... 249
"
Table 170. Core Register States After Reset--32-Bit Registers...................................................................... 249
"
Table 171. Core Register States After Reset--20-Bit Registers...................................................................... 250
"
Table 172. Core Register States After Reset--16-Bit Registers...................................................................... 250
"
Table 173. Off-Core (Peripheral) Register Reset Values ................................................................................. 250
"
Table 174. Memory-Mapped Register Reset Values--32-Bit Registers .......................................................... 251
"
Table 175. Memory-Mapped Register Reset Values--20-Bit Registers .......................................................... 251
"
Table 176. Memory-Mapped Register Reset Values--16-Bit Registers .......................................................... 251
"
Table 177. RB Field .........................................................................................................................................252
"
Table 178. 208-Ball PBGA Ball Assignments Sorted Alphabetically by Symbol .............................................. 254
"
Table 179. Absolute Maximum Ratings ........................................................................................................... 265
"
Table 180. Minimum ESD Voltage Thresholds ................................................................................................ 265
"
Table 181. Recommended Operating Conditions ............................................................................................ 265
"
Table 182. Package Thermal Considerations .................................................................................................. 266
"
Table 183. Electrical Characteristics and Requirements ................................................................................. 267
"
Table 184. Effect of EYMODE Pin and BHEDIS Field ..................................................................................... 269
"
Table 185. Typical Internal Power Dissipation at 1.2 V and 285 MHz .............................................................272
"
Table 186. Typical I/O Power Dissipation at 3.3 V and 285 MHz .................................................................... 274
"
Table 187. Reference Voltage Level for Timing Characteristics and Requirements for Inputs and Outputs ...276
"
Table 188. PLL Requirements ......................................................................................................................... 277
"
Table 189. Wake-Up Latency........................................................................................................................... 278
"
Table 190. Timing Requirements for Input Clock .............................................................................................279
"
Table 191. Timing Characteristics for Output Clock......................................................................................... 279
"
Table 192. Timing Requirements for Powerup and Device Reset ...................................................................280
"
Table 193. Timing Characteristics for Device Reset ........................................................................................ 280
"
Table 194. Timing Requirements for Reset Synchronization Timing ............................................................... 281
"
Table 195. Timing Requirements for JTAG I/O ................................................................................................ 282
"
Table 196. Timing Characteristics for JTAG I/O .............................................................................................. 282
"
Table 197. Timing Requirements for Interrupt and Trap .................................................................................. 283
"
Table 198. Timing Requirements for BIO Input Read ...................................................................................... 284
"
Table 199. Timing Characteristics for BIO Output ........................................................................................... 284
"
Table 200. Timing Characteristics for ERWN and Memory Enables................................................................ 285
"
Table 201. Timing Requirements for EREQN .................................................................................................. 286
"
Table 202. Timing Characteristics for EACKN and SEMI Bus Disable ............................................................ 286
"
Table 203. Timing Requirements for Asynchronous Memory Read Operations .............................................. 287
"
Table 204. Timing Characteristics for Asynchronous Memory Read Operations ............................................ 287
List of Tables
(continued)
Table
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Use pursuant to Company instructions
Data Sheet
May 2003
DSP16411 Digital Signal Processor
"
Table 205. Timing Characteristics for Asynchronous Memory Write Operations.............................................288
"
Table 206. Timing Requirements for Synchronous Read Operations..............................................................289
"
Table 207. Timing Characteristics for Synchronous Read Operations ............................................................289
"
Table 208. Timing Characteristics for Synchronous Write Operations.............................................................290
"
Table 209. Timing Requirements for ERDY Pin...............................................................................................291
"
Table 210. Timing Requirements for PIU Data Write Operations .................................................................... 292
"
Table 211. Timing Characteristics for PIU Data Write Operations ...................................................................292
"
Table 212. Timing Requirements for PIU Data Read Operations ....................................................................293
"
Table 213. Timing Characteristics for PIU Data Read Operations...................................................................293
"
Table 214. Timing Requirements for PIU Register Write Operations...............................................................294
"
Table 215. Timing Characteristics for PIU Register Write Operations .............................................................295
"
Table 216. Timing Requirements for PIU Register Read Operations ..............................................................295
"
Table 217. Timing Characteristics for PIU Register Read Operations .............................................................295
"
Table 218. Timing Requirements for SIU Passive Frame Mode Input .............................................................296
"
Table 219. Timing Requirements for SIU Passive Channel Mode Input ..........................................................296
"
Table 220. Timing Requirements for SIU Passive Frame Mode Output ..........................................................297
"
Table 221. Timing Characteristics for SIU Passive Frame Mode Output.........................................................297
"
Table 222. Timing Requirements for SIU Passive Channel Mode Output .......................................................298
"
Table 223. Timing Characteristics for SIU Passive Channel Mode Output......................................................298
"
Table 224. Timing Requirements for SCK External Clock Source ...................................................................299
"
Table 225. Timing Requirements for SIU Active Frame Mode Input................................................................300
"
Table 226. Timing Characteristics for SIU Active Frame Mode Input ..............................................................300
"
Table 227. Timing Requirements for SIU Active Channel Mode Input.............................................................301
"
Table 228. Timing Characteristics for SIU Active Channel Mode Input ...........................................................301
"
Table 229. Timing Requirements for SIU Active Frame Mode Output .............................................................302
"
Table 230. Timing Characteristics for SIU Active Frame Mode Output............................................................302
"
Table 231. Timing Requirements for SIU Active Channel Mode Output ..........................................................303
"
Table 232. Timing Characteristics for SIU Active Channel Mode Output.........................................................303
"
Table 233. ST-Bus 2x Input Timing Requirements ..........................................................................................304
"
Table 234. ST-Bus 2x Output Timing Requirements .......................................................................................305
"
Table 235. ST-Bus 2x Output Timing Characteristics ......................................................................................305
"
Table 236. Pin Name Inconsistencies ..............................................................................................................306
"
Table 237. Register Name Inconsistencies......................................................................................................306
Data Sheet
DSP16411 Digital Signal Processor
May 2003
14
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Agere Systems Inc.
Use pursuant to Company instructions
3 Notation Conventions
The following notation conventions apply to this data
sheet.
Table 134 on page 218
specifies the notation
conventions for the DSP16000 instruction set.
lower-case
Registers that are directly writable or
readable by DSP16411 core instruc-
tions are lower-case.
UPPER-CASE Device flags, I/O pins, control register
fields, and registers that are not directly
writable or readable by DSP16411 core
instructions are upper-case.
boldface
Register names and DSP16411 core
instructions are printed in boldface
when used in text descriptions.
italics
Documentation variables that are
replaced are printed in italics.
courier
DSP16411 program examples or
C-language representations are printed
in courier font.
[ ]
Square brackets enclose a range of
numbers that represents multiple bits in
a single register or bus. The range of
numbers is delimited by a colon. For
example, imux[11:10] are bits 11 and
10 of the program-accessible imux reg-
ister.
Angle brackets enclose a list of items
delimited by commas or a range of
items delimited by a dash (--), one of
which is selected if used in an
instruction. For example, SADD
0--3
represents the four memory-mapped
registers SADD0, SADD1, SADD2,
and SADD3, and the general instruc-
tion aTE
h,l
= RB can be replaced
with a0h = timer0.
blue
In this document, blue text or the blue
graphic object
"
indicates a hypertext
link. Click on the text or
"
to display
the referenced item.
4 Hardware Architecture
4.1 DSP16411 Architectural Overview
The DSP16411 device is a 16-bit fixed-point program-
mable digital signal processor (DSP). The DSP16411
consists of two DSP16000 cores together with on-chip
memory and peripherals. Advanced architectural fea-
tures with an expanded instruction set deliver a dra-
matic increase in performance compared to traditional
DSP architectures for signal coding algorithms. This
increase in performance, together with an efficient
design implementation, results in an extremely cost-
efficient and power-efficient solution for wireless and
multimedia applications.
Figure 1 on page 15
shows a block diagram of the
DSP16411.
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
15
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.1 DSP16411 Architectural Overview
(continued)
DSP16411B Block Diagram
Figure 1. DSP16411 Block Diagram
YDB YAB
XDB XAB
YDB YAB
XDB XAB
IDB
XAB0
XDB0
YAB0
YDB0
YAB1
YDB1
32
20
32
32
20
32
20
CORE0
SAB
SDB
ZEAB
ZEDB
ZIDB
ZIAB
SDB SAB
ZEDB
ZEAB
SDB SAB
32
20
TPRAM0
IROM0
PAB DPI
27
16
PIU
SIU0
DMAU
DSI0
DSI1
IMUX0
imux
32
MGU0
signal
jiob
BOUNDARY SCAN
JTAG0
TIMER0_0
TIMER1_0
TIMER0_1
TIMER1_1
32
BIO0
pid
16
16
HDS0
cbit
PD[15:0]
PODS
PCSN
PIDS
PADD[3:0]
PRWN
PRDYMD
POBE
PIBF
PRDY
PINT
SDB
SAB
SIU1
SICK0
SID0
SIFS0
SOCK0
SOD0
SOFS0
SCK0
SICK1
SID1
SIFS1
SOCK1
SOD1
SOFS1
SCK1
ED[31:0]
EA[18:0]
ERAMN
EROMN
EION
ERWN[1:0]
ECKO
EREQN
EACKN
ERDY
EXM
ERTYPE
ESIZE
INT[3:0]
TCK0
TMS0
TDO0
TDI0
TRST0N
CKI
RSTN
TRAP
IO0BIT[6:0]
IO1BIT[6:0]
TCK1
TMS1
TDO1
TDI1
TRST1N
INT[3:0]
SEMI
CLK
DDO
DDO
DDO
DSI
DSI
DDO
XAB
XDB
YAB
YDB
IDB
CORE1
(160K x 16)
MGU1
IMUX1
imux
CLOCK/CONTROL
pllcon
20
XAB1
XDB1
ZSEG
ZSEG
4
YDB YAB
XDB XAB
ZIDB
ZIAB
TPRAM1
(160K x 16)
IROM1
SLM
(2K x 16)
32
20
SDB SAB
32
20
PAB DPI
32
ESEG[3:0]
16
16
20
32
16
16
BIO1
SDB SAB
32
20
TO IMUX1
TO HDS1/MGU1
TRAP
ZIAB
ZIDB
sbit
cbit
timer1
timer1c
timer1
timer1c
timer0
timer0c
timer0
timer0c
mgi
mgo
mgo
mgi
signal
pid
20
32
ID
pllfrq
plldly
jiob
BOUNDARY SCAN
JTAG1
HDS1
ID
KEY:
OFF-CORE REGISTER-MAPPED REGISTERS
ACCESSIBLE BY CORE0
sbit
OFF-CORE REGISTER-MAPPED REGISTERS
ACCESSIBLE BY CORE1
pllfrq1
Data Sheet
DSP16411 Digital Signal Processor
May 2003
16
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.1 DSP16411 Architectural Overview
(continued)
Table 1. DSP16411 Block Diagram Legend
Symbol
Description
BIO
0--1
Bit I/O Units. One for each core.
cbit
16-Bit BIO Control Register.
CLK
Internal Clock Signal.
CORE0
DSP16000 Core--System Master.
CORE1
DSP16000 Core--System Slave.
DDO
DMA Data Out. (For transferring data from DMAU to PIU, SIU0, and SIU1.)
DMAU
Direct Memory Access Unit.
DPI
DMA Parallel In. (For transferring 16-bit data from PIU to DMAU.)
DSI0
DMA Serial Data In Zero. (For transferring data from SIU0 to DMAU.)
DSI1
DMA Serial Data In One. (For transferring data from SIU1 to DMAU.)
HDS
0--1
Hardware Development Systems. One for each core.
ID
JTAG Port Identification Register Accessible Via the JTAG Port. One for each of the two JTAG
0--1
ports.
IDB
Internal Data Bus. One for each core.
imux
16-Bit IMUX Control Register.
IMUX
0--1
Interrupt Multiplexers. One for each core; selects ten interrupts from DMAU, SIU0, SIU1, PIU, INT[3:0],
TIMER
0--1
, and MGU.
IROM
0--1
Internal Read-Only Memories (one for each core) for Boot and HDS Code.
jiob
32-Bit JTAG Test Register.
JTAG
0--1
JTAG Test Ports. One for each core.
mgi
16-Bit Core-to-Core Message Input Register.
mgo
16-Bit Core-to-Core Message Output Register.
MGU
0--1
Core-to-Core Messaging Unit. One for each core.
PAB
27-Bit Parallel Address Bus. (For DMAU/PIU communications.)
pid
16-Bit Processor ID Register (CORE0: 0x0000; CORE1: 0x0001).
PIU
Parallel Interface Unit. (16-bit parallel host interface.)
pllcon
16-Bit Phase-Lock Loop Control Register.
pllfrq
16-Bit Phase-Lock Loop Frequency Control Register.
pllfrq1
16-Bit Phase-Lock Loop Frequency Control 1 Register.
plldly
16-Bit Phase-Lock Loop Delay Control Register.
SAB
20-Bit System Address Bus. Address for system bus (S-bus) accesses.
sbit
16-Bit BIO Status/Control Register.
SDB
32-Bit System Data Bus. Data for system bus (S-bus) accesses.
SEMI
System and External Memory Interface.
signal
16-Bit Signal Register for Core-to-Core Communication.
SIU0
Serial Input/Output Unit Zero.
SIU1
Serial Input/Output Unit One.
SLM
2 Kword Shared Local Memory.
timer0
16-Bit Timer Running Count Register for TIMER0.
TIMER0_0
Programmable Timer 0 for CORE0.
TIMER0_1
Programmable Timer 0 for CORE1.
timer0c
16-Bit Timer Control Register for TIMER0.
timer1
16-Bit Timer Running Count Register for TIMER1.
TIMER1_0
Programmable Timer 1 for CORE0.
TIMER1_1
Programmable Timer 1 for CORE1.
Table 1. DSP16411 Block Diagram Legend (continued)
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
17
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.1 DSP16411 Architectural Overview
(continued)
4.1.1 DSP16000 Cores
The two DSP16000 cores (CORE0 and CORE1) are
the signal-processing engines of the DSP16411. The
DSP16000 is a modified Harvard architecture with sep-
arate sets of buses for the instruction/coefficient
(X-memory) and data (Y-memory) spaces. Each set of
buses has 20 bits of address and 32 bits of data. The
core contains data and address arithmetic units and
control for on-chip memory and peripherals.
4.1.2 Clock Synthesizer (PLL)
The DSP16411 powers up with an input clock (CKI) as
the source for the processor clock (CLK). An on-chip
clock synthesizer (PLL) that runs at a frequency multi-
ple of CKI can also be used to generate CLK. The
clock synthesizer is deselected and powered down on
reset. The selection of the clock source is under soft-
ware control of CORE0. See
Section 4.17, beginning
on page 200,
for details.
4.1.3 Triport RAMs (TPRAM
0--1
)
Each core has a private block of TPRAM consisting of
160 banks (banks 0--159) of zero wait-state memory.
Each bank consists of 1K 16-bit words and has three
separate address and data ports: one port to the core's
instruction/coefficient (X-memory) space, a second
port to the core's data (Y-memory) space, and a third
port to the DMA (Z-memory) space. TPRAM0 is
accessible by CORE0, TPRAM1 is accessible by
CORE1, and both TPRAM0 and TPRAM1 are accessi-
ble by the DMAU. TPRAM is organized into even and
odd interleaved banks for which each even/odd
address pair is a 32-bit wide module (see
Section 4.7
on page 48
for details). The TPRAMs support single-
word, aligned double-word, and misaligned double-
word accesses.
4.1.4 Shared Local Memory (SLM)
The SLM consists of two banks of memory. Each bank
consists of 1K 16-bit words. The SLM can be
accessed by both cores and by the DMAU and PIU
over the system bus (SAB, SDB). The SLM supports
single-word (16-bit) and aligned double-word (32-bit)
accesses. Misaligned double-word accesses are not
supported. An access to the SLM takes multiple clock
cycles to complete, and a core access to the SLM
causes the core to incur wait-states. See
Section 4.14.7.1 on page 128
for details on system bus
performance.
4.1.5 Internal Boot ROMs (IROM
0--1
)
Each core has its own boot ROM that contains a single
boot routine and software to support the Agere hard-
ware development system (HDS). The code in IROM0
and IROM1 is identical. See
Section 5 on page 208
for
details.
4.1.6 Messaging Units (MGU
0--1
)
The DSP16411 provides an MGU for each core: MGU0
for CORE0 and MGU1 for CORE1. The MGUs provide
interprocessor (core-to-core) communication and inter-
rupt generation. See
Section 4.5 on page 38
for
details.
timer1c
16-Bit Timer Control Register for TIMER1.
TPRAM
0--1
160 Kword Three-Port Random-Access Memories (one for each core). Private code (X), data (Y), and
DMA (Z).
XAB
0--1
20-Bit X-Memory Space Address Bus. One for each core.
XDB
0--1
32-Bit X-Memory Space Data Bus. One for each core.
YAB
0--1
20-Bit Y-Memory Space Address Bus. One for each core.
YDB
0--1
32-Bit Y-Memory Space Data Bus. One for each core.
ZEAB
20-Bit External Z-Memory Space Address Bus. Interfaces DMAU to SEMI.
ZEDB
32-Bit External Z-Memory Space Data Bus. Interfaces DMAU to SEMI.
ZIAB
20-Bit Internal Z-Memory Space Address Bus. Interfaces DMAU to TPRAM0 and TPRAM1.
ZIDB
32-Bit Internal Z-Memory Space Data Bus. Interfaces DMAU to TPRAM0 and TPRAM1.
ZSEG
External Segment Address Bits Associated with ZEAB. Interfaces DMAU to SEMI.
Symbol
Description
Data Sheet
DSP16411 Digital Signal Processor
May 2003
18
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.1 DSP16411 Architectural
Overview
(continued)
4.1.7 System and External Memory Interface
(SEMI)
The SEMI interfaces both cores and the DMAU to
external memory and I/O devices. It interfaces directly
to pipelined synchronous ZBT TM
SRAMs and asyn-
chronous SRAMs. The SEMI also interfaces the cores
and the DMAU to the internal SLM and to memory-
mapped registers in the DMAU, PIU, SIU0, and SIU1
via the internal system bus or S-bus (SAB and
SDB). See
Section 4.14, beginning on page 100,
for
details.
4.1.8 Bit Input/Output Units (BIO
0--1
)
The DSP16411 provides a BIO unit for each core: BIO0
for CORE0 and BIO1 for CORE1. Each BIO unit pro-
vides convenient and efficient monitoring and control of
seven individually configurable pins. If configured as
outputs, the pins can be individually set, cleared, or
toggled. If configured as inputs, individual pins or com-
binations of pins can be tested for patterns. Flags
returned by the BIO can be tested by conditional
instructions. See
Section 4.9 on page 50
for details.
4.1.9 Timer Units (TIMER0_
0--1
and
TIMER1_
0--1
)
The DSP16411 provides two timer units for each core:
TIMER0_0 and TIMER1_0 for CORE0, and TIMER0_1
and TIMER1_1 for CORE1. Each timer can be used to
provide an interrupt, either single or repetitive, at the
expiration of a programmed interval. More than nine
orders of magnitude of interval selection are provided.
See
Section 4.10 on page 53
for more information.
4.1.10 Direct Memory Access Unit (DMAU)
The direct memory access unit (DMAU) manages data
transfers in the DSP16411 memory space. Data can
be moved between DSP16411 memory and peripher-
als and between different memory spaces in the
DSP16411. Once initiated, DMAU transfers occur with-
out core intervention. The DMAU supports concurrent
core execution and I/O processing. See
Section 4.13,
beginning on page 64,
for details.
4.1.11 Interrupt Multiplexers (IMUX
0--1
)
The DSP16411 provides an interrupt multiplexer unit
for each core: IMUX0 for CORE0 and IMUX1 for
CORE1. Each IMUX multiplexes the 26 hardware
interrupts into the 20 available hardware interrupt
requests for each core. See
Section 4.4.2 on page 28
for details.
4.1.12 Parallel Interface Unit (PIU)
The parallel interface unit (PIU) is a 16-bit parallel port
that provides a host processor direct access to the
entire DSP16411 memory system (including memory-
mapped peripheral registers). See
Section 4.15,
beginning on page 135,
for details.
4.1.13 Serial Interface Units (SIU
0--1
)
The DSP16411 provides two identical SIUs. Each SIU
is a full-duplex, double-buffered serial port with inde-
pendent input and output frame and bit clock control.
Clock and frame signals can be generated externally
(passive) or by on-chip clock and frame generation
hardware (active). The SIU features multiple-channel
TDM mode for ST-bus (1x and 2x compatible) and
T1/E1 compatibility. Each SIU is provided a DMAU
interface for data transfer to memory (TPRAM0,
TPRAM1, SLM, memory-mapped registers, or external
memory) without core intervention. See
Section 4.16,
beginning on page 154,
for details.
4.1.14 Test Access Ports (JTAG
0--1
)
The DSP16411 provides a JTAG unit for each core:
JTAG0 for CORE0 and JTAG1 for CORE1. See
Section 4.12 on page 57
for details.
4.1.15 Hardware Development Systems
(HDS
0--1
)
The DSP16411 provides an HDS unit for each core:
HDS0 for CORE0 and HDS1 for CORE1. Each HDS is
an on-chip hardware module available for debugging
assembly-language programs that execute on the
DSP16000 core in real-time. The main capability of the
HDS is in allowing controlled visibility into the core's
state during program execution. The HDS is enhanced
with powerful debugging capabilities such as complex
breakpointing conditions, multiple data/address watch-
point registers, and an intelligent trace mechanism for
recording discontinuities. See
Section 4.11 on page 56
for details.
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
19
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.2 DSP16000 Core Architectural Overview
The DSP16411 contains two identical DSP16000
cores. As shown in
Figure 2 on page 21
, each core
consists of four major blocks: system control and cache
(SYS), data arithmetic unit (DAU), Y-memory space
address arithmetic unit (YAAU), and X-memory space
address arithmetic unit (XAAU). Bits within the auc0
and auc1 registers configure the DAU mode-controlled
operations. See the DSP16000 Digital Signal Proces-
sor Core
Information Manual for a complete description
of the DSP16000 core.
4.2.1 System Control and Cache (SYS)
This section consists of the control block and the
cache.
The control block provides overall system coordination
that is mostly invisible to the user. The control block
includes an instruction decoder and sequencer, a
pseudorandom sequence generator (PSG), an inter-
rupt and trap handler, a wait-state generator, and low-
power standby mode control logic. An interrupt and trap
handler provides a user-locatable vector table and
three levels of user-assigned interrupt priority.
SYS contains the alf register, which is a 16-bit register
that contains AWAIT, a power-saving standby mode
bit, and peripheral flags. The inc0 and inc1 registers
are 20-bit interrupt control registers, and ins is a 20-bit
interrupt status register.
Programs use the instruction cache to store and exe-
cute repetitive operations such as those found in an
FIR or IIR filter section. The cache can contain up to
thirty-one 16-bit and 32-bit instructions. The code in the
cache can repeat up to 2
16
1 times without looping
overhead. Operations in the cache that require a coeffi-
cient access execute at twice the normal rate because
the XAAU and its associated bus are not needed for
fetching instructions. The cache greatly reduces the
need for writing in-line repetitive code and, therefore,
reduces instruction/coefficient memory size require-
ments. In addition, the use of cache reduces power
consumption because it eliminates memory accesses
for instruction fetches.
The cache provides a convenient, low-overhead loop-
ing structure that is interruptible, savable, and restor-
able. The cache is addressable in both the X and Y
memory spaces. An interrupt or trap handling routine
can save and restore cloop, cstate, csave, and the
contents of the cache. The cloop register controls the
cache loop count. The cstate register contains the cur-
rent state of the cache. The 32-bit csave register holds
the opcode of the instruction following the loop instruc-
tion in program memory.
4.2.2 Data Arithmetic Unit (DAU)
The DAU is a power-efficient, dual-MAC (multiply/accu-
mulate), parallel-pipelined structure that is tailored to
communications applications. It can perform two dou-
ble-word (32-bit) fetches, two multiplications, and two
accumulations in a single instruction cycle. The dual-
MAC parallel pipeline begins with two 32-bit registers,
x and y. The pipeline treats the 32-bit registers as four
16-bit signed registers if used as input to two signed
16-bit x 16-bit multipliers. Each multiplier produces a
full 32-bit result stored into registers p0 and p1. The
DAU can direct the output of each multiplier to a 40-bit
ALU or a 40-bit 3-input ADDER. The ALU and ADDER
results are each stored in one of eight 40-bit accumula-
tors, a0 through a7. Both the ALU and ADDER include
an ACS (add/compare/select) function for Viterbi
decoding. The DAU can direct the output of each accu-
mulator to the ALU/ACS, the ADDER/ACS, or a 40-bit
BMU (bit manipulation unit).
The ALU implements 2-input addition, subtraction, and
various logical operations. The ADDER implements
2-input or 3-input addition and subtraction. To support
Viterbi decoding, the ALU and ADDER have a split
mode in which two simultaneous 16-bit additions or
subtractions are performed. This mode, available in
specialized dual-MAC instructions, is used to compute
the distance between a received symbol and its esti-
mate.
The ACS provides the add/compare/select function
required for Viterbi decoding. This unit provides flags to
the traceback encoder for implementing mode-con-
trolled side-effects for ACS operations. The source
operands for the ACS are any two accumulators, and
results are written back to one of the source accumula-
tors.
The BMU implements barrel-shift, bit-field insertion, bit-
field extraction, exponent extraction, normalization, and
accumulator shuffling operations. ar0 through ar3 are
auxiliary registers whose main function is to control
BMU operations.
The user can enable overflow saturation to affect the
multiplier output and the results of the three arithmetic
units. Overflow saturation can also affect an accumula-
tor value as it is transferred to memory or other
register. These features accommodate various speech
coding standards such as GSM-FR, GSM-HR, and
GSM-EFR. Shifting in the arithmetic pipeline occurs at
several stages to accommodate various standards for
mixed-precision and double-precision multiplications.
Data Sheet
DSP16411 Digital Signal Processor
May 2003
20
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.2 DSP16000 Core Architectural
Overview
(continued)
4.2.2 Data Arithmetic Unit (DAU) (continued)
The DAU contains control and status registers auc0,
auc1, psw0, psw1, vsw, and c0--c2.
The arithmetic unit control registers auc0 and auc1
select or deselect various modes of DAU operation.
These modes include scaling of products, saturation on
overflow, feedback to the x and y registers from accu-
mulators a6 and a7, simultaneous loading of x and y
registers with the same value (used for single-cycle
squaring), and clearing the low half of registers when
loading the high half to facilitate fixed-point operations.
The processor status word registers psw0 and psw1
contain flags set by ALU/ACS, ADDER, or BMU opera-
tions. They also include information on the current sta-
tus of the interrupt controller.
The vsw register is the Viterbi support word associated
with the traceback encoder. The traceback encoder is a
specialized block for accelerating Viterbi decoding. The
vsw controls side-effects for three compare functions:
cmp0( ), cmp1( ), and cmp2( ). These instructions are
part of the MAC group that utilizes the traceback
encoder. The side-effects allow the DAU to store, with
no overhead, state information necessary for traceback
decoding. Side-effects use the c1 counter, the ar0 and
ar1 auxiliary registers, and bits 1 and 0 of vsw.
The c1 and c0 counters are 16-bit signed registers
used to count events such as the number of times the
program has executed a sequence of code. The c2
register is a holding register for counter c1. Conditional
instructions control these counters and provide a con-
venient method of program looping.
4.2.3 Y-Memory Space Address Arithmetic Unit
(YAAU)
The YAAU supports high-speed, register-indirect, data
memory addressing with postincrement of the address
register. Eight 20-bit pointer registers (r0--r7) store
read or write addresses for the data (Y-memory) space.
Two sets of 20-bit registers (rb0 and re0; rb1 and re1)
define the upper and lower boundaries of two zero-
overhead circular buffers for efficient filter implementa-
tions. The j and k registers are two 20-bit signed regis-
ters that are used to hold user-defined postincrement
values for r0--r7. Fixed increments of +1, 1, 0, +2,
and 2 are also available. (Postincrement options 0
and 2 are not available for some specialized transfers.
See the DSP16000 Digital Signal Processor Core Infor-
mation Manual for details.)
The YAAU includes a 20-bit stack pointer (sp). The
data move group includes a set of stack instructions
that consists of push, pop, stack-relative, and pipelined
stack-relative operations. The addressing mode used
for the stack-relative instructions is register-plus-dis-
placement indirect addressing (the displacement is
optional). The displacement is specified as either an
immediate value as part of the instruction or a value
stored in j or k. The YAAU computes the address by
adding the displacement to sp and leaves the contents
of sp unchanged. The data move group also includes
instructions with register-plus-displacement indirect
addressing for the pointer registers r0--r6 in addition
to sp.
The data move group of instructions includes instruc-
tions for loading and storing any YAAU register from or
to memory or another core register. It also includes
instructions for loading any YAAU register with an
immediate value stored with the instruction. The
pointer arithmetic group of instructions allows adding of
an immediate value or the contents of the j or k register
to any YAAU pointer register and storing the result to
any YAAU register.
4.2.4 X-Memory Space Address Arithmetic Unit
(XAAU)
The XAAU contains registers and an adder that control
the sequencing of instructions in the processor. The
program counter (PC ) automatically increments
through the instruction space. The interrupt return reg-
ister pi, the subroutine return register pr, and the trap
return register ptrap are automatically loaded with the
return address of an interrupt service routine, subrou-
tine, and trap service routine, respectively. High-speed,
register-indirect, read-only memory addressing with
postincrementing is done with the pt0 and pt1 regis-
ters. The signed registers h and i are used to hold a
user-defined signed postincrement value. Fixed postin-
crement values of 0, +1, 1, +2, and 2 are also avail-
able. (Postincrement options 0 and 2 are available
only if the target of the data transfer is an accumulator.
See the DSP16000 Digital Signal Processor Core Infor-
mation Manual for details.)
The data move group includes instructions for loading
and storing any XAAU register from or to memory or
another core register. It also includes instructions for
loading any XAAU register with an immediate value
stored with the instruction.
vbase is the 20-bit vector base offset register. The user
programs this register with the base address of the
interrupt and trap vector table.
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
21
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.2 DSP16000 Core Architectural Overview
(continued)
4.2.5 Core Block Diagram
DSP16000 Core Block Diagram
Figure 2. DSP16000 Core Block Diagram
pr (20)
ptrap(20)
DAU
+
XAAU
SINGLE
1, 0, 1
MUX
+
YAAU
MUX
COMPARE
SYS
cstate (16)
csave (32)
CACHE
CONTROL
(32)
IMMEDIATE
OFF-
CORE
SHIFT(2, 1, 0, 2)/SAT.
16
16 MULTIPLY
16
16 MULTIPLY
SPLIT/MUX
SAT.
ALU/ACS
ADDER/ACS
BMU
MUX
MUX
MUX/EXTRACT
ENCODER
TRACEBACK
SHIFT(0, 1)
SHIFT(0, 1)
SWAP MUX
SHIFT(0, 1)
SHIFT
(0, 14)
SAT.
SHIFT(0, 15, 16)
SAT.
SAT.
SHIFT(2, 1, 0, 2)/SAT.
KEY:
PROGRAM-ACCESSIBLE REGISTERS
MODE-CONTROLLED OPTIONS
PSG
BUSES
VALUE
SAT.
SAT.
SAT.
ar0 (16)
ar1 (16)
ar2 (16)
ar3 (16)
c0 (16)
c1 (16)
c2 (16)
vsw (16)
auc0 (16)
auc1 (16)
psw0 (16)
psw1 (16)
y (32)
x (32)
p0 (32)
p1 (32)
a0 (40)
a2 (40)
a3 (40)
a4 (40)
a5 (40)
a6 (40)
a7 (40)
a1 (40)
ins (20)
inc0 (20)
inc1 (20)
cloop (16)
PC (20)
pt0 (20)
pt1 (20)
pi (20)
vbase (20)
(20)
(20)
XDB
(32)
IDB
(32)
YAB
YAB
(20)
(20)
re0 (20)
re1 (20)
rb0 (20)
rb1 (20)
r0 (20)
r1 (20)
r2 (20)
r3 (20)
r4 (20)
r5 (20)
r6 (20)
r7 (20)
sp (20)
k (20)
j (20)
DOUBLE
2, 0, 2
31 INSTRUCTIONS
alf (16)
(32)
XDB
IDB
(32)
SINGLE
1, 0, 1
MUX
IMMEDIATE
VALUE
i (20)
h (20)
DOUBLE
2, 0, 2
Associated with PC-relative branch addressing.
XAB
(20)
YAB
(20)
TO
MEMORY
FROM
MEMORY
TO/FROM
MEMORY
TO
MEMORY
(32)
IDB
(32)
TO
PERIPH-
ERAL
XDB
YDB
XAB
XAB
Associated with register-plus-displacement indirect addressing.
MU
X
k (20)
j (20)
re0 (20)
re1 (20)
rb0 (20)
rb1 (20)
r0 (20)
r1 (20)
r2 (20)
r3 (20)
r4 (20)
r5 (20)
r6 (20)
r7 (20)
sp (20)
ar0 (16)
ar1 (16)
ar2 (16)
ar3 (16)
c0 (16)
c1 (16)
c2 (16)
vsw (16)
auc0 (16)
auc1 (16)
psw0 (16)
psw1 (16)
y (32)
x (32)
p0 (32)
p1 (32)
a0 (40)
a2 (40)
a3 (40)
a4 (40)
a5 (40)
a6 (40)
a7 (40)
a1 (40)
SHIFT(2, 1, 0, 2)/SAT.
SAT.
SAT.
SAT.
SAT.
SHIFT(2, 1, 0, 2)/SAT.
SAT.
SAT.
SAT.
pr (20)
ptrap(20)
cstate (16)
csave (32)
ins (20)
inc0 (20)
inc1 (20)
cloop (16)
pt0 (20)
pt1 (20)
pi (20)
vbase (20)
alf (16)
i (20)
h (20)
MU
X
DEMUX
Data Sheet
DSP16411 Digital Signal Processor
May 2003
22
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.2 DSP16000 Core Architectural Overview
(continued)
4.2.5 Core Block Diagram (continued)
Table 2. DSP16000 Core Block Diagram Legend
Symbol
Name
16 x 16 MULTIPLY
16-Bit x 16-Bit Multiplier.
a0--a7
40-Bit Accumulators 0--7.
ADDER/ACS
3-Input 40-Bit Adder/Subtractor and Add/Compare/Select Function. Used in Viterbi decoding.
alf
16-Bit AWAIT Low-Power and Flags Register.
ALU/ACS
40-Bit Arithmetic Logic Unit and Add/Compare/Select Function. Used in Viterbi decoding.
ar0--ar3
16-Bit Auxiliary Registers 0--3.
auc0, auc1
16-Bit Arithmetic Unit Control Registers.
BMU
40-Bit Manipulation Unit.
c0, c1
16-Bit Counters 0 and 1.
c2
16-Bit Counter Holding Register.
cloop
16-Bit Cache Loop Count Register.
COMPARE
Comparator. Used for circular buffer addressing.
csave
32-Bit Cache Save Register.
cstate
16-Bit Cache State Register.
DAU
Data Arithmetic Unit.
h
20-Bit Pointer Postincrement Register for the X-Memory Space.
i
20-Bit Pointer Postincrement Register for the X-Memory Space.
IDB
32-Bit Internal Data Bus.
inc0, inc1
20-Bit Interrupt Control Registers 0 and 1.
ins
20-Bit Interrupt Status Register.
j
20-Bit Pointer Postincrement/Offset Register for the Y-Memory Space.
k
20-Bit Pointer Postincrement/Offset Register for the Y-Memory Space.
MUX
Multiplexer.
p0, p1
32-Bit Product Registers 0 and 1.
PC
20-Bit Program Counter.
pi
20-Bit Program Interrupt Return Register.
pr
20-Bit Program Return Register.
PSG
Pseudorandom Sequence Generator.
psw0, psw1
16-Bit Processor Status Word Registers 0 and 1.
pt0, pt1
20-Bit Pointers 0 and 1 to X-Memory Space.
ptrap
20-Bit Program Trap Return Register.
r0--r7
20-Bit Pointers 0--7 to Y-Memory Space.
rb0, rb1
20-Bit Circular Buffer Pointers 0 and 1 (begin address).
re0, re1
20-Bit Circular Buffer Pointers 0 and 1 (end address).
SAT
Saturation.
SHIFT
Shifting Operation.
sp
20-Bit Stack Pointer.
SPLIT/MUX
Split/Multiplexer. Routes the appropriate ALU/ACS, BMU, and ADDER/ACS outputs to the appropriate
accumulator.
SWAP MUX
Swap Multiplexer. Routes the appropriate data to the appropriate multiplier input.
SYS
System Control and Cache.
vbase
20-Bit Vector Base Offset Register.
vsw
16-Bit Viterbi Support Word. Associated with the traceback encoder.
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
23
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.2 DSP16000 Core Architectural Overview
(continued)
Table 2. DSP16000 Core Block Diagram Legend (continued)
4.2.5 Core Block Diagram (continued)
4.3 Device Reset
The DSP16411 has three negative-assertion external
reset input pins: RSTN, TRST0N, and TRST1N. RSTN
is used to reset both CORE0 and CORE1. The primary
function of TRST0N and TRST1N is to reset the JTAG0
and JTAG1 controllers.
4.3.1 Reset After Powerup or Power Interruption
At initial powerup or if power is interrupted,
a reset is
required and RSTN, TRST0N, and TRST1N must all
be asserted (low) simultaneously for at least seven CKI
cycles (see
Section 11.4 on page 280
for details). The
TRST0N and TRST1N pins must be asserted even if
the JTAG controllers are not used by the application.
Failure to properly reset the device on powerup or after
a power interruption can lead to a loss of communica-
tion with the DSP16411 pins.
4.3.2 RSTN Pin Reset
The device is properly reset by asserting RSTN (low)
for at least seven CKI cycles and then deasserting
RSTN. Reset initializes the state of user registers,
synchronizes the internal clocks, and initiates code
execution. See
Section 6.2.4, beginning on page 249,
for the values of the user registers after reset.
After RSTN is deasserted, there is a delay of several
CKI cycles before the DSP16000 cores begin execut-
ing instructions (see
Section 11.5 on page 281
for
details). The state of the EXM pin on the rising edge of
RSTN controls the boot program address for both
cores, as described in
Section 5 on page 208
.
x
32-Bit Multiplier Input Register.
XAAU
X-Memory Space Address Arithmetic Unit.
XAB
X-Memory Space Address Bus.
XDB
X-Memory Space Data Bus.
y
32-Bit Multiplier Input Register.
YAAU
Y-Memory Space Address Arithmetic Unit.
YAB
Y-Memory Space Address Bus.
YDB
Y-Memory Space Data Bus.
Symbol
Name
Data Sheet
DSP16411 Digital Signal Processor
May 2003
24
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Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.3 Device Reset
(continued)
4.3.2 RSTN Pin Reset (continued)
Table 3
defines the states of the output and bidirectional pins both during and after reset. It does not include the
TDO0 and TDO1 output pins because their state is not affected by RSTN. The state of TDO0 and TDO1 are
affected only by the JTAG0 and JTAG1 controllers.
4.3.3 JTAG Controller Reset
The recommended method of resetting the JTAG controllers is to assert RSTN, TRST0N, and TRST1N low simul-
taneously. An alternate method is to clock TCK
0,1
through at least five cycles with TMS
0, 1
held high. Both
methods ensure that the user has control of the device pins. JTAG controller reset places it in the test logic reset
(TLR) state and does not initialize user registers, synchronize internal clocks, or initiate code execution unless
RSTN is also asserted (see
Section 6.2.4 on page 249
).
Table 3. State of Device Output and Bidirectional Pins During and After Reset
Type
Pin
Condition
State of Pin
During Reset (RSTN = 0)
Initial State of Pin
After Reset (RSTN = 1)
Output
PIBF, PINT
--
logic low
logic low
PRDY
PRDYMD = 0
logic low
logic low
PRDYMD = 1
logic high
logic high
EACKN, EION, ERAMN,
EROMN, ERWN0, ERWN1
INT0 = 0
(deasserted)
logic high
logichigh
INT0 = 1
(asserted)
3-state
logic high
POBE
--
logic high
logic high
SOD0, SOD1
--
3-state
3-state
ECKO
INT0 = 0
(deasserted)
logic low
CKI/2
INT0 = 1
(asserted)
3-state
CKI/2
EA[18:0]
The output/bidirectional pins EA[18:0], ESEG[3:0], ED[31:0], and PD[15:0] include bus hold circuits. If BHEDIS (ECON1[12]--
Table 61 on
page 112
) = 0, the bus hold circuits on EA[18:0], ESEG[3:0], and ED[31:0] are activated. If BHPDIS (ECON1[13]) = 0, the bus hold circuits on
PD[15:0] and PADD[3:0] are activated. The bus hold circuits are enabled and activated (BHEDIS = BHPDIS = 0) during and after reset. Acti-
vated bus hold circuits affect the electrical characteristics of the associated pins. See
Section 10.1, beginning on page 268,
and
Table 183 on
page 267
for details.
INT0 = 0
(deasserted)
logic low
logic low
INT0 = 1
(asserted)
3-state
logic low
ESEG[3:0]
INT0 = 0
(deasserted)
logic low
logic low
INT0 = 1
(asserted)
3-state
logic low
Bidirectional
(Input/Output)
PD[15:0]
--
3-statet
configured input
IO0BIT[6:0], IO1BIT[6:0]
SICK0, SICK1, SIFS0, SIFS1,
SOCK0, SOCK1, SOFS0,
SOFS1, TRAP
--
3-state
configured input
ED[31:0]
EYMODE = 0
3-state
3-state
EYMODE = 1
output
output
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
25
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.4 Interrupts and Traps
Each core in the DSP16411 supports the following
interrupts and traps:
!
26 hardware interrupts with three levels of user-
assigned priority:
-- 1 core-to-core interrupt.
-- 10 general DMAU interrupts.
-- 1 DMAU interrupt under control of the other core.
-- 4 SIU interrupts.
-- 3 PIU interrupts.
-- 1 MGU interrupt.
-- 2 timer interrupts.
-- 4 external interrupt pins.
!
64 software interrupts for each core, generated by
the execution of an icall IM6 instruction.
!
The TRAP pin.
!
The core-to-core trap.
Because the DSP16000 core supports a maximum of
20 hardware interrupts and the DSP16411 provides
26 hardware interrupts, each core has an associated
programmable interrupt multiplexer (IMUX
0,1
).
The interrupt and trap vectors are in contiguous loca-
tions in memory, and the base (starting) address of the
vectors is configurable in the core's vbase register.
Each interrupt and trap source is preassigned to a
unique vector offset that differentiates its service rou-
tine.
The core must reach an interruptible or trappable state
(completion of an interruptible or trappable instruction)
before it services an interrupt or trap. If the core ser-
vices an interrupt or trap, it saves the contents of its
program counter (PC) and begins executing instruc-
tions at the corresponding location in its vector table.
For interrupts, the core saves its PC in its program
interrupt (pi) register. For traps, the core saves its PC
in its program trap (ptrap) register. After servicing the
interrupt or trap, the servicing routine must return to the
interrupted or trapped program by executing an ireturn
or treturn instruction.
The core's ins register (see
Table 8 on page 32
) con-
tains a 1-bit status field for each of its hardware inter-
rupts. If a hardware interrupt occurs, the core sets the
corresponding ins field to indicate that the interrupt is
pending. If the core services that interrupt, it clears the
corresponding ins field. The psw1 register (see
Table 10 on page 35
) includes control and status bits
for the core's hardware interrupt logic.
If a hardware interrupt is disabled, the core does not
service it. If a hardware interrupt is enabled, the core
services it according to its priority. Device reset glo-
bally disables hardware interrupts. An application can
globally enable or disable hardware interrupts and can
individually enable or disable each hardware interrupt.
An application globally enables hardware interrupts by
executing the ei (enable interrupts) instruction and glo-
bally disables them by executing the di (disable inter-
rupts) instruction. Within an interrupt service routine
(ISR), the execution of an ireturn instruction also glo-
bally enables hardware interrupts. An application can
individually enable a hardware interrupt at an assigned
priority or individually disable a hardware interrupt by
configuring the inc0 or inc1 register (see
Table 7 on
page 31
).
Software interrupts emulate hardware interrupts. The
core services software interrupts even if hardware
interrupts are globally disabled.
A trap is similar to an interrupt but has the highest pos-
sible priority. An application cannot disable traps by
executing a di instruction or by any other means.
Traps do not nest, i.e., a trap service routine (TSR)
cannot be interrupted or trapped. A trap does not
affect the state of the psw1 register.
The DSP16000 Digital Signal Processor Core Informa-
tion Manual provides an extensive discussion of inter-
rupts and traps. The remainder of
Section 4.4
describes the interrupts and traps for the DSP16411.
4.4.1 Hardware Interrupt Logic
Figure 3 on page 26
illustrates the path of each inter-
rupt from its generating peripheral or pin to the interrupt
logic of CORE0 and CORE1. Some of the interrupts
connect directly to the cores, and others connect via
the IMUX
0,1
block. Some of the interrupts are spe-
cific to a core, and some are common to both cores.
The programmer can configure IMUX
0,1
using the
corresponding imux register. The programmer can
divide processing of the multiplexed interrupts PIBF,
POBE, S
O
,
I
INT
0,1
, DSINT[3:0], DDINT[3:0],
DMINT[5:4], and INT[3:2] between CORE0 and
CORE1, or cause some of these interrupts to be com-
mon to both cores by defining the fields in each core's
imux register. See
Section 4.4.2 on page 28
for
details on interrupt multiplexing.
Data Sheet
DSP16411 Digital Signal Processor
May 2003
26
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.4 Interrupts and Traps
(continued)
4.4.1 Hardware Interrupt Logic (continued)
Interrupt Block Diagram
These interrupts are specific to a core, not common to both cores.
Each of the MXI[9:0] interrupts can be either specific to a core or common to both cores, determined by how each interrupt is configured in
imux (see
Table 5 on page 28
).
Figure 3. CORE0 and CORE1 Interrupt Logic Block Diagram
TIMER0_0
IMUX0
MGU0
PIU
DMAU
CORE0
CORE1
IMUX1
MGU1
TIMER1_0
TIMER0_1
TIMER1_1
PIBF (PIU)
POBE (PIU)
INT[3:2]
DSINT[3:0], DDINT[3:0], DMINT[5:4]
S
O,I
INT
0,1
10
4
XIO
MXI[9:0]
XIO
10
10
MGIBF
SIGINT
INT[1:0]
PHINT
MXI[9:0]
MGIBF
SIGINT
DMINT[5:4]
PHINT
TIME0
TIME1
TIME0
TIME1
INT[1:0]
DMINT[5:4]
2
2
INT[1:0]
(SIU
0,1
)
inc0
imux
KEY:
PROGRAM-ACCESSIBLE REGISTERS
2
inc1
ins
inc0
inc1
ins
imux
Data Sheet
May 2003
DSP16411 Digital Signal Processor
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Agere Systems--Proprietary
27
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.4 Interrupts and Traps
(continued)
4.4.1 Hardware Interrupt Logic (continued)
Table 4
summarizes each hardware interrupt in the DSP16411, including whether it is internal or external, which
module generates it, and a brief description. For details on the operation of each internal interrupt, see the section
that describes the corresponding block.
Table 4. Hardware Interrupts
Interrupt
Type
Name
Description
DSINT0
Internal
DMAU Source Interrupt for SWT0 (for SIU0)
Channel SWT0
source (output) interrupt request.
DDINT0
Internal DMAU Destination Interrupt for SWT0 (for SIU0) Channel SWT0
destination (input) interrupt request.
DSINT1
Internal
DMAU Source Interrupt for SWT1 (for SIU0)
Channel SWT1
source (output) interrupt request.
DDINT1
Internal DMAU Destination Interrupt for SWT1 (for SIU0) Channel SWT1
destination (input) interrupt request.
DSINT2
Internal
DMAU Source Interrupt for SWT2 (for SIU1)
Channel SWT2
source (output) interrupt request.
DDINT2
Internal DMAU Destination Interrupt for SWT2 (for SIU1) Channel SWT2
destination (input) interrupt request.
DSINT3
Internal
DMAU Source Interrupt for SWT3 (for SIU1)
Channel SWT3
source (output) interrupt request.
DDINT3
Internal DMAU Destination Interrupt for SWT3 (for SIU1) Channel SWT3
destination (input) interrupt request.
DMINT4
Internal
DMAU Interrupt for MMT4
Channel MMT4
interrupt request.
DMINT5
Internal
DMAU Interrupt for MMT5
Channel MMT5
interrupt request.
INT[3:0]
External
External Interrupt Requests
An external device has requested service by asserting
the corresponding INT[3:0] pin (0-to-1 transition).
MGIBF
Internal
MGU Input Buffer Full
The MGU input buffer (mgi) is full.
PHINT
Internal
PIU Host Interrupt
The host sets the HINT field (PCON[4]).
PIBF
Internal
PIU Input Buffer Full
PDI contains data from a previous host write operation.
POBE
Internal
PIU Output Buffer Empty
The data in PDO has been read by the host.
SIGINT
Internal
Signal Interrupt (Core-to-Core)
The other core sets its signal[0] field.
SIINT0
Internal
SIU0 Input Interrupt
Based on the IINTSEL[1:0] field (SCON10[12:11]),
asserted if:
!
Input frame sync detected.
!
Input subframe transfer complete.
!
Input channel transfer complete.
!
Input error occurs.
SIINT1
Internal
SIU1 Input Interrupt
SOINT0
Internal
SIU0 Output Interrupt
Based on the OINTSEL[1:0] field (SCON10[14:13]):
!
Output frame sync detected.
!
Output subframe transfer complete.
!
Output channel transfer complete.
!
Output error occurs.
SOINT1
Internal
SIU1 Output Interrupt
TIME0
Internal
TIMER0 Delay/Interval Reached
TIMER0 has reached zero count.
TIME1
Internal
TIMER1 Delay/Interval Reached
TIMER1 has reached zero count.
XIO
Internal
Core-to-Core DMAU Interrupt
Based on the other core's XIOC[1:0] field:
!
Zero (logic low).
!
DMINT4 (MMT4 transfer complete).
!
DMINT5 (MMT5 transfer complete).
An SWT channel is a single-word transfer channel used for both input and output by an SIU. It transfers single words (16 bits).
An MMT channel is a memory-to-memory channel used by the cores to copy a block from any area of memory to any other area of memory. It
transfers single words (16 bits) or double words (32 bits).
Data Sheet
DSP16411 Digital Signal Processor
May 2003
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Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.4 Interrupts and Traps
(continued)
4.4.2 Hardware Interrupt Multiplexing
The total number of DSP16411 hardware interrupt sources (26) exceeds the number of interrupt requests sup-
ported by the DSP16000 core (20). Therefore, each core includes an interrupt multiplexer block (IMUX) and asso-
ciated control register (imux) to permit the 26 interrupts to be multiplexed into the 20 available hardware interrupt
requests. Each core supports ten dedicated interrupt requests. Each core's IMUX block multiplexes the remaining
16 hardware requests into the ten remaining hardware interrupt request lines.
Table 5
describes the imux register and
Figure 4 on page 29
illustrates the IMUX block.
Table 5. imux (Interrupt Multiplex Control) Register
15--14
13--12
11--10
9--8
7
6
5
4
3
2
1
0
XIOC[1:0]
Reserved
IMUX9[1:0]
IMUX8[1:0]
IMUX7 IMUX6 IMUX5 IMUX4 IMUX3 IMUX2 IMUX1 IMUX0
Bit
Field
Controls
Multiplexed
Interrupt
Value
Interrupt
Selected
Description
R/W Reset
Value
15--14
XIOC[1:0]
XIO
00
0 (logic low)
--
R/W
00
01
DMINT4
DMAU interrupt for MMT4.
10
DMINT5
DMAU interrupt for MMT5.
11
Reserved
Reserved.
13--12
Reserved
--
0
--
Reserved--write with zero.
R/W
0
11--10
IMUX9[1:0]
MXI9
00
INT3
Pin.
R/W
00
01
POBE
PIU output buffer empty.
10
PIBF
PIU input buffer full.
11
Reserved
Reserved.
9--8
IMUX8[1:0]
MXI8
00
INT2
Pin.
R/W
00
01
POBE
PIU output buffer empty.
10
PIBF
PIU input buffer full.
11
Reserved
Reserved.
7
IMUX7
MXI7
0
SIINT1
SIU1 input interrupt.
R/W
0
1
DDINT2
DMAU destination interrupt for SWT2 (SIU1).
6
IMUX6
MXI6
0
SOINT1
SIU1 output interrupt.
R/W
0
1
DSINT2
DMAU source interrupt for SWT2 (SIU1).
5
IMUX5
MXI5
0
SIINT0
SIU0 input interrupt.
R/W
0
1
DDINT0
DMAU destination interrupt for SWT0 (SIU0).
4
IMUX4
MXI4
0
SOINT0
SIU0 output interrupt.
R/W
0
1
DSINT0
DMAU source interrupt for SWT0 (SIU0).
3
IMUX3
MXI3
0
DDINT2
DMAU destination interrupt for SWT2 (SIU1). R/W
0
1
DDINT3
DMAU destination interrupt for SWT3 (SIU1).
2
IMUX2
MXI2
0
DSINT2
DMAU source interrupt for SWT2 (SIU1).
R/W
0
1
DSINT3
DMAU source interrupt for SWT3 (SIU1).
1
IMUX1
MXI1
0
DDINT0
DMAU destination interrupt for SWT0 (SIU0). R/W
0
1
DDINT1
DMAU destination interrupt for SWT1 (SIU0).
0
IMUX0
MXI0
0
DSINT0
DMAU source interrupt for SWT0 (SIU0).
R/W
0
1
DSINT1
DMAU source interrupt for SWT1 (SIU0).
The XIOC[1:0] field controls the XIO interrupt for the other core.
Data Sheet
May 2003
DSP16411 Digital Signal Processor
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Agere Systems--Proprietary
29
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.4 Interrupts and Traps
(continued)
4.4.2 Hardware Interrupt Multiplexing (continued)
IMUX Block Diagram
Figure 4. IMUX Block Diagram
MUX
MXI0
DSINT0
DSINT1
I
MUX0 (imux[0])
XIO (TO OTHER CORE)
0
DMINT4
DMINT5
XIOC[1:0] (imux[15:14])
MXI8
INT2
POBE
PIBF
IMUX8[1:0] (imux[9:8])
MXI9
INT3
POBE
PIBF
IMUX9[1:0] (imux[11:10])
MXI1
DDINT0
DDINT1
IMUX1 (imux[1])
MXI2
DSINT2
DSINT3
IMUX2 (imux[2])
MXI3
DDINT2
DDINT3
IMUX3 (imux[3])
MXI4
SOINT0
DSINT0
IMUX4 (imux[4])
MXI5
SIINT0
DDINT0
IMUX5 (imux[5])
MXI6
SOINT1
DSINT2
IMUX6 (imux[6])
MXI7
SIINT1
DDINT2
IMUX7 (imux[7])
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
IMUX
0,1
2
2
2
Data Sheet
DSP16411 Digital Signal Processor
May 2003
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Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.4 Interrupts and Traps
(continued)
4.4.3 Clearing Core Interrupt Requests
Internal hardware interrupt signals are pulses that the core latches into its ins register (see
Section 4.4.7 on
page 32
). Therefore, the user software need not clear the interrupt request. However, in the case of the PIU host
interrupt, PHINT, the user software must clear the HINT field (PCON[4]) to allow the host to request a subsequent
interrupt. See
Section 4.15.7 on page 153
for details.
4.4.4 Host Interrupt Output
The DSP16411 provides an interrupt output pin, PINT, that can interrupt a host processor connected to the PIU. A
core can assert this pin by setting the PINT field (PCON[3]). The host must clear the PINT field to allow a core to
request a subsequent interrupt. See
Section 4.15.7 on page 153
for details.
4.4.5 Globally Enabling and Disabling Hardware Interrupts
A device reset globally disables interrupts, i.e., the core does not service interrupts by default after reset. The
application must execute an ei instruction to globally enable interrupts, i.e., to cause the core to service interrupts
that are individually enabled.
Section 4.4.6 on page 31
describes individually enabling and disabling
interrupts. Executing the di instruction globally disables interrupts.
The core automatically globally disables interrupts if it begins servicing an interrupt, i.e., interrupt nesting is dis-
abled by default. When the ireturn instruction that the programmer must place at the end of the ISR is executed,
the core automatically globally re-enables interrupts. Therefore, the programmer does not need to explicitly re-
enable interrupts by executing an ei instruction before exiting the ISR. An interrupt service routine (ISR) can allow
nesting, i.e., can be interrupted by a higher-priority interrupt, if it globally enables interrupts in the correct sequence
as described in
Section 4.4.11 on page 35
, Nesting Interrupts.
The one-bit IEN field (psw1[14]--see
Table 10 on page 35
) is cleared if hardware interrupts are globally
disabled. The IEN field is set if interrupts are globally enabled.
Table 6
summarizes global disabling and enabling of hardware interrupts.
Table 6. Global Disabling and Enabling of Hardware Interrupts
Condition
Caused By
Indicated By
Effect
Hardware interrupts
globally
disabled
!
Device reset
!
Execution of a di instruction
!
The core begins to service an interrupt
IEN (psw1[14]) = 0
Core does not service
interrupts.
Hardware interrupts
globally
enabled
!
Execution of an ei instruction
!
Execution of an ireturn instruction
IEN (psw1[14]) = 1
Core services individually
enabled interrupts.
With the exception of device reset, CORE0 and CORE1 are independent with respect to global disabling and enabling of hardware interrupts.
Data Sheet
May 2003
DSP16411 Digital Signal Processor
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Agere Systems--Proprietary
31
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.4 Interrupts and Traps
(continued)
4.4.6 Individually Enabling, Disabling, and Prioritizing Hardware Interrupts
An application can individually disable a hardware interrupt by clearing both bits of its corresponding 2-bit field in
the inc0 or inc1 register (see
Table 7
). Reset clears the inc0 and inc1 registers, individually disabling all hard-
ware interrupts by default. An application can individually enable a hardware interrupt at one of three priority levels
by setting one or both bits of its corresponding 2-bit field in the inc0 or inc1 register.
The following are the advantages of interrupt prioritization:
!
An ISR can service concurrent interrupts according to their priority.
!
Interrupt nesting is supported, i.e., an interrupt can interrupt a lower-priority ISR. See
Section 4.4.11 on page 35
for details on interrupt nesting.
If multiple concurrent interrupts with the same assigned priority occur, the core first services the interrupt that has
its status field in the relative least significant bit location of the ins register (see
Table 8 on page 32
), i.e., the core
first services the interrupt with the lowest vector address (see
Table 9 on page 33
).
Note: If interrupts are globally enabled (see
Section 4.4.5 on page 30
), an application must not change inc
0--1
,
because doing so can cause a potential race condition between the detection of the interrupts and the deter-
mination of their relative priorities. Prior to changing inc
0--1
, the application must globally disable inter-
rupts by executing a di instruction. After changing inc
0--1
, the application can globally re-enable
interrupts by executing an ei instruction.
The following code segment is an example of properly changing inc
0--1
:
di
// Globally disable interrupts (default after reset).
inc1=0x00001
// Enable MGIBF at level 1 priority.
ei
// OK to globally re-enable interrupts.
di
// Before changing inc1, first globally disable interrupts.
inc1=0x00006
// Change MGIBF priority to level 2...
// Enable SIGINT at level 1 priority.
ei
// OK to globally re-enable interrupts.
Table 7. inc0 and inc1 (Interrupt Control) Registers 0 and 1
19--18
17--16
15--14
13--12
11--10
9--8
7--6
5--4
3--2
1--0
inc0 INT1[1:0] INT0[1:0] DMINT5[1:0] DMINT4[1:0] MXI3[1:0] MXI2[1:0] MXI1[1:0] MXI0[1:0] TIME1[1:0] TIME0[1:0]
inc1 MXI9[1:0] MXI8[1:0]
MXI7[1:0]
MXI6[1:0]
MXI5[1:0] MXI4[1:0] PHINT[1:0] XIO[1:0] SIGINT[1:0] MGIBF[1:0]
Field
Value
Description
R/W
Reset
Value
INT
0--1
[1:0]
DMINT
4--5
[1:0]
MXI
0--9
[1:0]
TIME
0--1
[1:0]
PHINT[1:0]
XIO[1:0]
SIGINT[1:0]
MGIBF[1:0]
00
Disable the selected interrupt (no priority).
R/W
00
01
Enable the selected interrupt at priority 1 (lowest).
10
Enable the selected interrupt at priority 2.
11
Enable the selected interrupt at priority 3 (highest).
See
Table 5 on page 28
for definition of MXI
0--9
(IMUX
0--9
).
Data Sheet
DSP16411 Digital Signal Processor
May 2003
32
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.4 Interrupts and Traps
(continued)
4.4.7 Hardware Interrupt Status
If a hardware interrupt occurs, the core sets the corre-
sponding bit in the ins register (
Table 8
) to indicate that
the interrupt is pending. If the core services the inter-
rupt, it clears the ins bit. Alternatively, if the application
uses interrupt polling (
Section 4.4.13 on page 37
), the
application program must explicitly clear the ins bit by
writing a 1 to that bit and a 0 to every other ins bit.
Writing a 0 to an ins bit leaves that bit unchanged. A
reset clears the ins register, indicating that no inter-
rupts are pending.
If a hardware interrupt occurs, the core sets its ins bit
(i.e., latches the interrupt as pending) regardless of
whether the interrupt is enabled or disabled. If a hard-
ware interrupt occurs while it is disabled and the inter-
rupt is later enabled, the core services the interrupt
after servicing any other pending interrupts of equal or
higher priority.
Note: The DSP16000 core globally disables interrupts
when it begins executing instructions in the vec-
tor table. If the ISR does not globally enable
interrupts by following the procedure specified in
Section 4.4.11 on page 35
, Nesting Interrupts,
and the same interrupt reoccurs while the core is
executing the ISR, the interrupt is not latched
into ins and is therefore not recognized by the
core.
4.4.8 Interrupt and Trap Vector Table
The interrupt and trap vectors for a core are in contigu-
ous locations in memory. The base (starting) address
of the vectors is configurable in the core's vbase
register. Each interrupt and trap source is pre-
assigned to a unique vector offset within a 352-word
vector table (see
Table 9 on page 33
). The program-
mer can place at the vector location an instruction that
branches to an interrupt service routine (ISR) or trap
service routine (TSR). After servicing the interrupt or
trap, the ISR or TSR must return to the interrupted or
trapped program by executing an ireturn or treturn
instruction. Alternatively, the programmer can place at
the vector location up to four words of instructions that
service the interrupt or trap, the last of which must be
an ireturn or treturn.
Table 8. ins (Interrupt Status) Register
19
18
17
16
15
14
13
12
11
10
MXI9
MXI8
MXI7
MXI6
MXI5
MXI4
PHINT
XIO
SIGINT
MGIBF
9
8
7
6
5
4
3
2
1
0
INT1
INT0
DMINT5
DMINT4
MXI3
MXI2
MXI1
MXI0
TIME1
TIME0
Field
Value
Description
R/W
Reset
Value
MXI
0--9
PHINT
XIO
SIGINT
MGIBF
INT
0--1
DMINT
4--5
TIME
0--1
0
Read--corresponding interrupt not pending.
Write--no effect.
R/Clear
0
1
Read--corresponding interrupt is pending.
Write--clears bit and changes corresponding interrupt status to not
pending.
See
Table 5 on page 28
for definition of MXI
0--9
(IMUX
0--9
).
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
33
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.4 Interrupts and Traps
(continued)
4.4.8 Interrupt and Trap Vector Table (continued)
Table 9. Interrupt and Trap Vector Table
Vector Description
Vector Address
Priority
Hexadecimal
Decimal
Reserved
vbase + 0x0
vbase + 0
--
PTRAP
vbase + 0x4
vbase + 4
6 (Highest)
UTRAP
vbase + 0x8
vbase + 8
5
Reserved
vbase + 0xC
vbase + 12
--
TIME0
vbase + 0x10
vbase + 16
0--3
TIME1
vbase + 0x14
vbase + 20
0--3
MXI0 (DSINT0 or DSINT1
)
vbase + 0x18
vbase + 24
0--3
MXI1 (DDINT0 or DDINT1
)
vbase + 0x1C
vbase + 28
0--3
MXI2 (DSINT2 or DSINT3
)
vbase + 0x20
vbase + 32
0--3
MXI3 (DDINT2 or DDINT3
)
vbase + 0x24
vbase + 36
0--3
DMINT4
vbase + 0x28
vbase + 40
0--3
DMINT5
vbase + 0x2C
vbase + 44
0--3
INT0
vbase + 0x30
vbase + 48
0--3
INT1
vbase + 0x34
vbase + 52
0--3
MGIBF
vbase + 0x38
vbase + 56
0--3
SIGINT
vbase + 0x3C
vbase + 60
0--3
XIO
vbase + 0x40
vbase + 64
0--3
PHINT
vbase + 0x44
vbase + 68
0--3
MXI4 (SOINT0 or DSINT0
)
vbase + 0x48
vbase + 72
0--3
MXI5 (SIINT0 or DDINT0
)
vbase + 0x4C
vbase + 76
0--3
MXI6 (SOINT1 or DSINT2
)
vbase + 0x50
vbase + 80
0--3
MXI7 (SIINT1 or DDINT2
)
vbase + 0x54
vbase + 84
0--3
MXI8 (INT2, POBE, or PIBF
)
vbase + 0x58
vbase + 88
0--3
MXI9 (INT3, POBE, or PIBF
)
vbase + 0x5C
vbase + 92
0--3
icall 0
vbase + 0x60
vbase + 96
--
icall 1
vbase + 0x64
vbase + 100
--
--
icall 62
vbase + 0x158
vbase + 344
--
icall 63
vbase + 0x15C
vbase + 348
--
vbase contains the base address of the 352-word vector table.
Driven by TRAP pin (see
Section 4.4.10 on page 34
) or core-to-core trap (see
Section 4.5.1 on page 39
).
Reserved for HDS.
The programmer specifies the relative priority levels 0--3 for hardware interrupts via inc0 and inc1 (see
Table 7 on page 31
). Level 0 indicates a dis-
abled interrupt. If multiple concurrent interrupts with the same assigned priority occur, the core first services the interrupt that has its status field in the
relative least significant bit location of the ins register (see
Table 8 on page 32
); i.e., the core first services the interrupt with the lowest vector
address.
The choice of interrupt is selected by the imux register (see
Table 5 on page 28
).
Reserved for system services.
...
...
...
Data Sheet
DSP16411 Digital Signal Processor
May 2003
34
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Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.4 Interrupts and Traps
(continued)
4.4.9 Software Interrupts
Software interrupts emulate hardware interrupts. A
software interrupt is always enabled and has no
assigned priority and no corresponding field in the ins
register. A program causes a software interrupt by exe-
cuting an icall IM6 instruction, where IM6 is replaced
with 0--63. When a software interrupt is serviced, the
core saves the contents of PC in the pi register and
transfers control to the interrupt vector defined in
Table 9 on page 33
.
CAUTION: If a software interrupt is inserted into an
ISR, it is explicitly nested in the ISR and
therefore the ISR must be structured for
nesting. See
Section 4.4.11 on page 35
for more information about nesting
interrupts.
4.4.10 INT[3:0] and TRAP Pins
The DSP16411 provides four positive-assertion edge-
detected interrupt pins (INT[3:0]) and a bidirectional
positive-assertion edge-detected trap pin (TRAP).
The TRAP pin is used by an application to gain control
of both processors for asynchronous event handling,
typically for catastrophic error recovery. It is a 3-state
bidirectional pin that connects to both cores and both
HDS blocks. TRAP is connected directly to both cores
via the PTRAP signal. After reset, TRAP is configured
as an input; it can be configured as an output under
JTAG control to support HDS multiple-device debug-
ging.
Figure 5 is a functional timing diagram for the INT[3:0]
and TRAP pins. A low-to-high transition of one of
these pins asserts the corresponding interrupt or trap.
INT[3:0] or TRAP must be held high for a minimum of
two CLK cycles and must be held low for at least two
CLK cycles before being reasserted. If INT[3:0] or
TRAP is asserted and stays high, the core services the
interrupt or trap only once.
A minimum of four cycles
1
after INT[3:0] or PTRAP is
asserted, the core services the interrupt or trap by exe-
cuting instructions starting at the vector location as
defined in
Table 9 on page 33
. In the case of PTRAP, a
maximum of three instructions are allowed to execute
before the core services the trap.
Functional Timing for INT[3:0] and TRAP
Figure 5. Functional Timing for INT[3:0] and TRAP
1. The number of cycles depends on the number of wait-states incurred by the interrupted or trapped instruction.
ECKO
A
B
INT[3:0]/TRAP
ECKO is programmed to be the internal clock CLK (the ECKOB[1:0] field (ECON1[3:2]--see
Table 61 on page 112
) which is programmed to
00 and the ECKOA[1:0] field (ECON1[1:0]) is programmed to 01).
The INT[3:0] or TRAP pin must be held high for a minimum of two CLK cycles and must be held low for a minimum of two CLK cycles before
being reasserted.
Notes:
A. The DSP16411 synchronizes INT[3:0] or TRAP on the falling edge of the internal clock CLK.
B. A minimum four-cycle delay before the core services the interrupt or trap (executes instructions starting at the vector location). For a trap, the
core executes a maximum of three instructions before it services the trap.
Data Sheet
May 2003
DSP16411 Digital Signal Processor
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Agere Systems--Proprietary
35
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.4 Interrupts and Traps
(continued)
4.4.11 Nesting Interrupts
The psw1 register (see
Table 10
) contains the IPL
C
[1:0] and IPL
P
[1:0] fields that are used for interrupt
nesting. See the DSP16000 Digital Signal Processor Core Information Manual for details on these fields.
Table 10. psw1 (Processor Status Word 1) Register
15
14
13--12
11--10
9--7
6
5--0
Reserved
IEN
IPL
C
[1:0]
IPL
P
[1:0]
Reserved
EPAR
a[7:2]V
Bit
Field
Value
Description
R/W
Reset
Value
15
Reserved
0
Reserved--write with zero.
R/W
0
14
IEN
0
Hardware interrupts are globally disabled.
R
0
1
Hardware interrupts are globally enabled.
13--12
IPL
C
[1:0]
00
Current hardware interrupt priority level is 0; core handles pending interrupts of
priority 1, 2, or 3.
R/W
00
01
Current hardware interrupt priority level is 1; core handles pending interrupts of
priority 2 or 3.
10
Current hardware interrupt priority level is 2; core handles pending interrupts of
priority 3 only.
11
Current hardware interrupt priority level is 3; core does not handle any pending
interrupts.
11--10
IPL
P
[1:0]
00
Previous hardware interrupt priority level
was 0.
R/W
XX
01
Previous hardware interrupt priority level
was 1.
10
Previous hardware interrupt priority level
was 2.
11
Previous hardware interrupt priority level
was 3.
9--7
Reserved
0
Reserved--write with zero.
R/W
X
6
EPAR
0
Most recent BMU or special function shift result has odd parity.
R/W
X
1
Most recent BMU or special function shift result has even parity.
5
a7V
0
The current contents of a7 are not mathematically overflowed.
R/W
X
1
The current contents of a7 are mathematically overflowed.
4
a6V
0
The current contents of a6 are not mathematically overflowed.
R/W
X
1
The current contents of a6 are mathematically overflowed.
3
a5V
0
The current contents of a5 are not mathematically overflowed.
R/W
X
1
The current contents of a5 are mathematically overflowed.
2
a4V
0
The current contents of a4 are not mathematically overflowed.
R/W
X
1
The current contents of a4 are mathematically overflowed.
1
a3V
0
The current contents of a3 are not mathematically overflowed.
R/W
X
1
The current contents of a3 are mathematically overflowed.
0
a2V
0
The current contents of a2 are not mathematically overflowed.
R/W
X
1
The current contents of a2 are mathematically overflowed.
In this column, X indicates unknown on powerup reset and unaffected on subsequent reset.
The user clears this bit by executing a di instruction and sets it by executing an ei or ireturn instruction. The core clears this bit whenever it begins to
service an interrupt.
Previous interrupt priority level is the priority level of the interrupt most recently serviced prior to the current interrupt. This field is used for interrupt
nesting.
The most recent DAU result that was written to that accumulator resulted in mathematical overflow (LMV) with FSAT = 0.
Data Sheet
DSP16411 Digital Signal Processor
May 2003
36
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.4 Interrupts and Traps
(continued)
4.4.11 Nesting Interrupts (continued)
Caution: The procedure for nesting interrupts described below is different than that described in
Section 5.4.9 of the DSP16000 Digital Signal Processor Core Information Manual. The DSP16411
contains version 2 of the DSP16000 core, and the manual describes version 1 of the core. See the
DSP16K V2 Core Nested Interrupt Design Exception Advisory (AY01-033WINF) for details.
The DSP16000 core automatically globally disables interrupts when it begins servicing an interrupt, disabling inter-
rupt nesting by default. To allow interrupt nesting, the interrupt service routine (ISR) must perform the steps speci-
fied in the following ISR code example. The code segment highlighted in bold globally enables interrupts in the
proper sequence. This code segment replaces the ei instruction in the ISR code example described in
Section 5.4.11 of the DSP16000 Digital Signal Processor Core Information Manual. (The code example in
Section 5.4.11 of the information manual contains additional instructions needed if the main body of the ISR uses
cache loops. These instructions have been omitted from the following example for simplicity.)
// Save Context:
ISR:
push pi
// Save pi to stack
- needed for nesting.
push psw1
// Save psw1 to stack
- needed for nesting.
push cstate // Save cstate to stack - needed for nesting.
cstate=0
// Clear cstate
- needed for nesting.
// (The cstate register must be saved and cleared so that, if this ISR has interrupted
// a cache loop and this ISR is interrupted by a higher-priority interrupt, the ireturn
// in the higher-priority ISR returns to this ISR and not to the cache loop.)
// Save (push) any other registers to stack that will be used in BODY below.
// If required, execute noninterruptible user code here.
// Globally enable interrupts -- replaces ei instruction and is needed for nesting.
push psw1
// Save current state of IPL
C
and IPL
P
.
pi=JMP
// Set jump location for ireturn.
psw1=0x3C00 // Set IPL
C
=IPL
P
=3 (set core to highest priority level) so that
// no interrupts will be accepted until psw1 is restored.
ireturn
// Globally enable interrupts and goto pi (JMP).
JMP:
pop psw1
// Restore psw1 -- restore core to correct priority level.
////////////////////////////////////////////////////////////////////////////////////
//
BODY -- Main body of ISR that services the interrupt. Can be interrupted
//
//
by an interrupt of higher priority.
//
////////////////////////////////////////////////////////////////////////////////////
di
// Globally disable interrupts for restoring state.
// If required, execute noninterruptible user code here.
// Restore (pop) any other registers from stack that have been saved (pushed).
pop cstate
// Restore cstate from stack.
pop psw1
// Restore psw1 from stack.
pop pi
// Restore pi from stack.
ireturn
// Return from interrupt and globally enable interrupts.
Data Sheet
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DSP16411 Digital Signal Processor
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Agere Systems--Proprietary
37
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.4 Interrupts and Traps
(continued)
4.4.12 Interrupts and Cache Usage
If an ISR or TSR uses cache (do or redo) loops, then it must first save the state of the cache and then restore it
before returning to normal program execution. This is necessary because the interrupt or trap can occur during the
execution of a cache loop. See Section 3.5.2.7 and Section 5.4.11 of the DSP16000 Digital Signal Processor Core
Information Manual for details on saving and restoring the state of the cache.
4.4.13 Interrupt Polling
If a core disables an interrupt and tests its ins field, it can poll that interrupt instead of automatically servicing
it. This procedure, however, costs in the amount of code that must be written and executed to replace what the
DSP16000 core does by design.
The programmer can poll an interrupt source by checking its pending status in ins. The program can clear an
interrupt and change its status from pending to not pending by writing a 1 to its corresponding ins field. This clears
the field and leaves the remaining fields of ins unchanged. The example code segment below polls the MGU input
buffer full (MGIBF):
poll:
a0=ins
// Copy ins register contents to a0.
a0=a0&0x00000400
// Mask out all but bit 10.
if eq goto poll
// If bit 10 is zero, then MGIBF not pending.
...
// Interrupt is now pending -- service it.
ins=0x00400
// Clear MGIBF; don't change other interrupts.
Data Sheet
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May 2003
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4 Hardware Architecture
(continued)
4.5 Interprocessor Communication
Effective interprocessor (core-to-core) communication
requires synchronization and access to required data.
The following hardware mechanisms support access
synchronization:
!
The MGU provides core-to-core interrupts and traps.
!
The MGU provides message buffer interrupts and
flags.
!
DMAU interrupts.
The following mechanisms support data access:
!
The MGU can control the occurrence of a synchro-
nizing event (interrupt/trap) for information/status
transfer.
!
The MGU provides data transfer through its full-
duplex message buffers (mgi and mgo).
!
The DMAU can copy data from one core's TPRAM to
the other core's TPRAM.
!
Cores can directly share data in external memory
(ERAM, EROM, or EIO spaces).
!
Cores can directly share data in the SLM.
Figure 6 illustrates the interprocessor communication
logic provided by MGU0 and MGU1.
Inter-Processor Communication Logic in MGU0 and MGU1
Figure 6. Interprocessor Communication Logic in MGU0 and MGU1
CORE0
MGU0
mgi
mgo
signal
pid
PTRAP
MGOBF MGIBE MGIBF
FLAGS
DMINT[5:4]
(INTERRUPTS
FROM DMAU)
INTERRUPTS
SIGINT
XIO
MUX
BIT 1
BIT 0
TRAP
16
16
CORE1
MGU1
mgi
mgo
signal
pid
PTRAP
MGOBF
MGIBE
MGIBF
FLAGS
INTERRUPTS
SIGINT
XIO
BIT 1
BIT 0
2
imux
0
2
2
MUX
2
0
IMUX0
IMUX1
KEY:
PROGRAM-ACCESSIBLE REGISTERS
imux
Data Sheet
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Agere Systems--Proprietary
39
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.5 Interprocessor Communication
(continued)
Note: Sharing data directly through external memory
(ERAM, EROM, or EIO spaces) or the SLM is
the least efficient means of interprocessor com-
munication involving large blocks of data. It is
more efficient to perform block memory-to-mem-
ory moves using a DMAU MMT channel. See
Section 4.8 on page 49
for details on SLM and
Section 4.6.3 on page 43
for details on ERAM,
EROM, or EIO.
4.5.1 Core-to-Core Interrupts and Traps
Software executing on one core can interrupt the other
core by writing a 1 to its own MGU signal register bit 0
(
Table 11
). This causes the assertion of the other
core's SIGINT interrupt signal.
The code segment below illustrates the code running
on one core to assert the SIGINT interrupt of the other
core:
signal=1
// interrupt other core
Software executing on one core can trap the other core
by writing a 1 to its own signal register bit 1. This
causes the assertion of the other core's PTRAP. As
shown in
Figure 6 on page 38
, the signal register bit 1
is logically ORed with the TRAP pin and the result is
input to the other core's PTRAP signal. (See
Section 4.4.10 on page 34
for more information on
PTRAP.) See the code segment below:
signal=2
// trap other core
To ensure correct operation, the execution of the
signal register write instruction must be followed by the
execution of any instruction other than another signal
register write instruction.
Table 11. signal Register
4.5.2 Message Buffer Data Exchange
Each core can use its MGU message buffers to transmit and receive status information to and from the other core.
A core can send a message to another core by writing to its own 16-bit output message register mgo. A core can
receive a message from another core by reading its own 16-bit input message register mgi.
If the transmitting core writes mgo, the following steps occur:
1. After two instruction cycles of latency, the transmitting core's message output buffer full (MGOBF) condition flag
is set.
2. After an additional two instruction cycles of latency:
!
The DSP16411 copies the contents of the transmitting core's mgo to the receiving core's input message reg-
ister mgi.
!
The DSP16411 clears the receiving core's message input buffer empty (MGIBE) condition flag.
!
The DSP16411 asserts the receiving core's message input buffer full (MGIBF) interrupt.
15--11
1
0
Reserved
SIGTRAP
SIGINT
Bit
Field
Value
Description
R/W
Reset
Value
15--11
Reserved
0
Reserved--write with zero.
W
0
1
SIGTRAP
0
No effect.
W
0
1
Trap the other core by asserting its PTRAP signal.
0
SIGINT
0
No effect.
W
0
1
Interrupt the other core by asserting its SIGINT interrupt.
Note: If the program sets the SIGTRAP or SIGINT field, the MGU automatically clears the field after asserting the trap or interrupt. Therefore, the pro-
gram must not explicitly clear the field.
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4 Hardware Architecture
(continued)
4.5 Interprocessor Communication
(continued)
4.5.2 Message Buffer Data Exchange (continued)
The receiving core can use interrupts or polling to
detect the presence of an incoming message. When
the receiving core reads mgi, the following steps occur:
1. After one instruction cycle of latency, the DSP16411
sets the receiving core's MGIBE flag.
2. After an additional instruction cycle of latency, the
DSP16411 clears the transmitting core's MGOBF
flag.
4.5.2.1 Message Buffer Write Protocol
To ensure an older message has been processed by
the receiving core, the transmitting core must not write
a new message to mgo until its MGOBF flag is cleared.
The example code segment below is executed by the
transmitting core:
if mgobf goto .
// Wait for old message
// to be read.
mgo=*r0++
// Write new message.
4.5.2.2 Message Buffer Read Protocol
The receiving core can detect an incoming message by
enabling the MGIBF interrupt in the inc1 register
(
Table 153 on page 241
). The following is an example
of a simple interrupt service routine for the receiving
core:
ISR:
a0h=mgi
*r0++=a0h
// Read new message and
// clear MGIBF.
ireturn
As an alternative to the interrupt-directed message
buffer read protocol described above, the receiving
core can poll its MGIBE flag for the arrival of a new
message. The example code segment below is exe-
cuted by the receiving core:
if mgibe goto .
// Wait for new
// message.
a0h=mgi
*r0++=a0h
// Read new message.
The DSP16411 can operate a full-duplex communica-
tion channel between CORE0 and CORE1, with each
core using its own mgi and mgo registers and its own
MGOBF and MGIBE flags.
Table 12
illustrates two
code segments for a full-duplex data exchange of N
words between CORE0 and CORE1. This segment
exchanges two words (one input, one output) between
the two cores every 18 CLK cycles.
Table 12. Full-Duplex Data Transfer Code Through Core-to-Core Message Buffer
CORE0 Message Buffer Transfer Code
CORE1 Message Buffer Transfer Code
c0=1-N
xfer: if mgobf goto .
mgo=*r0++
//Write message to
//CORE1 and set MGOBF.
//4 cycles latency
//until CORE1's MGIBE
//is cleared.
if mgibe goto .
//Wait for CORE1
//message to arrive.
a0h=mgi
*r1++=a0h
//Read CORE1 message
//and clear CORE1's
//MGOBF.
if c0lt goto xfer
c0=1-N
xfer: if mgobf goto .
mgo=*r0++
//Write message to
//CORE0 and set MGOBF.
//4 cycles latency
//until CORE0's MGIBE
//is cleared.
if mgibe goto .
//Wait for CORE0
//message to arrive.
a0h=mgi
*r0++=a0h //Read
CORE0
message
//and clear CORE0's
//MGOBF.
if c0lt goto xfer
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
41
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.5 Interprocessor Communication
(continued)
4.5.3 DMAU Data Transfer
The most efficient mechanism for synchronously trans-
ferring large data blocks between the two cores is
through the two DMAU memory-to-memory (MMT)
channels, MMT4 and MMT5, described in detail in
Section 4.13.6, beginning on page 90
. For example,
one core uses one MMT channel to transfer data and
the other core uses the other channel. In this way, a
transmitting core writes a message block via its MMT
channel and an interrupt notifies the receiving core
after the DMA transfer is complete.
Table 13
summa-
rizes the MMT interrupts, DMINT4 and DMINT5, used
to synchronize DMAU transfers. Both cores can moni-
tor both DMINT4 and DMINT5.
Table 13. DMAU MMT Channel Interrupts
If an MMT channel is dedicated to intercore transfers
and not used for intracore transfers, the transmitting
and receiving cores can use the DMINT4 and DMINT5
interrupts directly to synchronize transfers. For exam-
ple, MMT4 can be dedicated to CORE0-to-CORE1
transfers and MMT5 can be dedicated to CORE1-to-
CORE0 transfers. In this case, DMINT4 interrupts
CORE1 if a message block from CORE0 is in memory,
and likewise, DMINT5 interrupts CORE0 if a message
block from CORE1 is in memory.
If an MMT channel is used for both intracore and inter-
core transfers, DMINT4 or DMINT5 is used for syn-
chronizing intracore transfers and the XIO interrupt is
used for synchronizing intercore transfers. Each core
programs the XIO interrupt for the other core via its
imux register (
Table 5 on page 28
). The XIOC[1:0]
field (imux[15:14]) selects XIO for the other core as
either zero (XIOC[1:0] = 0), DMINT4 (XIOC[1:0] = 1),
or DMINT5 (XIOC[1:0] = 2).
Table 14
illustrates an example configuration for intrac-
ore and intercore transfers via DMA. This example
assigns CORE0 to MMT4 and CORE1 to MMT5.
Table 14. DMA Intracore and Intercore Transfers Example
If a core uses an MMT channel for intracore transfers, i.e., not for transfers with the other core, it must first program
its XIOC[1:0] field (imux[15:14]) to zero. This prevents the MMT interrupt from disturbing the other core via its XIO
interrupt. The core must enable the corresponding MMT interrupt (DMINT4 or DMINT5) in its inc0 register
(
Table 153 on page 241
).
If a core uses its MMT channel for intercore transfers, i.e., for transmitting to the other core, it must first program its
XIOC[1:0] field (imux[15:14]) to either 1 or 2 (DMINT4 or DMINT5). The receiving core must enable its XIO inter-
rupt in its inc1 register (
Table 153 on page 241
). The transmitting core must disable the corresponding MMT inter-
rupt (DMINT4 or DMINT5) in its own inc0 register.
DMAU
Channel
Interrupt
Name
Description
MMT4
DMINT4
MMT4 transfer complete.
MMT5
DMINT5
MMT5 transfer complete.
DMAU
Channel
Intracore
Intercore (Core-to-Core)
Transmitting
Receiving
Core
Interrupt
imux[XIOC[1:0]]
Core
imux[XIOC[1:0]]
Core
Interrupt
MMT4
CORE0
DMINT4
0
(CORE1's XIO = 0)
CORE0
1
(CORE1's XIO = DMINT4)
CORE1
XIO (DMINT4)
MMT5
CORE1
DMINT5
0
(CORE0's XIO = 0)
CORE1
2
(CORE0's XIO = DMINT5)
CORE0
XIO (DMINT5)
Data Sheet
DSP16411 Digital Signal Processor
May 2003
42
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.6 Memory Maps
The DSP16000 core is a modified Harvard architecture with separate program and data memory spaces
(X-memory space and Y-memory space). The core differentiates between the X- and Y-memory spaces by the
addressing unit used for the access (XAAU vs. YAAU) and not by the physical memory accessed. The core
accesses its X-memory space via its 20-bit X address bus (XAB) and 32-bit X data bus (XDB). The core accesses
its Y-memory space via its 20-bit Y address bus (YAB) and 32-bit Y data bus (YDB).
The DMAU accesses private internal memory (TPRAM
0--1
) via its 20-bit internal Z address bus (ZIAB) and
32-bit internal Z data bus (ZIDB) and shared external memory
1
(EIO and ERAM) via its 20-bit external Z address
bus (ZEAB) and 32-bit external Z data bus (ZEDB).
Although DSP16411 memory is 16-bit word-addressable, data or instruction widths can be either 16 bits or 32 bits
and applications can access the memories 32 bits at a time.
Table 15
summarizes the components of the DSP16411 memory. The table specifies the name and size of each
component, whether it is internal or external, whether it is private to a core or shared by both cores, and in which
memory space(s) it resides. The five memory spaces are CORE0's X-memory space, CORE0's Y-memory space,
CORE1's X-memory space, CORE1's Y-memory space, and the DMAU's Z-memory space.
Table 15. DSP16411 Memory Components
The remainder of this section consists of the following:
!
Section 4.6.1, Private Internal Memory, on page 43
.
!
Section 4.6.2, Shared Internal I/O, on page 43
.
!
Section 4.6.3, Shared External I/O and Memory, on page 43
.
!
Section 4.6.4, X-Memory Map, on page 44
.
!
Section 4.6.5, Y-Memory Maps, on page 45
.
!
Section 4.6.6, Z-Memory Maps, on page 46
.
!
Section 4.6.7, Internal I/O Detailed Memory Map, on page 47
.
1. ZEAB and ZEDB connect to EIO and ERAM through the SEMI.
Type
Memory
Component
Size
CORE0
CORE1
DMAU
X-Memory
Space
Y-Memory
Space
X-Memory
Space
Y-Memory
Space
Z-Memory
Space
Private Internal
TPRAM0
160 Kwords
#
#
#
CACHE0
62 words
#
#
IROM0
4 Kwords
#
TPRAM1
160 Kwords
#
#
#
CACHE1
62 words
#
#
IROM1
4 Kwords
#
Shared Internal
Internal I/O
128 Kwords
#
#
#
Shared External
EIO
128 Kwords
#
#
#
ERAM
512 Kwords
#
#
#
EROM
512 Kwords
#
#
Assumes that WEROM is 0 for normal operation. If WEROM is 1, ERAM is replaced by EROM in the memory space, allowing the normally
read-only EROM section to be written. WEROM is discussed in detail in
Section 4.6.3 on page 43
.
The internal I/O section consists of 2 Kwords of SLM and memory-mapped registers in the SEMI, DMAU, PIU, SIU0, and SIU1 blocks. Only a
small portion of the 128 Kwords reserved for internal I/O is actually populated with memory or registers.
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
43
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.6 Memory Maps
(continued)
4.6.1 Private Internal Memory
Each core has its own private internal memories for
program and data storage. CORE0 has IROM0,
CACHE0, and TPRAM0. CORE1 has IROM1,
CACHE1, and TPRAM1. A core cannot directly access
the other core's private memory. However, the DMAU
can access both TPRAM0 and TPRAM1 and can move
data between these two memories to facilitate core-to-
core communication (see
Section 4.5 on page 38
).
TPRAM is described in more detail in
Section 4.7 on
page 48
. Cache memory is described in detail in the
DSP16000 Digital Signal Processor Core Information
Manual. IROM contains boot and HDS code and is
described in
Section 5 on page 208
.
4.6.2 Shared Internal I/O
The 128 Kword internal I/O memory component is
accessible by both cores in their Y-memory spaces and
by the DMAU in its Z-memory space. Any access to
this memory component is made over the system bus
and is arbitrated by the SEMI. The internal shared I/O
memory component consists of:
!
2 Kwords of shared local memory (SLM). SLM can
be used for core-to-core communication (see
Section 4.5 on page 38
). SLM is described in
Section 4.1.4 on page 17
.
!
Memory-mapped control and data registers within
the following peripherals:
-- DMAU
-- SEMI
-- PIU
-- SIU0
-- SIU1
Only a small portion of the 128 Kwords reserved for
internal I/O is actually populated with memory or regis-
ters. Any access to the internal I/O memory compo-
nent takes multiple cycles to complete. DSP core or
DMAU writes take a minimum of two CLK cycles to
complete. DSP core or DMAU reads take a minimum
of five CLK cycles to complete.
4.6.3 Shared External I/O and Memory
External I/O and memory consists of three shared com-
ponents: EIO, ERAM, and EROM. EIO and ERAM are
accessible in the Y-memory spaces of both cores and
also in the DMAU's Z-memory space. EROM is nor-
mally read-only and accessible only in the X-memory
spaces of both cores. If the programmer sets the
WEROM field in the memory-mapped ECON1 register
(see
Table 61 on page 112
), EROM takes the place of
ERAM in the Y-memory spaces of both cores and in
the DMAU's Z-memory space (see
Section 4.6.5 on
page 45
and
Section 4.6.6 on page 46
for details).
This allows the EROM component to be written for pro-
gram downloads to external X memory.
The physical size of the EIO, ERAM, and EROM com-
ponents can be expanded from the sizes defined in
Table 15 on page 42
by employing the ESEG[3:0]
pins. The external memory system can use ESEG[3:0]
in either of the following ways:
1. ESEG[3:0] can be interpreted by the external mem-
ory system as four separate decoded address
enable signals. Each ESEG[3:0] pin individually
selects one of four segments for each memory
component. This results in four glueless 512 Kword
(1 Mbyte) ERAM segments, four glueless 512 Kword
(1 Mbyte) EROM segments, and four glueless
128 Kword (256 KB) EIO segments.
2. ESEG[3:0] can be interpreted by the external mem-
ory system as an extension of the address bus, i.e.,
the ESEG[3:0] pins can be concatenated with the
EAB[18:0] pins to form a 23-bit address. This results
in one glueless 8 Mword (16 Mbytes) ERAM seg-
ment, one glueless 8 Mword (16 Mbytes) EROM
segment, and one glueless 2 Mword (4 Mbytes) EIO
segment.
See
Section 4.14.1.5 on page 106
for details on config-
uring the ESEG[3:0] pins.
Data Sheet
DSP16411 Digital Signal Processor
May 2003
44
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.6 Memory Maps
(continued)
4.6.4 X-Memory Map
Figure 7. X-Memory Map
INTERNAL
EXTERNAL
0x00000
0x30FFF
IROMn (PRIVATE
)
4 Kwords
...
.......
......
....
...
0x31000
0x80000
0x2FFFF
XMAP
.....
.......
......
.......
......
.......
.
0x7FFFF
16 bits
0xFFFFF
..
.....
......
.....
......
......
.....
......
......
...
EROM (SHARED)
0x3FFFE
CACHEn (PRIVATE
)
RESERVED
RESERVED
0x27FFF
0x28000
0x3FFBF
62 words
n is 0 for CORE0 or 1 for CORE1. Private memory can be accessed by the core with which it is associated. TPRAM0, CACHE0, and IROM0
cannot be accessed directly by CORE1. TPRAM1, CACHE1, and IROM1 cannot be accessed directly by CORE0. Both TPRAM0 and
TPRAM1 can be accessed by the DMAU and PIU.
EROM can be configured as four glueless 512 Kword (1 Mbyte) segments or one 8 Mword (16 Mbytes) segment. See
Section 4.14.4.3 begin-
ning on page 114
for details. EROM is shared, i.e., is accessible by both CORE0 and CORE1, and is also accessible by the DMAU and the
PIU.
RESERVED
TPRAMn (PRIVATE
)
160 Kwords
0x30000
0x3FFC0
0x3FFFD
...
....
0x3FFBF
0x28000
512 Kwords
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
45
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.6 Memory Maps
(continued)
4.6.5 Y-Memory Maps
Figure 8. Y-Memory Maps
n is 0 for CORE0 or 1 for CORE1. Private memory can be accessed by the core with which it is associated. TPRAM0, CACHE0, and IROM0
cannot be accessed directly by CORE1. TPRAM1, CACHE1, and IROM1 cannot be accessed directly by CORE0. Both TPRAM0 and
TPRAM1 can be accessed by the DMAU and PIU.
Internal I/O consists of shared local memory (SLM) and internal memory-mapped registers. See
Section 4.6.7 on page 47
for details.
A shared memory space is accessible by both CORE0 and CORE1, and is also accessible by the DMAU and the PIU.
EROM and ERAM can each be configured as four glueless 512 Kword (1 Mbyte) segments or one 8 Mword (16 Mbytes) segment. EIO can
be configured as four glueless 128 Kword (256 Mbytes) segments or one glueless 2 Mword (4 Mbytes) segment. (See
Section 4.14.4.3 on
page 114
.)
CACHEn (PRIVATE
)
62 words
..
....
....
....
....
.
0x3FFFE
0x3FFFF
RESERVED
0x3FFBF
YMAP
(WEROM = 0)
RESERVED
....
....
....
..
0x7FFFF
16 bits
EIO
(SHARED
)
0xFFFFF
....
....
....
....
....
....
....
....
....
....
...
0x60000
INTERNAL I/O
(SHARED
)
ERAM
(SHARED
)
128 Kwords
TPRAMn (PRIVATE
)
160 Kwords
.
....
...
....
..
0x40000
0x28000
128 Kwords
0x27FFF
0x80000
0x00000
...
....
....
...
....
.
0x3FFC0
0x3FFFD
0x5FFFF
INTERNAL
EXTERNAL
CACHEn (PRIVATE
)
62 words
..
....
....
....
....
.
0x3FFFE
0x3FFFF
RESERVED
0x3FFBF
YMAP
(WEROM = 1)
RESERVED
....
....
....
..
0x7FFFF
16 bits
EIO
(SHARED
)
0xFFFFF
....
....
....
....
....
....
....
....
....
....
...
0x60000
INTERNAL I/O
(SHARED
)
EROM
(SHARED
)
128 Kwords
TPRAMn (PRIVATE
)
160 Kwords
.
....
...
....
..
0x40000
0x28000
128 Kwords
0x27FFF
0x80000
0x00000
...
....
....
...
....
.
0x3FFC0
0x3FFFD
0x5FFFF
512 Kwords
512 Kwords
512 Kwords
Data Sheet
DSP16411 Digital Signal Processor
May 2003
46
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.6 Memory Maps
(continued)
4.6.6 Z-Memory Maps
Figure 9. Z-Memory Maps
INTERNAL
EXTERNAL
The CMP[2:0] field in the DMAU address register (SADD
0--5
or DADD
0--5
--
Table 37 on page 77
) or in the parallel address register
(PA--
Table 80 on page 138
) selects either TPRAM0 or TPRAM1.
Internal I/O consists of shared local memory (SLM) and internal memory-mapped registers. See
Section 4.6.7 on page 47
for details.
A shared memory space is accessible by both CORE0 and CORE1, and is also accessible by the DMAU and the PIU.
EROM and ERAM can each be configured as four glueless 512 Kword (1 Mbyte) segments or one 8 Mword (16 Mbytes) segment. EIO can
be configured as four glueless 128 Kword (256 Mbytes) segments or one glueless 2 Mword (4 Mbytes) segment. (See
Section 4.14.1.3 on
page 104
.)
...
....
....
....
....
0x3FFFF
RESERVED
ZMAP
(WEROM = 0)
.
....
....
....
.
0x7FFFF
16 bits
EIO
(SHARED
)
0xFFFFF
.
....
....
....
....
....
....
....
...
....
....
...
0x60000
INTERNAL I/O
(SHARED
)
ERAM
(SHARED
)
128 Kwords
..
...
....
...
..
0x40000
0x28000
128 Kwords
0x27FFF
0x80000
0x00000
...
....
....
....
....
....
....
..
0x5FFFF
TPRAM0
(160 Kwords)
TPRAM1
(160 Kwords)
or
0x28000
...
....
....
....
....
0x3FFFF
RESERVED
ZMAP
(WEROM = 1)
.
....
....
....
.
0x7FFFF
16 bits
EIO
(SHARED
)
0xFFFFF
.
....
....
....
....
....
....
....
...
....
....
...
0x60000
INTERNAL I/O
(SHARED
)
EROM
(SHARED
)
128 Kwords
..
...
....
...
..
0x40000
0x28000
128 Kwords
0x27FFF
0x80000
0x00000
...
....
....
....
....
....
....
..
0x5FFFF
TPRAM0
(160 Kwords)
TPRAM1
(160 Kwords)
or
0x28000
512 Kwords
512 Kwords
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
47
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.6 Memory Maps
(continued)
4.6.7 Internal I/O Detailed Memory Map
Figure 10
is a detailed view of the 128 Kword internal I/O memory component shown in Figures
8
and
9
. It consists
of a 4 Kword block for the memory-mapped registers of each peripheral and a 2 Kword block for the SLM. The
internal I/O memory component is directly accessible by both cores and by the DMAU and PIU. The SEMI controls
access to the internal I/O memory component, which is subject to wait-state and contention penalties. The SEMI
permits only 16-bit and aligned 32-bit accesses to the internal I/O memory component. The SEMI does not sup-
port misaligned 32-bit accesses (double-word accesses with an odd address) for the internal I/O memory compo-
nent because they produce undefined results. An access to the internal I/O memory component takes multiple
clock cycles to complete and a core access to the internal I/O memory component causes that core to incur wait-
states. See
Section 4.14.7.1 on page 128
for details on system bus performance.
Figure 10. Internal I/O Memory Map
The memory-mapped registers located in their associated peripherals are each mapped to an even address. The
sizes of these registers are 16 bits, 20 bits, or 32 bits. A register that is 20 bits or 32 bits must be accessed as an
aligned double word. A register that is 16 bits can be accessed as a single word with an even address or as an
aligned double word. If a register that is 16 bits or 20 bits is accessed as a double word, the contents of the register
are right-justified.
Section 6.2.2 on page 231
details the memory-mapped registers.
0x40000
0x40FFF
...
...
16 bits
SEMI REGISTERS
Although 4 Kwords are reserved for the memory-mapped registers of each peripheral, not all of the 4 Kwords are actually used.
PIU REGISTERS
DMAU REGISTERS
SIU0 REGISTERS
SIU1 REGISTERS
SLM (2 Kwords)
0x42000
0x42FFF
......
0x44000
0x44FFF
..
....
0x45800
0x5FFFF
......
......
.......
......
..
0x41000
0x41FFF
.....
.
0x43000
0x43FFF
...
...
0x45000
0x457FF
(4 Kwords
)
(4 Kwords
)
(4 Kwords
)
(4 Kwords
)
(4 Kwords
)
RESERVED
(106 Kwords)
Data Sheet
DSP16411 Digital Signal Processor
May 2003
48
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.7 Triport Random-Access Memory (TPRAM)
Each core has a private block TPRAM (TPRAM0 and TPRAM1) consisting of 160 banks (banks 0--159) of zero
wait-state memory. Each bank consists of 1K 16-bit words and has three separate address and data ports: one
port to the core's instruction/coefficient (X-memory) space, a second port to the core's data (Y-memory) space, and
a third port to the DMAU's (Z-memory) space. TPRAM is organized into even and odd interleaved banks for which
each even/odd address pair is a 32-bit wide module as illustrated in
Figure 11
. The core's data buses (XDB and
YDB) and the DMAU's data bus (ZIDB) are each 32 bits wide, and therefore 32-bit data in the TPRAM with an
aligned (even) address can be accessed in a single cycle. Typically, a misaligned double word is accessed in two
cycles.
Figure 11. Interleaved Internal TPRAM
Figure 12
illustrates an example arrangement of single words (16 bits) and double words (32 bits) in memory. It
also illustrates an aligned double word and a misaligned double word. See the DSP16000 Digital Signal Processor
Core
Information Manual for details on word alignment and misalignment wait-states.
Example Memory Arrangement
Figure 12. Example Memory Arrangement
0x000
0x003
0x001
0x002
0x7FF
0x7FE
11 LSBs
16 bits
16 bits
32 bits
EVEN BANK
ODD BANK
OF
ADDRESS
11 LSBs
OF
ADDRESS
TPRAM MODULE
1K x 32 bits
(2 Kwords)
LESS SIGNIFICANT WORD
MORE SIGNIFICANT WORD
SINGLE WORD
SINGLE WORD
0
3
1
5
2
SINGLE WORD
7
4
6
LESS SIGNIFICANT WORD
SINGLE WORD
ADDRESS
ADDRESS
ALIGNED DOUBLE WORD AND DOUBLE-WORD ADDRESS
MISALIGNED DOUBLE WORD AND DOUBLE-WORD ADDRESS
KEY:
16 bits
32 bits
EVEN BANK
ODD BANK
LEAST SIGNIFICANT WORD
MOST SIGNIFICANT WORD
2
5
MOST SIGNIFICANT WORD
LEAST SIGNIFICANT WORD
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
49
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.7 Triport Random-Access Memory
(TPRAM)
(continued)
The core's X and Y ports and the DMAU's Z port can
access separate modules within a TPRAM simulta-
neously with no wait-states incurred by the core. If the
same module of TPRAM is accessed from multiple
ports simultaneously, the TPRAM automatically
sequences the accesses in the following priority order:
X port (instruction/coefficient), Y port (data), then Z port
(DMAU). This sequencing can cause the core to incur
a conflict wait-state. Because the core must complete
any consecutive accesses to a module of TPRAM
before the DMAU can access that module, the DMAU
can be blocked from accessing that module for a signif-
icant number of cycles.
4.8 Shared Local Memory (SLM)
Each core, the DMAU, and the PIU can access SLM
(shared local memory) through the SEMI and the sys-
tem buses (SAB and SDB). SLM is a 2 Kword block
located in the internal I/O memory component. SLM
supports both 16-bit and aligned 32-bit accesses, but
not 32-bit misaligned accesses.
The SEMI controls access to the SLM, which is subject
to wait-state and contention penalties; see
Section 4.14.7.1 on page 128
for details. Because
access to the SLM is subject to wait-state and conten-
tion penalties, it is not an efficient method for transfer-
ring large blocks of data between the cores. (An
efficient method is to use the DMAU memory-to-mem-
ory (MMT) channel.)
Data Sheet
DSP16411 Digital Signal Processor
May 2003
50
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.9 Bit Input/Output Units (BIO
0--1
)
The DSP16411 has two bit I/O units, BIO0 for CORE0
and BIO1 for CORE1. Each BIO unit connects to
seven bidirectional pins, IO0BIT[6:0] for BIO0 and
IO1BIT[6:0] for BIO1. User software running in CORE0
controls and monitors BIO0 via its sbit and cbit regis-
ters. User software running in CORE1 controls and
monitors BIO1 via its sbit and cbit registers. The soft-
ware can:
s
Individually configure each pin as an input or output.
s
Read the current state of the pins.
s
Test the combined state of input pins.
s
Individually set, clear, or toggle output pins.
The DIREC[6:0] field (sbit[14:8]--see
Table 16
) con-
trols the direction of the corresponding IO
0,1
BIT[6:0]
pin; a logic 0 configures the pin as an input or a logic 1
configures it as an output. Reset clears the
DIREC[6:0] field, configuring all BIO pins as inputs by
default. The read-only VALUE[6:0] field (sbit[6:0])
contains the current state of the corresponding pin,
regardless of whether the pin is configured as an input
or output.
The cbit register (
Table 17 on page 51
) contains two
7-bit fields, MODE[6:0]/MASK[6:0] and
DATA[6:0]/PAT[6:0]. The meaning of the individual
bits in these fields, MODE[n]/MASK[n] and
DATA[n]/PAT[n], is based on whether the correspond-
ing IO
0,1
BIT[n ] pin is configured as an input or an
output. If IO
0,1
BIT[n] is configured as an input, the
fields are MASK[n] and PAT[n]. If IO
0,1
BIT[n] is
configured as an output, the fields are MODE[n] and
DATA[n ].
Table 18 on page 52
summarizes the func-
tion of the MODE[6:0]/MASK[6:0] and
DATA[6:0]/PAT[6:0] fields.
If the software configures an IO
0,1
BIT[n ] pin as an
output and:
s
If the software clears MODE[n ] and clears DATA[n ],
the BIO
0, 1
drives the pin low.
s
If the software clears MODE[n ] and sets DATA[n],
the BIO
0, 1
drives the pin high.
s
If the software sets MODE[n] and clears DATA[n],
the BIO does not change the state of the pin.
s
If the software sets MODE[n] and sets DATA[n], the
BIO
0,1
toggles (inverts) the state of the pin.
If an IO
0,1
BIT[n ] pin is configured as an input and
the software sets MASK[n], the BIO
0,1
tests the state
of the pin by comparing it to the PAT[n] (pattern) field.
BIO
0,1
sets or clears its flags based on the result of
the comparison of all its tested inputs:
s
ALLT (all true) is set if all of the tested inputs match
the test pattern.
s
ALLF (all false) is set if all of the tested inputs do not
match the test pattern.
s
SOMET (some true) is set if some or all of the tested
inputs match the test pattern.
s
SOMEF (some false) is set if some or all of the
tested inputs do not match the test pattern.
Table 16. sbit (BIO Status/Control) Register
15
14--8
7
6--0
Reserved
DIREC[6:0]
Reserved
VALUE[6:0]
Bit
Field
Value
Description
R/W
Reset
Value
15
Reserved
X
Reserved--writing to this field has no functional effect.
R/W
0
14--8
DIREC[6:0]
(Controls direc-
tion of pins)
0
Configure the corresponding IO
0,1
BIT[6:0] pin as an input.
R/W
0
1
Configure the corresponding IO
0,1
BIT[6:0] pin as an output.
7
Reserved
X
Reserved--value is read-only and is undefined.
R
0
6--0
VALUE[6:0]
(Current value of
pins)
0
The current state of the corresponding IO
0,1
BIT[6:0] pin is logic 0.
R
P
1
The current state of the corresponding IO
0,1
BIT[6:0] pin is logic 1.
For this column, X indicates unknown on powerup reset and unaffected on subsequent reset.
This field is read-only; writing the VALUE[6:0] field of sbit has no effect. If the user software toggles a bit in the DIREC[6:0] field, there is a
latency of one cycle until the VALUE[6:0] field reflects the current state of the corresponding IO
0,1
BIT[6:0] pin. If an IO
0,1
BIT[6:0] pin is
configured as an output (DIREC[6:0] = 1) and the user software writes cbit to change the state of the pin, there is a latency of two cycles until
the VALUE[6:0] field reflects the current state of the corresponding IO
0,1
BIT[6:0] output pin.
The IO
0,1
BIT[6:0] pins are configured as inputs after reset. If external circuitry does not drive an IO
0,1
BIT[n ] pin, the VALUE[n] field is
undefined after reset.
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
51
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.9 Bit Input/Output Units (BIO
0--1
)
(continued)
Table 17. cbit (BIO Control) Register
If all the IO
0,1
BIT[6:0] pins are configured as outputs
or if the MASK[n] field is cleared for all pins that are
configured as inputs, the BIO
0,1
sets the ALLT and
ALLF flags and clears the SOMET and SOMEF flags.
Table 19 on page 52
summarizes the BIO flags, which
software can test with conditional instructions (see
Table 138 on page 226
). Software can test, save, or
restore the state of the flags by reading or writing the
alf register (see
Table 144 on page 235
). As illustrated
in
Table 19 on page 52
, ALLT is the logical inverse of
SOMEF and ALLF is the logical inverse of SOMET.
If an IO
0,1
BIT[n ] pin is configured as an input and
the software writes cbit to change the MASK[n] or
PAT[n] field, there is a latency of two cycles until the
DSP16411 updates the BIO flags to reflect the change.
The following code segment illustrates this latency by
the use of the two nop instructions:
sbit=0
// All pins are inputs.
cbit=0
// Test no inputs.
...
cbit=0x0302
// Test IOBIT[1:0].
2*nop
// Any 2 instructions.
if allt goto OK
// Branch if IOBIT1...
// is 1 and IOBIT0 is 0.
15
14--8
7
6--0
Reserved
MODE[6:0]/MASK[6:0]
Reserved
DATA[6:0]/PAT[6:0]
Bit
Field
Value
Description
R/W
Reset
Value
15
Reserved
0
Reserved--write with zero.
R/W
0
14--8
MODE[6:0]
(outputs
)
An IO
0,1
BIT[6:0] pin is configured as an output if the corresponding DIREC[6:0] field (sbit[14:8]) has been set by the user software. An
IO
0, 1
BIT[6:0] pin is configured as an input if the corresponding DIREC[6:0] field has been cleared by the user software or by device reset.
0
The BIO drives the corresponding IO
0,1
BIT[6:0] output pin to the corre-
sponding value in DATA[6:0].
R/W
0
1
s
If the corresponding DATA[6:0] field is 0, the BIO does not change the state
of the corresponding IO
0,1
BIT[6:0] output pin.
s
If the corresponding DATA[6:0] field is 1, the BIO toggles (inverts) the state
of the corresponding IO
0,1
BIT[6:0] output pin.
MASK[6:0]
(inputs
)
0
The BIO does not test the state of the corresponding IO
0,1
BIT[6:0] input pin
to determine the state of the BIO flags
.
The BIO flags are ALLT, ALLF, SOMET, and SOMEF. See
Table 19 on page 52
for details on BIO flags.
1
The BIO compares the state of the corresponding IO
0,1
BIT[6:0] input pin to
the corresponding value in the PAT[6:0] field to determine the state of the BIO
flags
; true if pin matches or false if pin doesn't match.
7
Reserved
0
Reserved--write with zero.
R/W
0
6--0
DATA[6:0]
(outputs
)
0
s
If the corresponding MODE[6:0] field is 0, the BIO drives the corresponding
IO
0,1
BIT[6:0] output pin to logic 0.
s
If the corresponding MODE[6:0] field is 1, the BIO does not change the
state of the corresponding IO
0,1
BIT[6:0] output pin.
R/W
0
1
s
If the corresponding MODE[6:0] field is 0, the BIO drives the corresponding
IO
0,1
BIT[6:0] output pin to logic 1.
s
If the corresponding MODE[6:0] field is 1, the BIO toggles (inverts) the
state of the corresponding IO
0,1
BIT[6:0] output pin.
PAT[6:0]
(inputs
)
0
If the corresponding MASK[6:0] field is 1, the BIO tests the state of the corre-
sponding IO
0,1
BIT[6:0] input pin to determine the state of the BIO flags
;
true if pin is logic 0 or false if pin is logic 1.
1
If the corresponding MASK[6:0] field is 1, the BIO tests the state of the corre-
sponding IO
0,1
BIT[6:0] input pin to determine the state of the BIO flags
;
true if pin is logic 1 or false if pin is logic 0.
Data Sheet
DSP16411 Digital Signal Processor
May 2003
52
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.9 Bit Input/Output Units
(BIO
0--1
)
(continued)
If an IO
0,1
BIT[n ] pin is configured as an output and
the software writes cbit to change the state of the pin,
there is a latency of one cycle until the DSP16411
changes the state of the pin and a latency of an addi-
tional cycle until the VALUE[n] field (sbit[6:0]) reflects
the change. The use of two nop instructions in the fol-
lowing code segment illustrates this latency:
sbit=0x1000
// IOBIT4 is an output.
cbit=0x0010
// Drive IOBIT4 high.
nop
// IOBIT4 goes high.
nop
// VALUE4 is updated.
a0h=sbit
// Bit 4 of a0h is 1.
If the software writes sbit to change an IO
0,1
BIT[n]
pin from an input to an output or from an output to an
input, there is a latency of one cycle before the
VALUE[n] field of sbit is updated to reflect the state of
the pin. If the software writes sbit to change an
IO
0,1
BIT[n] pin from an output to an input and back
to an output, the BIO drives the pin with its original out-
put value.
The following code segment illustrates the latency
described in the previous paragraph:
sbit=0x0F00
// IOBIT[3:0] - output.
cbit=0x000A
// IOBIT[3:0] = 1010
// ...after 1 cycle.
cbit=0x0101
// Toggle IOBIT0...
// IOBIT[3:0] = 1011
// ...after 1 cycle.
sbit=0
// IOBIT[3:0] - input.
sbit=0x0F00
// IOBIT[3:0] - output.
// IOBIT[3:0] = 1011
// ...after 0 cycles.
nop
// Any instruction.
a0h=sbit
// a0h[3:0] = 1011.
Table 18. BIO Operations
..
Table 19. BIO Flags
DIREC[n]
0
n
6.
MODE[n]/
MASK[n]
DATA[n]/
PAT[n]
BIO Action
1
(Output)
0
0
Clear IO
0,1
BIT[n].
1
Set IO
0,1
BIT[n].
1
0
Do not change
IO
0,1
BIT[n].
1
Toggle IO
0,1
BIT[n].
0
(Input)
0
X
Do not test
IO
0,1
BIT[n].
The BIO tests the state of input pins to determine the states of the
BIO flags. See Table 19 for details on the BIO flags.
1
0
Test
IO
0,1
BIT[n]
for logic zero.
1
Test
IO
0,1
BIT[n]
for logic one.
Condition
ALLT
(alf[0])
ALLF
(alf[1])
SOMET
(alf[2])
SOMEF
(alf[3])
All or some of the
IO
0,1
BIT[6:0] pins are
configured as inputs.
For at least one pin IO
0,1
BIT[n ], DIREC[n ] = 0.
All tested inputs match the pattern.
For every pin IO
0,1
BIT[n ] with DIREC[n] = 0 and MASK[n] = 1, IO
0,1
BIT[n ] = PAT[n ].
1
0
1
0
All tested inputs do not match the pattern.
For every pin IO
0,1
BIT[n ] with DIREC[n] = 0 and MASK[n] = 1, IO
0,1
BIT[n ]
PAT[n ].
0
1
0
1
Some (but not all) of the tested inputs match the pattern.
For at least one pin IO
0,1
BIT[n ] with DIREC[n ] = 0 and MASK[n ] = 1, IO
0,1
BIT[n] = PAT[n], and for at least one pin IO
0,1
BIT[n] with
DIREC[n] = 0 and MASK[n ] = 1, IO
0,1
BIT[n]
PAT[n].
0
0
1
1
All of the inputs are not tested.
For all pins IO
0,1
BIT[n] with DIREC[n ] = 0, MASK[n ] = 0.
1
1
0
0
All IO
0,1
BIT[6:0] pins are configured as outputs.
DIREC[6:0] are all ones.
1
1
0
0
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
53
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.10 Timer Units (TIMER0_
0--1
and
TIMER1_
0--1
)
The DSP16411 provides two timer units for each core:
TIMER0_0 and TIMER1_0 for CORE0 and TIMER0_1
and TIMER1_1 for CORE1. Each TIMER provides a
programmable single interval interrupt or a program-
mable periodic interrupt.
Figure 13 on page 54
is a
block diagram of a TIMER that contains:
s
A 16-bit control register timer
0,1
c (see
Table 20
on page 55
).
s
A running count register timer
0,1
(see
Table 21 on
page 56
) consisting of a 16-bit down counter and a
16-bit period register.
s
A prescaler that divides the internal clock (CLK) by
one of 16 programmed values in the range 2 to
65536. The prescaler output clock decrements the
timer
0,1
down counter. The programmed pres-
cale value and the value written to timer
0,1
deter-
mine the interrupt interval or period.
By default after device reset
1
, the DSP16411 clears
timer
0,1
c and powers up the TIMER. To save power
if the TIMER is not in use, the software can set the
PWR_DWN field (timer
0,1
c[6]). Until the user soft-
ware writes to timer
0,1
c and timer
0,1
, the TIMER
does not operate or generate interrupts.
Note: The software can read or write timer
0,1
only if
the TIMER is powered up (PWR_DWN = 0).
If the software reads timer
0,1
, the value read is the
output of the down counter. If the software writes
timer
0,1
, the TIMER loads the write value into the
down counter and into the period register simulta-
neously.
The prescaler consists of a 16-bit up counter and a
multiplexer controlled by the PRESCALE[3:0] field
(timer
0,1
c[3:0]). PRESCALE[3:0] contains a
value N that selects the period of the prescaler output
clock as:
where f
CLK
is the frequency of the internal clock (see
Section 4.17 on page 200
).
To operate the TIMER (i.e., for the prescaler to decre-
ment the timer
0,1
down counter), the user software
must perform the following steps.
s
Write timer
0,1
c to program its fields as follows:
-- Write 0 to the PWR_DWN field.
-- Write 0 to the RELOAD field (timer
0,1
c[5]) for a
single interval interrupt or write 1 to the RELOAD
field for periodic interrupts.
-- Write 1 to the COUNT field (timer
0,1
c[4]) to
enable the prescaler output clock.
-- Program the PRESCALE[3:0] field to configure
the frequency of the prescaler output clock.
s
Write a nonzero value to timer
0,1
to enable the
down counter input clock.
The software can perform the above steps in either
order, and the TIMER starts after the second step.
If the TIMER is operating and the timer
0,1
down
counter reaches zero, the TIMER asserts its interrupt
request pulse TIME
0,1
(see
Section 4.4, beginning
on page 25,
for details on interrupts). The interval from
starting the TIMER to the occurrence of the first inter-
rupt is the following:
If the down counter reaches zero and RELOAD is 0,
the TIMER disables the input clock to the down
counter, causing the down counter to hold its current
value of zero. The user software can restart the
TIMER by writing a nonzero value to timer
0,1
.
If the down counter reaches zero and RELOAD is 1, a
prescale period elapses and the TIMER reloads the
down counter from the timer
0,1
period register.
Another prescale period elapses and the prescaler
decrements the down counter. Therefore, the subse-
quent interval between periodic interrupts is the follow-
ing:
Software can read or write timer
0,1
while the timer is
running. If the software writes timer
0,1
, the TIMER
loads the write value into the down counter and period
register and initializes the prescaler by clearing the
16-bit up counter. Because the TIMER initializes the
prescaler if the software writes timer
0,1
, the interval
from writing timer
0,1
to decrementing the down
counter is one complete prescale period.
Clearing COUNT disables the clock to the prescaler,
causing the down counter to hold its current value and
the prescaler to retain its current state. If the TIMER
remains powered up (PWR_DWN = 0), software can
stop and restart the TIMER at any time by clearing and
setting COUNT.
1. After device reset, the DSP16411 clears the down counter of timer
0,1
and leaves the period register of timer
0, 1
unchanged.
2
N
1
+
f
CLK
-------------
timer
0,1
2
N
1
+
f
CLK
-------------------------------------------------
timer
0,1
1
+
(
)
2
N
1
+
f
CLK
---------------------------------------------------------------
Data Sheet
DSP16411 Digital Signal Processor
May 2003
54
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.10 Timer Units (TIMER0_
0--1
and TIMER1_
0--1
)
(continued)
Figure 13. Timer Block Diagram
15--7
6
5
4
3--0
RESERVED
PWR_DWN
RELOAD
COUNT
PRESCALE[3:0]
4
16-bit RELOAD VALUE
16-bit DOWN COUNTER
16
16
16
16
timer
0,1
c
timer
0,1
1
0
LD
LD
(PERIOD) REGISTER
LD
15
14
0
16-bit
UP
COUNTER
15
14
0
MU
X
CLR
MUX
16
CLK
PRESCALER
COUNTER = 0 (LEVEL)
16
N
CLK
N
1
+
2
-------------
LOAD
timer
0,1
REGISTER
TIME
0,1
INTERRUPT
PULSE
IDB[15:0]
TO CORE
KEY:
PROGRAM-ACCESSIBLE
REGISTER
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
55
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.10 Timer Units (TIMER0_
0--1
and TIMER1_
0--1
)
(continued)
Table 20. timer
0,1
c (TIMER
0,1
Control) Register
15--7
6
5
4
3--0
Reserved
PWR_DWN
RELOAD
COUNT
PRESCALE[3:0]
Bit
Field
Value
Description
R/W
Reset
Value
15--7
Reserved
0
Reserved--write with zero.
R/W
0
6
PWR_DWN
0
Power up the timer.
R/W
0
1
Power down the timer
.
5
RELOAD
0
Stop decrementing the down counter after it reaches zero.
R/W
0
1
Automatically reload the down counter from the period register after
the counter reaches zero and continue decrementing the counter
indefinitely.
4
COUNT
0
Hold the down counter at its current value, i.e., stop the timer.
R/W
0
1
Decrement the down counter, i.e., run the timer.
3--0
PRESCALE[3:0]
0000
Controls the counter prescaler to determine the fre-
quency of the timer, i.e., the frequency of the clock
applied to the timer down counter. This frequency is a
ratio of the internal clock frequency f
CLK
.
f
CLK
/2
R/W
0000
0001
f
CLK
/4
0010
f
CLK
/8
0011
f
CLK
/16
0100
f
CLK
/32
0101
f
CLK
/64
0110
f
CLK
/128
0111
f
CLK
/256
1000
f
CLK
/512
1001
f
CLK
/1024
1010
f
CLK
/2048
1011
f
CLK
/4096
1100
f
CLK
/8192
1101
f
CLK
/16384
1110
f
CLK
/32768
1111
f
CLK
/65536
If TIMER
0,1
is powered down, timer
0,1
cannot be read or written. While the timer is powered down, the state of the down counter and
period register remain unchanged.
Data Sheet
DSP16411 Digital Signal Processor
May 2003
56
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.10 Timer Units (TIMER0_
0--1
and TIMER1_
0--1
)
(continued)
Table 21. timer
0,1
(TIMER
0,1
Running Count) Register
4.11 Hardware Development System
(HDS
0--1
)
The DSP16411 provides an on-chip hardware develop-
ment module for each of the two cores (HDS
0--1
).
Each HDS is available for debugging assembly-
language programs that execute on the DSP16000
core at the core's rated speed. The main capability of
the HDS is allowing controlled visibility into the core's
state during program execution.
The fundamental steps in debugging an application
using the HDS include the following:
1. Setup: Download program code and data into the
correct memory regions and set breakpointing con-
ditions.
2. Run: Start execution or single step from a desired
starting point (i.e., allow device to run under simu-
lated or real-time conditions).
3. Break: Break program execution on satisfying break-
pointing conditions; upload and allow user accessi-
bility to internal state of the device and its pins.
4. Resume: Resume execution (normally or single
step) after hitting a breakpoint and finally upload
internal state at the end of execution.
A powerful debugging capability of the HDS is the abil-
ity to break program execution on complex breakpoint-
ing conditions. A complex breakpoint condition, for
example, can be an instruction that executes from a
particular instruction-address location (or from a partic-
ular instruction-address range such as a subroutine)
and accesses a coefficient/data element from a specific
memory location (or from a memory region such as
inside an array or outside an array). Complex condi-
tions can also be chained to form more complex break-
point conditions. For example, a complex breakpoint
condition can be defined as the back-to-back execution
of two different subroutines.
The HDS also provides a debugging feature that allows
a number of complex breakpoints to be ignored. The
number of breakpoints ignored is programmable by the
user.
An intelligent trace mechanism for recording disconti-
nuity points during program execution is also available
in the HDS. This mechanism allows unambiguous
reconstruction of program flow involving discontinuity
points such as gotos, calls, returns, and interrupts. The
trace mechanism compresses single-level (non-
nested) loops and records them as a single discontinu-
ity. This feature prevents single-level loops from filling
up the trace buffers. Also, cache loops do not get reg-
istered as discontinuities in the trace buffers. There-
fore, two-level loops with inner cache loops are
registered as a single discontinuity.
The HDS provides a 32-bit cycle counter for accurate
code profiling during program development. The cycle
counter records processor CLK cycles between a user-
defined start point and end point. The cycle counter
can optionally be used to break program execution
after a user-specified number of clock cycles.
15--0
TIMER
0,1
Down Counter
TIMER
0,1
Period Register
Bit
Field
Description
R/W
Reset
Value
15--0
Down Counter
If the COUNT field (timer
0,1
c[4]) is set, TIMER
0,1
decrements this portion
of the timer
0,1
register every prescale period. When the down counter
reaches zero, TIMER
0,1
generates an interrupt.
R/W
0
15--0
Period Register
If the COUNT field (timer
0,1
c[4]) and the RELOAD field (timer
0,1
c[5]) are
both set and the down counter contains zero, TIMER
0,1
reloads the down
counter with the contents of this portion of the timer
0,1
register.
W
X
If the user program writes to the timer
0,1
register, TIMER
0,1
loads the 16-bit write value into the down counter and into the period register
simultaneously. If the user program reads the timer
0,1
register, TIMER
0,1
returns the current 16-bit value from the down counter.
To read or write the timer
0,1
register, TIMER
0,1
must be powered up, i.e., the PWR_DWN field (timer
0,1
c[6]) must be cleared.
For this column, X indicates unknown on powerup reset and unaffected on subsequent reset.
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
57
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.12 JTAG Test Port (JTAG
0--1
)
The DSP16411 provides an on-chip IEEE 1149.1 com-
pliant JTAG port for each of the two cores
(JTAG
0--1
). JTAG is an on-chip hardware module
that controls the HDS. All communication between the
HDS software, running on the host computer, and the
on-chip HDS is in a bit-serial manner through the JTAG
port. The JTAG port pins consist of test data input,
TDI
0--1
, test data output, TDO
0--1
, test mode
select, TMS
0--1
, test clock, TCK
0--1
, and test
reset, TRST
0--1
N.
The set of test registers includes the JTAG identifica-
tion register (ID), the boundary-scan register, and the
scannable peripheral registers.
4.12.1 Port Identification
Each JTAG port has a read-only identification register,
ID, as defined in
Table 22
. As specified in the table, the
contents of the ID register for JTAG0 is 0x1C815321
and the contents of the ID register for JTAG1 is
0x0C815321.
Table 22. ID (JTAG Identification) Register
31--28
27--19
18--12
11--1
0
DEVICE OPTIONS
ROMCODE
PART ID
AGERE ID
One
Bit
Field
Value
Description
R/W
Reset Value
31--28
DEVICE OPTIONS
0x1
JTAG0--device options.
R
0x1
0x0
JTAG1--device options.
0x0
27--19
ROMCODE
0x190
ROMCODE of device.
0x190
18--12
PART ID
0x15
Part ID--DSP16411.
0x15
11--1
AGERE ID
0x190
Agere identification.
0x190
0
One
1
Logic one.
1
Data Sheet
DSP16411 Digital Signal Processor
May 2003
58
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.12 JTAG Test Port (JTAG
0--1
)
(continued)
4.12.2 Emulation Interface Signals to the DSP16411
For in-circuit emulation and application software
debugging, the Agere TargetViewTM Communication
System (TCS) provides communication between a host
PC and one or more DSP16411 devices. Users of the
TCS hardware have the option of using one of three
connectors to interface this tool with DSP16411
devices on the target application. The pinouts for these
connectors are described in the following three sec-
tions.
4.12.2.1 TCS 14-Pin Header
The TCS interface pod provides a 14-pin, dual-row
(0.10 in. x 0.10 in.) socket (female) for connection to
the user's target hardware.
Figure 14
illustrates the
pinout of this connector.
Table 23
describes the signal
names and their relationship to the DSP16411 signals.
Figure 14. TCS 14-Pin Connector
5-7333 (F)
PIN 1
PIN 13
PIN 2
PIN 14
Table 23. TCS 14-Pin Socket Pinout
TCS Pin
Number
TCS Signal
Name
Description
TCS
I/O
DSP16411
Pin Number
DSP16411
Signal Name
DSP16411
I/O
1
TCK
Test clock
O
F4 and L13
TCK0 and TCK1
I
2
NC
No connect
NA
NA
NA
NA
3
Ground
System ground
G
See
Section 7 on page 253
V
SS
G
4
Ground
System ground
G
See
Section 7 on page 253
V
SS
G
5
TMS
Test mode select
O
G2 and K15
TMS0 and TMS1
I
6
V
TARG
Target I/O voltage
I
See
Section 7 on page 253
V
DD
2
P
7
NC
No connect
NA
NA
NA
NA
8
NC
No connect
NA
NA
NA
NA
9
TDO
Test data output
I
F1 or L16 (not both)
TDO0 or TDO1 (not both)
O
10
TDI
Test data input
O
G1 or K16 (not both)
TDI0 or TDI1 (not both)
I
11
Ground
System ground
G
See
Section 7 on page 253
V
SS
G
12
Ground
System ground
G
See
Section 7 on page 253
V
SS
G
13
NC
No connect
NA
NA
NA
NA
14
NC
No connect
NA
NA
NA
NA
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
59
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.12 JTAG Test Port (JTAG
0--1
)
(continued)
4.12.2 Emulation Interface Signals to the
DSP16411 (continued)
4.12.2.2 JCS 20-Pin Header
The TCS tools provide an interface adapter to convert
the 14-pin interface pod to a 20-pin dual-row
(0.05 in. x 0.10 in.) socket (female, 3M
part number
82020-6006) for connection to the user's target hard-
ware.
Figure 15
illustrates the pinout of this
connector.
Table 24
describes the signal names and
their relationship to the DSP16411 signals. This con-
nector is also compatible with the Agere JTAG commu-
nications system (JCS) tools.
Figure 15. JCS 20-Pin Connector
5-7334 (F)
PIN 19
PIN 20
PIN 1
PIN 2
Table 24. JCS 20-Pin Socket Pinout
JCS Pin
Number
JCS Signal
Name
Description
JCS I/O
DSP16411
Pin Number
DSP16411
Signal Name
DSP16411 I/O
1
NC
No connect
NA
NA
NA
NA
2
Ground
System ground
G
See
Section 7 on page 253
V
SS
G
3
NC
No connect
NA
NA
NA
NA
4
NC
No connect
NA
NA
NA
NA
5
NC
No connect
NA
NA
NA
NA
6
TMS
Test mode select
O
G2 and K15
TMS0 and TMS1
I
7
Ground
System ground
G
See
Section 7 on page 253
V
SS
G
8
V
TARG
Target I/O voltage
I
See
Section 7 on page 253
V
DD
2
P
9
NC
No connect
NA
NA
NA
NA
10
Ground
System ground
G
See
Section 7 on page 253
V
SS
G
11
NC
No connect
NA
NA
NA
NA
12
TDI
Test data input
O
G1 or K16 (not both)
TDI0 or TDI1 (not both)
I
13
Ground
System ground
G
See
Section 7 on page 253
V
SS
G
14
TCK
Test clock
O
F4 and L13
TCK0 and TCK1
I
15
Ground
System ground
G
See
Section 7 on page 253
V
SS
G
16
TDO
Test data output
I
F1 or L16 (not both)
TDO0 or TDO1 (not both)
O
17
NC
No connect
NA
NA
NA
NA
18
Ground
System ground
G
See
Section 7 on page 253
V
SS
G
19
NC
No connect
NA
NA
NA
NA
20
NC
No connect
NA
NA
NA
NA
Data Sheet
DSP16411 Digital Signal Processor
May 2003
60
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.12 JTAG Test Port (JTAG
0--1
)
(continued)
4.12.2 Emulation Interface Signals to the
DSP16411 (continued)
4.12.2.3 HDS 9-Pin, D-Type Connector
The TCS tools also provide an interface adapter to
convert the 14-pin interface pod to a 9-pin, subminia-
ture, D-type plug (male) for connection to the user's
target hardware.
Figure 16
illustrates the pinout of this
connector.
Table 25
describes the signal names and
their relationship to the DSP16411 signals. This con-
nector is also compatible with the Agere JTAG commu-
nications system (JCS) and hardware development
system (HDS) tools.
Figure 16. HDS 9-Pin Connector
5-7335 (F)
PIN 5
PIN 9
PIN 1
PIN 6
Table 25. HDS 9-Pin, Subminiature, D-Type Plug Pinout
HDS Pin
Number
HDS Signal
Name
Description
HDS I/O
DSP16411
Pin Number
DSP16411
Signal Name
DSP16411
I/O
1
Ground
System ground
G
See
Section 7 on page 253
V
SS
G
2
TCK
Test clock
O
F4 and L13
TCK0 and TCK1
I
3
NC
No connect
NA
NA
NA
NA
4
TMS
Test mode select
O
G2 and K15
TMS0 and TMS1
I
5
Ground
System ground
G
See
Section 7 on page 253
V
SS
G
6
TDO
Test data output
I
F1 or L16 (not both)
TDO0 or TDO1
(not both)
O
7
TDI
Test data input
O
G1 or K16 (not both)
TDI0 or TDI1
(not both)
I
8
V
TARG
Target I/O voltage
I
See
Section 7 on page 253
V
DD
2
P
9
NC
No connect
NA
NA
NA
NA
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
61
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.12 JTAG Test Port (JTAG
0--1
)
(continued)
4.12.3 Multiprocessor JTAG Connections
The DSP16411 has two JTAG ports, one for each
DSP16000 core. The user can daisy chain these ports
onto the same scan chain, potentially with other
DSP16411 devices, or interface to each JTAG port indi-
vidually for debugging. If multiple JTAG ports are inter-
faced together on the same scan chain, TMS and TCK
are broadcast to all DSPs in the scan chain. TDI of the
first JTAG port in the chain is then connected to TDI of
the TCS connector on the user's board, TDO of the first
JTAG port is connected to TDI of the next JTAG port in
the chain, and so on. TDO of the last JTAG port in the
chain is then tied to TDO of the TCS connector. If
more than six JTAG ports are in the same scan chain,
TMS and TCK must be buffered to ensure compatibility
with t155 and t156 (see
Table 195 on page 282
). In the
typical application, the user's board ties the DSP16411
JTAG reset signals, TRST0N and TRST1N, to the
device reset, RSTN.
Figure 17
illustrates a typical
daisy-chain connection between the TCS hardware
and the two cores of a single DSP16411.
Note: CORE0 is DSP1 on the scan chain and CORE1 is DSP2 on the scan chain. For multiple DSP16411 devices on a single scan chain,
maintain the CORE0-to-CORE1 daisy-chain.
Figure 17. Typical Multiprocessor JTAG Connection with Single Scan Chain
JCS/TCS
TDO
TCK
TMS
TDI
TCK0
TMS0
TDI0
TDO0
TCK1
TMS1
TDI1
TDO1
CORE1
CORE0
RESET
TRST0N
TRST1N
RSTN
DSP16411
Data Sheet
DSP16411 Digital Signal Processor
May 2003
62
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.12 JTAG Test Port (JTAG
0--1
)
(continued)
4.12.4 Boundary Scan
JTAG0 contains a full boundary-scan register as described in
Table 26
and JTAG1 contains a single-bit boundary-
scan register as described in
Table 27 on page 63
. As described in
Section 4.12.3 on page 61
, JTAG0 and JTAG1
of multiple DSP16411 devices can be chained together with full boundary-scan capabilities.
Table 26. JTAG0 Boundary-Scan Register
Cell
Type
Signal Name/
Function
Control
Cell
Cell
Type
Signal Name/
Function
Control
Cell
0
I
ERTYPE
--
87
DC
IO1BIT[1] direction control
--
1
I
EXM
--
88
I/O
IO1BIT[1]
87
2
I
ESIZE
--
89
DC
IO1BIT[2] direction control
--
3
I
EREQN
--
90
I/O
IO1BIT[2]
89
4
I
ERDY
--
91
DC
IO1BIT[3] direction control
--
20--5
I/O
ED[15:0]
21
92
I/O
IO1BIT[3]
91
21
DC
ED[15:0] direction control
--
93
DC
IO1BIT[4] direction control
--
37--22
I/O
ED[31:16]
38
94
I/O
IO1BIT[4]
93
38
DC
ED[31:16] direction control
--
95
DC
IO1BIT[5] direction control
--
39
O
EACKN
65
96
I/O
IO1BIT[5]
95
41--40
O
ERWN[1:0]
45
97
DC
IO1BIT[6] direction control
--
42
O
EROMN
45
98
I/O
IO1BIT[6]
97
43
O
ERAMN
45
99
DC
IO1BIT[7] direction control
--
44
O
EION
45
100
I/O
IO1BIT[7]
99
45
OE
EION, ERAMN, EROMN,
ERWN[1:0] 3-state control
--
104--101
I
PADD[3:0]
--
64--46
O
EA[18:0]
65
105
I
PCSN
--
65
OE
EA[18:0] 3-state control
--
106
I
PRWN
--
69--66
O
ESEG[3:0]
70
107
I
PIDS
--
70
OE
ESEG[3:0] 3-state control
--
108
I
PODS
--
71
OE
ECKO and EACKN
3-state control
--
109
I
PRDYMD
--
72
O
ECKO
71
110
O
PINT
114
73
OE
SOD1 3-state control
--
111
O
PRDY
114
74
O
SOD1
73
112
O
PIBF
114
75
I
SID1
--
113
O
POBE
114
76
I
SCK1
--
114
OE
PINT, PRDY, PIBF,
POBE 3-state control
--
77
DC
SOFS1 direction control
--
130--115
I/O
PD[15:0]
131
78
I/O
SOFS1
77
131
DC
PD[15:0] direction control
--
79
DC
SOCK1 direction control
--
132
I
EYMODE
--
80
I/O
SOCK1
79
133
DC
IO0BIT[0] direction control
--
81
DC
SIFS1 direction control
--
134
I/O
IO0BIT[0]
132
82
I/O
SIFS1
81
135
DC
IO0BIT[1] direction control
--
83
DC
SICK1 direction control
--
136
I/O
IO0BIT[1]
134
84
I/O
SICK1
83
137
DC
IO0BIT[2] direction control
--
85
DC
IO1BIT[0] direction control
--
138
I/O
IO0BIT[2]
136
Key to this column: I = input; OE = 3-state control cell; O = output; DC = bidirectional control cell; I/O = input/output.
There is no pin associated with this signal
.
This is a pad only and is not connected in the package.
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
63
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.12 JTAG Test Port (JTAG
0--1
)
(continued)
4.12.4 Boundary Scan (continued)
86
I/O
IO1BIT[0]
85
139
DC
IO0BIT[3] direction control
--
140
I/O
IO0BIT[3]
138
153
DC
SOFS0 direction control
--
141
DC
IO0BIT[4] direction control
--
154
I/O
SOFS0
152
142
I/O
IO0BIT[4]
140
155
DC
SOCK0 direction control
--
143
DC
IO0BIT[5] direction control
--
156
I/O
SOCK0
154
144
I/O
IO0BIT[5]
142
157
DC
SIFS0 direction control
--
145
DC
IO0BIT[6] direction control
--
158
I/O
SIFS0
156
146
I/O
IO0BIT[6]
144
159
DC
SICK0 direction control
--
147
DC
IO0BIT[7] direction control
--
160
I/O
SICK0
158
148
I/O
IO0BIT[7]
146
164--161
I
INT[3:0]
--
149
OE
SOD0 3-state control
--
165
DC
TRAP direction control
--
150
O
SOD0
148
166
I/O
TRAP
164
151
I
SID0
--
167
I
RSTN
--
152
I
SCK0
--
168
I
CKI
--
Table 27. JTAG1 Boundary-Scan Register
Cell
Function
Control Cell
0
Internal Cell
--
Table 26. JTAG0 Boundary-Scan Register (continued)
Cell
Type
Signal Name/
Function
Control
Cell
Cell
Type
Signal Name/
Function
Control
Cell
Key to this column: I = input; OE = 3-state control cell; O = output; DC = bidirectional control cell; I/O = input/output.
There is no pin associated with this signal
.
This is a pad only and is not connected in the package.
Data Sheet
DSP16411 Digital Signal Processor
May 2003
64
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.13 Direct Memory Access Unit (DMAU)
The DMAU (direct memory access unit) manages
movement of data to or from the DSP16411 internal or
external memory with minimal core intervention:
!
The DMAU can move data between memory and the
I/O units:
-- The DMAU provides four single-word transfer
(SWT) channels for moving data between memory
and SIU
0--1
. A core initially defines the data
structure and the DMAU provides address gener-
ation, compare, and update functions. Two-
dimensional array capability facilitates applica-
tions such as TDM channel multiplexing/demulti-
plexing. Each SWT channel allows an SIU to
access memory one word (16 bits) at a time.
-- The DMAU provides a single addressing bypass
channel for moving data between memory and the
PIU. Unlike the SWT channels, the bypass chan-
nel does not provide address generation, com-
pare, and update functions. The bypass channel
allows a host to address and access memory one
word (16 bits) at a time.
!
The DMAU can move data between two blocks of
memory. It provides two memory-to-memory (MMT)
channels for which a core initially defines the data
structure. The DMAU provides address generation,
compare, and update functions for each channel.
The DMAU can perform a block transfer either a sin-
gle word (16 bits) at a time or a double word (32 bits)
at a time.
4.13.1 Overview
The DMAU has six independent channels and an
addressing bypass channel as detailed in
Table 28
.
These channels can access any DSP16411 memory
component, including TPRAM0, TPRAM1, and exter-
nal memory.
Figure 18 on page 65
is a functional overview of the
DMAU channels and their interconnections to the
peripherals and memory buses. The DMAU arbitrates
among the seven channels for access to the memory.
For an SWT channel, a core can define a data struc-
ture (array) in DSP16411 memory by programming
DMAU memory-mapped registers. The DMAU can
then perform source or destination transfers. A
source transfer is defined as a series of read opera-
tions from the memory array to an SIU. A destination
transfer
is defined as a series of write operations to
the memory array from an SIU. A transfer consists of a
series of transactions in response to SIU requests. A
source transaction is defined as reading a word
(16 bits) from the array, writing the word to the SIU out-
put data register (SODR), and updating the appropriate
DMAU registers. A destination transaction is defined
as reading a word from the SIU input data register
(SIDR), writing the word to the array, and updating the
appropriate DMAU registers. See
Section 4.13.5,
beginning on page 87,
for details on SWT transactions.
The DMAU also provides two channels for memory-to-
memory transfers (MMT). These channels allow a
user-defined block of data to be transferred between
any two DSP16411 memory blocks, including external
memory. Each MMT channel transfers data between a
source block and a destination block. The DMAU
can perform a block transfer either a single word
(16 bits) at a time or a double word (32 bits) at a
time. See
Section 4.13.6, beginning on page 90,
for
details on memory-to-memory block transfers.
Finally, the DMAU provides an addressing bypass
channel that is dedicated to the PIU. This channel
bypasses the DMAU address generation, compare,
and update processes. The DMAU relies on the PIU to
provide the memory address for each PIU transaction
(data transfer between a host and the DSP16411).
The addressing bypass channel provides a host with
fast access to any DSP16411 memory space. See
Section 4.13.4 on page 86
for more details.
Table 28. DMAU Channel Assignment
DMAU Channel
Description
Associated With
SWT0
Single-word (16-bit) transfers
SIU0
SWT1
Single-word (16-bit) transfers
SWT2
Single-word (16-bit) transfers
SIU1
SWT3
Single-word (16-bit) transfers
MMT4
Single-word (16-bit) or double-word (32-bit) transfers
Memory
MMT5
Single-word (16-bit) or double-word (32-bit) transfers
Bypass
Single-word (16-bit) transfers
PIU
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
65
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.13 Direct Memory Access Unit (DMAU)
(continued)
4.13.1 Overview (continued)
DMAU Channels
Figure 18. DMAU Interconnections and Channels
Figure 19
is a block diagram of the DMAU. The DMAU includes 55 memory-mapped registers that it uses in pro-
cessing source transfers, destination transfers, and memory-to-memory block transfers. These registers are con-
figured by programs running in the cores that access the registers. The registers control the DMAU and contain its
current status. See
Section 4.13.2, beginning on page 67,
for details on these registers. Although the DMAU reg-
isters are memory-mapped, they are physically located in the DMAU and are accessible by either core via the
SEMI and the SDB (system data bus).
TPRAM0
TPRAM1
SEMI
ZEDB
ZIDB
Z-BUS
ARBITER
SWT0
SWT1
SWT2
SWT3
PIU
CHANNEL
CHANNEL
CHANNEL
CHANNEL
16
32
32
DMAU
DESTINATION
DATA
16
SOURCE
DATA
16
DESTINATION
DATA
16
SOURCE
DATA
BYPASS
CHANNEL
16
DATA
16/32
DESTINATION
DATA
16/32
SOURCE
DATA
16/32
DESTINATION
DATA
16/32
SOURCE
DATA
SIU1
SIU0
MMT4
CHANNEL
MMT5
CHANNEL
Data Sheet
DSP16411 Digital Signal Processor
May 2003
66
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.13 Direct Memory Access Unit (DMAU)
(continued)
4.13.1 Overview (continued)
DMAU Block Diagram
Figure 19. DMAU Block Diagram
DMAU
SAB SDB
ZSEG ZEAB ZEDB
DPI
PAB
DDO
DSI0
8 CONTROL REGISTERS
DMCON
0--1
16 bits
CTL
0--5
4 STRIDE REGISTERS
16 bits
STR
0--3
4 REINDEX REGISTERS
RI
0--3
20 bits
8 BASE REGISTERS
SBAS
0--3
DBAS
0--3
20 bits
6 LIMIT REGISTERS
LIM
0--5
20 bits
12 COUNTER REGISTERS
SCNT
0--5
DCNT
0--5
20 bits
12 ADDRESS REGISTERS
32 bits
SADD
0--5
DADD
0--5
ADDRESS
COMPARE
&
UPDATE
DSINT[3:0], DDINT[3:0], DMINT[5:4]
10
20
4
20
32
32
16
16
32
16
SEMI
TPRAM
0,1
SEMI
1 STATUS REGISTER
32 bits
DSTAT
DDO
PIU
SIU0
DDO
DSI1
SIU1
16
27
16
27
20
20
20
20
20
20
14
(TO CORES)
PIU ADDRESSING
BYPASS CHANNEL
SOCIX1
SICIX1
SOCIX0
SICIX0
REQUEST
ZIAB ZIDB
32
20
MMT
SOURCE
LOOK-AHEAD
BUFFER
(6 x 32 FIFO)
Z-BUS
ARBITER
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
67
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.13 Direct Memory Access Unit (DMAU)
(continued)
4.13.2 Registers
Table 29
lists the DMAU memory-mapped registers in functional order, not in address order.
Section 6.2.2 on
page 231
describes addressing of memory-mapped registers. The DMAU contains a status register and two mas-
ter control registers for all SWT and MMT channels: DMCON0, DMCON1, and DSTAT. Every DMAU channel has
a corresponding control register CTL
0--5
, source and destination address register (SADD
0--5
and
DADD
0--5
), source and destination counter register (SCNT
0--5
and DCNT
0--5
), and limit register
(LIM
0--5
). In addition, each SWT channel has a corresponding source and destination base address register
(SBAS
0--3
and DBAS
0--3
), reindex register (RI
0--3
), and stride register (STR
0--3
).
Table 29. DMAU Memory-Mapped Registers
Type
Register
Name
Channel
Address
Size
(Bits)
R/W
Type
Signed/
Unsigned
Reset
Value
DMAU Status
DSTAT
All
0x4206C
32
R
status
unsigned
X
DMAU Master Control 0
DMCON0
All
0x4205C
16
R/W
control
unsigned
0
DMAU Master Control 1
DMCON1
All
0x4205E
Channel Control
CTL0
SWT0
0x42060
16
R/W
control
unsigned
X
CTL1
SWT1
0x42062
CTL2
SWT2
0x42064
CTL3
SWT3
0x42066
CTL4
MMT4
0x42068
CTL5
MMT5
0x4206A
Source Address
SADD0
SWT0
0x42000
32
R/W
address
unsigned
X
Destination Address
DADD0
0x42002
Source Address
SADD1
SWT1
0x42004
Destination Address
DADD1
0x42006
Source Address
SADD2
SWT2
0x42008
Destination Address
DADD2
0x4200A
Source Address
SADD3
SWT3
0x4200C
Destination Address
DADD3
0x4200E
Source Address
SADD4
MMT4
0x42010
Destination Address
DADD4
0x42012
Source Address
SADD5
MMT5
0x42014
Destination Address
DADD5
0x42016
Source Count
SCNT0
SWT0
0x42020
20
R/W
data
unsigned
X
Destination Count
DCNT0
0x42022
Source Count
SCNT1
SWT1
0x42024
Destination Count
DCNT1
0x42026
Source Count
SCNT2
SWT2
0x42028
Destination Count
DCNT2
0x4202A
Source Count
SCNT3
SWT3
0x4202C
Destination Count
DCNT3
0x4202E
Source Count
SCNT4
MMT4
0x42030
Destination Count
DCNT4
0x42032
Source Count
SCNT5
MMT5
0x42034
Destination Count
DCNT5
0x42036
For this column, X indicates unknown on powerup reset and unaffected on subsequent reset. Any reserved fields within the register are reset to zero.
The reindex registers are in sign-magnitude format.
Data Sheet
DSP16411 Digital Signal Processor
May 2003
68
Agere Systems--Proprietary
Agere Systems Inc.
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.13 Direct Memory Access Unit (DMAU)
(continued)
Table 29. DMAU Memory-Mapped Registers (continued)
4.13.2 Registers (continued)
Note: The remainder of
Section 4.13.2
describes the detailed encoding for each register.
Limit
LIM0
SWT0
0x42050
20
R/W
data
unsigned
X
LIM1
SWT1
0x42052
LIM2
SWT2
0x42054
LIM3
SWT3
0x42056
LIM4
MMT4
0x42058
LIM5
MMT5
0x4205A
Source Base
SBAS0
SWT0
0x42040
20
R/W
address
unsigned
X
Destination Base
DBAS0
0x42042
Source Base
SBAS1
SWT1
0x42044
Destination Base
DBAS1
0x42046
Source Base
SBAS2
SWT2
0x42048
Destination Base
DBAS2
0x4204A
Source Base
SBAS3
SWT3
0x4204C
Destination Base
DBAS3
0x4204E
Stride
STR0
SWT0
0x42018
16
R/W
data
unsigned
X
STR1
SWT1
0x4201A
STR2
SWT2
0x4201C
STR3
SWT3
0x4201E
Reindex
RI0
SWT0
0x42038
20
R/W
data
signed
X
RI1
SWT1
0x4203A
RI2
SWT2
0x4203C
RI3
SWT3
0x4203E
Type
Register
Name
Channel
Address
Size
(Bits)
R/W
Type
Signed/
Unsigned
Reset
Value
For this column, X indicates unknown on powerup reset and unaffected on subsequent reset. Any reserved fields within the register are reset to zero.
The reindex registers are in sign-magnitude format.
Data Sheet
May 2003
DSP16411 Digital Signal Processor
Agere Systems Inc.
Agere Systems--Proprietary
69
Use pursuant to Company instructions
4 Hardware Architecture
(continued)
4.13 Direct Memory Access Unit (DMAU)
(continued)
4.13.2 Registers (continued)
The DMAU status register (DSTAT) reports current DMAU channel activity for both source and destination opera-
tions and reports channel errors. This register can be read by the user software executing in either core to deter-
mine if a specific DMAU channel is already in use, or if an error has occurred that may result in data corruption.
The ERR[5:0] fields of the DSTAT register reflect DMAU protocol errors. See
Section 4.13.8 on page 94
for infor-
mation on error reporting and recovery.
Table 30. DSTAT (DMAU Status) Register
The memory address for this register is 0x4206C.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RBSY5 RBSY4 SBSY5 DBSY5 SRDY5 DRDY5
ERR5
SBSY4 DBSY4 SRDY4 DRDY4 ERR4 SBSY3 DBSY3 SRDY3 DRDY3
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ERR3
SBSY2 DBSY2 SRDY2 DRDY2
ERR2
SBSY1 DBSY1 SRDY1 DRDY1
ERR1
SBSY0 DBSY0 SRDY0 DRDY0
ERR0
Bits
Field
Value
Description
R/W
Reset
Value
31
RBSY5
1
MMT5 is busy completing a reset operation
.
R
X
0
MMT5 is not completing a reset operation.
30
RBSY4
1
MMT4 is busy completing a reset operation
.
R
X
0
MMT4 is not completing a reset operation.
29
SBSY5
1
MMT5 is reading memory.
R
X
0
MMT5 is not reading memory.
28
DBSY5
1
MMT5 is writing memory.
R
X
0
MMT5 is not writing memory.
27
SRDY5
1
MMT5 has a source transaction pending.
R
X
0
MMT5 does not have a source transaction pending.
26
DRDY5
1
MMT5 has a destination transaction pending.
R
X
0
MMT5 does not have a destination transaction pending.
25
ERR5
1
MMT5 has detected a protocol error (source or destination). Error report is cleared by
writing a 1 to this bit.
R/Clear
X
0
MMT5--no errors.
24
SBSY4
1
MMT4 is reading memory.
R
X
0
MMT4 is not reading memory.
23
DBSY4
1
MMT4 is writing memory.
R
X
0
MMT4 is not writing memory.
22
SRDY4
1
MMT4 has a source transaction pending.
R
X
0
MMT4 does not have a source transaction pending.
21
DRDY4
1
MMT4 has a destination transaction pending.
R
X
0
MMT4 does not have a destination transaction pending.
20
ERR4
1
MMT4 has detected a protocol error (source or destination). Error report is cleared by
writing a 1 to this bit.
R/Clear
X
0
MMT4--no errors.
19
SBSY3
1
SWT3 is reading memory.
R
X
0
SWT3 is not reading memory.
18
DBSY3
1
SWT3 is writing memory.
R
X
0
SWT3 is not writing memory.
For this column, X indicates unknown on powerup reset and una