Preliminary Data Sheet
August 2000

LU5X31F

Gigabit Ethernet Transceiver

Overview

The LU5X31F is a low-cost, low-power gigabit Ether-
net transceiver. It is used for data transmission over
fiber or coaxial media in conformance with

IEEE*

802.3z Gigabit Ethernet specification and Fibre
Channel

ANSI

X3T11 at 1.0 Gbit/s and

1.25 Gbits/s.

The transmitter section accepts parallel 10-bit, 8b/
10b encoded data that is latched on the rising edge
of REFCLK. It also uses this clock to synthesize the
internal high-speed serial bit clock. The serialized
data is then available at the differential PECL out-
puts, terminated in 50

or 75

to drive either an

optical transmitter or coaxial media.

The receive section receives high-speed serial data
at its differential PECL input port. This data is fed to
the digital clock recovery section, which generates a
recovered clock and retimes the data. The retimed
data is deserialized and presented as 10-bit parallel
data on the output port. A divided-down version of
the recovered clock, synchronous with parallel data
bytes, is also available as a TTL compatible output.
The receive section recognizes the comma character
and aligns the comma containing byte on the word
boundary, when ENCDET = 1.

IEEE

is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

ANSI

is a registered trademark of American National Standards

Institute.

FireWire

is a registered trademark of Apple Computer, Inc.

Features

Designed to operate in Ethernet, fibre channel,

FireWire

or backplane applications.

Operationally compliant to

IEEE

802.3z Gigabit

Ethernet specification.

Operationally compliant to Fibre Channel

ANSI

X3T11. Provides FC-0 services at 1.0 Gbit/s--
1.25 Gbits/s (10-bit encoded data rate).

100 MHz--125 MHz differential or single-ended
reference clock.

10-bit parallel interface.

8b/10b encoded data.

High-speed comma character recognition (K28.1,
K28.5, K28.7) for latency-sensitive applications
and alignment to word boundary.

Two 62.5 MHz receive-byte clocks.

Single-analog PLL design requires no external
components for the frequency synthesizer.

Novel digital data lock in receiver avoids the need

for multiple analog PLLs.

Expandable beyond single-channel SERDES.

PECL high-speed interface I/O for use with optical
transceiver or coaxial copper media.

Requires one external resistor for PECL output ref-

erence level definition.

Available in both 64-pin MQFP (14 mm) and 64-pin

TQFP (10 mm) packages.

Low-power digital 0.25 µm CMOS technology.

3.3 V ± 5% power supply.

0 °C--70 °C ambient temperature.

Table of Contents

Lucent Technologies Inc.

Contents

Page

Figure

Page

LU5X31F

Preliminary Data Sheet

Gigabit Ethernet Transceiver

August 2000

Overview ................................................................. 1
Features .................................................................. 1
Functional Description ............................................ 3

Transmitter Section .............................................. 3
Receiver Section .................................................. 3
Byte Alignment ..................................................... 4
Parallel Output Port .............................................. 4
Loopback Mode Operation ................................... 4
Powerup Sequence .............................................. 5
Device Reset ........................................................ 5
Block Diagram ...................................................... 6

Input/Output Information ......................................... 7
Electrical Specifications ........................................ 10

Transmitter ......................................................... 10
Receiver ............................................................. 11

Timing Characteristics .......................................... 12

Serial Timing ...................................................... 12
Receiver Section Timing .................................... 13
Receiver Port Timing .......................................... 13
Transmitter Section Timing ................................ 14

Application Section ............................................... 15
Test Modes ........................................................... 17
Outline Diagrams .................................................. 19

64-Pin MQFP ..................................................... 19
64-Pin TQFP ...................................................... 20

Ordering Information ............................................. 21

Table

Page

Table 1. Definition of Bit Transmission/Reception

Order ......................................................................4

Table 2a. I/O Channel Signal Description .................8
Table 2b. I/O Control/PLL Interface Descriptions .....9
Table 2c. Power Connections ...................................9
Table 3. Reference Clock Specifications (REFCLK) 10
Table 4. PLL Characteristics ...................................10
Table 5. Output Jitter at 1.0 Gbit/s--1.25 Gbits/s Data

Rate ......................................................................10

Table 6. Input Data Rate .........................................11
Table 7. Data Lock Characteristics .........................11
Table 8. Power Dissipation* ....................................11
Table 9. dc Electrical Specifications* ......................11
Table 10. Absolute Maximum Ratings ....................11
Table 11. Serial Output Timing Levels ....................12
Table 12. Serial Input Interface Timing ...................12
Table 13. Receiver Parallel Port Timing .................13
Table 14. Transmitter Timing at Parallel Interface ..14
Table 15. External Resistor Value vs. Differential Output

Level Viewing .......................................................16

Table 16. Test Modes .............................................17

Figure 1. LU5X31F Single-Channel Gigabit Ethernet

Transceiver Functional Diagram .......................... 6

Figure 2. 64-Pin MQFP Package (14 mm) Pinout .. 7
Figure 3. Serial Interface Timing ........................... 12
Figure 4. Receiver Section Timing ........................ 13
Figure 5. Receiver Port Timing ............................. 13
Figure 6. Parallel Interface Transmit Timing ......... 14
Figure 7. Reference Clock Connections with Single-

Ended Source ..................................................... 15

Figure 8. Typical Termination for a Single-Channel,

High-Speed Serial Transmit-and-Receive Port in a
50

Backplane Application ............................... 15

Figure 9. Typical Termination for a Single-Channel,

High-Speed Serial Transmit Port Interfacing a 5 V
GBIC Transceiver ............................................... 16

Lucent Technologies Inc.

Preliminary Data Sheet

LU5X31F

August 2000

Gigabit Ethernet Transceiver

Functional Description

The LU5X31F transceiver provides for data transmis-
sion over fiber or coaxial media at 1.0 Gbits/s to
1.25 Gbits/s. The block diagram of a single channel is
shown in Figure 1. The input/output designations are
given in Table 3.

Transmitter Section

The transmitter accepts 8B/10B encoded bits in 10-bit
parallel form and converts to serial format for up
to 1.25 Gbits/s transmission. The serial nonreturn to
zero (NRZ) bits are shifted out of the device at a maxi-
mum rate of 1.25 Gbits/s. Internally, the device uses
two parallel shift registers that operate at half rate (i.e.,
a maximum of 625 MHz) for reduced power consump-
tion. The two shift registers drive the PECL output
buffer in an interleaved manner to construct the
1.25 Gbits/s output data stream.

The typical transmit and receive high-speed I/O inter-
facing is shown in Figures 8 and 9, for a single-channel
application.

The transmit shift register and other circuits are driven
with clocks generated from a 500 MHz--625 MHz inter-
nal clock. This internal clock is sourced from a voltage-
controlled oscillator (VCO) that is locked to the external
reference of 100 MHz--125 MHz. The internal transmit
phase-lock loop multiplies the frequency of the input
reference clock by a factor of 5, and controls the trans-
mit jitter bandwidth with appropriate design of the jitter
transfer function. The transmit phase-lock loop gener-
ates multiple clock phases that are all used by each of
the four receiver circuits. The clock phases are derived
from the transmit VCO.

Receiver Section

The receiver circuit extracts the clock from, and
retimes, the serial input data. The data is input to the
receiver on differential PECL buffers. External termina-
tion resistors are supplied by the user in accordance
with

ANSI

standard, X3T11. The serial differential

inputs, HDINP and HDINN, are ac-coupled to the
device and internally biased to the PECL input com-
mon-mode range center. See Figures 8 and 9 for the
typical termination of the transmission lines.

The receiver data retiming circuit uses a digital timing
recovery loop that compares the phase of the input
data to multiple phases of the on-device VCO in the
transmit section. One of the phases is chosen to retime
the receive data. A digital low-pass filter is used in the
timing recovery loop to reject jitter from the data input.
A novel phase interpolation circuit permits the retiming
clock's phase to be stepped with fine resolution for pre-
cise alignment of the sampling clock within the data
eye. Use of this digital data locking scheme avoids the
use of multiple analog phase-lock loops on-device that
can potentially injection lock to one another when
expanded to multiple receivers. Additionally, the digital
data locking loop maintains precise loop dynamics,
hence, the jitter transfer function is process and tem-
perature independent.

Lucent Technologies Inc.

LU5X31F

Preliminary Data Sheet

Gigabit Ethernet Transceiver

August 2000

Functional Description

(continued)

Byte Alignment

When ENCDET = 1, the LU5X31F recognizes the
comma character and aligns this 10-bit character to the
word boundary, bits RX[0:9].

COMDET = 1 when the parallel output word contains a
byte-aligned comma character. The COMDET flag will
continue to pulse a logic 1 whenever a byte-aligned
comma character is at the parallel output port, indepen-
dent of ENCDET. When ENCDET = 0 there are two pos-
sible scenarios, depending upon when the comma
character is received:

1. If byte alignment had been previously achieved when

ENCDET had been a logic 1, the COMDET flag will
continue to pulse a logic 1 whenever a byte-aligned
comma character is at the parallel output port. If a
comma character occurs that is not on the word
boundary, no attempt will be made to align this
comma character, and the COMDET flag will remain
at a logic 0.

2. If byte alignment had not been previously achieved

when ENCDET had been a logic 1, then the first (and
only the first) comma character received will be
aligned to the word boundary. COMDET will pulse
when the comma character is aligned to the word
boundary.

Parallel Output Port

Timing for the parallel output data and the 62.5 MHz
receive-byte clock is given in Table 14.

Two low data-rate, receive-byte clocks are available as
outputs during use of the parallel output port in 10-bit
mode. RXCLK1 is the receive-byte clock used by the
protocol device to register bytes 0 and 2. RXCLK0 is
the receive-byte clock used by the protocol device to
register bytes 1 and 3, and it is 180 degrees out of
phase with RXCLK1. Both RXCLK1 and RXCLK0 can
be stretched during byte alignment, but not truncated
or slivered. The maximum allowable frequency of these
two clocks under all circumstances, excluding start-up,
will not exceed 80 MHz. The start-up time is specified
as 1 ms.

Loopback Mode Operation

A control signal input, EWRAP, selects between two
possible sets of inputs: normal data (HDINP, HDINN),
or internal loopback data. When EWRAP = 1, the serial
output ports, HDOUTP and HDOUTN, remain active.
The serial transmit data prior to the PECL output driver
is directed to the data recovery circuit, where the clock
is recovered and data is resynchronized to the recov-
ered clock. Retimed data and clock then go to the
serial-to-parallel converter.

Table 1. Definition of Bit Transmission/Reception Order

Serial Transmit/

Receive Rate

TX[9:0]

RX[9:0]

1.0 Gbits/s to 1.25 Gbits/s TX[0] bit serially transmitted first at

HDOUTP, HDOUTN.

RX[0] bit received first at serial inputs,
HDINP, HDINN.

Lucent Technologies Inc.

Preliminary Data Sheet

LU5X31F

August 2000

Gigabit Ethernet Transceiver

Functional Description

(continued)

Powerup Sequence

The power ramp time for the LU5X31F is specified at
V

> 2.7 V within 20 µs of start-up. Once 2.7 V is

reached, the device is held in reset for 15 µs--
70 µs. The REFCLK must be active and within specifi-
cation at this point and remain active while the device
is powered up, unless in reset.

When signals RESETN, BYPPLL, and LPWR are all
low, the following start-up sequence occurs:

1. 0 µs--32 µs, the analog PLL is held at minimum fre-

quency to allow dc bias to settle.

2. 32 µs--262 µs, the analog PLL has locked in and

receiver analog circuits start to lock in.

3. 262 µs--326 µs, the receiver analog circuits are

locked; receiver starts to lock onto incoming data.

4. After 358 µs, the receiver is locked onto incoming

data and can be viewed at the parallel output ports.
The comma-detect circuit is enabled at this point,
allowing byte alignment if ENCDET = 1.

Device Reset

The RESETN input to the device is an active-low.
When activated with a pulse duration of 1 µs, the
RESETN signal globally resets the device and the fol-
lowing is performed:

1. The single analog PLL is forced to operate at the

minimum frequency possible for its VCO. The PLL
will not be locked in this condition.

2. The HDOUTP, HDOUTN outputs are forced to a

PECL logic 0.

3. The deserializer clocks are reset, input data at

HDINP, HDINN is ignored, and the RX[9:0] signals
remain in their previous state.

4. The phase interpolation/selection circuits are deacti-

vated and the selected phase is reset.

5. The receiver digital low-pass filter in the DPLL is

reset. Normally, a reset is not necessary for correct
operation, although a reset can aid rapid lock-in of
the internal PLL circuitry. This signal is internally
pulled high.

Lucent Technologies Inc.

Preliminary Data Sheet

LU5X31F

August 2000

Gigabit Ethernet Transceiver

Input/Output Information

Figure 2. 64-Pin MQFP Package (14 mm) Pinout

NC/T

EST

NC/T

EST

VSS

31 32

NC/RES

VSS

CDET

TX4

TX7

VSS/TEST3

TX1

VDD

TX9

VSS/BYPPLL

TX6

TX3

VDD/TEST5

TX0

TX2

TX8

VSS

NC/TEST1

TX5

VDD

RX6

OLRVS

VSS

RX1

RX7

RX9

RX4

RX2

RX5

COMDET

RX0

VDD

RX8

VSS

RX3

VSS

HDINP

VSS

HDOUT

VDDT

HDINN

VDDP

VSS

50 49

VDDT

VDDR

VDD

HDOUT

VDDR

VSS

VDDR

5-8869(F)

Lucent Technologies Inc.

LU5X31F

Preliminary Data Sheet

Gigabit Ethernet Transceiver

August 2000

Input/Output Information

(continued)

Table 2a. I/O Channel Signal Description

PIN

Name

I/O

Level

Description

2--4,
6--9,

11--13

TX[9:0]

Input

TTL/

CMOS

Transmit Data. One 10-bit, parallel 8b/10b encoded
data byte clocked in on the rising edge of REFCLK.
TX0 is the leading LSB.

34--36,
38--41,

43--45

RX[9:0]

Output

TTL/

CMOS

Receive Data. One 10-bit parallel 8b/10b encoded
data byte clocked out on the alternate rising edges of
RXCLK0, RXCLK1. RX0 is the leading LSB. Any
receive code-group containing a comma character is
clocked by the RXCLK1.

REFCLK

Input

TTL/

CMOS

Reference Clock. This 100 MHz--125 MHz clock is
used to latch TX[9:0] data into the LU5X31F for trans-
mission and is used by the transmitter PLL to generate
the 1.0 Gbits/s--1.25 Gbits/s serial data. REFCLK has
a ±100 ppm tolerance requirement.

RXCLK0

Output

TTL/

CMOS

Receive Clock 0. 62.5 MHz used to latch odd-num-
bered code-groups in the receive data stream. This
clock may be stretched during code-group alignment,
but should not be truncated or slivered.

RXCLK1

Output

TTL/

CMOS

Receive Clock 1. 62.5 MHz used to latch even-num-
bered code-groups in the receive data stream. This
clock may be stretched during code-group alignment
but should not be truncated or slivered. RXCLK1 is
180 degrees out of phase with RXCLK0. Note that the
comma pattern (contained in groups K28.1, K28.5,
K28.7) is constrained to only appear in even-numbered
code-group positions.

HDOUTP

Output

PECL

Transmit Data. Positive differential PECL serialized
transmit data at 1.25 Gbits/s; requires external trans-
mission line termination, as given in Figure 8.

HDOUTN

Output

PECL

Transmit Data. Negative differential PECL serialized
transmit data at 1.25 Gbits/s; requires external trans-
mission line termination, as given in Figure 8.

HDINP

Input

PECL

Receive Data. Positive differential PECL serialized
receive data at 1.25 Gbits/s; requires external transmis-
sion line termination, as given in Figure 8.

HDINN

Input

PECL

Receive Data. Negative differential PECL serialized
receive data at 1.25 Gbits/s; requires external transmis-
sion line termination, as given in Figure 8.

COMDET

Output

TTL/

CMOS

Comma Detect. Asserted high for a full RXCLK1 cycle
to indicate that a comma code-word is present on
RX[9:0].

ENCDET

Input

TTL/

CMOS

Enable Comma Detect. Enables COMDET and code-
word synchronization when set high. When low, dis-
ables COMDET and maintains current code-word
alignment.

EWRAP

Input

TTL/

CMOS

Enable Wrap. Enables the LU5X31F to internally loop
serialized transmit data to the deserializer. HDOUTP
and HDOUTN outputs remain active.

Lucent Technologies Inc.

Preliminary Data Sheet

LU5X31F

August 2000

Gigabit Ethernet Transceiver

Input/Output Information

(continued)

Table 2b. I/O Control/PLL Interface Descriptions

Table 2c. Power Connections

Pin

Name

I/O

Level

Description

OLREF

Input/Output

Analog

Output Level Reference. PECL level set resistor
terminal 1.

OLRVS

Input/Output

Analog

Output Level Ground. PECL level set resistor
terminal 2.

(NC)/

RESETN

Input

TTL/CMOS

RESETN. Active-low, internally pulled high.

TEST5

Input/Output

TTL/CMOS

Global Test Control Input/Output.

1, 16, 17, 27

(NC)/

TEST[4:1]

Input

TTL/CMOS

Factory Test Pins. Internally pulled low.

BYPPLL

Input

TTL/CMOS

Test Control-PLL Bypass Mode.

Pin

Name

Description

5, 10, 18, 20, 23, 28, 29, 37, 42, 63

Digital Power.

53, 55, 57

High-Speed Receive Analog Power.

59, 60

High-Speed Transmit Analog Power.

PLL Power.

1, 14, 15, 21, 25, 32, 33, 46, 64

Digital Ground.

High-Speed Receive Analog Ground.

High-Speed Transmit Analog Ground.

PLL Ground.

Lucent Technologies Inc.

LU5X31F

Preliminary Data Sheet

Gigabit Ethernet Transceiver

August 2000

Electrical Specifications

Transmitter

Table 3. Reference Clock Specifications (REFCLK)

* Measured at 50% amplitude point.

Table 4. PLL Characteristics

Table 5. Output Jitter

at 1.0 Gbit/s--1.25 Gbits/s Data Rate

Parameter

Min

Max

Unit

Frequency Range

100

125

MHz

Frequency Tolerance

100

ppm

Duty Cycle*

Rise Time (PECL)

0.8

Fall Time (PECL)

0.8

Rise Time (TTL/CMOS)

1.5

Fall Time (TTL/CMOS)

1.5

In-band Jitter 1 Gbit/s--1.25 Gbits/s

ps p-p

Out-of-Band Jitter

ps p-p

Parameter

Min

Typ

Max

Unit

Bandwidth

1.5 --

MHz

Jitter Peaking

0.5

Lock Time

230

µs

Parameter

Min

Max

Unit

Deterministic

0.08

UI p-p

Random

0.12

UI p-p

Total

0.2

UI p-p

Lucent Technologies Inc.

Preliminary Data Sheet

LU5X31F

August 2000

Gigabit Ethernet Transceiver

Electrical Specifications

(continued)

Receiver

Table 6. Input Data Rate

Table 7. Data Lock Characteristics

Data pattern: 111110000 . . .

Data pattern: 101010 . . .

Table 8. Power Dissipation*

* Depending on application (PCB layout, etc.)

Table 9. dc Electrical Specifications*

* Depending on application (PCB layout, etc.).

Table 10. Absolute Maximum Ratings

Parameter

Min

Max

Unit

Frequency Range

1.0

1.25

Gbits/s

Frequency Tolerance with REFCLK

100

ppm

Parameter

Min

Typ

Max

Unit

Bandwidth 0.3

MHz

Jitter Peaking

0.5

Lock Time*

µs

Parameter

Min

Max

Unit

Power --

750

Parameter

Symbol

Condition

Min

Typ

Max Unit

Supply Voltage

, V

3.135

3.3

3.465

Output Low

0.6

Output High

2.4

Input Low

0.8

Input High

2.0

Differential PECL
Output

Load, as in Figure 8.

800

Differential PECL
Input

Source configuration,

as in Figure 8.

400

1600

Parameter

Min Max

Unit

Supply Voltage

3.135

3.465

TTL High Input Voltage

3.0

3.6

PECL Output Current

Junction Operating Temperature

125

°C

Storage Temperature

150

°C

Lucent Technologies Inc.

Preliminary Data Sheet

LU5X31F

August 2000

Gigabit Ethernet Transceiver

Timing Characteristics

(continued)

Receiver Section Timing

Figure 4. Receiver Section Timing

Receiver Port Timing

Figure 5. Receiver Port Timing

Table 13. Receiver Parallel Port Timing

* 1.25 Gbits/s.
0.5 pF load.

Symbol

Parameter

Min

Max

Unit

RXCLK[1:0] Frequency*

62.5

MHz

RXCLK[1:0] Low

7.0

9.0

RXCLK[1:0] High

7.0

9.0

tR/F

RXCLK[1:0] (0.4 V to 2.6 V)

0.2

0.5

tR/F

Data Output (0.4 V to 2.6 V)

0.2

0.5

Setup Time

3.0

Hold Time

2.0

tSKEW

Skew

1.0

RX[9:0]

D7.2

HDNIP

RECOVERED CLOCK

RXCLK1

RXCLK0

COMDET

(INTERNAL)

K28.5

D7.2

D0.0

D1.0

RXCLK1

RXCLK0

RX0

RX1

RX2

RX3

RXCLK1 HIGH

RXCLK1 LOW

RXCLK PERIOD

tSKEW

5-8813(F)

5-8814(F)

Lucent Technologies Inc.

LU5X31F

Preliminary Data Sheet

Gigabit Ethernet Transceiver

August 2000

Application Section

(continued)

* External resistor connected between OLREF and OLRVS

See Table 16 for resistor value vs. termination impedance and output swing.

Damping resistor, maximum = 10

Figure 9. Typical Termination for a Single-Channel, High-Speed Serial

Transmit Port Interfacing a 5 V GBIC Transceiver

Table 15. External Resistor Value vs. Differential Output Level Viewing

Resistor Value (

)

Termination Impedance (

)

Differential Output Voltage (V)

7.5 K/11.25 K

50/75

0.8

5 K/7.5 K

1.2

4 K/6 K

1.6

5-8811(F)b

TX(+)

TX()

HDOUTP

HDOUTN

0.01

191

0.01

TRANSMIT

LU5X31F

TRANSMIT

GBIC

OLREF

OLRVS

TXA[9:0]

REFCLK

0.1

= 50

191

= 50

5 V

Lucent Technologies Inc.

Preliminary Data Sheet

LU5X31F

August 2000

Gigabit Ethernet Transceiver

Test Modes

Note: Test modes are intended for manufacture test only and are not guaranteed to be operational. They may be

modified or eliminated without prior notice.

The device has per-channel test modes as well as global test modes. The bypass PLL, BYPPLL, is a global test
input because it modifies the operation of the analog PLL. Test bits TEST[4:1] generally operate in the localized
mode. The LDST[A:D] inputs are enable signals that permit the TEST[4:1] signals to be injected into a particular
channel.

For example, if LDST = 1, the TEST[4:1] signals directly control the test modes in the A channel. Once LDST = 0,
the previous values of TEST[4:1] are held for the A channel. The TEST[4:1] signals control the four channels (A, B,
C, D) via level-sense latches that are gated with the LDST[A:D] inputs. TEST[5] is a global test pin used for both
injection of signals as well as for monitoring points within the device.

Table 16. Test Modes

Global

Local Test Configuration

Global

Operation

BYPPLL

TEST1

TEST2

TEST3

TEST4

TEST5

Normal operation.

Output

Analog PLL feedback signal viewed at
TEST5 pin.

Transceiver operates normally except
RX[9:0] output is from digital filter, not
the serial data.

Output

Transceiver operates normally except
RX[9:0] output is from digital filter and
the analog PLL feedback signal is
viewed at TEST5 pin.

Digital filter forced to count. Pulses
applied at TEST4 increment accumula-
tor; pulses at TEST5 decrement accu-
mulator.

RX[9:0] output is from digital filter, not
the serial data. Digital filter forced to
count. Pulses applied at TEST4 incre-
ment accumulator; pulses at TEST5
decrement accumulator.

Parallel loopback. TX[9:0] = RX[9:0].
RX[9:0] remains active.

Output

Parallel loopback. TX[9:0] = RX[9:0]
and analog PLL feedback signal viewed
at TEST5 pin. RX[9:0] remains active.

RX[9:0] output is from digital filter, not
the serial data. Receive channel is held
in reset. BYPPLL overrides this reset.

Output

RX[9:0] output is from digital filter, not
the serial data. Receive channel is held
in reset. BYPPLL overrides this reset.
Analog PLL feedback signal viewed at
TEST5 pin.

Transmitter is held in reset. BYPPLL
overrides this reset.

Lucent Technologies Inc.

LU5X31F

Preliminary Data Sheet

Gigabit Ethernet Transceiver

August 2000

Test Modes

(continued)

Table 16. Test Modes (continued)

Global

Local Test Configuration

Global

Operation

BYPPLL

TEST1

TEST2

TEST3

TEST4

TEST5

Output

Transmitter is held in reset. BYPPLL
overrides this reset. Analog PLL feed-
back signal viewed at TEST5 pin.

Transmitter and receiver are held in
reset. RX[9:0] output is from digital fil-
ter, not the serial data.

Output

Transmitter and receiver are held in
reset. RX[9:0] output is from digital fil-
ter, not the serial data. Analog PLL
feedback signal viewed at TEST5 pin.

C-0

C-90

Analog PLL is bypassed for low-speed
functional test. A low-speed clock is
input to TEST4, and a quadrature clock
is applied to TEST5. Frequency of
clocks is 5X REFCLK, but here REF-
CLK is lowered to about 1 MHz.

C-0

C-90

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200233 P. R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652

JAPAN:

Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700

EUROPE:

Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148

Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),

FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)

Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.

August 2000
DS00-387LAN (Replaces DS00-350LAN)

LU5X31F

Preliminary Data Sheet

Gigabit Ethernet Transceiver

August 2000

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Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LU5X31F

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LU5X31F