Document Outline
- Features
- Description
- Pin Information
- MII Station Management
- MODE Selection
- Absolute Maximum Ratings (TA = 25 C)
- Electrical Characteristics
- Timing Characteristics (Preliminary)
- Outline Diagram
- Technical Document Types
- Ordering Information
- List of Figures
- Figure 1 . Functional Block Diagram: Device Overview
- Figure 2 . Functional Block Diagram: Device Detail
- Figure 3 . Typical Twisted-Pair (TP) Interface
- Figure 4 . Onboard Universal Twisted-Pair Interface Circuit to Interchange Lucent and
- Figure 5 . LU6612 Pinout
- Figure 6 . MDIO Input Timing
- Figure 7 . MDIO Output Timing
- Figure 8 . MDIO During TA (Turnaround) of a Read Transaction
- Figure 9 . MII Timing Requirements for LU6612
- Figure 10 . Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK
- Figure 11 . Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK
- Figure 12 . Serial 10 Mbits/s Timing for TX_EN, RX/RY, and COL
- Figure 13 . Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD
- Figure 14 . Serial 10 Mbits/s Timing Diagram for RX_CLK and TX_CLK
- Figure 15 . 100 Mbits/s MII Transmit Timing
- Figure 16 . 100 Mbits/s MII Receive Timing
- List of Tables
- Table 1. MII/Serial Interface Pins (17)
- Table 2. MII Management Pins (2)
- Table 3. 10/100 Mbits/s Twisted-Pair (TP) Interface Pins (4)
- Table 4. Ground and Power Pins (21)
- Table 5. Miscellaneous Pins (20)
- Table 6. MII Management Frame Fields and Format
- Table 7. MII Management Frame Descriptions
- Table 8. MII Management Registers (MR)
- Table 9. MR0Control Register Bit Descriptions
- Table 10. MR1Status Register Bit Descriptions
- Table 11. MR2, 3PHY Identifier Registers (1 and 2) Bit Descriptions
- Table 12. MR4Autonegotiation Advertisement Register Bit Descriptions
- Table 13. MR5Autonegotiation Link Partner (LP) Ability Register Bit Descriptions (Base_Page)
- Table 14. MR5Autonegotiation Link Partner (LP) Ability Register Bit Descriptions (Next_Page)
- Table 15. MR6Autonegotiation Expansion Register Bit Descriptions
- Table 16. MR7Next_Page Transmit Register Bit Descriptions
- Table 17. MR28Device-Specific Register 1 (Status Register) Bit Descriptions
- Table 18. MR29Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions
- Table 19. MR30Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions
- Table 20. Operation Modes of LU6612
- Table 21. LU6612 Crystal Specifications
- Table 22 . Absolute Maximum Ratings
- Table 23 . Operating Conditions
- Table 24. dc Characteristics
- Table 25. MII Management Interface Timing (25 pF Load)
- Table 26. MII Data Timing (25 pF Load)
- Table 27. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK
- Table 28. Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK
- Table 29. Serial 10 Mbits/s Timing for TX_EN, RX/RY, and COL
- Table 30. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD (25 pF Load)
- Table 31. Serial 10 Mbits/s Timing for RX_CLK and TX_CLK (25 pF Load)
- Table 32. 100 Mbits/s MII Transmit Timing
- Table 33. 100 Mbits/s MII Receive Timing
- Contact Us
Data Sheet
July 2000
LU6612
FASTCAT
TM
Single-FET
for 10Base-T/100Base-TX
Features
10 Mbits/s Transceiver
s
Compatible with
IEEE
* 802.3u 10Base-T standard
for twisted-pair cable
s
Autopolarity detection and correction
s
Adjustable squelch level for extended wire line
length capability (2 levels)
s
Interfaces with
IEEE
802.3u media independent
interface (MII)
s
On-chip filtering eliminates the need for external fil-
ters
s
Half- and full-duplex operations
100 Mbits/s Transceiver
s
Compatible with
IEEE
802.3u MII (clause 22), PCS
(clause 23), PMA (clause 24), autonegotiation
(clause 28), and PMD (clause 25) specifications
s
Scrambler/descrambler bypass
s
Encoder/decoder bypass
s
3-statable MII in 100 Mbits/s mode
s
Selectable carrier sense signal generation (CRS
asserted during either transmission or reception in
half duplex, CRS asserted during reception only in
full duplex)
s
Selectable MII or 5-bit code group interface
s
Half- or full-duplex operations
s
On-chip filtering and adaptive equalization that
eliminates the need for external filters
General
s
Autonegotiation (
IEEE
802.3u clause 28):
-- Fast link pulse (FLP) burst generator
-- Arbitration function
-- Accepts preamble suppression
-- Operates up to 12.5 MHz
s
Supports the station management protocol and
frame format (clause 22):
-- Basic and extended registers
-- Supports next-page function
-- Accepts preamble suppression
-- Operates up to 12.5 MHz
s
Supports the following management functions via
pins if station management is unavailable:
-- Speed select
-- Encoder/decoder bypass
-- Scrambler/descrambler bypass
-- Full duplex
-- Autonegotiation
s
Supports half- and full-duplex operations
s
Provides four status signals: receive/transmit activ-
ity, full duplex, link integrity, and speed indication
s
Powerdown mode for 10 Mbits/s and 100 Mbits/s
operation
s
Loopback for 10 Mbits/s and 100 Mbits/s operation
s
0.35
m low-power CMOS technology
s
64-pin TQFP
s
Single 5 V power supply
*
IEEE
is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact
your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product.
Table of Contents
Contents
Page
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
2
Lucent Technologies Inc.
Features .................................................................................................................................................................... 1
10 Mbits/s Transceiver ............................................................................................................................................ 1
100 Mbits/s Transceiver .......................................................................................................................................... 1
General ................................................................................................................................................................... 1
Description................................................................................................................................................................. 4
Pin Information and Descriptions............................................................................................................................... 8
MII Station Management ......................................................................................................................................... 13
Basic Operations................................................................................................................................................... 13
MII Management Frames ...................................................................................................................................... 13
MODE Selection ...................................................................................................................................................... 23
Absolute Maximum Ratings (T
A
= 25
C) ................................................................................................................ 24
Electrical Characteristics ......................................................................................................................................... 24
Timing Characteristics (Preliminary)........................................................................................................................ 25
Outline Diagram....................................................................................................................................................... 34
64-Pin TQFP ......................................................................................................................................................... 34
Technical Document Types .....................................................................................................................................35
Ordering Information................................................................................................................................................ 36
List of Tables
Tables
Page
Table 1. MII/Serial Interface Pins (17) ..................................................................................................................... 9
Table 2. MII Management Pins (2) ........................................................................................................................ 10
Table 3. 10/100 Mbits/s Twisted-Pair (TP) Interface Pins (4) ................................................................................ 10
Table 4. Ground and Power Pins (21) ................................................................................................................... 11
Table 5. Miscellaneous Pins (20) .......................................................................................................................... 11
Table 5 . Miscellaneous Pins (20) (continued) ....................................................................................................... 12
Table 6. MII Management Frame Fields and Format ............................................................................................. 13
Table 7. MII Management Frame Descriptions ...................................................................................................... 13
Table 8. MII Management Registers (MR) ............................................................................................................. 14
Table 9. MR0--Control Register Bit Descriptions .................................................................................................. 15
Table 10. MR1--Status Register Bit Descriptions ................................................................................................. 16
Table 11. MR2, 3--PHY Identifier Registers (1 and 2) Bit Descriptions ................................................................ 17
Table 12. MR4--Autonegotiation Advertisement Register Bit Descriptions........................................................... 17
Table 13. MR5--Autonegotiation Link Partner (LP) Ability Register Bit Descriptions (Base_Page) ...................... 18
Table 14. MR5--Autonegotiation Link Partner (LP) Ability Register Bit Descriptions (Next_Page) ....................... 18
Table 15. MR6--Autonegotiation Expansion Register Bit Descriptions ................................................................. 19
Table 16. MR7--Next_Page Transmit Register Bit Descriptions............................................................................ 19
Table 17. MR28--Device-Specific Register 1 (Status Register) Bit Descriptions ................................................. 20
Table 18. MR29--Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions ........................................... 21
Table 19. MR30--Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions ............................................. 22
Table 20. Operation Modes of LU6612 ................................................................................................................. 23
Table 21. LU6612 Crystal Specifications ............................................................................................................... 23
Table 22 . Absolute Maximum Ratings .................................................................................................................. 24
Table 23 . Operating Conditions ............................................................................................................................ 24
Table 24. dc Characteristics................................................................................................................................... 24
Table 25. MII Management Interface Timing (25 pF Load) .................................................................................... 25
Table 26. MII Data Timing (25 pF Load) ................................................................................................................ 26
Table 27. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK ........................................................................ 28
Table of Contents
(continued)
Tables
(continued)
Page
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
Lucent Technologies Inc.
3
Table 28. Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK ........................................................... 28
Table 29. Serial 10 Mbits/s Timing for TX_EN, RX/RY, and COL........................................................................... 29
Table 30. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD (25 pF Load) ............... 30
Table 31. Serial 10 Mbits/s Timing for RX_CLK and TX_CLK (25 pF Load).......................................................... 31
Table 32. 100 Mbits/s MII Transmit Timing............................................................................................................. 32
Table 33. 100 Mbits/s MII Receive Timing ............................................................................................................. 33
List of Figures
Figures
Page
Figure 1. Functional Block Diagram: Device Overview ............................................................................................ 4
Figure 2. Functional Block Diagram: Device Detail .................................................................................................. 5
Figure 3. Typical Twisted-Pair (TP) Interface ........................................................................................................... 6
Figure 4. Onboard Universal Twisted-Pair Interface Circuit to Interchange Lucent and Quality
Semiconductor Inc. Parts .......................................................................................................................... 7
Figure 5. LU6612 Pinout........................................................................................................................................... 8
Figure 6. MDIO Input Timing .................................................................................................................................. 25
Figure 7. MDIO Output Timing ............................................................................................................................... 25
Figure 8. MDIO During TA (Turnaround) of a Read Transaction ........................................................................... 25
Figure 9. MII Timing Requirements for LU6612 ..................................................................................................... 27
Figure 10. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK ...................................................................... 28
Figure 11. Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK.......................................................... 28
Figure 12. Serial 10 Mbits/s Timing for TX_EN, RX/RY, and COL ......................................................................... 29
Figure 13. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD ................................... 30
Figure 14. Serial 10 Mbits/s Timing Diagram for RX_CLK and TX_CLK................................................................ 31
Figure 15. 100 Mbits/s MII Transmit Timing ........................................................................................................... 32
Figure 16. 100 Mbits/s MII Receive Timing ............................................................................................................ 33
4
4
Lucent Technologies Inc.
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
Description
The LU6612 is a single-channel, single-chip complete
transceiver designed specifically for dual-speed
10Base-T and 100Base-TX repeaters and switches.
LU6612 implements:
s
The 10Base-T transceiver function of
IEEE
802.3u.
s
The physical coding sublayer (PCS) of
IEEE
802.3u.
s
The physical medium attachment (PMA) of
IEEE
802.3u.
s
Autonegotiation of
IEEE
802.3u.
s
MII management of
IEEE
802.3u.
s
Physical medium dependent (PMD) of
IEEE
802.3u.
This device supports operation over category 3
unshielded twisted-pair (UTP) cable, according to
IEEE
802.3u 10Base-T specification, and over category 5,
Type 1, UTP and Type 1 shielded twisted-pair cable,
according to
IEEE
802.3u 100Base-X specification.
Figure 1 illustrates a functional overview of the LU6612
while Figure 2 details the functions. Figure 3 shows
how the LU6612 interfaces to the twisted pair.
5-5600(F).r1
Figure 1. Functional Block Diagram: Device Overview
10 Mbits/s TRANSCEIVER
AUTONEGOTIATION
PMA
TX
MUX
MANAGEMENT
PCS
DPLL
25 MHz
125 MHz
LSCLK
PMD
MII/SERIAL
INTERFACE
25 MHz
DRIVER AND FILTERS
DRIVER AND
FILTERS
20 MHz
TO/FROM
MAGNETICS
Lucent Technologies Inc.
5
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
Description
(continued)
5-5136(F).cr1
Figure 2. Functional Block Diagram: Device Detail
AUTONEGOTIATION
AND LINK MONITOR
TXD[3:0]
4B/5B
ENCODER
FAR-END
FAULT GEN
SCRAMBLER
PDT
DCRU
SD
PDR
DESCRAMBLER
ALIGNER
5B/4B
DECODER
FAR-END
FAULT DETECT
10 Mbits/s TRANSCEIVER
RXC
RXD
TXC
TEN
TXD
CLK20
MDC
MDIO
MII
RX/RY
TX STATE
MACHINE
SD
COLLISION
DETECT
SD
RX STATE
MACHINE
MII
TX_ER/TXD[4]
TX_EN
TXD[3:0]
TX_CLK
RX_CLK
RX_ER/RXD[4]
RX_DV
RXD[3:0]
COL
CRS
REF10
MANAGEMENT
25 MHz
125 MHz
LSCLK
PMD
TX
PMD
RX
SD
TX/TY
100 Mbits/s TRANSCEIVER
LC10 LS10
LC100
LS100
CARRIER
CIM
DETECT
RXERR_ST
CAR_STAT
MI
I
IN
T
E
R
F
A
C
E
SE
R
I
A
L
IN
TE
R
F
AC
E
DPLL
20 MH
Z
MA
N
A
GE
ME
N
T
INTE
RFA
C
E
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
6
Lucent Technologies Inc.
Description
(continued)
5-5433.i.r3
Figure 3. Typical Twisted-Pair (TP) Interface
LU6612
RJ-45
1
2
3
4
5
6
7
8
75
75
0.01
F
1:1
1:1
0.001
F
0.01
F
0.001
F
220
RX
RY
TX
TY
220
50
50
V
DD
75
0.01
F
75
63
64
50
50
9
8
0.01
F
Lucent Technologies Inc.
7
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
Description
(continued)
5-5433.j
Key:
L = Lucent's LU6612.
Q = Quality Semiconductor Inc. QS6612.
Figure 4. Onboard Universal Twisted-Pair Interface Circuit to Interchange Lucent and
Quality Semiconductor Inc. Parts
LU6612
RJ-45
1
2
3
4
5
6
7
8
L = Q = 1:1
L = 1:1; Q = 1.25:1
RX
RY
TX
TY
L = 50
VDD
63
64
8
9
VDD
Q = 0
L = OPEN
Q = 86.6
L = 0
Q = OPEN
L = 50
Q = 86.6
L = 220
Q = 39
L = 220
Q = OPEN
Q = 0.1
F
L = 0
Q = OPEN
L = Q = 75
L = Q = 75
L = Q = 75
L = Q = 75
Q = 1000 pF
L = 0.01
Q = 0.1
F
L = 0
Q = 20
L = 0
Q = 20
Q = 0
L = OPEN
L = 0
Q = OPEN
Q = 0
L = OPEN
L = 0.001
F
L = 0.001
F
Q = 60
L = 50
L = 50
Q = 0
L = 0
Q = 20
L = 0.01
F
L = 0.01
F
L = 0.01
F
Q = OPEN
QS6612
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
8
Lucent Technologies Inc.
Pin Information
5-5866.r2
Figure 5. LU6612 Pinout
V
CC
BG
ISET_100
GNDBG
LINKLED/PHYAD[0]
ACTLED/PHYAD[1]
V
CC
IOA
GNDIOA
TX
TY
GNDT
V
CC
T
CLKREF
GNDBT
V
CC
BT
TEST[0]
TEST[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GNDDIGB
TX_CLK
RX_ER/RXD[4]
RX_DV
RX_CLK
COL
CRS
GNDIOC
RXD[0]
RXD[1]
RXD[2]
RXD[3]
GNDDIGA
V
CC
DIGA
TXD[0]
TXD[1]
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P
H
YA
D[
4]
P
C
SE
N
TE
ST
[2
]
V
CC
PL
L
LSCLK
1
LSCLK
2
GNDP
LL
I
S
ET_10
MD
IO
MD
C
RES
E
T
RX_E
N
TX_E
R/
TX
D[
4]
TX
_EN
T
X
D[
3]
T
X
D[
2]
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
V
CC
DIG
B
MOD
E
[0
]
MOD
E
[1
]
MOD
E
[2
]
GNDIOB
V
CC
IO
B
FUDUP
LED/PHY
A
D[3]
S
P
E
E
DLE
D/
P
H
YA
D[
2]
B
G
REF[
1]
B
G
REF[
0]
GNDRE
C
V
CC
REC
V
CC
EQ
A
P
RY
RX
GNDE
QAP
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
LU6612
Lucent Technologies Inc.
9
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
Pin Information
(continued)
Pin Descriptions
Table 1. MII/Serial Interface Pins (17)
Signal
Type
Pin
Description
COL
O
43
Collision Detect. This signal signifies in half-duplex mode that a collision has
occurred on the network. COL is asserted high whenever there is transmit and
receive activity on the UTP media. COL is the logical AND of TX_EN and receive
activity, and is an asynchronous output. When SERIAL_SEL (register 30, bit 1) is high
and in 10Base-T mode, this signal indicates the jabber timer has expired. This signal
is held low in full-duplex mode.
CRS
O
42
Carrier Sense. When CRS_SEL (register 29, bit 10) is low, CRS is asserted high
when either the transmit or receive is nonidle. This signal remains asserted through-
out a collision condition. When CRS_SEL (register 29, bit 10) is high, CRS is
asserted on receive activity only.
RX_CLK
O
44
Receive Clock. 25 MHz clock output in 100 Mbits/s mode, 2.5 MHz output in
10 Mbits/s nibble mode, 10 MHz in 10 Mbits/s serial mode. RX_CLK has a worst-case
45/55 duty cycle. RX_CLK provides the timing reference for the transfer of RX_DV,
RXD, and RX_ER signals.
RXD[3:0]
O
37:40 Receive Data. 4-bit parallel data outputs that are synchronous to the falling edge of
RX_CLK. When RX_ER is asserted high in 100 Mbits/s mode, an error code will be
presented on RXD[3:0] where appropriate. The codes are as follows:
s
Packet errors: ERROR_CODES = 2h;
s
Link errors: ERROR_CODES = 3h (Packet and link error codes will only be
repeated if registers [29.9] and [29.8] are enabled.);
s
Premature end errors: ERROR_CODES = 4h;
s
Code errors: ERROR_CODES = 5h.
When SERIAL_SEL (register 30, bit 1) is active-high and 10 Mbits/s mode is selected,
RXD[0] is used for data output and RXD[3:1] are 3-stated.
RX_DV
O
45
Receive Data Valid. When this pin is high, it indicates the LU6612 is recovering and
decoding valid nibbles on RXD[3:0], and the data is synchronous with RX_CLK.
RX_DV is synchronous with RX_CLK. This pin is not used in serial 10 Mbits/s mode.
RX_ER/
RXD[4]
O
46
Receive Error. When high, RX_ER indicates the LU6612 has detected a coding error
in the frame presently being transferred. RX_ER is synchronous with RX_CLK. When
the encode/decode bypass (EDB) is selected through the MII management interface,
this output serves as the RXD[4] output. This pin is only valid when LU6612 is in
100 Mbits/s mode.
TX_CLK
O
47
Transmit Clock. 25 MHz clock output in 100 Mbits/s mode, 2.5 MHz output in
10 Mbits/s MII mode, 10 MHz output in 10 Mbits/s serial mode. TX_CLK provides tim-
ing reference for the transfer of the TX_EN, TXD, and TX_ER signals. These signals
are sampled on the rising edge of TX_CLK.
TXD[3:0]
I
31:34 Transmit Data. 4-bit parallel input synchronous with TX_CLK. When SERIAL_SEL
(register 30, bit 1) is active-high and 10 Mbits/s mode is selected, only TXD[0] is valid.
TX_EN
I
30
Transmit Enable. When driven high, this signal indicates there is valid data on
TXD[3:0]. TX_EN is synchronous with TX_CLK. When SERIAL_SEL
(register 30, bit 1) is active-high and 10 Mbits/s mode is selected, this pin indicates
there is valid data on TXD[0].
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
10
Lucent Technologies Inc.
Table 2. MII Management Pins (2)
Table 3. 10/100 Mbits/s Twisted-Pair (TP) Interface Pins (4)
TX_ER/
TXD[4]
I
29
Transmit Coding Error. When driven high, this signal causes the encoder to inten-
tionally corrupt the byte being transmitted across the MII (00100 will be transmitted).
When the encoder/decoder bypass bit is set, this input serves as the TXD[4] input.
When in 10 Mbits/s mode and SERIAL_SEL (register 30, bit 1) is active-high, this pin
is ignored.
RX_EN
I
28
Receive Enable. When this pin is high, the outputs (RXD[3:0], RX_ER, RX_CLK,
RX_DV) are enabled. This pin has an internal 100 k
pull-up resistor.
Signal
Type
Pin
Description
MDC
I
26
Management Data Clock. This is the timing reference for the transfer of data on
the MDIO signal. This signal may be asynchronous to RX_CLK and TX_CLK. The
standard clock rate is 2.5 MHz, the maximum clock rate is 12.5 MHz. When running
MDC above 6.25 MHz, MDC must be synchronous with LSCLK and have a setup time
of 15 ns and a hold time of 5 ns with respect to LSCLK.
MDIO
IO
25
Management Data Input/Output. This I/O is used to transfer control and status infor-
mation between LU6612 and the station management. Control information is driven by
the station management synchronous with MDC. Status information is driven by the
LU6612 synchronous with MDC.
Signal
Type
Pin
Description
RX
I
63
Received Data. Positive differential received 125 Mbaud MLT3 or 10 Mbaud
Manchester data from magnetics.
RY
I
62
Received Data. Negative differential received 125 Mbaud MLT3 or 10 Mbaud
Manchester data from magnetics.
TX
O
8
Transmit Data. Positive differential transmit 125 Mbaud MLT3 or 10 Mbaud
Manchester data to magnetics.
TY
O
9
Transmit Data. Negative differential transmit 125 Mbaud MLT3 or 10 Mbaud
Manchester data to magnetics.
Signal
Type
Pin
Description
Pin Information
(continued)
Table 1. MII/Serial Interface Pins (17) (continued)
Lucent Technologies Inc.
11
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
Pin Information
(continued)
Table 4. Ground and Power Pins (21)
Table 5. Miscellaneous Pins (20)
*
indicates there is an internal pull-up;
indicates there is an internal pull-down.
Signal
Type
Pin
Description
V
CC
IOA
PWR
6
Digital +5 V power supply for I/O
GNDIOA
PWR
7
Digital ground for I/O
V
CC
IOB
PWR
54
Digital +5 V power supply for I/O
GNDIOB
PWR
53
Digital ground for I/O
GNDIOC
PWR
41
Digital ground for I/O
V
CC
DIGA
PWR
35
Digital +5 V power supply for logic
GNDDIGA
PWR
36
Digital ground for logic
V
CC
DIGB
PWR
49
Digital +5 V power supply for logic
GNDDIGB
PWR
48
Digital ground for logic
V
CC
REC
PWR
60
Digital +5 V power supply for clock recovery circuit
GNDREC
PWR
59
Digital ground for clock recovery circuit
V
CC
PLL
PWR
20
Analog +5 V power supply for 10 MHz and 100 MHz PLL clock synthesizer
GNDPLL
PWR
23
Analog ground for 10 MHz and 100 MHz PLL clock synthesizer
V
CC
T
PWR
11
Analog +5 V power supply for transmitter
GNDT
PWR
10
Analog ground for transmitter
V
CC
EQAP
PWR
61
Analog +5 V power supply for equalizer and adaptation circuit
GNDEQAP
PWR
64
Analog ground for adaptation circuit.
V
CC
BG
PWR
1
Analog +5 V power supply for band-gap circuit
GNDBG
PWR
3
Analog ground band-gap circuit
V
CC
BT
PWR
14
Analog +5 V power supply for 10Base-T transmitter
GNDBT
PWR
13
Analog ground for 10Base-T transmitter
Signal
Type*
Pin
Description
LSCLK1
I
21
Local Symbol Clock. 25 MHz clock,
100 ppm, 40%--60% duty cycle. This input is
connected to one terminal of a 25 MHz crystal or an external 25 MHz clock source.
LSCLK2
O
22
Local Symbol Clock. 25 MHz crystal feedback. This output is connected to the
other terminal of a 25 MHz crystal or an external 25 MHz. If LSCLK1 is driven from
an external clock source, LSCLK2 is left unconnected.
LINKLED/
PHYAD[0]
I/O
4
Link LED. This pin indicates good link status. At powerup/reset, this pin is sampled
as input and to set the PHYAD[0] bit. If pulled high through a resistor, this pin will set
PHYAD[0] to a high or if pulled low through a resistor, will set PHYAD[0] to a zero.
When this pin is pulled high the LED output will be active-low, when pulled low the
LED output will be active-high.
ACTLED/
PHYAD[1]
I/O
5
Activity LED. This pin indicates transmit/receive activity. At powerup/reset, this pin
is sampled as input to set the PHYAD[1] bit. If pulled high through a resistor, this pin
will set PHYAD[1] to a high or if pulled low through a resistor, will set PHYAD[1] to a
zero. When this pin is pulled high the LED output will be active-low, when pulled low
the LED output will be active-high.
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
12
Lucent Technologies Inc.
Pin Information
(continued)
Table 5. Miscellaneous Pins (20) (continued)
Signal
Type*
Pin
Description
SPEED-
LED/
PHYAD[2]
I/O
56
Speed LED. This pin indicates the operating speed of LU6612:
s
LED is active when in 100 Mbits/s operation.
s
LED is not active when in 10 Mbits/s operation.
At powerup/reset, this pin is sampled as input and to set the PHYAD[2] bit. If pulled
high through a resistor, this pin will set PHYAD[2] to a high or if pulled low through a
resistor, will set PHYAD[2] to a zero. When this pin is pulled high, the LED output will
be active-low, when pulled low, the LED output will be active-high.
FUDU-
PLED/
PHYAD[3]
I/O
55
Full-Duplex LED. This pin indicates the operating mode of LU6612 and is only valid
when link is up:
s
LED is active when in full-duplex mode of operation.
s
LED is not active when in half-duplex mode of operation.
At powerup/reset, this pin is sampled as an input to set the PHYAD[3] bit. If pulled
high through a resistor, this pin will set PHYAD[3] to a high or if pulled low through a
resistor, will set PHYAD[3] to a zero. When this pin is pulled high, the LED output will
be active-low, when pulled low, the LED output will be active-high.
PHYAD[4]
I
17
PHYAD[4]. At powerup/reset, this pin is sampled as an input to set the PHYAD[4] bit.
If pulled high through a resistor, this pin will set PHYAD[4] to a high or if pulled low
through a resistor, will set PHYAD[4] to a zero.
This pin has an internal 100 k
pull-
up resistor.
MODE[2:0]
I
52:50 Mode Selection. These pins carry encoded signals that are latched into the LU6612
upon powerup/reset and define specific modes of operation: half/full duplex, autone-
gotiation enabled/disabled, and transceiver isolation. Refer to Table 20 for the various
modes and how various registers are affected. Pins [52:50] have internal 100 k
pull-
ups. If left floating, LU6612 will default to all capable, autonegotiation enabled mode.
TEST[0]
I
15
Test Enable Pin for Factory Testing. This pin has an internal 100 k
pull-down
resistor. The pin can be either left floating or tied down.
TEST[2:1]
I
19,
16
Test Enable Pin for Factory Testing. These two pins have internal 50 k
pull-down
resistors. These pins can either be left floating or tied low.
CLKREF
I
12
Clock Reference. Connect this pin to a 1 nF
10% capacitor to ground.
RESET
I
27
Full Chip Reset (Active-Low). Reset is an active-low signal. Reset must be
asserted low for at least five LSCLK cycles. The LU6612 will come out of reset after
400
s. LSCLK1 must remain running during reset.
BGREF[1:0]
I
57:58 Band-Gap Reference. Connect these pins to a 24.9 k
1% resistor to ground. The
parasitic load capacitance should be less than 15 pF.
ISET_100
I
2
Current Set 100 Mbits/s. An external reference resistor (24.9 k
) is placed from this
pin to ground to set the 100 Mbits/s TP driver transmit output level.
ISET_10
I
24
Current Set 10 Mbits/s. An external reference resistor (22.1 k
) is placed from this
pin to ground to set the 10 Mbits/s TP driver transmit output level.
PCSEN
I
18
PCS Enable (Active-Low). When this pin is active-low, the encoded 5-bit symbols
appear on RXD[4:0] and TXD[4:0]. When this pin high, 4-bit data appears on
RXD[3:0] and TXD[3:0]. When PCSEN is low, LU6612 bypasses the 4B5B encoder/
decoder, the align function, the scrambler/descrambler, and does not detect and gen-
erate J/K and R/T code groups at the start or end of frame. This pin has an internal
100 k
pull-up.
*
indicates there is an internal pull-up;
indicates there is an internal pull-down.
Lucent Technologies Inc.
13
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
MII Station Management
Basic Operations
The primary function of station management is to transfer control and status information about the LU6612 to a
management entity. This function is accomplished by the MDC clock input, which has a maximum frequency of
12.5 MHz, along with the MDIO pin. The management interface (MII) uses MDC and MDIO to physically transport
information between the PHY and the station management entity.
A specific set of registers and their contents (described in Table 8) defines the nature of the information transferred
across this interface. Frames transmitted on the MII management interface will have the frame structure shown in
Table 6. The order of bit transmission is from left to right. Note that reading and writing of the management register
must be completed without interruption.
MII Management Frames
The fields and format for management frames are described in the following tables.
Table 6. MII Management Frame Fields and Format
Table 7. MII Management Frame Descriptions
Read/Write
(R/W)
Pre
ST
OP
PHYADD
REGAD
TA
DATA
Idle
R
1 . . . 1
01
10
AAAAA
RRRRR
Z0
DDDDDDDDDDDDDDDD
Z
W
1 . . . 1
01
01
AAAAA
RRRRR
10
DDDDDDDDDDDDDDDD
Z
Field
Description
Pre
Preamble. The preamble is a series of 32 1s. The LU6612 will accept frames with no preamble.
This is indicated by a 1 in register 1, bit 6.
ST
Start of Frame. The start of frame is indicated by a 01 pattern.
OP
Operation Code. The operation code for a read transaction is 10. The operation code for a write
transaction is 01.
PHYADD
PHY Address. The PHY address is 5 bits, allowing for 32 unique addresses. The first PHY address
bit transmitted and received is the MSB of the address. A station management entity, which is
attached to multiple PHY entities, must have prior knowledge of the appropriate PHY address for
each entity. The address 00000 is the broadcast address. This address will produce a match
regardless of the local address.
REGAD
Register Address. The register address is 5 bits, allowing for 32 unique registers within each PHY.
The first register address bit transmitted and received is the MSB of the address.
TA
Turnaround. The turnaround time is a 2-bit time spacing between the register address field and the
data field of a frame to avoid drive contention on MDIO during a read transaction. During a write to
the LU6612, these bits are driven to a 10 by the station. During a read, the MDIO is not driven dur-
ing the first bit time and is driven to a 0 by the LU6612 during the second bit time.
DATA
Data. The data field is 16 bits. The first bit transmitted and received is bit 15 of the register being
addressed.
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
14
Lucent Technologies Inc.
MII Station Management
(continued)
Register Overview
The MII management 16-bit register (MR) set is implemented as described in Table 8 below.
Table 8. MII Management Registers (MR)
Register
Address
Symbol
Name
Default
(Hex Code)
0
MR0
Control Register
3000
1
MR1
Status Register
7849
2
MR2
PHY Identifier Register 1
0180
3
MR3
PHY Identifier Register 2
7641
4
MR4
Autonegotiation Advertisement Register
01E1
5
MR5
Autonegotiation Link Partner Ability Register (Base_Page)
0000
5
MR5
Autonegotiation Link Partner Ability Register (Next_Page)
--
6
MR6
Autonegotiation Expansion Register
0000
7
MR7
Next-Page Transmit Register
0000
8--27
MR8--MR27
Reserved
0000
28
MR28
Device Specific Register 1
0000
29
MR29
Device Specific Register 2
1000
30
MR30
Device Specific Register 3
0000
Lucent Technologies Inc.
15
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
MII Station Management
(continued)
This section provides a detailed discussion of each management register and its bit definitions.
Table 9. MR0--Control Register Bit Descriptions
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read, W = write, NA = not applicable.
Bit
1
Type
2
Description
0.15 (SW_RESET)
R/W
Reset. Setting this bit to a 1 will reset the LU6612. All registers will be set to
their default state. This bit is self-clearing. The default is 0.
0.14 (LOOPBACK)
R/W
Loopback. When this bit is set to 1, no data transmission will take place on the
media. Any receive data will be ignored. The loopback signal path will contain
all circuitry up to, but not including, the PMD. The autonegotiation must be
turned off, before loopback can be initiated, transmit data can be started 2 ms
after loopback is initiated. The default value is a 0.
0.13 (SPEED100)
R/W
Speed Selection. The value of this bit reflects the current speed of operation
(1 = 100 Mbits/s; 0 = 10 Mbits/s). This bit will only affect operating speed when
the autonegotiation enable bit (register 0, bit 12) is disabled (0). This bit is
ignored when autonegotiation is enabled (register 0, bit 12). The bit is set high
when MODE[2:0] is 010 or 011 or 100. The default is 1.
0.12 (NWAY_ENA)
R/W
Autonegotiation Enable. The autonegotiation process will be enabled by set-
ting this bit to a 1. This bit overrides SPEED100 bit (register 0, bit 13) and
FULL_DUP bit (register 0, bit 8). This bit is set high when MODE[2:0] is 100 or
111. Autonegotiation must be disabled before loopback can be initiated. The
default state is a 1.
0.11 (PWRDN)
R/W
Powerdown. The LU6612 may be placed in a low-power state by setting this
bit to a 1, both the 10 Mbits/s transceiver and the 100 Mbits/s transceiver will
be powered down. While in the powerdown state, the LU6612 will respond to
management transactions. The default state is a 0.
0.10 (ISOLATE)
R/W
Isolate. When this bit is set to a 1, the MII outputs will be brought to the high-
impedance state. The default state is a 0.
0.9 (REDONWAY)
R/W
Restart Autonegotiation. Normally, the autonegotiation process is started at
powerup. The process may be restarted by setting this bit to a 1. The default
state is a 0. The NWAYDONE bit (register 1, bit 5) is reset when this bit goes to
a 1. This bit is self-cleared when autonegotiation restarts.
0.8 (FULL_DUP)
R/W
Duplex Mode. This bit reflects the mode of operation (1 = full duplex; 0 = half
duplex). This bit is ignored when the autonegotiation enable bit (register 0,
bit 12) is enabled. The default state is a 0. This bit is set as a 1 during powerup/
reset, when MODE[2:0] is 001 or 011.
0.7 (COLTST)
R/W
Collision Test. When this bit is set to a 1, the LU6612 will assert the COL sig-
nal in response to TX_EN. This bit should only be set when in loopback mode.
0.6:0 NA
Reserved.
All bits will read 0.
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
16
Lucent Technologies Inc.
MII Station Management
(continued)
Table 10. MR1--Status Register Bit Descriptions
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read.
Bit
1
Type
2
Description
1.15 (T4ABLE)
R
100Base-T4 Ability. This bit will always be a 0.
0: Not able
1: Able
1.14 (TXFULDUP)
R
100Base-TX Full-Duplex Ability. This bit will always be a 1.
0: Not able
1: Able
1.13 (TXHAFDUP)
R
100Base-TX Half-Duplex Ability. This bit will always be a 1.
0: Not able
1: Able
1.12 (ENFULDUP)
R
10Base-T Full-Duplex Ability. This bit will always be a 1.
0: Not able
1: Able
1.11 (ENHAFDUP)
R
10Base-T Half-Duplex Ability. This bit will always be a 1.
0: Not able
1: Able
1.10:7
R
Reserved. All bits will read as a 0.
1.6 (NO_PA_OK)
R
Suppress Preamble. This bit is set to a 1, indicating that the LU6612 accepts
management frames with the preamble suppressed. (This function is not sup-
ported by QS6611.)
1.5 (NWAYDONE)
R
Autonegotiation Complete. When this bit is a 1, it indicates the autonegotiation
process has been completed. The contents of registers MR4, MR5, MR6, and
MR7 are now valid. The default value is a 0. This bit is reset when autonegotia-
tion is started.
1.4 (REM_FLT)
R
Remote Fault. When this bit is a 1, it indicates a remote fault has been detected.
This bit will remain set until cleared by reading the register. The default is a 0.
1.3 (NWAYABLE)
R
Autonegotiation Ability. When this bit is a 1, it indicates the ability to perform
autonegotiation. The value of this bit is always a 1.
1.2 (LSTAT_OK)
R
Link Status. When this bit is a 1, it indicates a valid link has been established.
This bit has a latching function: a link failure will cause the bit to clear and stay
cleared until it has been read via the management interface.
1.1 (JABBER)
R
Jabber Detect. This bit will be a 1 whenever a jabber condition is detected. It will
remain set until it is read, and the jabber condition no longer exists.
1.0 (EXT_ABLE)
R
Extended Capability. This bit indicates that the LU6612 supports the extended
register set (MR2 and beyond). It will always read a 1.
Lucent Technologies Inc.
17
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
MII Station Management
(continued)
Table 11. MR2, 3--PHY Identifier Registers (1 and 2) Bit Descriptions
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read.
Table 12. MR4--Autonegotiation Advertisement Register Bit Descriptions
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read, W = write.
Bit
1
Type
2
Description
2.15:0 (OUI[3:18])
R
Organizationally Unique Identifier. The third through the 24th bits of the
OUI assigned to the PHY manufacturer by the
IEEE
are to be placed in bits
2.15:0 and 3.15:10. The value for bits 15:0 of register 2 is 0180h.
3.15:10 (OUI[19:24])
R
Organizationally Unique Identifier. The remaining 6 bits of the OUI. The
value for bits 15:10 of register 3 is 1Dh.
3.9:4 (MODEL[5:0])
R
Model Number. 6-bit model number of the device. The model number is 12
decimal.
3.3:0 (VERSION[3:0])
R
Revision Number. The value of the present revision number. The value is
0001b for the first version.
Bit
1
Type
2
Description
4.15 (NEXT_PAGE)
R/W
Next Page. The next page function is activated by setting this bit to a 1.
This will allow the exchange of arbitrary pieces of data. Data is carried by
optional next pages of information. (This function is not supported by
QS6611.)
4.14 (ACK)
R/W
Acknowledge. This bit is written to a logic zero and ignored on read.
4.13 (REM_FAULT)
R/W
Remote Fault. When set to 1, the LU6612 indicates to the link partner a
remote fault condition.
4.12:10 (PAUSE)
R/W
Pause. When set to 1, indicates that the LU6612 wishes to exchange flow
control information with its link partner.
4.9 (100BASET4)
R/W
100Base-T4. This bit should always be set to a 0.
4.8 (100BASET_FD)
R/W
100Base-TX Full Duplex. If written to 1, autonegotiation will advertise that
the LU6612 is capable of 100Base-TX full-duplex operation. This bit is set
high when MODE[2:0] is 111.
4.7 (100BASETX)
R/W
100Base-TX. If written to 1, autonegotiation will advertise that the LU6612
is capable of 100Base-TX operation.
4.6 (10BASET_FD)
R/W
10Base-T Full Duplex. If written to 1, autonegotiation will advertise that the
LU6612 is capable of 10Base-T full-duplex operation. This bit is set high
when MODE[2:0] is 111.
4.5 (10BASET)
R/W
10Base-T. If written to 1, autonegotiation will advertise that the LU6612 is
capable of 10Base-T operation. This bit is set high when MODE[2:0] is 111.
4.4:0 (SELECT)
R/W
Selector Field. Reset with the value 00001 for
IEEE
802.3.
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
18
Lucent Technologies Inc.
MII Station Management
(continued)
Table 13. MR5--Autonegotiation Link Partner (LP) Ability Register Bit Descriptions (Base_Page)
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read.
Table 14. MR5--Autonegotiation Link Partner (LP) Ability Register Bit Descriptions (Next_Page)
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read.
Bit
1
Type
2
Description
5.15 (LP_NEXT_PAGE)
R
Link Partner Next Page. When this bit is set to 1, it indicates that the link
partner wishes to engage in next page exchange.
5.14 (LP_ACK)
R
Link Partner Acknowledge. When this bit is set to 1, it indicates that the link
partner has successfully received at least three consecutive and consistent
FLP bursts.
5.13 (LP_REM_FAULT)
R
Link Partner Remote Fault. When this bit is set to 1, it indicates that the link
partner has a fault.
5.12:10
R
Reserved. These bits are reserved.
5.9 (LP_100BASET4)
R
Link Partner 100Base-T4. When this bit is set to 1, it indicates that link part-
ner is capable of 100Base-T4 operation.
5.8 (LP_100BASET_FD)
R
Link Partner 100Base-TX Full Duplex. When this bit is set to 1, it indicates
that link partner is capable of 100Base-TX full-duplex operation.
5.7 (LP_100BASETX)
R
Link Partner 100Base-TX. When this bit is set to 1, it indicates that link part-
ner is capable of 100Base-TX operation.
5.6 (LP_10BASET_FD)
R
Link Partner 10Base-T Full Duplex. When this bit is set to 1, it indicates that
link partner is capable of 10Base-T full-duplex operation.
5.5 (LP_10BASET)
R
Link Partner 10Base-T. When this bit is set to 1, it indicates that link partner
is capable of 10Base-T operation.
5.4:0 (LP_SELECT)
R
Selector Field. This field contains the type of message sent by the link part-
ner. For
IEEE
802.3 compliant link partners, this field should read 00001.
Bit
1
Type
2
Description
5.15 (LP_NEXT_PAGE)
R
Next Page. When this bit is set to a logic 0, it indicates that this is the last
page to be transmitted. A logic 1 indicates that additional pages will follow.
5.14 (LP_ACK)
R
Acknowledge. When this bit is set to a logic 1, it indicates that the link part-
ner has successfully received its partner's link code word.
5.13 (LP_MES_PAGE)
R
Message Page. This bit is used by the Next_Page function to differentiate a
Message Page (logic one) from an unformatted page (logic zero).
5.12 (LP_ACK2)
R
Acknowledge 2. This bit is used by Next_Page function to indicate that a
device has the ability to comply with the message (logic one) or not (logic
zero).
5.11 (LP_TOGGLE)
R
Toggle. This bit is used by the arbitration function to ensure synchronization
with the link partner during next page exchange. Logic 0 indicates that the
previous value of the transmitted link code word was logic 1. Logic 1 indicates
that the previous value of the transmitted link code word was logic 0.
5.10:0 (MCF)
R
Message/Unformatted Code Field. With these 11 bits, there are 2048 possi-
ble messages. Message code field definitions are described in annex 28C of
the
IEEE
802.3u standard.
Lucent Technologies Inc.
19
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
MII Station Management
(continued)
Table 15. MR6--Autonegotiation Expansion Register Bit Descriptions
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read, LH = latched high.
Table 16. MR7--Next_Page Transmit Register Bit Descriptions
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read, W = write.
Bit
1
Type
2
Description
6.15:5
R
Reserved.
6.4 (PAR_DET_FAULT)
R/LH
Parallel Detection Fault. When this bit is set to 1, it indicates that a fault
has been detected in the parallel detection function. This fault is due to more
than one technology detecting concurrent link conditions. This bit can only
be cleared by reading this register.
6.3
(LP_NEXT_PAGE_ABLE)
R
Link Partner Next Page Able. When this bit is set to 1, it indicates that the
link partner supports the next page function.
6.2 (NEXT_PAGE_ABLE)
R
Next Page Able. This bit is set to 1, indicating that this device supports the
next page function.
6.1 (PAGE_REC)
R/LH
Page Received. When this bit is set to 1, it indicates that a next page has
been received.
6.0 (LP_NWAY_ABLE)
R
Link Partner Autonegotiation Capable. When this bit is set to 1, it indi-
cates that the link partner is autonegotiation capable.
Bit
1
Type
2
Description
7.15 (NEXT_PAGE)
R/W
Next Page. This bit indicates whether or not this is the last next page to be trans-
mitted. When this bit is 0, it indicates that this is the last page. When this bit is 1, it
indicates there is an additional next page.
7.14 (ACK)
R
Acknowledge. This bit is the acknowledge bit from the link code word.
7.13 (MESSAGE)
R/W
Message Page. This bit is used to differentiate a message page from an unfor-
matted page. When this bit is 0, it indicates an unformatted page. When this bit is
1, it indicates a formatted page.
7.12 (ACK2)
R/W
Acknowledge 2. This bit is used by the next page function to indicate that a
device has the ability to comply with the message. Acknowledge 2 will be set as
follows:
s
When this bit is 0, it indicates the device cannot comply with the message.
s
When this bit is 1, it indicates the device will comply with the message.
7.11 (TOGGLE)
R
Toggle. This bit is used by the arbitration function to ensure synchronization with
the link partner during next page exchange. This bit will always take the opposite
value of the toggle bit in the previously exchanged link code word:
s
If the bit is a logic 0, the previous value of the transmitted link code word was a
logic 1.
s
If the bit is a 1, the previous value of the transmitted link code word was a 0.
The initial value of the toggle bit in the first next page transmitted is the inverse of
the value of bit 11 in the base link code word and, therefore, may assume a value
of 1 or 0.
7.10:0 (MCF)
R/W
Message/Unformatted Code Field. With these 11 bits, there are 2048 possible
messages. Message code field definitions are described in annex 28C of the
IEEE
802.3u standard.
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
20
Lucent Technologies Inc.
MII Station Management
(continued)
Table 17. MR28--Device-Specific Register 1 (Status Register) Bit Descriptions
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read, LH = latched high.
Bit
1
Type
2
Description
28.15:9 (R28[15:9])
R
Unused. Read as 0.
28.8 (BAD_FRM)
R/LH
Bad Frame. If this bit is a 1, it indicates a packet has been received without an
SFD. This bit is only valid in 10 Mbits/s mode.
This bit is latching high and will only clear after it has been read or the device has
been reset. The default is 0.
28.7 (CODE)
R/LH
Code Violation. When this bit is a 1, it indicates a Manchester code violation has
occurred. The error code will be output on the RXD lines. Refer to Table 1 for a
detailed description of the RXD pin error codes. This bit is only valid in 10 Mbits/s
mode.
This bit is latching high and will only clear after it has been read or the device has
been reset. The default is 0.
28.6 (APS)
R
Autopolarity Status. When register 30, bit 3 is set and this bit is a 1, it indicates
the LU6612 has detected and corrected a polarity reversal on the twisted pair.
If the APF_EN bit (register 30, bit 3) is set, the reversal will be corrected inside the
LU6612. This bit is not valid in 100 Mbits/s operation. The default is 0.
28.5 (DISCON)
R/LH
Disconnect. If this bit is a 1, it indicates a disconnect. This bit will latch high until
read. This bit is only valid in 100 Mbits/s mode. The default is 0.
28.4 (UNLOCKED)
R/LH
Unlocked. Indicates that the TX scrambler lost lock. This bit will latch high until
read. This bit is only valid in 100 Mbits/s mode. The default is 0.
28.3 (RXERR_ST)
R/LH
RX Error Status. Indicates a false carrier. This bit will latch high until read. This
bit is only valid in 100 Mbits/s mode. The default is 0.
28.2 (FRC_JAM)
R/LH
Force Jam. This bit will latch high until read. This bit is only valid in 100 Mbits/s
mode. The default is 0.
28.1 (LNK100UP)
R
Link Up 100. This bit, when set to a 1, indicates a 100 Mbits/s transceiver is up
and operational. The default is 0.
28.0 (LNK10UP)
R
Link Up 10. This bit, when set to a 1, indicates a 10 Mbits/s transceiver is up and
operational. The default is 0.
Lucent Technologies Inc.
21
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
MII Station Management
(continued)
Table 18. MR29--Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read, W = write.
Bit
1
Type
2
Description
29.15 (LOCALRST)
R/W
Management Reset. This is the local management reset bit. Writing a logic 1 to
this bit will cause the lower 16 registers and registers 28 and 29 to be reset to
their default values. This bit is self-clearing. The default is 0.
29.14 (RST1)
R/W
Generic Reset 1. This register is used for manufacture test only. The default is 0.
29.13 (RST2)
R/W
Generic Reset 2. This register is used for manufacture test only. The default is 0.
29.12 (100OFF)
R/W
100 Mbits/s Transmitter Off. When this bit is set to 0, it forces RX low and RY
high. This bit defaults to 1.
29.11
R/W
Reserved. Program to zero.
29.10 (CRS_SEL)
R/W
Carrier Sense Select. CRS will be asserted on receive only when this bit is set to
a 1. If this bit is set to logic 0, CRS will be asserted on receive or transmit. The
default is 0.
29.9 (LINK_ERR)
R/W
Link Error Indication. When this bit is a 1, a link error code will be reported on
RXD[3:0] of the LU6612 when RX_ER is asserted on the MII. The specific error
codes are listed in the RXD pin description. If it is 0, it will disable this function.
The default is 0.
29.8 (PKT_ERR)
R/W
Packet Error Indication Enable. When this bit is a 1, a packet error code, which
indicates that the scrambler is not locked, will be reported on RXD[3:0] of the
LU6612 when RX_ER is asserted on the MII. When this bit is 0, it will disable this
function. The default is 0.
29.7 (RESERVED)
R/W
Reserved. This bit must remain as a zero. The default is 0.
29.6 (EDB)
R/W
Encoder/Decoder Bypass. When this bit is set to 1, the 4B/5B encoder and
5B/4B decoder function will be disabled. The default is a zero. At powerup/reset, if
PCSEN
is strapped low, then this bit is set to a 1. The default is 0.
29.5 (SAB)
R/W
Symbol Aligner Bypass. When this bit is set to 1, the aligner function will be dis-
abled. The default is 0.
29.4 (SDB)
R/W
Scrambler/Descrambler Bypass. When this bit is set to 1, the scrambling/
descrambling functions will be disabled. The default is a zero. At powerup/reset, if
PCSEN
is strapped low, then this bit is set to a 1. The default is 0.
29.3 (CARIN_EN)
R/W
Carrier Integrity Enable. When this bit is set to a 1, carrier integrity is enabled.
(This function is not supported by QS6611.) The default is 0.
29.2 (JAM_COL)
R/W
Jam Enable. When this bit is a 1, it enables JAM associated with carrier integrity
to be ORed with COL. The default is 0.
29.1 (RESERVED)
R/W
Reserved. This bit must remain as a zero. The default is 0.
29.0 (RESERVED)
R/W
Reserved. This bit must remain as a zero. The default is 0.
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
22
Lucent Technologies Inc.
MII Station Management
(continued)
Table 19. MR30--Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read, W = write.
Bit
1
Type
2
Description
30.15:6 (R30[15:6])
R/W
Unused. Read as 0.
30.5 (HBT_EN)
R/W
Heartbeat Enable. When this bit is a 1, the heartbeat function will be
enabled. Valid in 10 Mbits/s mode only. The default is 0.
30.4 (ELL_EN)
R/W
Extended Line Length Enable. When this bit is a 1, the receive squelch lev-
els are reduced from a nominal 435 mV to 350 mV, allowing reception of sig-
nals with a lower amplitude. Valid in 10 Mbits/s mode only. The default is 0.
30.3 (APF_EN)
R/W
Autopolarity Function Enable. When this bit is a 1 and the LU6612 is in
10 Mbits/s mode, the autopolarity function will determine if the TP link is wired
with a polarity reversal. If there is a polarity reversal, the LU6612 will assert
the APS bit (register 28, bit 6) and correct the polarity reversal. If this bit is a 0
and the device is in 10 Mbits/s mode, the reversal will not be corrected. The
default is 0.
30.2 (REF_SEL)
R/W
Reference Select. When this bit is a 1, the external 10 MHz reference of pin
REF10 is used for phase alignment. This bit defaults to a 0.
30.1 (SERIAL _SEL)
R/W
Serial Select. When this bit is set to a 1, 10 Mbits/s serial mode will be
selected. When the LU6612 is in 100 Mbits/s mode, this bit will be ignored.
The default is 0.
30.0 (ENA_NO_LP)
R/W
No Link Partner Mode. Setting this bit to a 1 will allow 10 Mbits/s operation
with link pulses disabled. If the LU6612 is configured for 100 Mbits/s opera-
tion, setting this bit will not affect operation. The default is 0.
Lucent Technologies Inc.
23
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
MODE Selection
LU6612 can be forced to operate in specific operating modes. This is achieved by configuring the MODE pins to
the appropriate values at powerup/reset. The strapping options of the MODE pins are latched on reset to set the
default values of various registers. The values can be modified by writing into the registers. The MODE[2:0] pins
have 100 k
internal pull-ups. If MODE[2:0] are left floating, LU6612 will default to all capable, autonegotiation
enabled mode.
The different modes of operation of LU6612 and the register bits affected are presented in the following table.
Table 20. Operation Modes of LU6612
Table 21. LU6612 Crystal Specifications
MODE
[2:0]
Definition
Register.Bit
0.8
0.10 0.12 0.13
4.5
4.6
4.8
000
10Base-T, half-duplex with autonegotiation disabled
0
0
0
0
1
0
1
001
10Base-T, full-duplex with autonegotiation disabled
1
0
0
0
1
1
1
010
100Base-TX, half-duplex with autonegotiation disabled
0
0
0
1
0
0
1
011
100Base-TX, full-duplex with autonegotiation disabled
1
0
0
1
0
0
1
100
Advertise 100Base-TX, half-duplex autonegotiation enabled
0
0
1
1
0
0
0
101
Reserved
--
--
--
--
--
--
--
110
Isolate MII
0
1
0
1
1
1
0
111
All capable, autonegotiation enabled
0
0
1
1
1
1
1
Parameter
Requirement
Type
Quartz Fundamental Mode
Frequency
25 MHz
Stability
25 ppm, 0--70 C
Shunt Capacitor
7 pF
Load Capacitor
20 pF
Series Resistance
<30
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
24
Lucent Technologies Inc.
Absolute Maximum Ratings
(T
A
= 25
C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Table 22. Absolute Maximum Ratings
Table 23. Operating Conditions
* Typical power dissipations are specified at 5.0 V and 25 C. This is the power dissipated by the LU6612 transmitting over 100 meters of cable.
Electrical Characteristics
The following specifications apply for V
DD
= 5 V
5%.
Table 24. dc Characteristics
Parameter
Symbol
Min
Max
Unit
Ambient Operating Temperature
T
A
0
70
C
Storage Temperature
T
stg
40
125
C
Voltage on Any Pin with Respect to Ground
--
0.5
V
DD
+ 0.5
V
Maximum Supply Voltage
--
--
5.5
V
Parameter
Symbol
Min
Typ*
Max
Unit
Operating Supply Voltage
--
4.75
5.0
5.25
V
Power Dissipation:
100 Mbits/s TX
10 Mbits/s
Autonegotiating
P
D
P
D
P
D
--
--
--
1.4
1.0
1.0
1.6
1.35
--
W
W
mW
Parameter
Symbol
Min
Typ
Max
Unit
TTL Inputs:
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Leakage Current
V
IH
V
IL
I
IH
I
IL
I
L
2.0
--
--
--
--
--
--
--
--
--
--
0.8
50
400
50
V
V
A
A
A
TTL Outputs:
Output High Voltage
Output Low Voltage
Output Short-circuit Current
V
OH
V
OL
I
SC
2.4
--
15
--
--
--
--
0.45
85
V
V
mA
10 Mbits/s Twisted Pair: Input Voltage
V
DIFF
0.35
--
2.0
V
100 Mbits/s Twisted Pair: Input Voltage
V
DIFF
--
--
1.5
V
10 Mbits/s Twisted Pair: Output Current
V
DIFF
45
50
55
mA
100 Mbits/s Twisted Pair: Output Current
V
DIFF
19
20
21
mA
Lucent Technologies Inc.
25
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
Timing Characteristics (Preliminary)
Table 25. MII Management Interface Timing (25 pF Load)
* When operating MDC above 6.25 MHz, MDC must be synchronous with LSCLK and have a setup time of 15 ns and a hold time of 5 ns,
with respect to LSCLK.
5-4959(F).a
Figure 6. MDIO Input Timing
5-4960(F).c
Figure 7. MDIO Output Timing
5-5312(F).r1
Note: MDIO turnaround (TA) time is a 2-bit time spacing between the register address field, and the data field of a frame to avoid drive conten-
tion on MDIO during a read transaction. During a write to the LU6612, these bits are driven to a 10 by the station. During a read, the
MDIO is not driven during the first bit time and is driven to a 0 by the LU6612 during the second bit time.
Figure 8. MDIO During TA (Turnaround) of a Read Transaction
Name
Parameter
Min
Typ
Max
Unit
t1
MDIO Valid to Rising Edge of MDC (setup)
10
--
--
ns
t2
Rising Edge of MDC to MDIO Invalid (hold)
10
--
--
ns
t3
MDC Falling Edge to MDIO Valid (prop. delay)
0
--
40
ns
t4
MDC High*
--
200
--
ns
t5
MDC Low*
40
200
--
ns
t6
MDC Period*
80
400
--
ns
MDC
MDIO
t1
t2
MDC
MDIO
t5
t4
t6
t3
MDC
MDIO
< R >
< Z >
< O >
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
26
Lucent Technologies Inc.
Timing Characteristics (Preliminary)
(continued)
Table 26. MII Data Timing (25 pF Load)
* 100 Mbits/s only.
Name
Parameter
Min
Typ
Max
Unit
t1
RXD[3:0], RX_ER, RX_DV, Valid to RX_CLK High
10/100
--
--
ns
t2
RX_CLK High to RXD[3:0], RX_DV, RX_ER Invalid
10/100
--
--
ns
t3
RX_CLK High
14/180
--
26/220
ns
t4
RX_CLK Low
14/180
--
26/220
ns
t5
RX_CLK Period
--
40
--
ns
t6
TX_CLK High
14/180
--
26/220
ns
t7
TX_CLK Low
14/180
--
26/220
ns
t8
TX_CLK Period
--
40
--
ns
t9
TXD[3:0], TX_EN, TX_ER, Setup to TX_CLK
15/140
--
--
ns
t10
TXD[3:0], TX_EN, TX_ER, Hold to TX_CLK
0/0
--
--
ns
t11
TXD[3:0], TX_EN, TX_ER Setup to LSCLK*
10
--
--
ns
t12
TXD[3:0], TX_EN, TX_ER, Hold to LSCLK*
0
--
--
ns
t13
First Bit of J on RX/RY While Transmitting Data to COL
Assert (half-duplex mode)
--
--
170
ns
t14
First Bit of T Received on RX/RY While Transmitting to COL
Deasserted (half-duplex mode)
--
--
210
ns
Lucent Technologies Inc.
27
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
Timing Characteristics (Preliminary)
(continued)
5-5432(F).cr1
Figure 9. MII Timing Requirements for LU6612
RX/RY
t13
COL
1st BIT OF J
t7
TX_CLK
TXD[3:0]
t6
t8
RX_CLK
RXD[3:0]
t1
t2
TX_EN
t3
t4
t5
RX_DV
RX_ER
TX_ER
t9
t10
LSCLK
TXD[3:0]
t11
TX_EN
TX_ER
t12
1st BIT OF T
t14
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
28
Lucent Technologies Inc.
Timing Characteristics (Preliminary)
(continued)
Table 27. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK
5-5293(F).mr1
Figure 10. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK
Table 28. Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK
5-5293(F).nr1
Figure 11. Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK
Name
Parameter
Min
Max
Unit
t15
RX/RY Activity to CRS Assertion
40
500
ns
t16
RX/RY Activity to RX_CLK Valid
800
2300
ns
t17
IDL to CRS Deassertion
200
550
ns
t18
Dead Signal to CRS Deassertion
400
1000
ns
Name
Parameter
Min
Max
Unit
t19
TX_EN Asserted to Transmit Pair Activity
50
400
ns
t20
TX_EN Asserted to CRS Asserted Due to Internal Loopback
5
1900
ns
t21
TX_EN Asserted to RX_CLK Valid Due to Internal Loopback
1000
1700
ns
t22
TX_EN Deasserted to IDL Transmission
50
300
ns
t23
IDL Pulse Width
250
350
ns
RX/RY
CRS
(RECEIVE--START OF PACKET)
(RECEIVE--END OF PACKET)
(RECEIVE--DEAD SIGNAL)
(NOT IDL)
IDL
t15
t17
t16
t18
RX_CLK
TX/TY
CRS
(TRANSMIT--START OF PACKET)
(TRANSMIT--END OF PACKET)
IDL
t19
t22
t20
t21
t23
TX_EN
RX_CLK
Lucent Technologies Inc.
29
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
Timing Characteristics (Preliminary)
(continued)
Table 29. Serial 10 Mbits/s Timing for TX_EN, RX/RY, and COL
5-5293(F).l
Figure 12. Serial 10 Mbits/s Timing for TX_EN, RX/RY, and COL
Name
Parameter
Min
Max
Unit
t24
Time to Assert COL; LU6612 Is Transmitting; Receive Activity Starts
40
400
ns
t25
Time to Deassert COL; LU6612 Is Transmitting; Receive Activity Ceases
300
900
ns
t26
Time to Assert COL; LU6612 Is Receiving; Transmit Activity Starts
5
400
ns
t27
Time to Deassert COL; LU6612 Is Receiving; Transmit Activity Ceases
5
900
ns
t28
COL Pulse Width
100
--
ns
RX/RY
COL
(TRANSMITTING--RECEIVE COLLISION DETECTED)
(RECEIVING--TRANSMIT COLLISON DETECTED)
IDL
t24
t25
t26
t27
t28
TX_EN
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
30
Lucent Technologies Inc.
Timing Characteristics (Preliminary)
(continued)
Table 30. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD (25 pF Load)
5-2736(F).d
Figure 13. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD
Name
Parameter
Min
Max
Unit
t29
RXD Setup Before RX_CLK Rising Edge
30
--
ns
t30
RXD Held Past RX_CLK Edge
30
--
ns
t31
RX_CLK Low to CRS Deassertion (at end of received packet)
40
--
ns
t32
TX_EN Setup Before TX_CLK Rising Edge
30
--
ns
t33
TX_EN Held Past TX_CLK Rising Edge
0
--
ns
t34
TXD Setup Before TX_CLK Rising Edge
30
--
ns
t35
TXD Held Past TX_CLK Rising Edge
0
--
ns
t31
t30
t29
RX_CLK
CRS
RXD
t32
t34
t33
t35
LAST BIT
TX_CLK
TX_EN
TXD
(START OF PACKET)
(END OF PACKET)
Lucent Technologies Inc.
31
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
Timing Characteristics (Preliminary)
(continued)
Table 31. Serial 10 Mbits/s Timing for RX_CLK and TX_CLK (25 pF Load)
5-2737(F).dr1
Figure 14. Serial 10 Mbits/s Timing Diagram for RX_CLK and TX_CLK
Name
Parameter
Min
Max
Unit
t36
RX_CLK Low Pulse Width
45
55
ns
t37
RX_CLK High Pulse Width
45
55
ns
t38
TX_CLK Low Pulse Width
45
55
ns
t39
TX_CLK High Pulse Width
45
55
ns
RX/RY
COL
(TRANSMITTING--RECEIVE COLLISION DETECTED)
(RECEIVING--TRANSMIT COLLISON DETECTED)
IDL
t24
t25
t26
t27
t28
TX_EN
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
32
Lucent Technologies Inc.
Timing Characteristics (Preliminary)
(continued)
Table 32. 100 Mbits/s MII Transmit Timing
5-3745(F).er1
Figure 15. 100 Mbits/s MII Transmit Timing
Name
Parameter
Min
Max
Unit
t40
Rising Edge of TX_CLK Following TX_EN Assertion to CRS Assertion
--
40
ns
t41
Rising Edge of TX_CLK Following TX_EN Assertion to TX/TY
--
60
ns
t42
Rising Edge of TX_CLK Following TX_EN Deassertion to CRS Deassertion
--
40
ns
TX_CLK
TX_EN
TXD[3:0]
CRS
TX/TY
t40
t41
t42
1st BIT OF J
1st BIT OF T
Lucent Technologies Inc.
33
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
Timing Characteristics (Preliminary)
(continued)
Table 33. 100 Mbits/s MII Receive Timing
5-3747(F).er1
Figure 16. 100 Mbits/s MII Receive Timing
Name
Parameter
Min
Max
Unit
t43
RX/RY 1st Bit of J Receive Activity to CRS Asserted
--
170
ns
t44
RX/RY Receive Activity to Receive Data Valid
--
210
ns
t45
RX/RY Receive Activity Cease (1st bit of T) to CRS Deasserted
--
210
ns
t46
RX/RY Receive Activity Cease (1st bit of T) to Receive Data Not Valid
--
210
ns
RX/RY
t43
t45
t46
CRS
RX_CLK
RX_DV
RX_ER
RXD[3:0]
t44
1st BIT OF J
1st BIT OF T
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
34
Lucent Technologies Inc.
Outline Diagram
64-Pin TQFP
Dimensions are in millimeters.
5-3080r5
DETAIL A
0.50 TYP
1.60 MAX
SEATING PLANE
0.08
DETAIL B
0.05/0.15
1.40
0.05
10.00
0.20
12.00
0.20
1
64
49
16
17
32
48
33
10.00
0.20
12.00
0.20
PIN #1
IDENTIFIER ZONE
DETAIL B
0.19/0.27
0.08
M
0.106/0.200
DETAIL A
0.45/0.75
GAGE PLANE
SEATING PLANE
1.00 REF
0.25
Lucent Technologies Inc.
35
Data Sheet
LU6612
July 2000
FASTCAT Single-FET for 10Base-T/100Base-TX
Technical Document Types
The following descriptions pertain to the types of individual product data sheets.
Data sheets provide a definition of the particular integrated circuit device by detailing its full electrical and physical
specifications. They are intended to be the basic source of information for designers of new systems and to provide
data for users requiring information on equipment troubleshooting, training, incoming inspection, equipment test-
ing, and system design modification.
A data sheet is classified according to the following criteria:
Advance Data Sheet: An advance data sheet presents the device's proposed design architecture. It lists target
specifications but may not have complete parameter values and is subject to change.
Preliminary Data Sheet: Preliminary data sheets describe the characteristics of initial prototypes.
Data Sheet: When a data sheet has the specifications of a product in full production and has complete parameter
values, it is considered final and is classified as a data sheet.
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.
FASTCAT is a trademark of Lucent Technologies Inc.
Copyright 2000 Lucent Technologies Inc.
All Rights Reserved
July 2000
DS00-355LAN (Replaces DS99-105LAN)
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET:
http://www.lucent.com/micro
E-MAIL:
docmaster@micro.lucent.com
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1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
CHINA:
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Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652
JAPAN:
Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
EUROPE:
Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148
Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),
FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 600 7070 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
LU6612
Data Sheet
FASTCAT Single-FET for 10Base-T/100Base-TX
July 2000
Ordering Information
Device Code
Comcode
Package
Temperature
LU6612-T64-DB
108160680
64-Pin TQFP
0
C to 70
C
PDF 
ZIP