Advance Product Brief
March 1997
LUC4AC01
ATM Crossbar Element (ACE)
Section 5.5
LUCENT TECHNOLOGIES--PROPRIETARY
Use pursuant to Company Instructions
Introduction
The ACE IC is part of the ATLANTA chip set consist-
ing of four devices that provide a highly integrated,
innovative, and complete VLSI solution for imple-
menting the ATM layer core of an ATM switch system.
The chip set enables construction of high-perfor-
mance, feature-rich, and cost-effective ATM switches,
scalable over a wide range of switching capacities.
This document discusses the ACE device.
Features
s
Functions as a highly efficient, 5 Gbits/s, ATM
crossbar element.
-- Allows construction of nonblocking, lossless,
and self-routing three-stage switch fabrics.
-- Supports variable configurations for more com-
pact fabric design with higher port density. Each
ACE can be programmed to provide 1, 2, or 4
crossbars of different sizes.
s
Supports I/O port speeds up to 622 Mbits/s of ATM
traffic.
s
Incorporates independent clocking of input ports to
facilitate robust system designs by eliminating
clock trees and allowing for varied clock skews.
s
Uses differential clocking to provide noise immu-
nity.
s
Provides system diagnostic features, including
detection and reporting of the following error condi-
tions:
-- Input port parity error.
-- Loss of input port clock.
s
Supports a generic
Intel
* or
Motorola
compatible
16-bit microprocessor interface with interrupt.
s
Facilitates circuit board testing with on-chip
IEEE
standard boundary scan.
s
Low-power monolithic IC fabricated in 0.5
m,
3.3 V CMOS technology, with 5 V tolerant and TTL-
level compatible I/O.
s
Available in a 352-pin PBGA package.
Description
Figure 1 shows the architecture of an ATM switch
designed with the ATLANTA chip set. This document
summarizes ATLANTA switch fabrics and the
LUC4AC01 ATM Crossbar Element (ACE). The
ATLANTA ACE device provides the switching cross-
bar function for a three-stage ATM switch fabric. This
8 x 8 crossbar element is a key building block for
larger scalable three-stage switch fabrics (up to 40 x
40 OC-12 equivalent ports, 25 Gbits/s systems). The
ACE interfaces directly to the ATLANTA LUC4AS01
ATM Switch Element (ASX) device and is used for
linking switch elements. Nonblocking, lossless, and
self-routing switch fabrics can be constructed using
the ATLANTA chip set.
Each ACE is configurable to provide four crossbars of
a 2 x 2 configuration, two crossbars of up to a 4 x 4
configuration, or a single crossbar of up to an 8 x 8
configuration. It supports the novel internal backpres-
sure and routing algorithms of the companion ASX
device and provides fail-safe access to the output
ports.
The ACE also provides system diagnostic features.
Diagnostic reports include parity errors on inputs,
and loss of input port clock.
*
Intel
is a registered trademark of Intel Corporation.
Motorola
is a registered trademark of Motorola, Inc.
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
2
Lucent Technologies Inc.
Advance Product Brief
March 1997
ATM Crossbar Element (ACE)
LUC4AC01
Section 5.5
LUCENT TECHNOLOGIES--PROPRIETARY
Use pursuant to Company Instructions
Description
(continued)
5-4554r9
Figure 1. Architecture of an ATM Switch Using the ATLANTA Chip Set
ALM
LUC4AU01
MICROPROCESSOR
INTERFACE
SRAM
LINE CARD #1
#1
#1
LINE CARD #N
N x N SWITCH FABRIC
#N
BA
CKPLANE
REDUND
ANT BA
CKPLANE
ABM
LUC4AB01
SRAM
PHYSICAL LAYER
INTERFACE (MPHY)
ALM
LUC4AU01
SRAM
ABM
LUC4B01
SRAM
ASX
LUC4AS01
ACE
LUC4AC01
ASX
LUC4AS01
ASX
LUC4AS01
ACE
LUC4AC01
ASX
LUC4AS01
#1
#1
#N
N x N REDUNDANT SWITCH FABRIC
#N
ASX
LUC4AS01
ACE
LUC4AC01
ASX
LUC4AS01
ASX
LUC4AS01
ACE
LUC4AC01
ASX
LUC4AS01
#1
#1
#N
INGRESS DIRECTION
EGRESS DIRECTION
#1
#1
#N
#N
#N
#N
1
M
PHY PORTS
1
M
PHY PORTS
MICROPROCESSOR
INTERFACE
MICROPROCESSOR
INTERFACE
MICROPROCESSOR
INTERFACE
Lucent Technologies Inc.
3
Advance Product Brief
March 1997
ATM Crossbar Element (ACE)
LUC4AC01
Section 5.5
LUCENT TECHNOLOGIES--PROPRIETARY
Use pursuant to Company Instructions
Description
(continued)
The ACE block diagram and a brief description of the functionality of each block follows.
5-4515Br6
Figure 2. ACE Block Diagram
TEST ACCESS
INPUT
CLOCKING
26
12
12
12
12
12
12
8 (DATA)
1 (PARITY)
1 (START OF CELL)
2 (CLOCK)
SOURCE
FEEDBACK
CONFIGURATION
OUTPUT
12
12
12
12
12
12
12
12
16
5
8 (DATA)
1 (PARITY)
1 (START OF CELL)
2 (CLOCK)
TEST ACCESS
PORT
PROCESSOR
INPUT
PROCESSOR
INPUT
PROCESSOR
INPUT
PROCESSOR
INPUT
PROCESSOR
INPUT
PROCESSOR
INPUT
PROCESSOR
INPUT
PROCESSOR
12
12
ARBITER
PROCESSOR
OUTPUT
PROCESSOR
OUTPUT
PROCESSOR
OUTPUT
PROCESSOR
OUTPUT
PROCESSOR
OUTPUT
PROCESSOR
OUTPUT
PROCESSOR
OUTPUT
PROCESSOR
EGRESS
PORTS
INGRESS
PORTS
SYNCHRONIZATION
GTSYNC
SYSTEM CLOCK
(GCLK)
MICROPROCESSOR
INTERFACE
RESET (GRST)
OUTPUT ENABLE
AND
GENERATION
BACKPRESSURE
REGISTERS
AND STATUS
FROM THIRD-STAGE
(ACEOE)
GRANT_n
F3T2CLK)
8
ASX (F3T2 AND
PORT (JTAG)
4
4
Lucent Technologies Inc.
Advance Product Brief
March 1997
ATM Crossbar Element (ACE)
LUC4AC01
Section 5.5
LUCENT TECHNOLOGIES--PROPRIETARY
Use pursuant to Company Instructions
Description
(continued)
Overview
As shown in Figure 2, data for each port is clocked into
an input processor, and then routed to the appropriate
output processor. The routing and arbitration circuit,
and backpressure feedback generation circuit control
the movement of data into and out of the crossbar ele-
ments. Control and status is communicated through a
16-bit asynchronous microprocessor interface.
Figure 3 shows an example 16 x 16 ATLANTA-based
switch fabric. The switch fabric will switch any of the 16
inputs to any of the 16 outputs. This is achieved by
staging devices and is referred to as a three-stage
switch fabric. The input stage is called the
first stage
(expander), and the output stage is called the
third
stage
(concentrator). The ACE is functionally similar to
the ASX, but without the internal cell buffer (a hand-
shake protocol between the ASX and the ACE ensures
that the ACE need not store data). Conceptually, the
first stage ASX expands the number of paths available
for switching the data, while the third stage concen-
trates data from the center stage.
A three-stage ASX/ACE based switch fabric can sup-
port up to 40 ports with 622 Mbits/s I/O rates. A 40-port
(25 Gbits/s total ATM throughput) fabric design would
use eight devices per stage in a 5:8 expansion mode.
5-4523R5
Figure 3. Example 16 x 16 @ 622 Mbits/s Switch Fabric (10 Gbits/s throughput)
ASX
MODULE #0
ASX
MODULE #1
ASX
MODULE #2
ASX
MODULE #3
ACE
MODULE #0
ACE
MODULE #1
ACE
MODULE #2
ASX
MODULE #0
ASX
MODULE #1
ASX
MODULE #2
ASX
MODULE #3
INPUT FROM
PORT CARDS
OUTPUT TO
PORT CARDS
FIRST-STAGE EXPANDER
THIRD-STAGE CONCENTRATOR
CENTER-STAGE CROSSBAR
ACE
MODULE #3
Lucent Technologies Inc.
5
Advance Product Brief
March 1997
ATM Crossbar Element (ACE)
LUC4AC01
Section 5.5
LUCENT TECHNOLOGIES--PROPRIETARY
Use pursuant to Company Instructions
Description
(continued)
Input Processors
The input processors are responsible for accepting
data into the device. There are eight input processors,
one for each port. Each input port has eight data bits,
one parity bit, one start of cell bit, and a differential
clock. The microprocessor must enable the appropriate
input ports. The input processor shifts data in and
checks parity. Input ports are clocked independently.
The input port interface is designed to minimize the risk
of undetected errors. The differential clock provides
system noise immunity to prevent errors. In addition,
the input processor detects the presence of an input
clock and reports when the input clock is lost. The input
processor also checks for incoming parity errors. Parity
errors and loss of clock are reported through the micro-
processor interface.
Output Processors
The output processors perform the opposite functions
of the input processors. They handle the shifting out of
the data. The microprocessor can disable any output
port.
Source Arbiter
The source arbiter arbitrates access to the crossbar
outputs of the center-stage ACE module. The source
arbiter receives requests from the first-stage ASX mod-
ules. The source arbiter then determines which of
these requests are granted or denied, taking into con-
sideration any output contention in the center-stage or
congestion in the third-stage ASX modules in the
switch fabric.
Microprocessor Interface
The microprocessor interface (MPI) provides a general
16-bit asynchronous interface to an external processor
for accessing the ASX configuration and status regis-
ters and internal memory. The MPI also supports per-
function, maskable interrupts. The interface operates
identically to the interface in the ALM, ABM, and ASX.
The MPI is designed to support various 16-bit micro-
processors with minimal glue logic, and to directly inter-
face to popular
Intel
and
Motorola
microprocessors.
Test Access Port
The ACE incorporates logic to support a standard five-
pin test access port (TAP), compatible with the
IEEE
P1149.1 standard (JTAG), used for boundary scan.
TAP contains instruction registers, data registers, and
control logic, and has its own set of instructions. It is
controlled externally by a JTAG bus master. The TAP
gives the ACE board-level test capability.
Advance Product Brief
March 1997
ATM Crossbar Element (ACE)
LUC4AC01
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET:
http://www.lucent.com/micro
U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103
1-800-372-2447
, FAX 610-712-4106 (In CANADA:
1-800-553-2448
, FAX 610-712-4106), e-mail
docmaster@micro.lucent.com
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Tel. (65) 778 8833
, FAX (65) 777 7495
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Tel. (81) 3 5421 1600
, FAX (81) 3 5421 1700
For data requests in Europe:
MICROELECTRONICS GROUP DATALINE:
Tel. (44) 1734 324 299
, FAX (44) 1734 328 148
For technical inquiries in Europe:
CENTRAL EUROPE:
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(Bracknell UK),
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(33) 1 41 45 77 00
(Paris), SOUTHERN EUROPE:
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(Milan) or
(34) 1 807 1700
(Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.
Copyright 1997 Lucent Technologies Inc.
All Rights Reserved
Printed in U.S.A.
March 1997
PN96-066ATM
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