Preliminary Data Sheet

September 2001

L9216A/G
Short-Loop Ringing SLIC with Ground Start

Introduction

The Agere Systems Inc. L9216 is a subscriber line
interface circuit (SLIC) that is optimized for short-
loop, power-sensitive applications. This device pro-
vides the complete set of line interface functionality,
including power ringing needed to interface to a sub-
scriber loop. This device has the capability to operate
with a V

supply of 3.3 V or 5 V and is designed to

minimize external components required at all device
interfaces.

Features

Onboard ringing generation

Three ringing input options:
-- Sine wave
-- PWM
-- Logic level square wave

Flexible V

options:

-- 5 V or 3.3 V V

-- No 5 V required

Battery switch to minimize off-hook power

Eight operating states:
-- Scan mode for minimal power dissipation
-- Forward and reverse battery active
-- On-hook transmission states
-- Ground start (tip open)
-- Ring mode
-- Disconnect mode

Ultralow on-hook power:
-- 27 mW scan mode
-- 41 mW active mode

Two SLIC gain options to minimal external compo-
nents in codec interface

Loop start, ring trip, and ground start detectors

Software-controllable dual current-limit option

28-pin PLCC package

48-pin MLCC package

Applications

Voice over Internet Protocol (VoIP)

Cable Modems

Terminal Adapters (TA)

Wireless Local Loop (WLL)

Telcordia

Technologies

GR-909 Access

Network Termination (NT)

Key Systems

Description

This device is optimized to provide battery feed, ring-
ing, and supervision on short-loop plain old tele-
phone service (POTS) loops.

This device provides power ring to the subscriber
loop through amplification of a low-voltage input. It
provides forward and reverse battery feed states, on-
hook transmission, a low-power scan state, ground
start (tip open), and a forward disconnect state.

The device requires a V

and battery to operate.

may be either a 5 V or a 3.3 V supply. The ring-

ing signal is derived from the high-voltage battery. A
battery switch is included to allow for use of a lower-
voltage battery in the off-hook mode, thus minimizing
short-loop off-hook power.

Loop closure, ring trip, and ground start detectors are
available. The loop closure detector has a fixed
threshold with hysteresis. The ring trip detector
requires a single-pole filter, thus minimizing external
components required.

The dc current limit is set and fixed by a logic control-
lable pin. Ground or open is applied to this pin set the
current limit at the low or high value.

The device is offered with two gain options. This
allows for an optimized codec interface, with minimal
external components regardless of whether a first-
generation or a programmable third-generation
codec is used.

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Table of Contents

Contents

Page

Introduction..................................................................1

Features ....................................................................1
Applications...............................................................1
Description ................................................................1

Features ......................................................................4
Description...................................................................4
Architecture Diagram...................................................7
Pin Information ............................................................8
Operating States .......................................................10
State Definitions ........................................................11

Forward Active ........................................................11
Reverse Active ........................................................11
Scan ........................................................................11
On-Hook Transmission--Forward Battery ..............11
On-Hook Transmission--Reverse Battery ..............11
Disconnect ..............................................................11
Ring.........................................................................11
Ground Start ...........................................................11
Thermal Shutdown ..................................................12

Absolute Maximum Ratings (@ T

= 25 °C) ..............12

Electrical Characteristics ...........................................13
Test Configurations ...................................................20
Applications ...............................................................22

Power Control .........................................................22
dc Loop Current Limit..............................................23
Overhead Voltage ...................................................23

Active Mode .........................................................23
Scan Mode ...........................................................23
On-Hook Transmission Mode...............................23
Ring Mode ............................................................24

Loop Range ............................................................24
Battery Reversal Rate .............................................24

Supervision................................................................24

Loop Closure...........................................................24
Ring Trip .................................................................24
Tip or Ring Ground Detector ...................................24
Power Ring .............................................................25

Sine Wave Input Signal and Sine Wave

Power Ring Signal Output .................................26

PWM Input Signal and Sine Wave Power

Ring Signal Output.............................................28

5 V V

Operation ................................................29

3.3 V V

Operation .............................................30

Square Wave Input Signal and Trapezoidal

Power Ring Signal Output .................................30

Contents

Page

ac Applications ......................................................... 32

ac Parameters........................................................ 32
Codec Types .......................................................... 32

First-Generation Codecs ..................................... 32
Third-Generation Codecs .................................... 32

ac Interface Network .............................................. 32
Design Examples ................................................... 34

First-Generation Codec ac Interface

Network--Resistive Termination ...................... 34

Example 1, Real Termination .............................. 34
First-Generation Codec ac Interface

Network--Complex Termination ....................... 37

Complex Termination Impedance Design

Example ............................................................ 37

ac Interface Using First-Generation Codec ......... 37
Transmit Gain...................................................... 38
Receive Gain....................................................... 39
Hybrid Balance .................................................... 39
Blocking Capacitors ............................................ 40
Third-Generation Codec ac Interface

Network--Complex Termination ....................... 42

Outline Diagrams...................................................... 44

28-Pin PLCC .......................................................... 44
48-Pin MLCC.......................................................... 45
48-Pin MLCC, JEDEC MO-220 VKKD-2................ 46

Ordering Information ................................................ 47

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC w/ Ground Start

L9216A/G

Agere Systems Inc.

Table of Contents

(continued)

Figures

Page

Figure 1. Architecture Diagram ...................................7
Figure 2. 28-Pin PLCC ...............................................8
Figure 3. 48-Pin MLCC ................................................8
Figure 4. Basic Test Circuit ......................................20
Figure 5. Metallic PSRR ...........................................21
Figure 6. Longitudinal PSRR ....................................21
Figure 7. Longitudinal Balance .................................21
Figure 8. ac Gains ....................................................21
Figure 9. Ringing Waveform Crest Factor = 1.6 .......25
Figure 10. Ringing Waveform Crest Factor = 1.2 .....25
Figure 11. Ring Mode Typical Operation ..................26
Figure 12. RING

Operation ....................................27

Figure 13. L9215/16 Ringing Input Circuit Selection

Table for Square Wave and PWM
Inputs .......................................................28

Figure 14. Modulation Waveforms ............................29
Figure 15. 5 V PWM Signal Amplitude .....................29
Figure 16. Ringing Output on RING, with

= 5 V .................................................29

Figure 17. 3.3 V PWM Signal Amplitude ..................30
Figure 18. Ringing Output on RING, with

= 3.1 V ..............................................30

Figure 19. Square Wave Input Signal and

Trapezoidal Power Ring Signal Output ...30

Figure 20. Crest Factor vs. Battery Voltage .............31
Figure 21. Crest Factor vs. R (k

) ...........................31

Figure 22. ac Equivalent Circuit ................................35
Figure 23. Agere T7504 First-Generation Codec

Resistive Termination ..............................35

Figure 24. Interface Circuit Using First-Generation

Codec (Blocking Capacitors Not
Shown) ....................................................38

Figure 25. ac Interface Using First-Generation Codec

(Including Blocking Capacitors) for
Complex Termination Impedance ...........40

Figure 26. Agere T7504 First-Generation Codec

Complex Termination ..............................40

Figure 27. Third-Generation Codec ac Interface

Network; Complex Termination ...............42

Tables

Page

Table 1. Pin Descriptions .......................................... 9
Table 2. Control States ............................................. 10
Table 3. Supervision Coding ................................... 10
Table 4. Recommended Operating

Characteristics .......................................... 12

Table 5. Thermal Characteristics.............................. 12
Table 6. Environmental Characteristics .................... 13
Table 7. 5 V Supply Currents ................................... 13
Table 8. 5 V Powering .............................................. 13
Table 9. 3.3 V Supply Currents ............................... 14
Table 10. 3.3 V Powering ......................................... 14
Table 11. 2-Wire Port .............................................. 15
Table 12. Analog Pin Characteristics ..................... 16
Table 13. ac Feed Characteristics .......................... 17
Table 14. Logic Inputs and Outputs (V

= 5 V) ..... 18

Table 15. Logic Inputs and Outputs (V

= 3.3 V) .. 18

Table 16. Ground Start ............................................ 18
Table 17. Ringing Specifications ............................. 19
Table 18. Ring Trip .................................................. 19
Table 19. Typical Active Mode On- to Off-Hook

Tip/Ring Current-Limit Transient
Response ................................................ 23

Table 20. FB1 and FB2 Values vs. Typical Ramp

Time ......................................................... 24

Table 21. Onset of Power Ringing Clipping

= 5 V, Cinput = 0.47

F ................... 27

Table 22. Onset of Power Ringing Clipping

= 3.1 V, Cinput = 0.47

F ................ 27

Table 23. Signal and Component Selection Chart ... 28
Table 24. Parts List L9216; Agere T7504 First-

Generation Codec Resistive Termination;
Nonmeter Pulse Application ................... 36

Table 25. Parts List L9216; Agere T7504 First-

Generation Codec Complex Termination;
Meter Pulse Application ........................... 41

Table 26. Parts List L9216; Agere T8536

Third-Generation Codec ac and
dc Parameters; Fully Programmable ...... 43

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Features

Onboard balanced ringing generation:
-- No ring relay
-- No bulk ring generator required
-- 15 Hz to 70 Hz ring frequency supported
-- Sine wave input-sine wave output
-- PWM input-sine wave output
-- Square wave input-trapezoidal output

Power supplies requirements:
-- V

talk battery and ringing battery required

-- No 5 V supply required
-- No high-voltage positive supply required

Flexible Vcc options:
-- 5 V or 3.3 V V

operation

-- 5 V or 3.3 V V

interchangeable and transparent

to users

Battery switch via logic control:
-- Minimize off-hook power dissipation

Minimal external components required

Eight operating states:
-- Forward active, V

BAT2

applied

-- Polarity reversal active, V

BAT2

applied

-- On-hook transmission, V

BAT1

applied

-- On-hook transmission polarity reversal, V

BAT1

applied

-- Ground start
-- Scan
-- Forward disconnect
-- Ring mode

Unlatched parallel data control interface

Ultralow SLIC power:
-- Scan 37 mW (V

= 5 V)

-- Forward/reverse active 54 mW (V

= 5 V)

-- Scan 27 mW (V

= 3.3 V)

-- Forward/reverse active 41 mW (V

= 3.3 V)

Supervision:
-- Loop start, fixed threshold with hysteresis
-- Ring trip, single-pole ring trip filtering, fixed thresh-

old as a function of battery voltage

-- Ring current for ground start applications, user-

adjustable threshold

Adjustable current limit:
-- 25 mA or 40 mA via ground or open to control

input

Overhead voltage:
-- Clamped typically <51 V differentially
-- Clamped maximum <56.5 V single-ended

Thermal shutdown protection with hysteresis

Longitudinal balance:
--

Telcordia

Technologies

GR-909 balance

ac interface:
-- Two SLIC gain options to minimize external com-

ponents required for interface to first- or third-gen-
eration codecs

-- Sufficient dynamic range for direct coupling to

codec output

28-pin PLCC/48-pin MLCC package

90 V CBIC-S technology

Description

The L9216 is designed to provide battery feed, ringing,
and supervision functions on short plain old telephone
service (POTS) loops. This device is designed for
ultralow power in all operating states.

The L9216 offers eight operating states. The device
assumes uses of a lower-voltage talk battery, a higher-
voltage ringing battery, and a V

supply.

The L9216 requires only a positive V

supply. No

5 V supply is needed. The L9216 can operate with a
V

of either 5 V or 3.3 V, allowing for greater user flex-

ibility. The choice of V

voltage is transparent to the

user; the device will function with either supply voltage
connected.

Two batteries are used:

1. A high-voltage ring battery (V

BAT1

is a maximum 75 V. V

BAT1

is used for power

ring signal amplification and for scan, on-hook
transmission, and ground start modes. This supply
is current limited to approximately the maximum
power ringing current, typically 50 mA.

2. A lower-voltage talk battery (V

BAT2

is used for active mode powering.

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Description

(continued)

Forward and reverse battery active modes are used for
off-hook conditions. Since this device is designed for
short-loop applications, the lower-voltage V

BAT2

applied during the forward and reverse active states

Battery reversal is quiet, without breaking the ac path.
Rate of battery reversal may be ramped to control
switching time.

The magnitude of the overhead voltage in the forward
and reverse active modes has a typical default value of
6.0 V, allowing for an undistorted signal of 3.14 dBm
into 900

. This overhead is fixed. The ring trip detec-

tor is turned off during active modes to conserve power.

Because on-hook transmission is not allowed in the
scan mode, an on-hook transmission mode is defined.
This mode is functionally similar to the active mode,
except the tip ring voltage is derived from the higher
V

BAT1

rather than V

BAT2

In the on-hook transmission modes with a primary
battery whose magnitude is greater than a nominal
51 V, the magnitude of the tip to ground and ring to
ground voltage is clamped at less than 56.5 V.

To minimize on-hook power, a low-power scan mode is
available. In this mode, all functions except off-hook
supervision are turned off to conserve power. On-hook
transmission is not allowed in the scan mode.

In the scan mode with a primary battery whose magni-
tude is greater than a nominal 51 V, the magnitude of
the tip to ground and ring to ground voltage is clamped
at less than 56.5 V.

A forward disconnect mode is provided, where all cir-
cuits are turned off and power is denied to the loop.

The device offers a ring mode, in which a power ring
signal is provided to the tip/ring pair. During the ring
mode, a user-supplied low-voltage ring signal (ac-cou-
pled) is input to the device's RING

input. This signal is

amplified to produce the power ring signal. This signal
may be a sine wave or filtered square wave to produce
a sine wave on trapezoidal output. Ring trip detector
and common-mode current detector are active during
the ring mode.

This feature eliminates the need for a separate external
ring relay, associated external circuitry, and a bulk ring-
ing generator. See the Applications section of this data
sheet for more information.

The device offers a ground start mode. In this mode,
the tip drive amplifier is turned off. The device presents
a high impedance (>100 k

) to PT and a current-lim-

ited battery (V

BAT1

) to PR. V

BAT1

is clamped to less than

56.5 V in this mode as PR. A ring current detector for
ring ground detection is included for ground start appli-
cations. The threshold is user programmable via exter-
nal resistors. See the Applications section of this data
sheet for more information on supervision functions.
Output pin RGDET indicates current flowing in the ring
lead.

Both the ring trip and loop closure supervision func-
tions are included. The loop closure has a fixed typical
10.5 mA on- to off-hook threshold in the active mode
and a fixed 11.5 mA on- to off-hook threshold from the
scan mode. In either case, there is a 2 mA hysteresis.
The ring trip detector requires only a single-pole filter at
the input, minimizing external components. The ring
trip threshold at a given battery voltage is fixed. Typical
ring trip threshold is 42.5 mA for a 70 V V

BAT1.

Upon reaching the thermal shutdown temperature, the
device will enter an all-off mode. Upon cooling, the
device will re-enter the state it was in prior to thermal
shutdown. Hysteresis is built in to prevent oscillation.

Longitudinal balance is consistent with North American
GR-909 requirements. Specifications are given in Table
12.

Data control is via a parallel unlatched control scheme.

The dc current limit is fixed to either 25 mA or 40 mA
depending if ground or open is applied to the V

PROG

current-limit programming pin. Programming accuracy
is ±8%.

Circuitry is added to the L9216 to minimize the inrush
of current from the V

supply and to the battery supply

during an on- to off-hook transition, thus saving in
power supply design cost. See the Applications section
of this data sheet for more information.

Overhead in the active modes (V

BAT2

applied) is fixed

to approximately 6.0 V is achieved. This is adequate
for a 3.14 dBm overload into 900

Transmit and receive gains have been chosen to mini-
mize the number of external components required in
the SLIC-codec ac interface, regardless of the choice
of codec.

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Description

(continued)

The L9216 uses a voltage feed-current sense architec-
ture; thus, the transmit gain is a transconductance. The
L9216 transconductance is set via a single external
resistor, and this device is designed for optimal perfor-
mance with a transconductance set at 300 V/A.

The L9216 offers an option for a single-ended to differ-
ential receive gain of either 8 or 2. These options are
mask programmable at the factory and are selected by
choice of code.

A receive gain of 8 is more appropriate when choosing
a first-generation type codec where termination imped-
ance, hybrid balance, and overall gains are set by
external analog filters. The higher gain is typically
required for synthesization of complex termination
impedance.

A receive gain of 2 is more appropriate when choosing
a third-generation type codec. Third-generation codecs
will synthesize termination impedance and set hybrid
balance and overall gains. To accomplish these func-
tions, third-generation codecs typically have both ana-
log and digital gain filters. For optimal signal to noise

performance, it is best to operate the codec at a higher
gain level. If the SLIC then provides a high gain, the
SLIC output may be saturated causing clipping distor-
tion of the signal at tip and ring. To avoid this situation,
with a higher gain SLIC, external resistor dividers are
used. These external components are not necessary
with the lower gain offered by the L9216. See the Appli-
cations section of this data sheet for more information.

The L9216 is internally referenced to 1.5 V. This refer-
ence voltage is output at the V

REF

output of the device.

The SLIC output VITR is also referenced to 1.5 V;
therefore, it must be ac coupled to the codec input.
However, the SLIC inputs RCVP/RCVN

are floating

inputs. If there is not feedback from RCVP/RCVN to
VITR, RCVP/RCVN may be directly coupled to the
codec output. If there is feedback from RCVP/RCVN to
VITR, RCVP/RCVN must be ac coupled to the codec
output.

The L9216 is packaged in a 28-pin PLCC package and
an ultrasmall 48-pin MLCC package. Use L9216A for
gain of eight applications and L9216G for gain of two
applications.

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Pin Information

12-3558.d (F)

Figure 2. 28-Pin PLCC

Figure 3. 48-Pin MLCC

FB1

DCOUT

CF2

CF1

RTFLT

NST

ICM

RGD

PROG

RING

REF

FB2

RCVP

RCVN

L9216

28-PIN PLCC

FB1

RING

TXI

ITR

FB2

VITR

VTX

DCOUT

CF2

CF1

RTFLT

L9216A/G

48-PIN MLCC

DET

PROG

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Pin Information

(continued)

Table 1. Pin Descriptions

28-Pin

PLCC

48-Pin

MLCC

Symbol Type

Name/Function

NSTAT

Loop Closure Detector Output--Ring Trip Detector Output.
When low, this logic output indicates that an off-hook condition
exists or ringing is tripped.

VITR

Transmit ac Output Voltage. Output of internal AAC amplifier.
This output is a voltage that is directly proportional to the differen-
tial ac tip/ring current.

RCVP

Receive ac Signal Input (Noninverting). This high-impedance
input controls the ac differential voltage on tip and ring. This node
is a floating input.

RCVN

Receive ac Signal Input (Inverting). This high-impedance input
controls the ac differential voltage on tip and ring. This node is a
floating input.

RING

Power Ring Signal Input. ac-couple to a sine wave or lower crest
factor low-voltage ring signal. The input here is amplified to pro-
vide the full power ring signal at tip and ring. This signal may be
applied continuously, even during nonringing states.

DCOUT

dc Output Voltage. This output is a voltage that is directly propor-
tional to the absolute value of the differential tip/ring current. This
is used to set ring trip threshold.

PROG

Current-Limit Program Input. Connect ground to this pin to set
current-limit to 25 mA, float to this pin to set current limit to 40 mA.

CF2

Filter Capacitor. Connect a capacitor from this node to ground.

CF1

Filter Capacitor. Connect a capacitor from this node to CF2.

RTFLT

Ring Trip Filter. Connect this lead to DCOUT via a resistor and to
AGND with a capacitor to filter the ring trip circuit to prevent spuri-
ous responses. A single-pole filter is needed.

REF

SLIC Internal Reference Voltage. Output of internal 1.5 V refer-
ence voltage.

AGND

GND

Analog Signal Ground.

PWR

Analog Power Supply. User choice of 5 V or 3.3 V nominal power
or supply.

BAT1

PWR

Battery Supply 1. High-voltage battery.

BAT2

PWR

Battery Supply 2. Lower-voltage battery.

BGND

GND

Battery Ground. Ground return for the battery supplies.

2, 3, 4, 5, 8,

11, 14, 17,

18, 21, 27,
28, 30, 32,
36, 37, 39,

42, 44, 46

No Connection.

RGDET

Ring Ground Detect. When high, this open collector output indi-
cates the presence of a ring ground or a tip ground. This supervi-
sion output may be used in ground key, ground start or common-
mode fault detection applications.

ICM

Common-Mode Current Sense. To program tip or ring ground
sense threshold, connect a resistor to V

and connect a capacitor

to AGND to filter 50/60 Hz. If unused, the pin is connected to
ground.

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Pin Information

(continued)

Table 1. Pin Descriptions (continued)

Operating States

Table 2. Control States

Table 3. Supervision Coding

28-Pin

PLCC

48-Pin

MLCC

Symbol Type

Name/Function

FB2

Polarity Reversal Slowdown Capacitor. Connect a capacitor from
this node to ground for controlling rate of battery reversal. If ramped
battery reversal is not desired, this pin is left open.

FB1

Polarity Reversal Slowdown Capacitor. Connect a capacitor from
this node to ground for controlling rate of battery reversal. If ramped
battery reversal is not desired, this pin is left open.

I/O

Protected Tip. The output drive of the tip amplifier and input to the
loop sensing circuit. Connect to loop through overvoltage and overcur-
rent protection.

I/O

Protected Ring. The output drive of the ring amplifier and input to the
loop sensing circuit. Connect to loop through overvoltage and overcur-
rent protection.

State Control Input. These pins have an internal 110 k

pull-down.

ITR

Transmit Gain. Input to AX amplifier. Connect a 4.75 k

resistor from

this node to VTX to set transmit gain. Gain shaping for termination
impedance with a first-generation codec is also achieved with a net-
work from this node to VTX.

VTX

ac Output Voltage. Output of internal AX amplifier. The voltage at this
pin is directly proportional to the differential tip/ring current.

TXI

ac/dc Separation. Input to internal AAC amplifier. Connect a 0.1

capacitor from this pin to VTX.

State

Forward active

Reverse active

On-hook transmission forward battery

On-hook transmission reverse battery

Ground start

Scan

Disconnect, device will power up in this state

Ring

NSTAT

RGDET

0 = off-hook or ring trip or TSD.
1 = on-hook and no ring trip and no TSD or DISCONNECT state.

0 = no ring or tip ground.
1 = ring or tip ground.

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

State Definitions

Forward Active

Pin PT is positive with respect to PR.

BAT2

is applied to tip/ring drive amplifiers.

Loop closure and common-mode detect are active.

Ring trip detector is turned off to conserve power.

Overhead is set to nominal 6.0 V for undistorted
transmission of 3.14 dBm into 900

Reverse Active

Pin PR is positive with respect to PT.

BAT2

is applied to tip/ring drive amplifiers.

Loop closure and common-mode detect are active.

Ring trip detector is turned off to conserve power.

Overhead is set to nominal 6.0 V for undistorted
transmission of 3.14 dBm into 900

Scan

Except for loop closure, all circuits (including ring trip
and common-mode detector) are powered down.

On-hook transmission is disabled.

Pin PT is positive with respect to PR, and V

BAT1

applied to tip/ring.

The tip to ring on-hook differential voltage will be typ-
icallybetween 44 V and 51 V with a 70 V primary
battery.

On-Hook Transmission

Forward Battery

Pin PT is positive with respect to PR.

BAT1

is applied to tip/ring drive amplifiers.

Supervision circuits, loop closure, and common-
mode detect are active.

Ring trip detector is turned off to conserve power.

On-hook transmission is allowed.

The tip-to-ring on-hook differential voltage will be typ-
ically between 41 V and 49 V with a 70 V primary
battery.

On-Hook Transmission

Reverse Battery

Pin PR is positive with respect to PT.

BAT1

is applied to tip/ring drive amplifiers.

Supervision circuits, loop closure, and common-
mode detect are active.

Ring trip detector is turned off to conserve power.

On-hook transmission is allowed.

The tip-to-ring on-hook differential voltage will be typ-
ically between 41 V and 49 V with a 70 V primary
battery.

Disconnect

The tip/ring amplifiers and all supervision are turned
off.

The SLIC goes into a high-impedance state.

NSTAT is forced high (on-hook).

Device will power up in this state.

Ring

Power ring signal is applied to tip and ring.

Input waveform at RING

is amplified.

Ring trip supervision and common-mode current
supervision are active; loop closure is inactive.

Overhead voltage is reduced to typically 4 V.

Current is limited by saturation current of the amplifi-
ers themselves, typically 100 mA at 125 °C.

Ground Start

Tip drive amplifer is turned off.

Device presents a high impedance (>100 k

) to pin

PT.

Device presents a clamped (<56.5 V) current-limited
battery (V

BAT1

) to PR.

Output pin RGDET indicates current flowing in the
ring lead.

Thermal Shutdown

Not controlled via truth table inputs.

NSTAT is forced low (off-hook) during this state.

This mode is caused by excessive heating of the
device, such as may be encountered in an extended
power cross situation.

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Absolute Maximum Ratings

(@ T

= 25 °C)

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.

Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when

powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the
device ratings. For example, inductance in a supply lead could resonate with the supply filter capacitor to cause a destructive overvoltage.

Table 4. Recommended Operating Characteristics

Table 5. Thermal Characteristics

1. This parameter is not tested in production. It is guaranteed by design and device characterization.
2. Airflow, PCB board layers, and other factors can greatly affect this parameter.

Parameter

Symbol

Min

Typ

Max

Unit

dc Supply (V

) --

0.5

7.0

Battery Supply (V

BAT1

)

Battery Supply (V

BAT2

)

BAT1

Logic Input Voltage

0.5

+ 0.5

Logic Output Voltage

0.5

+ 0.5

Operating Temperature Range

125

°C

Storage Temperature Range

150

°C

Relative Humidity Range

PT or PR Fault Voltage (dc)

, V

BAT

PT or PR Fault Voltage (10 x 1000

, V

BAT

Ground Potential Difference (BGND to AGND)

±1

Parameter

Min

Typ

Max

Unit

5 V dc Supplies (V

)

5.0

5.25

3 V dc Supplies (V

)

3.13

3.3

High Office Battery Supply (V

BAT1

)

Auxiliary Office Battery Supply (V

BAT2

)

BAT1

Operating

Temperature

Range

40 25

°C

Parameter

Min

Typ

Max

Unit

Thermal Protection Shutdown (T

)

150

165

28-pin PLCC Thermal Resistance Junction to Ambient (

)

Natural Convection 2S2P Board
Natural Convection 2S0P Board
Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S2P Board
Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S0P Board

--
--
--
--

35.5
50.5
31.5
42.5

--
--
--
--

C/W

48-pin MLCC Thermal Resistance Junction to Ambient (

)

1, 2

C/W

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Electrical Characteristics

Table 6. Environmental Characteristics

1. Not to exceed 26 grams of water per kilogram of dry air.

Table 7. 5 V Supply Currents

BAT1

= 70 V, V

BAT2

= 21 V, V

= 5 V.

Table 8. 5 V Powering

BAT1

= 70 V, V

BAT2

= 21 V, V

= 5 V.

Parameter

Min

Typ

Max

Unit

Temperature Range

°C

Humidity Range

%RH

Parameter

Min

Typ

Max

Unit

Supply Currents (scan state; no loop current):

VCC

VBAT1

VBAT2

--
--
--

4.30
0.24

4.80
0.35

mA
mA

Supply Currents (forward/reverse active; no loop current, with or without PPM,

BAT2

applied):

VCC

VBAT1

VBAT2

--
--
--

5.95

1.2

7.0

1.40

Supply Currents (on-hook transmission mode; no loop current, with or without

PPM, V

BAT1

applied):

VCC

VBAT1

VBAT2

--
--
--

6.0
1.5
1.5

7.0
1.9

mA
mA

Supply Currents (disconnect mode):

VCC

VBAT1

VBAT2

--
--
--

2.7

3.5

3.75

110

Supply Currents (ground start mode, no loop current):

VCC

VBAT1

VBAT2

--
--
--

4.0

0.24

--
--
--

mA
mA

Supply Currents (ring mode; no load):

VCC

VBAT1

VBAT2

--
--
--

5.9
1.8

6.5
2.2

mA
mA

Parameter

Min

Typ

Max

Unit

Power Dissipation (scan state; no loop current)

Power Dissipation (forward/reverse active; no loop current, V

BAT2

applied)

Power Dissipation (on-hook transmission mode; no loop current, V

BAT1

applied)

135

165

Power Dissipation (disconnect mode)

Power Dissipation (ground start mode)

Power Dissipation (ring mode; no load)

156

184

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Electrical Characteristics

(continued)

Table 9. 3.3 V Supply currents

BAT1

= 70 V, V

BAT2

= 21 V, V

= 3.3 V.

Table 10. 3.3 V Powering

BAT1

= 70 V, V

BAT2

= 21 V, V

= 3.3 V.

Parameter

Min

Typ

Max

Unit

Supply Currents (scan state; no loop current):

VCC

VBAT1

VBAT2

--
--
--

3.2

0.24

3.6

0.35

mA
mA

Supply Currents (forward/reverse active; no loop current, V

BAT2

applied):

VCC

VBAT1

VBAT2

--
--
--

4.8

1.2

5.7

1.4

Supply Currents (on-hook transmission mode; no loop current, V

BAT1

applied):

VCC

VBAT1

VBAT2

--
--
--

4.9
1.5
1.5

5.7
1.9

mA
mA

Supply Currents (disconnect mode):

VCC

VBAT1

VBAT2

--
--
--

1.8

8
2

2.5

110

Supply Currents (ground start mode, no loop current):

VCC

VBAT1

VBAT2

--
--
--

3.1

0.24

--
--
--

mA
mA

Supply Currents (ring mode; no load):

VCC

VBAT1

VBAT2

--
--
--

4.70

1.8

5.4
2.2

mA
mA

Parameter

Min

Typ

Max

Unit

Power Dissipation (scan state; no loop current)

36.5

Power Dissipation (forward/reverse active; no loop current, V

BAT2

applied)

Power Dissipation (on-hook transmission mode; no loop current, V

BAT1

applied)

121

151

Power Dissipation (disconnect mode)

6.5

Power Dissipation (ground start mode)

Power Dissipation (ring mode; no loop current)

141

172

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Electrical Characteristics

(continued)

Table 11. 2-Wire Port

Parameter

Min

Typ

Max

Unit

Tip or Ring Drive Current = dc + Longitudinal + Signal Currents

105

mAp

Tip or Ring Drive Current = Ringing + Longitudinal

mAp

Signal Current

mArms

Longitudinal Current Capability per Wire (Longitudinal current is indepen-

dent of dc loop current.)

8.5

mArms

Ringing Current (R

LOAD

= 1386

+ 40

mArms

Ringing Current Limit (R

LOAD

= 100

)

mAp

dc Loop Current--I

LIM

BAT2

applied, R

LOOP

= 100

PROG

= 0

PROG

= Open

--
--

25
40

--
--

mA
mA

dc Current Variation

±8

dc Feed Resistance (does not include protection resistors)

Open Loop Voltages:

Scan Mode:

BAT1

| > 51 V |V

TIP

| |V

RING

PR to Battery Ground
PT to Battery Ground

OHT Mode:

BAT1

| > 51 V |V

TIP

| |V

RING

PR to Battery Ground
PT to Battery Ground

Active Mode:

|PT PR| |V

BAT2

Ring Mode:

|PT PR| |V

BAT1

--
--

5.75

--
--

6.25

56.5
56.5

6.75

V
V
V

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Electrical Characteristics

(continued)

Table 11. 2-Wire Port (continued)

Table 12. Analog Pin Characteristics

Parameter

Min

Typ

Max

Unit

Loop Closure Threshold:

Active/On-hook Transmission Modes
Scan Mode

--
--

10.5

11.5

--
--

mA
mA

Loop Closure Threshold Hysteresis:

= 5 V Active Mode

= 3.3 V Active Mode

= 5 V Ground Start Mode

= 3.3 V Ground Start Mode

--
--
--
--

2
1
6
5

--
--
--
--

mA
mA
mA
mA

Longitudinal to Metallic Balance at PT/PR

Test Method: Q552 (11/96) Section 2.1.2 and

IEEE

455:

300 Hz to 600 Hz
600 Hz to 3.4 kHz

52
52

--
--

dB
dB

Metallic to Longitudinal (harm) Balance:

200 Hz to 1000 Hz
100 Hz to 4000 Hz

40
40

--
--

dB
dB

PSRR 500 Hz--3000 Hz:

BAT1

, V

BAT2

(5 V operation)

45
35

--
--

dB
dB

Parameter

Min

Typ

Max

Unit

TXI (input impedance)

100

Output Offset (VTX)
Output Offset (VITR)
Output Drive Current (VTX)
Output Drive Current (VITR)
Output Voltage Swing:

Maximum (VTX, VITR)
Minimum (VTX)
Minimum (VITR)

Output Short-circuit Current
Output Load Resistance
Output Load Capacitance

--
--

±300

±10

AGND

AGND + 0.25
AGND + 0.35

--
--
--
--

--
--
--
--
--

±10
100

--
--

0.5

0.4

±50

--
--

mV
mV

V
V
V

RCVN and RCVP:

Input Voltage Range (V

= 5 V)

Input Voltage Range (V

= 3.3 V)

Input Bias Current

0
0

--
--

0.05

0.5

0.3

V
V

Differential PT/PR Current Sense (DCOUT):

Gain (PT/PR to DCOUT)
Offset Voltage at I

LOOP

= 0

V/A

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Electrical Characteristics

(continued)

Table 13. ac Feed Characteristics

1. Set externally either by discrete external components or a third- or fourth-generation codec. Any complex impedance R1 + R2 || C between

150

and 1400

can be synthesized.

2. This parameter is not tested in production. It is guaranteed by design and device characterization.
3. VITR transconductance depends on the resistor from ITR to VTX. This gain assumes an ideal 4750

, the recommended value. Positive cur-

rent is defined as the differential current flowing from PT to PR.

Parameter

Min

Typ

Max

Unit

ac Termination Impedance

150

600

1400

Total Harmonic Distortion (200 Hz--4 kHz)

Off-hook
On-hook

--
--

0.3
1.0

%
%

Transmit Gain (f = 1004 Hz, 1020 Hz, current limit)

PT/PR Current to VITR

300 3%

300

300 + 3%

V/A

Receive Gain, f = 1004 Hz, 1020 Hz Open Loop:

RCVP or RCVN to PT--PR (gain of 8 option, L9216A)
RCVP or RCVN to PT--PR (gain of 2 option, L9216G)

7.76
1.94

8
2

8.24
2.06

--
--

Gain vs. Frequency (transmit and receive)

600

Termination,

1004 Hz, 1020 Hz Reference:

200 Hz--300 Hz
300 Hz--3.4 kHz
3.4 kHz--20 kHz
20 kHz--266 kHz

0.3

0.05

3.0

0
0
0

0.05
0.05
0.05

2.0

dB
dB
dB
dB

Gain vs. Level (transmit and receive)

0 dBV Reference:

55 dB to +3.0 dB

0.05

Idle-channel Noise (tip/ring) 600

Termination:

Psophometric
C-Message
3 kHz Flat

--
--
--

13
20

dBmp

dBrnC

dBrn

Idle-channel Noise (VTX) 600

Termination:

Psophometric
C-Message
3 kHz Flat

--
--
--

13
20

dBmp

dBrnC

dBrn

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Electrical Characteristics

(continued)

Table 14. Logic Inputs and Outputs (V

= 5 V)

Table 15. Logic Inputs and Outputs (V

= 3.3 V)

Table 16. Ground Start

Parameter

Symbol

Min

Typ

Max

Unit

Input Voltages:

Low Level
High Level

0.5

2.0

0.4
2.4

0.7

V
V

Input Current:

Low Level (V

= 5.25 V, V

= 0.4 V)

High Level (V

= 5.25 V, V

= 2.4 V)

--
--

±50
±50

Output Voltages (open collector with internal pull-up resistor):

Low Level (V

= 4.75 V, I

= 200

High Level (V

= 4.75 V, I

= 20

2.4

0.2

0.4

V
V

Parameter

Symbol

Min

Typ

Max

Unit

Input Voltages:

Low Level
High Level

0.5

2.0

0.2
2.5

0.5

V
V

Input Current:

Low Level (V

= 3.46 V, V

= 0.4 V)

High Level (V

= 3.46 V, V

= 2.4 V)

--
--

±50
±50

Output Voltages (open collector with internal 60 k

pull-up resistor):

Low Level (V

= 3.13 V, I

= 200

High Level (V

= 3.13 V, I

= 5

2.2

0.2

0.5

V
V

Parameter

Min

Typ

Max

Unit

Tip Open Mode:

Tip Input Impedance

150

Detector Accuracy

Detection

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Electrical Characteristics

(continued)

Table 17. Ringing Specifications

Table 18. Ring Trip

Ringing will not be tripped by the following loads:

10 k

resistor in parallel with a 6 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.

100

resistor in series with a 2 µF capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.

Parameter

Min

Typ

Max

Unit

RING

(This input is ac coupled through 0.47 µF.):

Input Voltage Swing
Input Impedance

100

Ring Signal Isolation:

PT/PR to VITR
Ring Mode

Ring Signal Isolation:

RING

to PT/PR

Nonring Mode

Ringing Voltage (5 REN 1380

+ 40 µF load, 100

loop, 2 x 50

protection

resistors, 70 V battery)

Vrms

Ringing Voltage (3 REN 2310

+ 24 µF load, 250

loop, 2 x 50

protection

resistors, 70 V battery)

Vrms

Ring Signal Distortion:

5 REN 1380

, 40 µF Load, 100

Loop

3 REN 2310

, 24 µF Load, 250

Loop

--
--

3
3

--
--

%
%

Differential Gain:

RING

to PT/PR--No Load

Parameter Min

Typ

Max

Unit

Ring Trip (NSTAT = 0): Loop Resistance (total) High Battery

100

600

Ring Trip (NSTAT = 1): Loop Resistance (total) High Battery

Trip Time (f = 20 Hz)

100

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Applications

Power Control

Under normal device operating conditions, power dissi-
pation on the device must be controlled to prevent the
device temperature from rising above the thermal shut-
down and causing the device to shut down. Power dis-
sipation is highest with higher battery voltages, higher
current limit, and under shorter dc loop conditions.
Additionally, higher ambient temperature will also
reduce thermal margin.

To support required power ringing voltages, this device
is meant to operate with a high-voltage primary battery
(65 V to 75 V typically). Thus, power control is nor-
mally achieved by use of the battery switch and an aux-
iliary lower absolute voltage battery. Operating
temperature range, maximum current limit, maximum
battery voltage, minimum dc loop length and protection
resistor values, airflow, and number of PC board layers
will influence the overall thermal performance. The fol-
lowing example illustrates typical thermal design con-
siderations.

The thermal resistance of the 28-pin PLCC package is
typically 35.5

C/W, which is representative of the natu-

ral airflow as seen in a typical switch cabinet with a
multilayer board.

The L9216 will enter thermal shutdown at a tempera-
ture of 150

C. The thermal design should ensure that

the SLIC does not reach this temperature under normal
operating conditions.

For this example, assume a maximum ambient operat-
ing temperature of 85

C, a maximum current limit of

30 mA, a maximum battery of 75 V, and an auxiliary
battery of 21 V. Assume a (worst-case) minimum dc
loop of 20

of wire resistance, 30

protection resis-

tors, and 200

for the handset. Additionally, include

the effects of parameter tolerance.

1. T

TSD

AMBIENT(max)

= allowed thermal rise.

150 °C 85 °C = 65 °C.

2. Allowed thermal rise = package thermal

impedance

SLIC power dissipation.

65 °C = 35.5 °C/W

SLIC power dissipation

SLIC power dissipation (P

) = 1.83 W.

Thus, if the total power dissipated in the SLIC is less
than 1.83 W, it will not enter the thermal shutdown
state. Total SLIC power is calculated as:

Total P

= maximum battery

maximum current

limit + SLIC quiescent power.

For the L9216, the worst-case SLIC on-hook active
power is 75 mW. Thus,

Total off-hook power = (I

LOOP

)(current-limit

tolerance)*(V

BATAPPLIED

) + SLIC on-hook power

Total off-hook power = (0.030 A)(1.08) * (21) +
75 mW
Total off-hook power = 755.4 mW

The power dissipated in the SLIC is the total power dis-
sipation less the power that is dissipated in the loop.

SLIC P

= total power loop power

Loop off-hook power = (I

LOOP

* 1.08)

LOOP(dc)

min + 2R

HANDSET

)

Loop off-hook power = (0.030 A)(1.08)

(20

+ 200

)

Loop off-hook power = 293.9 mW
SLIC off-hook power = Total off-hook power loop
off-hook power
SLIC off-hook power = 755.4 mW 293.9 mW
SLIC off-hook power = 461.5 mW < 1.83 W

Thus, under the operating conditions of this example,
the thermal design, using the auxiliary, is adequate to
ensure the device is not driven into thermal shutdown
under worst-case operating conditions.

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Applications

(continued)

dc Loop Current Limit

Current limit may be chosen from two discrete values,
25 mA or 40 mA, depending on if V

PROG

is grounded

(25 mA) or left floating (40 mA). Note that there is a
12.5 k

slope to the I/V characteristic in the current-

limit region; thus, once in current limit, the actual loop
current will increase slightly, as loop length decreases.

The above describes the active mode steady-state cur-
rent-limit response. There will be a transient response
of the current-limit circuit upon an on- to off-hook transi-
tion. Typical active mode transient current-limit
response is given in Table 19.

Table 19. Typical Active Mode On- to Off-Hook Tip/

Ring Current-Limit Transient Response

Overhead Voltage

Active Mode

Overhead is fixed to a nominal 6.0 V, which is adequate
for on-hook transmission of 3.14 dBm into 900

Scan Mode

If the magnitude of the primary battery is greater than
51 V, the magnitude of the open loop tip-to-ring open
loop voltage is clamped typically between 44 V and
51 V. If the magnitude of the primary battery is less
than a nominal 51 V, the overhead voltage will track the
magnitude of the battery voltage, i.e., the magnitude of
the open circuit tip-to-ring voltage will be 4 V to 6 V less
than battery. In the scan mode, overhead is unaffected
by V

OVH

On Hook Transmission Mode

If the magnitude of the primary battery is greater than
51 V, the magnitude of the open loop tip-to-ring open
loop voltage is clamped typically between 41 V and
49 V. If the magnitude of the primary battery is less
than a nominal 51 V, the overhead voltage will track the
magnitude of the battery voltage, i.e., the magnitude of
the open circuit tip-to-ring voltage will be 6 V to 8 V less
than battery. In the scan mode, overhead is unaffected
by V

OVH

Parameter

Value

Unit

dc Loop Current:

Active Mode
R

LOOP

= 100

On- to Off-hook

Transition t < 5 ms

LIM

+ 60

dc Loop Current:

Active Mode
R

LOOP

= 100

On- to Off-hook

Transition t < 50 ms

LIM

+ 20

dc Loop Current:

Active Mode
R

LOOP

= 100

On- to Off-hook

Transition t < 300 ms

LIM

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Applications

(continued)

Overhead Voltage

(continued)

Ring Mode

In the ring mode, to maximize ringing loop length, the
overhead is decreased to the saturation of the tip ring
drive amplifiers, a nominal 4 V. The tip to ground volt-
age is 1 V, and the ring to V

BAT1

voltage is 3 V.

During the ring mode, to conserve power, the receive
input at RCVN/RCVP is deactivated. During the ring
mode, to conserve power, the AAC amplifier in the
transmit direction at VITR is deactivated. However, if
the AX amplifier at VTX is active during the ring mode,
differential ring current may be sensed at VTX during
the ring mode.

Loop Range

The dc loop range is calculated using:

BAT2

is typically applied under off-hook conditions for

power conservation and SLIC thermal considerations.
The L9216 is intended for short-loop applications and,
therefore, will always be in current limit during off-hook
conditions. However, note that the ringing loop length
rather than the dc loop length, will be the factor to
determine operating loop length.

Battery Reversal Rate

The rate of battery reverse is controlled or ramped by
capacitors FB1 and FB2. Table 20 below shows FB1
and FB2 values vs. typical ramp time. Leave FB1 and
FB2 open if it is not desired to ramp the rate of battery
reversal.

Table 20. FB1 and FB2 Values vs. Typical Ramp

Time

Supervision

The L9216 offers the loop closure and ring trip supervi-
sion functions. Internal to the device, the outputs of
these detectors are multiplexed into a single package
output, NSTAT. Additionally, a common-mode current
detector for tip or ring ground detection is included for
ground key applications.

Loop Closure

The loop closure has a fixed typical 10.5 mA on- to off-
hook threshold in the active mode and a fixed 11.5 mA
on- to off-hook threshold from the scan mode. In either
case, there is a 2 mA hysteresis with V

= 5 V and a

1 mA hysteresis with V

= 3.3 V.

Ring Trip

The ring trip detector requires only a single-pole filter at
the input, minimizing external components. An R/C
combination of 383 k

and 0.1

F, for a filter pole at

5.15 Hz, is recommended.

The ring trip threshold is internally fixed as a function of
battery voltage and is given by:

RT (mA) = 67 * {(0.0045 * V

BAT1

) + 0.317}

where:
RT is ring trip current in mA.
V

BAT1

is the magnitude of the ring battery in V.

There is a 6 mA to 8 mA hysteresis.

Tip or Ring Ground Detector

In the ground key or ground start applications, a com-
mon-mode current detector is used to indicate either a
tip- or ring-ground has occurred (ground key) or an off-
hook has occurred (ground start).

For ground start applications detection may be seen at
the output of the common mode current detector
(RGDET) or the loop closure detector (NSTAT).

If ICM is used, the detection threshold is set by con-
necting a resistor from ICM to V

205 x V

ICM

) = I

(mA)

Additionally, a filter capacitor across R

ICM

will set the

time constant of the detector. No hysteresis is associ-
ated with this detector. The RC filter at ICM gives
immunity to longitudinal currents.

FB1

and C

FB2

Transition

Time

0.01

20 ms

0.1

220 ms

0.22

440 ms

0.47

900 ms

1.0

1.8 s

1.22

2.25 s

1.3

2.5 s

1.4

2.7 s

1.6

3.2 s

BAT2

LIMIT

--------------------------------------

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Supervision

(continued)

Tip or Ring Ground Detector

(continued)

Also in the ground start mode, the fixed loop current
threshold associated with the NSTAT detector output is
internally adjusted to account for common-mode cur-
rent detection in ground start mode (as opposed to dif-
ferential current in loop start mode) maintain the
detector at 10 mA. Thus, NSTAT may also be used for
loop closure detion in ground start. However, the detec-
tor at NSTAT is not filtered against longitudinal cur-
rents, which may or may not be an issue in short loop
applications. Using NSTAT will also save components
at ICM.

Power Ring

The device offers a ring mode, in which a balanced
power ring signal is provided to the tip/ring pair. During
the ring mode, a user-supplied low-voltage ring signal
is input to the device's RING

input. This signal is

amplified to produce the balanced power ring signal.
The user may supply a sine wave input, PWM input, or
a square wave to produce sinusoidal or trapezoidal
ringing at tip and ring.

Various crest factors are shown for illustrative pur-
poses.

12-3346a (F)

Note: Slew rate = 5.65 V/ms; trise = tfall = 23 ms; pwidth = 2 ms;

period = 50 ms.

Figure 9. Ringing Waveform Crest Factor = 1.6

12-3347a (F)

Note: Slew rate = 10.83 V/ms; trise = tfall = 12 ms; pwidth = 13 ms;

period = 50 ms.

Figure 10. Ringing Waveform Crest Factor = 1.2

Voltage applied to the load may be increased by using
a filtered square wave input to produce a lower crest
factor trapezoidal power ring signal at tip and ring.

TIME (s)

0.00

0.02 0.06

0.04 0.08

0.10

0.12

0.14

0.16

0.18

0.20

)

TIME (s)

0.00

0.02 0.06

0.04 0.08

0.10

0.12

0.14

0.16

0.18

0.20

S (

)

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Supervision

(continued)

Power Ring

(continued)

Sine Wave Input Signal and Sine Wave Power Ring
Signal Output

The low-voltage sine wave input is applied to the L9216
at pin RING

. This signal should be ac-coupled

through 0.47

F. During the ring mode, the signal at

RING

is amplified and presented to the subscriber

loop. The differential gain from RING

to tip and ring is

a nominal 55.

When the device enters the ring mode, the tip/ring
overhead set at OVH and the scan clamp circuit is dis-
abled, allowing the voltage magnitude of the power ring
signal to be maximized. Additionally, in the ring mode,
the loop current limit is increased 2.5X the value set by
the V

PROG

voltage.

The magnitude of the power ring voltage will be a func-
tion of the gain of the ring amplifier, the high voltage
battery, and the input signal at RING

. The input range

of the signal at RING

is 0 V to Vcc. As the input volt-

age at RING

is increased, the magnitude of the power

ring voltage at tip and ring will increase linearly, per the
differential gain of 55, until the tip and ring drive amplifi-
ers begin to saturate. Once the tip and ring amplifiers
reach saturation, further increases of the input signal
will cause clipping distortion of the power ring signal
at tip and ring. The ring signal will appear balanced on
tip and ring. That is, the power ring signal is applied
to both tip and ring, with the signal on tip 180

(180 degrees) out of phase from the signal on ring.

Figure 11 shows typical operation of the ring mode,
prior to saturation of the tip and ring drive amplifiers. A
70 V battery is used with a 100

loop and a 1 REN

load. The input signal is 1 V through a 0.47

F capaci-

tor at RING

, (the input circuit is shown in Figure 12).

This produces a voltage swing from 34 V to 60 V

on ring and from 8 V to 34 V on tip, as shown in
Figure 11. Thus, the total voltage swing is 52 V (60 V to
8 V) for a 1 V input, which is approximately the differen-
tial gain of the device. Note that the tip and ring power
ring signals will swing around V

BATTERY

divided by two.

In this case, there is a 70 V battery so tip and ring
swing around 34 V.

12-3573F

12-3574F

Figure 11. Ring Mode Typical Operation

0.60

0.62

0.64

0.66

0.68

0.70

0.72

0.74

0.76

0.78

TIME

0.80

VRING

VTIP

1.0

0.60

0.62

0.64

0.66

0.68

0.70

0.72

0.74

0.76

0.78

TIME

0.80

0.5

0.0

0.5

VRINGIN

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Supervision

(continued)

Power Ring

(continued)

Sine Wave Input Signal and Sine Wave Power Ring Signal Output (continued)

It is recommended that the input level at RING

be adjusted so that the power ring signal at tip and ring is just at

the edge or slightly clipping. This gives maximum power transfer with minimal distortion of the sine wave. The tip
side will saturate at a nominal 1 V above ground. The ring side will saturate at a nominal 3 V above battery. The
input circuit for a sine wave along with waveforms to illustrate the tip and ring saturation is shown in Figure 12.

12-3532J

Figure 12. RING

Operation

The point at which clipping of the power ring signal begins at tip and ring is a function of the battery voltage, the
input capacitor at RING

, and the input signal at RING

and Vcc. Typical characteristic conditions showing the

onset of clipping are given below.

Table 21. Onset of Power Ringing Clipping V

= 5 V, Cinput = 0.47

Table 22. Onset of Power Ringing Clipping V

= 3.1 V, Cinput = 0.47

Input T/R

BAT1

(V)

Vrms (mV)

Vrms (V)

Gain

70.15

891

46.88

52.62

68.06

858

45.11

52.58

66.00

833

43.69

52.45

64.08

814

42.57

52.30

62.04

789

41.21

52.23

60.05

747

39.11

52.36

Input T/R

BAT1

(V)

Vrms (mV)

Vrms (V)

Gain

70.12

894

47.15

52.74

68.07

855

45.11

52.76

66.06

824

43.38

52.65

64.01

799

41.95

52.5

62.00

780

40.79

52.29

60.00

749

39.09

52.19

GND

BAT

27.5x

RING

0.47

INPUT

L9216

TIP

RING

3 V

100 k

1 V

BAT

= 75 V

71 V

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Supervision

(continued)

Power Ring

(continued)

Sine Wave Input Signal and Sine Wave Power Ring Signal Output (continued)

During nonring modes, the sinusoidal ringing waveform may be left on at RING

. Via the state table, the ring signal

will be removed from tip and ring even if the low- voltage input is still present at RING

. There are certain timing

considerations that should be made with respect to state changes which are detailed in the

Switching Behavior of

L9215/6 Ringing SLIC

Application Note.

PWM Input Signal and Sine Wave Power Ring Signal Output

A pulse-width modulated (PWM) signal may be used to provide the ringing input to RING

. The signal is applied

through a low-pass filter and ac-coupled into RING

as shown in Figure 13 below. This approach gives a sine

wave output at tip and ring.

12-3578bF

Figure 13. L9215/16 Ringing Input Circuit Selection Table for Square Wave and PWM Inputs

Table 23. Signal and Component Selection Chart

BAT

Input

Typical 5 REN Ringing Voltage RMS

70 V

5 V

5 V Square

12 k

0.47

1.3

48 V

70 V

3 V

3 V Square

7 k

0.47

1.3

49 V

70 V

5 V

10 kHz PWM 5 V

10 k

0.22

0.47

sine

42 V

70 V

3 V

10 kHz PWM 3 V

10 k

0.22

0.47

sine

42 V

70 V

5 V

90 kHz PWM 5 V

7 k

0.1

0.47

sine

42 V

70 V

3 V

90 kHz PWM 3 V

7 k

0.1

0.47

sine

42 V

85 V

5 V

5 V Square

10 k

0.47

1.3

59 V

85 V

3 V

3 V Square

7 k

0.47

1.3

51 V

85 V

5 V

10 kHz PWM 5 V

10 k

0.22

0.47

sine

51 V

85 V

3 V

10 kHz PWM 3 V

4 k

0.22

0.47

sine

47 V

85 V

5 V

90 kHz PWM 5 V

4 k

0.1

0.47

sine

51 V

85 V

3 V

90 kHz PWM 3 V

4 k

0.1

0.47

sine

49 V

INPUT

RING

L9215/16

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Supervision

(continued)

Power Ring

(continued)

PWM Input Signal and Sine Wave Power Ring Sig-
nal Output (continued)

Modulation waveforms showing PWM are in Figure 14
below.

Figure 14. Modulation Waveforms

5 V V

Operation

A PWM signal was generated with an

8116

Function Generator modulated with a 20 Hz signal. The
optimal frequency used was 10 kHz. The PWM signal
amplitude was 5.0 V (0 V to 5 V). This signal is shown
in Figure 15.

12-3575F

Figure 15. 5 V PWM Signal Amplitude

This input produced 44.96 Vrms ringing signal on
tip/ring under open-loop conditions and 42.0 Vrms was
delivered to 5 REN load. The ringing output on ring,
with V

= 5 V, is shown in Figure 16.

1660

Notes:
The modulating 20 Hz signal THD was measured at 1.3%.

The tip/ring 20 Hz signal THD was measured at 1%.

BAT1

= 70.6 V, V

BAT2

= 26.5 V, V

= 5.019 V.

PWM input 10 kHz, 5.0 Vp-p.

= 10 k

, C

= 0.22

F, C

= 0.47

Figure 16. Ringing Output on RING, with V

= 5 V

12-3381(F)

A. Upper = Pwm Signal Centered at 10 kHz

Lower = Modulation Signal

12-3380(F)

B. Same as A but Expanded

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Supervision

(continued)

Power Ring

(continued)

3.3 V V

Operation

A PWM signal was generated with an

8116 Func-

tion Generator modulated with a 20 Hz signal. The opti-
mal frequency used was 10 kHz. The PWM signal
amplitude was 3.10 V (0 V to 3.10 V). This input signal
is shown in Figure 17.

12-3571F

Figure 17. 3.3 V PWM Signal Amplitude

This produced 44.96 Vrms ringing signal on tip/ring
under open-loop conditions and 42.0 Vrms was deliv-
ered to 5 REN load. The ringing output on ring with V

= 3.1 V is shown in Figure 18.

1660

Notes:
The modulating 20 Hz signal THD was measured at 1.3%.

The tip/ring 20 Hz signal THD was measured at 1%.

BAT1

= 70.6 V, V

BAT2

= 26.5 V, V

= 3.10 V.

PWM input 10 kHz, 3.1 Vp-p.

= 10 k

, C

= 0.22

F, C

= 0.47

Figure 18. Ringing Output on RING, with V

= 3.1 V

During nonring modes, the PWM waveform may be left
on at RING

. Via the state table, the ring signal will be

removed from tip and ring even if the low-voltage input
is still present at RING

. There are certain timing con-

siderations that should be made with respect to state
changes which are detailed in the

Switching Behavior

of L9215/6 Ringing SLIC

Application Note.

Square Wave Input Signal and Trapezoidal Power
Ring Signal Output

A low-voltage square wave signal may be used to pro-
vide the ringing input to RING

. The signal is applied

through a low-pass filter and ac-coupled into RING

shown in Figure 13 and Table 23. This approach gives
a trapezoidal wave output at tip and ring.

Using this approach, a trapezoidal waveform can be
achieved at tip and ring. This has the advantage of
increasing the power transfer to the load for a given
battery voltage, thus increasing the effective ringing
loop length as compared to a sine wave. The actual
crest factor achieved is a function of the magnitude of
the battery, the magnitude of the input voltage, fre-
quency, and R

12-3572F

Notes:
CH1--CMOS Input (5 V) at RING

CH2--Filtered input at RING

CH3--Tip.

CH4--Ring.

= 14 k

, C

= 1.0

F, C

= 0.47

BAT1

= 70 V, Vrms

= 51 V, V

p-p

= 67 V, frequency = 20 Hz, Crest

Factor = 1.3.

Figure 19. Square Wave Input Signal and Trapezoi-

dal Power Ring Signal Output

CH1

CH2

CH3

CH4

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

Supervision

(continued)

Power Ring

(continued)

Square Wave Input Signal and Trapezoidal Power Ring Signal Output (continued)

Figure 20 and Figure 21 provide some guidance to the relationship between crest factor, battery voltage, and R

value.

12-3576F

Figure 20. Crest Factor vs. Battery Voltage

12-3577F

Figure 21. Crest Factor vs. R (k

)

During nonring modes, the square wave input may be left on or removed from RING

. Via the state table, the ring

signal will be removed from tip and ring even if the low-voltage input is still present at RING

. However, removing

the waveform has certain advantages in terms of the timing of state. These advantages are detailed in the

Switch-

ing Behavior of L9215/16 Ringing SLIC

Application Note.

1.36

BAT V

1.35

1.34

1.33

1.32

1.31

1.3

1.29

1.28

1.27

1.26

1.5

1.45

R (k

)

1.4

1.35

1.3

1.25

10.5

11.5

12.5

13.5

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

ac Applications

ac Parameters

There are four key ac design parameters. Termination
impedance is the impedance looking into the 2-wire
port of the line card. It is set to match the impedance of
the telephone loop in order to minimize echo return to
the telephone set. Transmit gain is measured from the
2-wire port to the PCM highway, while receive gain is
done from the PCM highway to the transmit port.
Transmit and receive gains may be specified in terms
of an actual gain, or in terms of a transmission level
point (TLP), that is the actual ac transmission level
in dBm. Finally, the hybrid balance network cancels
the unwanted amount of the receive signal that
appears at the transmit port.

Codec Types

At this point in the design, the codec needs to be
selected. The interface network between the SLIC and
codec can then be designed. Below is a brief codec
feature summary.

First-Generation Codecs

These perform the basic filtering, A/D (transmit), D/A
(receive), and

-law/A-law companding. They all have

an op amp in front of the A/D converter for transmit
gain setting and hybrid balance (cancellation at the
summing node). Depending on the type, some have
differential analog input stages, differential analog out-
put stages, 5 V only or

5 V operation, and

-law/A-law

selectability. These are available in single and quad
designs. This type of codec requires continuous time
analog filtering via external resistor/capacitor networks
to set the ac design parameters. An example of this
type of codec is the Agere T7504 quad 5 V only codec.

This type of codec tends to be the most economical in
terms of piece part price, but tends to require more
external components than a third-generation codec.
Further ac parameters are fixed by the external R/C
network so software control of ac parameters is diffi-
cult.

Third-Generation Codecs

This class of devices includes all ac parameters set
digitally under microprocessor control. Depending on
the device, it may or may not have data control latches.
Additional functionality sometimes offered includes
tone plant generation and reception, PPM generation,
test algorithms, and echo cancellation. Again, this type
of codec may be 3.3 V, 5 V only, or

5 V operation, sin-

gle quad or multichannel, and

-law/A-law or 16-bit lin-

ear coding selectable. Examples of this type of codec
are the Agere T8535/6 (5 V only, quad, standard fea-
tures), T8537/8 (3.3 V only, quad, standard features),
T8533/4 (5 V only, quad with echo cancellation), and
the T8531/32 (5 V only multichannel).

ac Interface Network

The ac interface network between the L9216 and the
codec will vary depending on the codec selected. With
a first-generation codec, the interface between the
L9216 and codec actually sets the ac parameters. With
a third-generation codec, all ac parameters are set dig-
itally, internal to the codec; thus, the interface between
the L9216 and this type of codec is designed to avoid
overload at the codec input in the transmit direction
and to optimize signal to noise ratio (S/N) in the receive
direction.

Because the design requirements are very different
with a first- or third-generation codec, the L9216 is
offered with two different receive gains. Each receive
gain was chosen to optimize, in terms of external com-
ponents required, the ac interface between the L9216
and codec.

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

ac Applications

(continued)

ac Interface Network

(continued)

With a first-generation codec, the termination imped-
ance is set by providing gain shaping through a feed-
back network from the SLIC VITR output to the SLIC
RCVN/RCVP inputs. The L9216 provides a transcon-
ductance from T/R to VITR in the transmit direction and
a single-ended to differential gain from either RCVN or
RCVP to T/R in the receive direction. Assuming a short
from VITR to RCVN or RCVP, the maximum imped-
ance that is seen looking into the SLIC is the product of
the SLIC transconductance multiplied by the SLIC
receive gain, plus the protection resistors. The various
specified termination impedances can range over the
voiceband as low as 300

up to over 1000

. Thus, if

the SLIC gains are too low, it will be impossible to syn-
thesize the higher termination impedances. Further, the
termination that is achieved will be far less than what is
calculated by assuming a short for SLIC output to SLIC
input. In the receive direction, in order to control echo,
the gain is typically a loss, which requires a loss net-
work at the SLIC RCVN/RCVP inputs, which will
reduce the amount of gain that is available for termina-
tion impedance. For this reason, a high-gain SLIC is
required with a first-generation codec.

With a third-generation codec, the line card designer
has different concerns. To design the ac interface, the
designer must first decide upon all termination imped-
ance, hybrid balances, and transmission level point
(TLP) requirements that the line card must meet. In the
transmit direction, the only concern is that the SLIC
does not provide a signal that is too hot and overloads
the codec input. Thus, for the highest TLP that is being
designed to, given the SLIC gain, the designer, as a
function of voiceband frequency, must ensure the
codec is not overloaded. With a given TLP and a given
SLIC gain, if the signal will cause a codec overload, the
designer must insert some sort of loss, typically a resis-
tor divider, between the SLIC output and codec input.

Note also that some third-generation codecs require
the designer to provide an inherent resistive termina-
tion via external networks. The codec will then provide
gain shaping, as a function of frequency, to meet the
return loss requirements. This feedback will increase
the signal at the codec input and increase the likeli-
hood that a resistor divider is needed in the transmit
direction. Further stability issues may add external
components or excessive ground plane requirements
to the design.

In the receive direction, the issue is to optimize the
S/N. Again, the designer must consider all the consid-
ered TLPs. The idea, for all desired TLPs, is to run the
codec at or as close as possible to its maximum output
signal, to optimize the S/N. Remember, noise floor is
constant, so the hotter the signal from the codec, the
better the S/N. The problem is if the codec is feeding a
high gain SLIC, either an external resistor divider is
needed to knock the gain down to meet the TLP
requirements, or the codec is not operated near maxi-
mum signal levels, thus compromising the S/N.

Thus, it appears that the solution is to have a SLIC with
a low gain, especially in the receive direction. This will
allow the codec to operate near its maximum output
signal (to optimize S/N), without an external resistor
divider (to minimize cost).

To meet the unique requirements of both types of
codecs, the L9216 offers two receive gain choices.
These receive gains are mask-programmable at the
factory and are offered as two different code variations.
For interface with a first-generation codec, the L9216 is
offered with a receive gain of 8. For interface with a
third-generation codec, the L9216 is offered with a
receive gain of 2. In either case, the transconductance
in the transmit direction or the transmit gain is 300

These receive gain options afford the designer the flex-
ibility to maximize performance and minimize external
components, regardless of the type of codec chosen.

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

ac Applications

(continued)

Design Examples

First-Generation Codec ac Interface Network--
Resistive Termination

The reference circuit in Figure 23 shows the complete
SLIC schematic for interface to the Agere T7504 first-
generation codec for a resistive termination imped-
ance. For this example, the ac interface was designed
for a 600

resistive termination and hybrid balance

with transmit gain and receive gain set to 0 dBm.

This is a lower feature application example and uses
single battery operation, fixed overhead, current limit,
and loop closure threshold.

Resistor R

is optional. It compensates for any mis-

match of input bias voltage at the RCVN/RCVP inputs.
If it is not used, there may be a slight offset at tip and
ring due to mismatch of input bias voltage at the
RCVN/RCVP inputs. It is very common to simply tie
RCVN directly to ground in this particular mode of oper-
ation. If used, to calculate RGN, the impedance from
RCVN to ac ground should equal the impedance from
RCVP to ac ground.

Example 1, Real Termination

The following design equations refer to the circuit in
Figure 22. Use these to synthesize real termination
impedance.

Termination Impedance:

Receive Gain:

Transmit Gain:

Hybrid Balance:

bal

= 20log

bal

= 20log

To optimize the hybrid balance, the sum of the currents
at the VFX input of the codec op amp should be set to
0. The expression for ZHB becomes the following:

T/R

------------

2400

T 1

G P

---------

T 1

R CV

------------

-----------------------------------

rcv

T/R

------------

rcv

R CV

T 1

-----------

R C V

G P

------------

T/R

---------

------------------------------------------------------------------

GSX

T/R

-----------

t x

T 2

---------

300

T/R

---------

------------

rcv

GSX

F R

---------------

H B

( )

rcv

-------------------

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

ac Applications

(continued)

Design Examples

(continued)

Example 1, Real Termination (continued)

0586 (F)

Figure 22. ac Equivalent Circuit

Figure 23. Agere T7504 First-Generation Codec Resistive Termination

T/R

RING

= 1

VITR

CURRENT

SENSE

TIP

RCV

HB1

RCVN

RCVP

VGSX

1/4 T7504 CODEC

+2.4 V

0.300 V/mA

= 4

L9216

BAT1

BGND V

BAT2

AGND

ICM

RGDET

BAT1

0.1

BAT2

0.1

RTFLT

DCOUT

REF

0.1

383 k

AGERE

L7591

BAT1

FUSIBLE OR PTC

CF1

CF2

rate of battery

reversal not

ramped

FB1 FB2 NSTAT B2 B1 B0

0.22

0.1

RING

VITR

RCVP

RCVN

ITR

VTX

TXI

4750

BAT1

BAT2

0.1

0.47

1/4 T7504

CODEC

GSX

+2.4 V

HB1

VFXIN

RCV

FRO

FSE

FSEP

MCLK

ASEL

CONTROL

INPUTS

SYNC

AND

PCM

HIGHWAY

CLOCK

49.9 k

100 k

60.4 k

0.1

17.65 k

26.7 k

69.8 k

0.1 µF

L9216A

FUSIBLE OR PTC

PROG

REF

12 k

1.0

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

ac Applications

(continued)

Design Examples

(continued)

Example 1, Real Termination (continued)

Table 24. Parts List L9216; Agere T7504 First-Generation Codec Resistive Termination; Nonmeter Pulse

Application

Notes:
Termination Impedance = 600

Hybrid Balance = 600

Tx = 0 dBm.

Rx = 0 dBm.

Name

Value

Tolerance

Rating

Function

Fault Protection
R

Fusible or PTC Protection resistor.

Protector

Agere L7591

Secondary protection.

Power Supply
C

BAT1

0.1

20%

100 V

BAT

filter capacitor.

BAT2

0.1

20%

50 V

BAT

filter capacitor. |V

BAT2

| < |V

BAT1

1N4004

Reverse current.

0.1

20%

10 V

filter capacitor.

0.22

20%

100 V

Filter capacitor.

0.1

20%

100 V

Filter capacitor.

Ring/Ring Trip
C

1.0

20%

10 V

Ring filter for square wave.

0.47

20%

10 V

ac-couple input ring signal.

12 k

1/16 W

Ring filter for square wave.

0.1

20%

10 V

Ring trip filter capacitor.

383 k

1/16 W

Ring trip filter resistor.

ac Interface
R

4750

1/16 W

Sets T/R to VITR transconductance.

0.1

20%

10 V

ac/dc separation.

0.1

20%

10 V

dc blocking capacitor.

0.1

20%

10 V

dc blocking capacitor.

69.8 k

1/16 W

With R

and R

RCV

, sets termination impedance

and receive gain.

49.9 k

1/16 W

With R

, sets transmit gain.

100 k

1/16 W

With R

, sets transmit gain.

HB1

100 k

1/16 W

With R

, sets hybrid balance.

RCV

60.4 k

1/16 W

With R

and R

, sets termination impedance

and receive gain.

26.7 k

1/16 W

With R

RCV

and R

, sets termination impedance

and receive gain.

Optional

17.6 k

1/16 W

Optional. Compensates for input offset at
RCVN/RCVP.

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

ac Applications

(continued)

Design Examples

(continued)

First-Generation Codec ac Interface Network--
Complex Termination

The reference circuit in Figure 26 shows the complete
SLIC schematic for interface to the Agere T7504 first-
generation codec for the German complex termination
impedance. For this example, the ac interface was
designed for a 220

+ (820

|| 115 nF) complex

termination and hybrid balance with transmit gain and
receive gain set to 0 dBm. For illustration purposes,
1 Vrms PPM injection was assumed in this example.
This implies the overhead voltage is increased to
7.24 V and no meter pulse rejection is required. Also,
this example illustrates the device using fixed overhead
and current limit.

Complex Termination Impedance Design Example

The gain shaping necessary for a complex termination
impedance may be done by shaping across the AX
amplifier at nodes ITR and VTX.

Complex termination is specified in the form:

5-6396(F)

To work with this application, convert termination to the
form:

5-6398(F)

where:

´ = R

+ R

´ =

+ R

)

C´ =

ac Interface Using First-Generation Codec

TGS

): these components give gain shap-

ing to get good gain flatness. These components are a
scaled version of the specified complex termination
impedance.

Note for pure (600

) resistive terminations, compo-

nents R

TGS

and C

are not used. Resistor R

is used

and is still 4750

: with other components set, the transmit gain

(for complex and resistive terminations) R

and R

are

varied to give specified transmit gain.

RCV

: for both complex and resistive termina-

tions, the ratio of these resistors sets the receive gain.
For resistive terminations, the ratio of these resistors
sets the return loss characteristic. For complex termi-
nations, the ratio of these resistors sets the low-fre-
quency return loss characteristic.

: for complex terminations, these compo-

nents provide high-frequency compensation to the
return loss characteristic.

For resistive terminations, these components are not
used and RCVN is connected to ground via a resistor.

: sets hybrid balance for all terminations.

Set Z

--Gain Shaping:

= R

|| R

TGS

+ C

which is a scaled version of

T/R

(the specified termination resistance) in the

´ || R

´ + C´ form.

must be 4750

to set SLIC transconductance to

300 V/A.

= 4750

At dc, C

and C´ are open.

= M x R

where M is the scale factor.

M =

It can be shown:

TGS

= M x R

and

TGS

C´

-------

---------------------

4750

--------------

------

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

ac Applications

(continued)

Design Examples

(continued)

Transmit Gain

Transmit gain will be specified as a gain from T/R to
PCM, T

(dB). Since PCM is referenced to 600

and

assumed to be 0 dB, and in the case of T/R being refer-
enced to some complex impedance other than 600

resistive, the effects of the impedance transformation
must be taken into account.

Again, specified complex termination impedance at T/R
is of the form:

5-6396(F)

First, calculate the equivalent resistance of this network
at the midband frequency of 1000 Hz.

Using R

, calculate the desired transmit gain, taking

into account the impedance transformation:

(dB) = T

X (specified[dB])

+ 20log

X (specified[dB])

is the specified transmit gain. 600

is the

impedance at the PCM, and R

is the impedance at

tip and ring. 20log

represents the power

loss/gain due to the impedance transformation.

Note that in the case of a 600

pure resistive termina-

tion

at T/R 20log

= 20log

= 0.

Thus, there is no power loss/gain due to impedance
transformation and T

(dB) = T

X (specified[dB])

Finally, convert T

(dB) to a ratio, g

(dB) = 20log g

The ratio of R

is used to set the transmit gain:

= g

with a quad Agere codec

such as T7504:

< 200 k

(

)

(

)

-----------------------------------------------------------------------------

(

)

---------------------------------------------------

600

-----------

600

-----------

600

-----------

600
600

----------

318.25

------------------

-----

5-6400.P (F)

Figure 24. Interface Circuit Using First-Generation Codec (Blocking Capacitors Not Shown)

0.1

TGS

4750

ITR

CODEC
OUTPUT
DRIVE
AMP

CODEC

OP AMP

RCV

T/R

318.25

RCVN

RCVP

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

ac Applications

(continued)

Design Examples

(continued)

Receive Gain

Ratios of R

RCV

, R

will set both the low-frequency

termination and receive gain for the complex case. In
the complex case, additional high-frequency compen-
sation, via C

, R

, and R

, is needed for the return

loss characteristic. For resistive termination, C

, R

and R

are not used and RCVN is tied to ground via a

resistor.

Determine the receive gain, g

RCV

, taking into account

the impedance transformation in a manner similar to
transmit gain.

(dB) = R

X (specified[dB])

+ 20log

(dB) = 20log g

RCV

Then:

RCV

and low-frequency termination

TER(low)

+ 2R

+ 50

TER(low)

is the specified termination impedance assum-

ing low frequency (C or C´ is open).

is the series protection resistor.

is the typical internal feed resistance.

These two equations are best solved using a computer
spreadsheet.

Next, solve for the high-frequency return loss compen-
sation circuit, C

, R

, and R

TGP

= R

There is an input offset voltage associated with nodes
RCVN and RCVP. To minimize the effect of mismatch
of this voltage at T/R, the equivalent resistance to ac
ground at RCVN should be approximately equal to that
at RCVP. Refer to Figure 25 (with dc blocking capaci-
tors). To meet this requirement, R

= R

|| R

Hybrid Balance

Set the hybrid cancellation via R

If a 5 V only codec such as the Agere T7504 is used,
dc blocking capacitors must be added as shown in
Figure 25. This is because the codec is referenced to
2.5 V and the SLIC to ground--with the ac coupling, a
dc bias at T/R is eliminated and power associated with
this bias is not consumed.

Typically, values of 0.1 µF to 0.47 µF capacitors are
used for dc blocking. The addition of blocking capaci-
tors will cause a shift in the return loss and hybrid bal-
ance frequency response toward higher frequencies,
degrading the lower-frequency response. The lower
the value of the blocking capacitor, the more pro-
nounced the effect is, but the cost of the capacitor is
lower. It may be necessary to scale resistor values
higher to compensate for the low-frequency response.
This effect is best evaluated via simulation. A

PSPICE

model for the L9216 is available.

Design equation calculations seldom yield standard
component values. Conversion from the calculated
value to standard value may have an effect on the ac
parameters. This effect should be evaluated and opti-
mized via simulation.

600

-----------

RCV

---------------

RCV

---------------

------------------------------------------------

2400

------------

RCV

---------------

--------------------------------------------

2400

-------------

2400

-------------

T GS

T GP

--------------

RCV

-------------------------------

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

ac Applications

(continued)

Design Examples

(continued)

Blocking Capacitors

5-6401.M (F)

Figure 25. ac Interface Using First-Generation Codec (Including Blocking Capacitors) for Complex Termi-

nation Impedance

Figure 26. Agere T7504 First-Generation Codec Complex Termination

0.1

TGS

VTX

4750

TXI

VITR

CODEC

OUTPUT

DRIVE

AMP

CODEC

OP AMP

RCV

T/R

318.25

2.5 V

RCVN

RCVP

BAT1

BGND

BAT2

AGND

ICM

RGDET

ground key

not used

BAT1

0.1

BAT2

0.1

RTFLT

DCOUT

0.1

383 k

AGERE

L7591

BAT1

FUSIBLE

rate of battery

reversal not

ramped

VITR

RCVP

RCVN

ITR

VTX

TXI

4750

TGS

1.74 k

12 nF

BAT1

BAT2

0.1

HB1

RCV

L9216A

CF1

CF2

FB1 FB2

NSTAT

0.22

0.1

RING

0.47

FROM/TO CONTROL

RING

FUSIBLE

47.5 k

54.9 k

127

59.0 k

49.9 k

113 k

120 pF

0.1

40.6 k

REF

OR PTC

VFXIN

+2.4

GSX

VFRO

1/4 T7504

CODEC

PCM

HIGHWAY

SYNC

AND

CLOCK

CONTROL

INPUTS

FSE

FSEP

MCLK

ASEL

PROG

REF

115 k

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

ac Applications

(continued)

Design Examples

(continued)

Blocking Capacitors (continued)

Table 25. Parts List L9216; Agere T7504 First-Generation Codec Complex Termination; Meter Pulse

Application

Termination impedance = 220

+ (820

|| 115 nF), hybrid balance = 220

+ (820

|| 115 nF) Tx = 0 dBm,

Rx = 0 dBm.

Name

Value

Tolerance

Rating

Function

Fault Protection
R

Fusible or PTC Protection resistor.

Protector

Agere

L7591

Secondary protection.

Power Supply
C

BAT1

0.1

20%

100 V

BAT

filter capacitor.

BAT2

0.1

20%

50 V

BAT

filter capacitor. |V

BAT2

| < |V

BAT1

1N4004

Reverse current.

0.1

20%

10 V

filter capacitor.

0.22

20%

100 V

Filter capacitor.

0.1

20%

100 V

Filter capacitor.

Ring/Ring Trip
C

RING

0.47

20%

10 V

ac-couple input ring signal.

0.1

20%

10 V

Ring trip filter capacitor.

383 k

1/16 W

Ring trip filter resistor.

ac Interface
R

4750

1/16 W

Sets T/R to VITR transconductance.

TGS

1.74 k

1/16 W

Gain shaping for complex termination.

12 nF

10 V

Gain shaping for complex termination.

0.1

20%

10 V

ac/dc separation.

0.1

20%

10 V

dc blocking capacitor.

0.1

20%

10 V

dc blocking capacitor.

49.9 k

1/16 W

With R

and R

RCV

, sets termination impedance and receive

gain.

40.2 k

1/16 W

With R

, sets transmit gain.

115 k

1/16 W

With R

, sets transmit gain.

HB1

113 k

1/16 W

With R

, sets hybrid balance.

RCV

59.0 k

1/16 W

With R

and R

, sets termination impedance and receive

gain.

54.9 k

1/16 W

With R

RCV

and R

, sets termination impedance and receive

gain.

120 pF

20%

10 V

High frequency compensation.

127 k

1/16 W

High frequency compensation.

47.5 k

1/16 W

High frequency compensation, compensate for dc offset at
RCVP/RCVN.

Preliminary Data Sheet

September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

ac Applications

(continued)

Design Examples

(continued)

Third-Generation Codec ac Interface Network--Complex Termination

The following reference circuit, Figure 27, shows the complete SLIC schematic for interface to the Agere T8536
third-generation codec. All ac parameters are programmed by the T8536. Note this codec differentiates itself in that
no external components are required in the ac interface to provide a dc termination impedance or for stability. For
illustration purposes, 0.5 Vrms PPM injection was assumed in this example and no meter pulse rejection is used.
Also, this example illustrates the device using programmable overhead and current limit. Please see the T8535/6
data sheet for information on coefficient programming.

Figure 27. Third-Generation Codec ac Interface Network; Complex Termination

BAT1

BGND

BAT2

AGND

ICM

RGDET

ground key

not used

BAT1

0.1

BAT2

0.1

RTFLT

DCOUT

PROG

REF

0.1

383

AGERE

L7591

BAT1

FUSIBLE OR PTC

CF1

CF2

rate of battery

reversal not

ramped

FB1

FB2

NSTAT B2

0.22

0.1

RING

VITR

RCVP

RCVN

ITR

VTX

TXI

4750

BAT1

BAT2

0.1

RING

0.47

PCM

HIGHWAY

DX0

DR0

DX1

DR1

BCLK

DGND

SYNC

AND

VFXI

VFROP

VFRON

SLIC4a

SLIC3a

SLIC2a

SLIC0a

CLOCK

L9216G

FROM/TO

CONTROL

NSTAT

0.1

FUSIBLE OR PTC

CIN

20 M

1/4

T8536/8

Preliminary Data Sheet
September 2001

Short-Loop Ringing SLIC with Ground Start

L9216A/G

Agere Systems Inc.

ac Applications

(continued)

Design Examples

(continued)

Third-Generation Codec ac Interface Network--Complex Termination (continued)

Table 26. Parts List L9216; Agere T8536 Third-Generation Codec ac and dc Parameters; Fully

Programmable

* For loop stability, increase to 50

minimum if synthesizing 900

or 900

+ 2.16

F termination impedance.

Name

Value

Tolerance

Rating

Function

Fault Protection

Fusible or PTC Protection resistor*.

Protector

Agere L7591

Secondary protection.

Power Supply

BAT1

0.1

20%

100 V

BAT

filter capacitor.

BAT2

0.1

20%

50 V

BAT

filter capacitor. |V

BAT2

| < |V

BAT1

1N4004

Reverse current.

0.1

20%

10 V

filter capacitor.

0.22

20%

100 V

Filter capacitor.

0.1

20%

100 V

Filter capacitor.

Ring/Ring Trip

RING

0.47

20%

10 V

ac-couple input ring signal.

0.1

20%

10 V

Ring trip filter capacitor.

383 k

1/16 W

Ring trip filter resistor.

ac Interface

4750

1/16 W

Sets T/R to VITR transconductance.

CIN

20 M

1/16 W

dc bias.

0.1

20%

10 V

ac/dc separation.

0.1

20%

10 V

dc blocking capacitor.

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

September 2001
DS01-301ALC (Replaces DS00-133ALC)

For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:

http://www.agere.com

E-MAIL:

docmaster@agere.com

N. AMERICA:

Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA:

Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
Tel. (852) 3129-2000, FAX (852) 3129-2020
CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen)
JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)

EUROPE:

Tel. (44) 7000 624624, FAX (44) 1344 488 045

IEEE

is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.

PSPICE

is a registered trademark of MicroSim Corporation.

Telcordia Technologies

is a trademark of Bell Communications Research, Inc.

is a trademark of Hewlett-Packard Company.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LUCL9216ARG-D

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LUCL9216ARG-D