Document Outline
- Features
- Applications
- Description
- Pin Information
- Absolute Maximum Ratings
- Electrostatic Discharge Caution
- Electrical Characteristics
- Charge Pump Current
- PLL Programming Information
- Serial Data Input
- Serial Bus Timing Information
- Functional Descriptions
- REF Register
- MAIN Register
- PLL Lock-Detect Function
- Typical Performance Characteristics
- MAIN_IN Input Parallel Equivalent Circuit
- Application Example
- Application Information
- Typical Performance Data
- Outline Diagram
- Manufacturing Information
- Ordering Information
- List of Figures
- Figure 1. Block Diagram with Pinout
- Figure 2. Serial Bus Programming
- Figure 3. Pin Diagram
- Figure 4. Charge Pump Current vs. Voltage
- Figure 5. Serial Bus Timing Diagram
- Figure 6. Register Programming Diagram
- Figure 7. Programming the Phase Detector Slope
- Figure 8. MAIN_IN and REF_IN Sensitivity Test Circuit Diagram
- Figure 9. MAIN_IN Parallel Equivalent Circuit
- Figure 10. Application Circuit Diagram
- Figure 11. Typical PLL Model
- Figure 12. Third-Order Loop Filter
- Figure 13. Charge Pump Current vs. Voltage and Temperature (2.5 mA)
- Figure 14. Charge Pump Current vs. Voltage and Temperature (0.7 mA)
- Figure 16. Charge Pump Current vs. Voltage and Temperature (1.9 mA)
- Figure 15. Charge Pump Current vs. Voltage and Temperature (0.9 mA)
- Figure 17. Prescaler Sensitivity and Maximum Input Level
- Figure 18. Input Impedance Smith Chart: 0.5 GHz to 2.2 GHz Frequency
- Figure 20. Settling Time from 1150 MHz to 1230 MHz 50 Hz
- Figure 19. Phase Noise 1190 MHz, Fcomp = 200 kHz
- Figure 21. PLL Reference Spurs
- Figure 22. Dual-Band Locking
- List of Tables
- Table 1. Pin Descriptions
- Table 2. General Specifications
- Table 3. Electrical Specifications
- Table 4. Charge Pump Specifications
- Table 5. Serial Bus Timing Information
- Table 6. C0:C1: MAIN and REF Register Addressing (Destination of Serial Data) (Bits 1 and 24)
- Table 7. REF Register Bit Description (C0 = 1, C1 = 0)
- Table 8. REF Register
- Table 9. R1:R11: Reference Divider Ratio (Bits 2 to 12)
- Table 10. D1: Forced Counter Reload (Bit 13)
- Table 11. D2: Charge Pump Off Mode (Bit 14)
- Table 12. Band and Charge Pump Current (Band 1, Bits 18 and 19; Band 2, Bits 15 and 16)
- Table 13. D5: Phase Detector Polarity (Bit 17)
- Table 14. RE: Reset (Bit 20)
- Table 15. ERES: External Resistor Setting for Charge Pump Current (Bit 21)
- Table 16. EN1: Synthesizer Enable (Bit 22)
- Table 17. LD: Lock Detect Enable (Bit 23)
- Table 18. MAIN Register Bit Description (C0 = 0, C1 = 0)
- Table 19. MAIN Register
- Table 20. A1:A7: Swallow Counter Count (Bits 2 to 8)
- Table 21. M1:M11: Programmable Main Counter Divide Ratio (Bits 9 to 19)
- Table 22. EN2: Synthesizer Enable (Bit 22)
- Table 23. B: Band Select (Bit 23)
- Table 24. MAIN_IN Input Parallel Equivalent Circuit Values
- Contact Us
W3000 PLL Dual-Band Frequency Synthesizer
Advance Data Sheet
December 1999
Features
+
2.2 GHz operational
+
Dual-band optimized
+
Low supply current (5.1 mA)
+
Surface-mount 14-pin TSSOP package
+
Scaled PD gain for dual-band operation
+
Programmable phase-detector polarity
+
Synchronous or forced counter update loading
+
Powerdown mode via external pin or serial bus
+
Low-load capacitance on reference input buffer
Applications
+
GSM900/1800/1900
+
North American IS-136/137
+
Personal Digital Cellular (Japan RCR-27)
+
Personal Handy Phone (Japan RCR-28)
+
CDMA (IS-95)
PHASE
DETECTOR
REF_IN
LD
TCXO
R
11-BIT COUNTER
V
DDC
PRESCALER
64/65
MAIN_IN
M
11-BIT COUNTER
A
7-BIT COUNTER
RREF
HIGH-PRECISION
CURRENT
REFERENCE
V
DDC
CONTROL
LOGIC
24-BIT SERIAL
SHIFT REGISTER
LAT
DAT
CLK
IPD SETTING
PD POLARITY
IREF
IREF
VCO BAND A
VCO BAND B
BAND
IPD SETTING
PD POLARITY
V
CP
OFF CHIP
Figure 1. Block Diagram with Pinout
Advance Data Sheet
W3000 PLL Dual-Band Frequency Synthesizer
December 1999
Lucent Technologies Inc.
2
Table of Contents
Features...............................................................................................................................................................1
Applications .........................................................................................................................................................1
Description ...........................................................................................................................................................3
Pin Information.....................................................................................................................................................4
Absolute Maximum Ratings..................................................................................................................................5
Electrostatic Discharge Caution............................................................................................................................5
Electrical Characteristics ......................................................................................................................................6
Charge Pump Current ..........................................................................................................................................7
PLL Programming Information .............................................................................................................................8
Serial Data Input ..................................................................................................................................................9
Serial Bus Timing Information ..............................................................................................................................9
Functional Descriptions ......................................................................................................................................10
REF Register .....................................................................................................................................................11
MAIN Register....................................................................................................................................................15
PLL Lock-Detect Function ..................................................................................................................................17
Typical Performance Characteristics ..................................................................................................................17
MAIN_IN Input Parallel Equivalent Circuit.......................................................................................................18
Application Example ..........................................................................................................................................18
Application Information ......................................................................................................................................19
Typical Performance Data..................................................................................................................................22
Outline Diagram .................................................................................................................................................26
14-Pin TSSOP................................................................................................................................................26
Manufacturing Information .................................................................................................................................27
Ordering Information ..........................................................................................................................................27
Advance Data Sheet
December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Lucent Technologies Inc.
3
Description
The W3000 is a high-performance UHF RF PLL synthesizer, designed for use in digital wireless communication
applications. Particular emphasis in the design has been placed on dual-band applications, with near-seamless
switching between operational bands without the need for external loop-filter circuitry other than that required for
single band applications. In combination with a suitable reference crystal, UHF VCO, and associated loop-filter
components, the W3000 offers a very low-noise oscillator solution.
The reference signal is divided by a programmable 11-bit counter to provide a wide range of comparison
frequencies, allowing compliance with the various standards. The reference input is rising-edge triggered, and we
recommend that an inverting buffer be used when the W3000 is interfaced to a commercial TCXO.
The MAIN_IN signal normally associated with the UHF VCO is fed into a dual modulus prescaler (64/65) and is
then divided by the 11-bit main counter to be compared to the output of the reference counter in a digital phase
detector.
The W3000 is implemented with programmable charge-pump currents to allow fast switching between bands for
dual-band applications,
without changing the loop filter. The charge pump can be programmed internally, or
externally with a resistor (recommended). Charge pump outputs can be disabled, thereby allowing open-loop
VCO modulation schemes.
With synchronous reloading, the counter reloads a new programmed value when the counter reaches zero. With
forced counter reloading, the reloading occurs when the programmed word is latched in. These techniques can
improve lock time when performing a dual-band hop or in start-up conditions.
The W3000 uses a standard 3-wire programming bus (data, enable, clock) that operates up to 10 MHz. This
serial interface is via a 24-bit word that incorporates both register addressing and device addressing allowing two
chips to share the bus.
TR REGISTER
CONFIG REGISTER
MAIN REGISTER
REF REGISTER
MAIN REGISTER
SC1
PARALLEL LATCH
SERLE1
SERCK
SERDA
SERIAL SHIFT
ADDRESS DECODER
ADDRESS
DECODER
PARALLEL LATCH
A[0:2]
CLK
DAT
SERIAL SHIFT
A[0:2]
LAT
DAT
CLK
LAT
W3020
W3000
Figure 2. Serial Bus Programming
Advance Data Sheet
W3000 PLL Dual-Band Frequency Synthesizer
December 1999
Lucent Technologies Inc.
4
Pin Information
V
DDC
CPOUT
V
SS
1
MAIN_IN
LAT
DAT
LOCKDET
REF_IN
PWRDN
CLK
RES
14
13
8
10
11
12
9
1
2
7
5
4
3
6
V
SS
2
V
DD
1
V
DD
2
Figure 3. Pin Diagram
Table 1. Pin Descriptions
Pin
Symbol
Function
Name/Description
1
V
DDC
Supply
Charge Pump Positive Supply Voltage. Must be
V
DD
. (V
DD
= V
DD
1 = V
DD
2).
2
CPOUT
Output
Charge Pump Output.
3
V
SS
1
Ground
Ground 1. Charge pump and logic ground.
4
V
SS
2
Ground
Ground 2. Prescaler and reference ground.
5
MAIN_IN
Input
VCO Signal Input. Must be ac-coupled.
6
V
DD
1
Supply
Voltage Supply 1. Prescaler supply voltage.
7
V
DD
2
Supply
Voltage Supply 2. Logic and reference supply (must be equal to V
DD
1).
8
LOCKDET
Output
Lock Detect Output.
9
RES
Input
External Resistor Input. Add resistor to V
DDC
if required (>10 k
).
10
REF_IN
Input
Reference Frequency Input. Connection from reference oscillator. Must be ac-
coupled.
11
PWRDN
Input
Powerdown. For low current operation. (Low is powerdown mode.)
12
CLK
Input
Serial Input. Programming clock line.
13
DAT
Input
Serial Input. Programming data line.
14
LAT
Input
Serial Input. Programming latch line.
Advance Data Sheet
December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Lucent Technologies Inc.
5
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.
Parameter
Symbol
Min
Max
Unit
Ambient Operating Temperature
T
A
30
85
C
Storage Temperature
T
stg
65
150
C
Lead Temperature (soldering, 10 s)
T
L
--
300
C
Positive Supply Voltage
V
DD
0
4.5
Vdc
Positive Charge Pump Supply Voltage
V
DDC
0
4.5
Vdc
Power Dissipation
P
D
--
250
mW
ac Input Voltage
--
0
V
DD
Vp-p
Digital Voltages
--
Vss 0.3
V
DD +
0.3
Vdc
Electrostatic Discharge Caution
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid
exposure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies Microelectronics
Group employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing
and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define
the model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance =
1500
, capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes.
Parameter
Model
Min
Max
Unit
ESD Threshold Voltage
HBM
1000
--
V
ESD Threshold Voltage (corner pins)
CDM
1000
--
V
ESD Threshold Voltage (noncorner pins)
CDM
1500
--
V
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