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Data Sheet
June 1999
ORCA
Series 3C and 3T
Field-Programmable Gate Arrays
Features
s
High-performance, cost-effective, 0.35 m (OR3C) and
0.3 m (OR3T) 4-level metal technology, (4- or 5-input
look-up table delay of 1.1 ns with -7 speed grade in
0.3 m).
s
Same basic architecture as lower-voltage, advanced
process technology Series 3 architectures. (See
ORCA
Series 3L FPGA documentation.)
s
Up to 186,000 usable gates.
s
Up to 452 user I/Os. (OR3Txxx I/Os are 5 V tolerant to
allow interconnection to both 3.3 V and 5 V devices,
selectable on a per-pin basis.)
s
Pin selectable I/O clamping diodes provide 5 V or 3.3 V
PCI compliance and 5 V tolerance on OR3Txxx devices.
s
Twin-quad programmable function unit (PFU) architec-
ture with eight 16-bit look-up tables (LUTs) per PFU,
organized in two nibbles for use in nibble- or byte-wide
functions. Allows for mixed arithmetic and logic functions
in a single PFU.
s
Nine user registers per PFU, one following each LUT,
plus one extra. All have programmable clock enable and
local set/reset, plus a global set/reset that can be dis-
abled per PFU.
s
Flexible input structure (FINS) of the PFUs provides a
routability enhancement for LUTs with shared inputs and
the logic flexibility of LUTs with independent inputs.
s
Fast-carry logic and routing to adjacent PFUs for nibble-,
byte-wide, or longer arithmetic functions, with the option
to register the PFU carry-out.
s
Softwired LUTs (SWL) allow fast cascading of up to
three levels of LUT logic in a single PFU for up to 40%
speed improvement.
s
Supplemental logic and interconnect cell (SLIC) provides
3-statable buffers, up to 10-bit decoder, and
PAL*-like
AND-OR with optional INVERT in each programmable
logic cell (PLC), with over 50% speed improvement typi-
cal.
s
Abundant hierarchical routing resources based on rout-
ing two data nibbles and two control lines per set provide
for faster place and route implementations and less rout-
ing delay.
s
TTL or CMOS input levels programmable per pin for the
OR3Cxx (5.0 V) devices.
s
Individually programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source.
s
Built-in boundary scan (
IEEE
1149.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
s
Enhanced system clock routing for low skew, high-speed
clocks originating on-chip or at any I/O.
s
Up to four ExpressCLK inputs allow extremely fast clock-
ing of signals on- and off-chip plus access to internal
general clock routing.
s
StopCLK feature to glitchlessly stop/start ExpressCLKs
independently by user command.
s
Programmable I/O (PIO) has:
-- Fast-capture input latch and input flip-flop (FF) latch
for reduced input setup time and zero hold time.
-- Capability to (de)multiplex I/O signals.
-- Fast access to SLIC for decodes and
PAL-like
functions.
-- Output FF and two-signal function generator to
reduce CLK to output propagation delay.
-- Fast open-drain dive capability
-- Capability to register 3-state enable signal.
s
Baseline FPGA family used in Series 3+ FPSCs (field
programmable system chips) which combine FPGA logic
and standard cell logic on one device.
*
PAL
is a trademark of Advanced Micro Devices, Inc.
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1.
ORCA
Series 3 (3C and 3T) FPGAs
The system gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per
PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch,
output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing
a 32 x 4 RAM (or 512 gates) per PFU.
Device
System
Gates
LUTs
Registers
Max User RAM
User I/Os
Array Size
Process
Technology
OR3T20
36K
1152
1872
18K
196
12 x 12
0.3 m/4 LM
OR3T30
48K
1568
2436
25K
228
14 x 14
0.3 m/4 LM
OR3C/3T55
80K
2592
3780
42K
292
18 x 18
0.3 m/4 LM
OR3C/3T80
116K
3872
5412
62K
356
22 x 22
0.3 m/4 LM
OR3T125
186K
6272
8400
100K
452
28 x 28
0.3 m/4 LM
Table of Contents
Contents
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Contents
Page
2
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Features ......................................................................1
System-Level Features................................................6
Description...................................................................7
FPGA Overview ........................................................7
PLC Logic ..................................................................7
PIC Logic ...................................................................8
System Features .......................................................8
Routing ......................................................................8
Configuration .............................................................8
ORCA
Foundry Development System ......................9
Architecture .................................................................9
Programmable Logic Cells ........................................11
Programmable Function Unit ..................................11
Look-Up Table Operating Modes ............................13
Supplemental Logic and Interconnect Cell (SLIC) ..21
PLC Latches/Flip-Flops ...........................................25
PLC Routing Resources ..........................................27
PLC Architectural Description .................................34
Programmable Input/Output Cells .............................36
5 V Tolerant I/O .......................................................37
PCI Compliant I/O ...................................................37
Inputs ......................................................................38
Outputs ....................................................................41
PIC Routing Resources ...........................................44
PIC Architectural Description ..................................45
High-Level Routing Resources..................................47
Interquad Routing ....................................................47
Programmable Corner Cell Routing ........................48
PIC Interquad (MID) Routing ...................................49
Clock Distribution Network ........................................50
PFU Clock Sources .................................................50
Clock Distribution in the PLC Array .........................51
Clock Sources to the PLC Array .............................52
Clocks in the PICs ...................................................52
ExpressCLK Inputs .................................................53
Selecting Clock Input Pins ......................................53
Special Function Blocks ............................................54
Single Function Blocks ............................................54
Boundary Scan ........................................................57
Microprocessor Interface (MPI) .................................64
PowerPC
System ....................................................65
i960
System ............................................................66
MPI Interface to FPGA ............................................67
MPI Setup and Control ............................................68
Programmable Clock Manager (PCM) ......................72
PCM Registers ........................................................73
Delay-Locked Loop (DLL) Mode .............................75
Phase-Locked Loop (PLL) Mode ............................76
PCM/FPGA Internal Interface .................................79
PCM Operation .......................................................79
PCM Detailed Programming ...................................80
PCM Applications ....................................................83
PCM Cautions ........................................................ 84
FPGA States of Operation ........................................ 85
Initialization ............................................................. 85
Configuration .......................................................... 86
Start-Up .................................................................. 87
Reconfiguration ...................................................... 88
Partial Reconfiguration ........................................... 88
Other Configuration Options ................................... 88
Configuration Data Format ...................................... 89
Using
ORCA
Foundry to Generate
Configuration RAM Data ....................................... 89
Configuration Data Frame ...................................... 89
Bit Stream Error Checking ...................................... 91
FPGA Configuration Modes...................................... 92
Master Parallel Mode ............................................. 92
Master Serial Mode ................................................ 93
Asynchronous Peripheral Mode ............................. 94
Microprocessor Interface (MPI) Mode .................... 94
Slave Serial Mode .................................................. 97
Slave Parallel Mode ............................................... 97
Daisy-Chaining ....................................................... 98
Daisy-Chaining with Boundary Scan ...................... 99
Absolute Maximum Ratings.................................... 100
Recommended Operating Conditions .................. 100
Electrical Characteristics ........................................ 101
Timing Characteristics ............................................ 103
Description ........................................................... 103
PFU Timing ......................................................... 104
PLC Timing ........................................................... 111
SLIC Timing .......................................................... 111
PIO Timing ........................................................... 112
Special Function Blocks Timing ........................... 115
Clock Timing ......................................................... 123
Configuration Timing ............................................ 133
Readback Timing ................................................. 142
Input/Output Buffer Measurement Conditions ........ 143
Output Buffer Characteristics ................................. 144
OR3Cxx ................................................................ 144
OR3Txxx .............................................................. 145
Estimating Power Dissipation ................................. 146
OR3Cxx ................................................................ 146
OR3Txxx (Preliminary Information) ...................... 147
Pin Information ....................................................... 149
Pin Descriptions ................................................... 149
Package Compatibility .......................................... 153
Compatibility with OR2C/TxxA Series .................. 154
Package Thermal Characteristics........................... 194
JA ....................................................................... 194
JC ...................................................................... 194
JC ...................................................................... 194
JB ...................................................................... 194
FPGA Maximum Junction Temperature ............... 195
Table of Contents
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Contents
Page
Lucent Technologies Inc.
3
ORCA Series 3C and 3T FPGAs
June 1999
Data Sheet
Package Coplanarity ...............................................196
Package Parasitics ..................................................196
Package Outline Diagrams......................................197
Terms and Definitions ...........................................197
208-Pin SQFP .......................................................198
208-Pin SQFP2 .....................................................199
240-Pin SQFP .......................................................200
240-Pin SQFP2 .....................................................201
256-Pin PBGA .......................................................202
352-Pin PBGA .......................................................203
432-Pin EBGA .......................................................204
600-Pin EBGA .......................................................205
Ordering Information................................................206
Index........................................................................207
Tables
Table 1.
ORCA
Series 3 (3C and 3T) FPGAs ............ 2
Table 2.
ORCA
Series 3 System Performance .......... 6
Table 3. Look-Up Table Operating Modes ............... 13
Table 4. Control Input Functionality .......................... 14
Table 5. Ripple Mode Equality Comparator
Functions and Outputs ............................................ 18
Table 6. SLIC Modes ................................................ 21
Table 7. Configuration RAM Controlled
Latch/Flip-Flop Operation ........................................ 25
Table 8. Inter-PLC Routing Resources ..................... 31
Table 9. PIO Options ................................................ 37
Table 10. PIO Logic Options .................................... 43
Table 11. PIO Register Control Signals .................... 43
Table 12. Readback Options .................................... 54
Table 13. Boundary-Scan Instructions ..................... 58
Table 14. Boundary-Scan ID Code ........................... 59
Table 15. TAP Controller Input/Outputs ................... 61
Table 16.
PowerPC
/MPI Configuration ..................... 65
Table 17.
i960
/MPI Configuration ............................. 66
Table 18. MPI Internal Interface Signals .................. 67
Table 19. MPI Setup and Control Registers ............. 68
Table 20. MPI Setup and Control Registers
Description ............................................................... 68
Table 21. MPI Control Register 2 ............................. 69
Table 22. Status Register ......................................... 70
Table 23. Device ID Code ........................................ 71
Table 24. Series 3 Family and Device ID Values ..... 71
Table 25.
ORCA
Series 3 Device ID Descriptions .... 71
Table 26. PCM Registers ......................................... 73
Table 27. DLL Mode Delay/1x Duty Cycle
Programming Values ............................................... 75
Table 28. DLL Mode Delay/2x Duty Cycle
Programming Values ............................................... 76
Table 29. PCM Oscillator Frequency Range 3Txxx . 78
Table 30. PCM Oscillator Frequency Range 3Cxx ... 78
Table 31. PCM Control Registers ............................. 80
Table 32. Configuration Frame Format and
Contents .................................................................. 90
Table 33. Configuration Frame Size ......................... 91
Table 34. Configuration Modes ................................ 92
Table 35. Absolute Maximum Ratings .................... 100
Table 36. Recommended Operating Conditions .... 100
Table 37. Electrical Characteristics ........................ 101
Table 38. Derating for Commercial Devices
(OR3Cxx) .............................................................. 103
Table 39. Derating for Industrial Devices (OR3Cxx) 103
Table 40. Derating for Commercial/Industrial
Devices (OR3Txxx) ............................................... 103
Table 41. Combinatorial PFU Timing
Characteristics ....................................................... 104
Table 42. Sequential PFU Timing Characteristics .. 106
Table 43. Ripple Mode PFU Timing
Characteristics ....................................................... 107
Table 44. Synchronous Memory Write
Characteristics ....................................................... 109
Table 45. Synchronous Memory Read
Characteristics ....................................................... 110
Table 46. PFU Output MUX and Direct Routing
Timing Characteristics ........................................... 111
Table 47. Supplemental Logic and Interconnect
Cell (SLIC) Timing Characteristics ........................ 111
Table 48. Programmable I/O (PIO) Timing
Characteristics ....................................................... 112
Table 49. Microprocessor Interface (MPI) Timing
Characteristics ....................................................... 115
Table 50. Programmable Clock Manager (PCM)
Timing Characteristics (Preliminary Information) .. 121
Table 51. Boundary-Scan Timing Characteristics .. 122
Table 52. ExpressCLK (ECLK) and Fast Clock
(FCLK) Timing Characteristics .............................. 123
Table 53. General-Purpose Clock Timing
Characteristics (Internally Generated Clock) .........124
Table 54. OR3Cxx ExpressCLK to Output Delay
(Pin-to-Pin) ............................................................ 125
Table 55. OR3Cxx Fast Clock (FCLK) to Output
Delay (Pin-to-Pin) .................................................. 126
Table 56. OR3Cxx General System Clock (SCLK)
to Output Delay (Pin-to-Pin) .................................. 127
Table 57. OR3C/Txxx Input to ExpressCLK (ECLK)
Fast-Capture Setup/Hold Time (Pin-to-Pin) .......... 128
Table 58. OR3C/Txxx Input to Fast Clock
Setup/Hold Time (Pin-to-Pin) ................................ 130
Table 59. OR3C/Txxx Input to General System
Clock (SCLK) Setup/Hold Time (Pin-to-Pin) .......... 132
Table 60. General Configuration Mode Timing
Characteristics ....................................................... 133
Table 61. Master Serial Configuration Mode Timing
Table of Contents
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4
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Characteristics ...................................................... 136
Table 62. Master Parallel Configuration Mode Timing
Characteristics ...................................................... 137
Table 63. Asynchronous Peripheral Configuration Mode
Timing Characteristics ........................................... 138
Table 64. Slave Serial Configuration Mode Timing
Characteristics ...................................................... 139
Table 65. Slave Parallel Configuration Mode
Timing Characteristics ........................................... 140
Table 66. Readback Timing Characteristics ........... 142
Table 67. Pin Descriptions ...................................... 149
Table 68.
ORCA
I/Os Summary ............................. 153
Table 69. Series 3 ExpressCLK Pins ..................... 154
Table 70. OR3T20, OR3T30, OR3C/T55,
OR3C/T80, and OR3T125 208-Pin
SQFP/SQFP2 Pinout ............................................ 155
Table 71. OR3T20, OR3T30, OR3C/T55,
OR3C/T80, and OR3T125 240-Pin
SQFP/SQFP2 Pinout ............................................ 161
Table 72. OR3T20, OR3T30, and OR3C/T55
256-Pin PBGA Pinout ............................................ 168
Table 73. OR3T20, OR3T30, OR3C/T55,
OR3C/T80, and OR3T125 352-Pin PBGA Pinout . 172
Table 74. OR3C/T80 and OR3T125 432-Pin
EBGA Pinout ......................................................... 182
Table 75. OR3T125 600-Pin EBGA Pinout ............ 187
Table 76. Plastic Package Thermal
Characteristics for the
ORCA
Series ..................... 195
Table 77. Package Coplanarity .............................. 196
Table 78. Package Parasitics ................................. 196
Table 79. Voltage Options ...................................... 206
Table 80. Temperature Options ............................. 206
Table 81. Package Options .................................... 206
Table 82.
ORCA
Series 3 Package Matrix ............. 206
Table 83. Speed Grade Options ............................. 206
Figures
Figure 1. OR3C/T55 Array ........................................ 10
Figure 2. PFU Ports .................................................. 11
Figure 3. Simplified PFU Diagram ............................ 12
Figure 4. Simplified F4 and F5 Logic Modes ............ 14
Figure 5. Softwired LUT Topology Examples ........... 15
Figure 6. Ripple Mode .............................................. 16
Figure 7. Counter Submode ..................................... 17
Figure 8. Multiplier Submode .................................... 18
Figure 9. Memory Mode ........................................... 19
Figure 10. Memory Mode Expansion Example--
128 x 8 RAM ........................................................... 20
Figure 11. SLIC All Modes Diagram ......................... 22
Figure 12. Buffer Mode ............................................. 22
Figure 13. Buffer-Buffer-Decoder Mode ................... 23
Figure 14. Buffer-Decoder-Buffer Mode ................... 23
Figure 15. Buffer-Decoder-Decoder Mode ............... 24
Figure 16. Decoder Mode ......................................... 24
Figure 17. Latch/FF Set/Reset Configurations ......... 26
Figure 18. Configurable Interconnect Point .............. 27
Figure 19. Single PLC View of Inter-PLC Route
Segments ................................................................ 28
Figure 20. Multiple PLC View of Inter-PLC Routing . 32
Figure 21. PLC Architecture .....................................35
Figure 22. OR3C/Txxx Programmable Input/Output
(PIO) Image from
ORCA
Foundry ........................... 36
Figure 23. Fast-Capture Latch and Timing ............... 39
Figure 24. PIO Input Demultiplexing ......................... 40
Figure 25. Output Multiplexing (OUT1OUT2 Mode) . 42
Figure 26. Output Multiplexing
(OUT2OUTREG Mode) ........................................... 42
Figure 27. PIC Architecture ...................................... 46
Figure 28. Interquad Routing .................................... 47
Figure 29. hIQ Block Detail ....................................... 48
Figure 30. Top (TMID) Routing ................................. 49
Figure 31. PFU Clock Sources ................................. 50
Figure 32.
ORCA
Series 3 System Clock
Distribution Overview .............................................. 51
Figure 33. PIC System Clock Spine Generation ...... 52
Figure 34. ExpressCLK and Fast Clock Distribution 53
Figure 35. Top CLKCNTRL Function Block .............. 56
Figure 36. Printed-Circuit Board with Boundary-
Scan Circuitry .......................................................... 57
Figure 37. Boundary-Scan Interface ......................... 58
Figure 38.
ORCA
Series Boundary-Scan Circuitry
Functional Diagram ................................................. 60
Figure 39. TAP Controller State Transition Diagram 61
Figure 40. Boundary-Scan Cell ................................ 62
Figure 41. Instruction Register Scan Timing
Diagram ................................................................... 63
Figure 42. MPI Block Diagram .................................. 64
Figure 43.
PowerPC
/MPI .......................................... 65
Figure 44.
i960
/MPI ..................................................66
Figure 45. PCM Block Diagram ................................ 72
Figure 46. PCM Functional Block Diagram .............. 74
Figure 47. ExpressCLK Delay Minimization Using
the PCM .................................................................. 76
Figure 48. Clock Phase Adjustment Using the PCM 83
Figure 49. FPGA States of Operation ....................... 85
Figure 50. Initialization/Configuration/Start-Up
Waveforms .............................................................. 86
Figure 51. Start-Up Waveforms ................................ 88
Figure 52. Serial Configuration Data Format--
Autoincrement Mode ............................................... 90
Figure 53. Serial Configuration Data Format--
Table of Contents
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Contents
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Lucent Technologies Inc.
5
ORCA Series 3C and 3T FPGAs
June 1999
Data Sheet
Explicit Mode ........................................................... 90
Figure 54. Master Parallel Configuration Schematic 92
Figure 55. Master Serial Configuration Schematic ... 93
Figure 56. Asynchronous Peripheral Configuration .. 94
Figure 57.
PowerPC
/MPI Configuration Schematic .. 95
Figure 58.
i960
/MPI Configuration Schematic .......... 95
Figure 59. Configuration Through MPI ..................... 95
Figure 60. Readback Through MPI .......................... 96
Figure 61. Slave Serial Configuration Schematic ..... 97
Figure 62. Slave Parallel Configuration Schematic .. 97
Figure 63. Daisy-Chain Configuration Schematic ..... 98
Figure 64. Combinatorial PFU Timing .................... 105
Figure 65. Synchronous Memory Write
Characteristics ...................................................... 109
Figure 66. Synchronous Memory Read Cycle ........ 110
Figure 67. MPI
PowerPC
User Space Read Timing 117
Figure 68. MPI
PowerPC
User Space Write Timing 117
Figure 69. MPI
PowerPC
Internal Read Timing ..... 118
Figure 70. MPI
PowerPC
Internal Write Timing ...... 118
Figure 71. MPI
i960
User Space Read Timing ....... 119
Figure 72. MPI
i960
User Space Write Timing ....... 119
Figure 73. MPI
i960
Internal Read Timing .............. 120
Figure 74. MPI
i960
Internal Write Timing .............. 120
Figure 75. Boundary-Scan Timing Diagram ........... 122
Figure 76. ExpressCLK to Output Delay ................ 125
Figure 77. Fast Clock to Output Delay ................... 126
Figure 78. System Clock to Output Delay .............. 127
Figure 79. Input to ExpressCLK Setup/Hold Time .. 129
Figure 80. Input to Fast Clock Setup/Hold Time ..... 131
Figure 81. Input to System Clock Setup/Hold Time 132
Figure 82. General Configuration Mode Timing
Diagram ................................................................. 135
Figure 83. Master Serial Configuration Mode
Timing Diagram ..................................................... 136
Figure 84. Master Parallel Configuration Mode
Timing Diagram ..................................................... 137
Figure 85. Asynchronous Peripheral Configuration
Mode Timing Diagram ........................................... 138
Figure 86. Slave Serial Configuration Mode
Timing Diagram ..................................................... 139
Figure 87. Slave Parallel Configuration Mode
Timing Diagram ..................................................... 140
Figure 88. Readback Timing Diagram .................... 142
Figure 89. ac Test Loads ........................................ 143
Figure 90. Output Buffer Delays .............................143
Figure 91. Input Buffer Delays ................................ 143
Figure 92. Sinklim (T
J
= 25 C, V
DD
= 5.0 V) .......... 144
Figure 93. Slewlim (T
J
= 25 C, V
DD
= 5.0 V) .........144
Figure 94. Fast (T
J
C, V
DD
= 5.0 V) ......................144
Figure 95. Sinklim (T
J
= 125 C, V
DD
= 4.5 V) ........ 144
Figure 96. Slewlim (T
J
= 125 C, V
DD
= 4.5 V) ....... 144
Figure 97. Fast (T
J
= 125 C, V
DD
= 4.5 V) ............ 144
Figure 98. Sinklim (T
J
= 25 C, V
DD
= 3.3 V) .......... 145
Figure 99. Slewlim (T
J
= 25 C, V
DD
= 3.3 V) .........145
Figure 100. Fast (T
J
= 25 C, V
DD
= 3.3 V) ............ 145
Figure 101. Sinklim (T
J
= 125 C, V
DD
= 3.0 V) ...... 145
Figure 102. Slewlim (T
J
= 125 C, V
DD
= 3.0 V) ..... 145
Figure 103. Fast (T
J
= 125 C, V
DD
= 3.0 V) .......... 145
Figure 104. Package Parasitics .............................. 196
6
6
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
System-Level Features
System-level features reduce glue logic requirements
and make a system on a chip possible. These features
in the
ORCA
Series 3 include:
s
Full PCI local bus compliance.
s
Dual-use microprocessor interface (MPI) can be
used for configuration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA. Glueless interface to
i960
* and
PowerPC
processors with user-configurable
address space provided.
s
Parallel readback of configuration data capability with
the built-in microprocessor interface.
s
Programmable clock manager (PCM) adjusts clock
phase and duty cycle for input clock rates from
5 MHz to 120 MHz. The PCM may be combined with
FPGA logic to create complex functions, such as dig-
ital phase-locked loops (DPLL), frequency counters,
and frequency synthesizers or clock doublers. Two
PCMs are provided per device.
s
True, internal, 3-state, bidirectional buses with simple
control provided by the SLIC.
s
32 x 4 RAM per PFU, configurable as single- or dual-
port at >176 MHz. Create large, fast RAM/ROM
blocks (128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
*
i960
is a registered trademark of Intel Corporation.
PowerPC
is a registered trademark of International Business
Machines Corporation.
Table 2.
ORCA
Series 3 System Performance
1. Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 32 x 12 ROMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (7 of 15 PFUs contain only pipelining registers).
4. Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.
5. Implemented using 32 x 4 dual-port RAM mode.
6. Implemented in one partially occupied SLIC with decoded output set up to CE in same PLC.
7. Implemented in five partially occupied SLICs.
Parameter
# PFUs
Speed
Unit
-4
-5
-6
-7
16-bit Loadable Up/Down Counter
2
78
102
131
168
MHz
16-bit Accumulator
2
78
102
131
168
MHz
8 x 8 Parallel Multiplier:
Multiplier Mode, Unpipelined
1
ROM Mode, Unpipelined
2
Multiplier Mode, Pipelined
3
11.5
8
15
19
51
76
25
66
104
30
80
127
38
102
166
MHz
MHz
MHz
32 x 16 RAM (synchronous):
Single-port, 3-state Bus
4
Dual-port
5
4
4
97
127
127
166
151
203
192
253
MHz
MHz
128 x 8 RAM (synchronous):
Single-port, 3-state Bus
4
Dual-port
5
8
8
88
88
116
116
139
139
176
176
MHz
MHz
8-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs
6
0.25
0
4.87
2.35
3.66
1.82
2.58
1.23
2.03
0.99
ns
ns
32-bit Address Decode (internal):
Using Softwired LUTs
Using SLICs
7
2
0
16.06
6.91
12.07
5.41
9.01
4.21
7.03
3.37
ns
ns
36-bit Parity Check (internal)
2
16.06
12.07
9.01
7.03
ns
Lucent Technologies Inc.
7
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Description
FPGA Overview
The
ORCA
Series 3 FPGAs are a new generation of
SRAM-based FPGAs built on the successful OR2C/
TxxA FPGA Series from Lucent Technologies Micro-
electronics Group, with enhancements and innovations
geared toward today's high-speed designs and tomor-
row's systems on a single chip. Designed from the start
to be synthesis friendly and to reduce place and route
times while maintaining the complete routability of the
ORCA
2C/2T devices, Series 3 more than doubles the
logic available in each logic block and incorporates sys-
tem-level features that can further reduce logic require-
ments and increase system speed.
ORCA
Series 3
devices contain many new patented enhancements
and are offered in a variety of packages, speed grades,
and temperature ranges.
The
ORCA
Series 3 FPGAs consist of three basic ele-
ments: programmable logic cells (PLCs), programma-
ble input/output cells (PICs), and system-level features.
An array of PLCs is surrounded by PICs. Each PLC
contains a programmable function unit (PFU), a sup-
plemental logic and interconnect cell (SLIC), local rout-
ing resources, and configuration RAM. Most of the
FPGA logic is performed in the PFU, but decoders,
PAL
-like functions, and 3-state buffering can be per-
formed in the SLIC. The PICs provide device inputs
and outputs and can be used to register signals and to
perform input demultiplexing, output multiplexing, and
other functions on two output signals. Some of the sys-
tem-level functions include the new microprocessor
interface (MPI) and the programmable clock manager
(PCM).
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit)
look-up tables (LUTs), eight latches/flip-flops (FFs),
and one additional flip-flop that may be used indepen-
dently or with arithmetic functions.
The PFU is organized in a twin-quad fashion: two sets
of four LUTs and FFs that can be controlled indepen-
dently. LUTs may also be combined for use in arith-
metic functions using fast-carry chain logic in either
4-bit or 8-bit modes. The carry-out of either mode may
be registered in the ninth FF for pipelining. Each PFU
may also be configured as a synchronous 32 x 4 sin-
gle- or dual-port RAM or ROM. The FFs (or latches)
may obtain input from LUT outputs or directly from
invertible PFU inputs, or they can be tied high or tied
low. The FFs also have programmable clock polarity,
clock enables, and local set/reset.
The SLIC is connected to PLC routing resources and to
the outputs of the PFU. It contains 3-state, bidirectional
buffers and logic to perform up to a 10-bit AND function
for decoding, or an AND-OR with optional INVERT
(AOI) to perform
PAL
-like functions. The 3-state drivers
in the SLIC and their direct connections to the PFU out-
puts make fast, true 3-state buses possible within the
FPGA, reducing required routing and allowing for real-
world system performance.
8
8
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Description
(continued)
PIC Logic
Series 3 PIC addresses the demand for ever-increas-
ing system clock speeds. Each PIC contains four pro-
grammable inputs/outputs (PIOs) and routing
resources. On the input side, each PIO contains a fast-
capture latch that is clocked by an ExpressCLK. This
latch is followed by a latch/FF that is clocked by a sys-
tem clock from the internal general clock routing. The
combination provides for very low setup requirements
and zero hold times for signals coming on-chip. It may
also be used to demultiplex an input signal, such as a
multiplexed address/data signal, and register the sig-
nals without explicitly building a demultiplexer. Two
input signals are available to the PLC array from each
PIO, and the
ORCA
2C/2T capability to use any input
pin as a clock or other global input is maintained.
On the output side of each PIO, two outputs from the
PLC array can be routed to each output flip-flop, and
logic can be associated with each I/O pad. The output
logic associated with each pad allows for multiplexing
of output signals and other functions of two output sig-
nals.
The output FF in combination with output signal multi-
plexing, is particularly useful for registering address
signals to be multiplexed with data, allowing a full clock
cycle for the data to propagate to the output. The I/O
buffer associated with each pad is very similar to the
ORCA
2C/2T Series buffer with a new, fast, open-drain
option for ease of use on system buses.
System Features
Series 3 also provides system-level functionality by
means of its dual-use microprocessor interface and its
innovative programmable clock manager. These func-
tional blocks allow for easy glueless system interfacing
and the capability to adjust to varying conditions in
today's high-speed systems.
Routing
The abundant routing resources of the
ORCA
Series 3
FPGAs are organized to route signals individually or as
buses with related control signals. Clocks are routed on
a low-skew, high-speed distribution network and may
be sourced from PLC logic, externally from any I/O
pad, or from the very fast ExpressCLK pins. Express-
CLKs may be glitchlessly and independently enabled
and disabled with a programmable control signal using
the new StopCLK feature. The improved PIC routing
resources are now similar to the patented intra-PLC
routing resources and provide great flexibility in moving
signals to and from the PIOs. This flexibility translates
into an improved capability to route designs at the
required speeds when the I/O signals have been locked
to specific pins.
Configuration
The FPGA's functionality is determined by internal
configuration RAM. The FPGA's internal initialization/
configuration circuitry loads the configuration data at
powerup or under system control. The RAM is loaded
by using one of several configuration modes. The con-
figuration data resides externally in an EEPROM or any
other storage media. Serial EEPROMs provide a sim-
ple, low pin count method for configuring FPGAs. A
new, easy method for configuring the devices is
through the microprocessor interface.
Lucent Technologies Inc.
9
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Description
(continued)
ORCA
Foundry Development System
The
ORCA
Foundry Development System is used to
process a design from a netlist to a configured FPGA.
This system is used to map a design onto the
ORCA
architecture and then place and route it using
ORCA
Foundry's timing-driven tools. The development system
also includes interfaces to, and libraries for, other popu-
lar CAE tools for design entry, synthesis, simulation,
and timing analysis.
The
ORCA
Foundry Development System interfaces to
front-end design entry tools and provides the tools to
produce a configured FPGA. In the design flow, the
user defines the functionality of the FPGA at two points
in the design flow: at design entry and at the bit stream
generation stage.
Following design entry, the development system's map,
place, and route tools translate the netlist into a routed
FPGA. A static timing analysis tool is provided to deter-
mine device speed and a back-annotated netlist can be
created to allow simulation. Timing and simulation out-
put files from
ORCA
Foundry are also compatible with
many third-party analysis tools. Its bit stream generator
is then used to generate the configuration data which is
loaded into the FPGA's internal configuration RAM.
When using the bit stream generator, the user selects
options that affect the functionality of the FPGA. Com-
bined with the front-end tools,
ORCA
Foundry pro-
duces configuration data that implements the various
logic and routing options discussed in this data sheet.
Architecture
The
ORCA
Series 3 FPGA comprises three basic ele-
ments: PLCs, PICs, and system-level functions. Figure
1 shows an array of programmable logic cells (PLCs)
surrounded by programmable input/output cells (PICs).
Also shown are the interquad routing blocks (hIQ, vIQ)
present in Series 3. System-level functions (located in
the corners of the array) and the routing resources and
configuration RAM are not shown in Figure 1.
The OR3C/T55 array in Figure 1 has PLCs arranged in
an array of 18 rows and 18 columns. The location of a
PLC is indicated by its row and column so that a PLC in
the second row and the third column is R2C3. PICs are
located on all four sides of the FPGA between the
PLCs and the device edge. PICs are indicated using
PT and PB to designate PICs on the top and bottom
sides of the array, respectively, and PL and PR to des-
ignate PICs along the left and right sides of the array,
respectively. The position of a PIC on an edge of the
array is indicated by a number, counting from left to
right for PT and PB and top to bottom for PL and PR
PICs.
Each PIC contains routing resources and four program-
mable I/Os (PIOs). Each PIO contains the necessary
I/O buffers to interface to bond pads. PIOs in Series 3
FPGAs also contain input and output FFs, fast open-
drain capability on output buffers, special output logic
functions, and signal multiplexing/demultiplexing capa-
bilities.
PLCs comprise a programmable function unit (PFU), a
supplemental logic and interconnect cell (SLIC), and
routing resources. The PFU is the main logic element
of the PLC, containing elements for both combinatorial
and sequential logic. Combinatorial logic is done in
look-up tables (LUTs) located in the PFU. The PFU can
be used in different modes to meet different logic
requirements. The LUT's twin-quad architecture pro-
vides a configurable medium-/large-grain architecture
that can be used to implement from one to eight inde-
pendent combinatorial logic functions or a large num-
ber of complex logic functions using multiple LUTs. The
flexibility of the LUT to handle wide input functions, as
well as multiple smaller input functions, maximizes the
gate count per PFU while increasing system speed.
The LUTs can be programmed to operate in one of
three modes: combinatorial, ripple, or memory. In com-
binatorial mode, the LUTs can realize any 4- or 5-input
logic function and many multilevel logic functions using
ORCA
's softwired LUT (SWL) connections. In ripple
mode, the high-speed carry logic is used for arithmetic
functions, comparator functions, or enhanced data path
functions. In memory mode, the LUTs can be used as a
32 x 4 synchronous read/write or read-only memory, in
either single- or dual-port mode.
10
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Architecture
(continued)
5-4489(F)
Figure 1. OR3C/T55 Array
VI
P
L
9
P
L
8
P
L
7
P
L
6
PL
5
P
L
4
PL
3
P
L
2
PL
1
P
L13
P
L12
P
L11
PR
1
2
PR
1
1
PR
9
PR
8
PR
7
PR
6
PR
5
PR
4
PR
3
PR
2
PR
1
PR
1
3
P
R
1
8
PR
1
7
PR
1
6
PR
1
5
PR
1
4
RM
I
D
PR
1
0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PT8
PT9
PT11
PT12
R1C1
R1C2
R1C3
R1C4
R1C5
R1C6
R1C7
R1C8
R1C9
R1C10
R1C18
R1C17
R1C16
R1C15
R1C14
R1C13
R1C12
R1C11
PT13
PT14
PT15
PT16
PT17
PT18
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PL
1
8
PL
1
7
PL
1
6
PL
1
5
PL
1
4
PB13
PB14
PB15
PB16
PB17
PB18
P
L10
BMID
PT10
vIQ
R2C1
R2C2
R2C3
R2C4
R2C5
R2C6
R2C7
R2C8
R2C9
R2C10
R3C1
R3C2
R3C3
R3C4
R3C5
R3C6
R3C7
R3C8
R3C9
R3C10
R4C1
R4C2
R4C3
R4C4
R4C5
R4C6
R4C7
R4C8
R4C9
R4C10
R5C1
R5C2
R5C3
R5C4
R5C5
R5C6
R5C7
R5C8
R5C9
R5C10
R6C1
R6C2
R6C3
R6C4
R6C5
R6C6
R6C7
R6C8
R6C9
R6C10
R7C1
R7C2
R7C3
R7C4
R7C5
R7C6
R7C7
R7C8
R7C9
R7C10
R8C1
R8C2
R8C3
R8C4
R8C5
R8C6
R8C7
R8C8
R8C9
R8C10
R9C1
R9C2
R9C3
R9C4
R9C5
R9C6
R9C7
R9C8
R9C9
R9C10
R10C1 R10C2 R10C3
R10C4 R10C5 R10C6
R10C7 R10C8 R10C9
R10C10
R2C18
R2C17
R2C16
R2C15
R2C14
R2C13
R2C12
R2C11
R3C18
R3C17
R13C16
R3C15
R3C14
R3C13
R3C12
R3C11
R4C18
R4C17
R4C16
R4C15
R4C14
R4C13
R4C12
R4C11
R5C18
R5C17
R5C16
R5C15
R5C14
R5C13
R5C12
R5C11
R6C18
R6C17
R6C16
R6C15
R6C14
R6C13
R6C12
R6C11
R7C18
R7C17
R7C16
R7C15
R7C14
R7C13
R7C12
R7C11
R8C18
R8C17
R8C16
R8C15
R8C14
R8C13
R8C12
R8C11
R9C18
R9C17
R9C16
R9C15
R9C14
R9C13
R9C12
R9C11
R10C18
R10C17
R10C16
R10C15
R10C14
R10C13
R10C12
R10C11
R18C18
R18C17
R18C16
R18C15
R18C14
R18C13
R18C12
R18C11
R17C18
R17C17
R17C16
R17C15
R17C14
R17C13
R17C12
R17C11
R16C18
R16C17
R16C16
R16C15
R16C14
R16C13
R16C12
R16C11
R15C18
R15C17
R15C16
R15C15
R15C14
R15C13
R15C12
R15C11
R14C18
R14C17
R14C16
R14C15
R14C14
R14C13
R14C12
R14C11
R13C18
R13C17
R13C16
R13C15
R13C14
R13C13
R13C12
R13C11
R12C18
R12C17
R12C16
R12C15
R12C14
R12C13
R12C12
R12C11
R11C18
R11C17
R11C16
R11C15
R11C14
R11C13
R11C12
R11C11
R18C10
R18C9
R18C8
R18C7
R18C6
R18C5
R18C4
R18C3
R18C2
R18C1
R17C10
R17C9
R17C8
R17C7
R17C6
R17C5
R17C4
R17C3
R17C2
R17C1
R16C10
R16C9
R16C8
R16C7
R16C6
R16C5
R16C4
R16C3
R16C2
R16C1
R15C10
R15C9
R15C8
R15C7
R15C6
R15C5
R15C4
R15C3
R15C2
R15C1
R14C10
R14C9
R14C8
R14C7
R14C6
R14C5
R14C4
R14C3
R14C2
R14C1
R13C10
R13C9
R13C8
R13C7
R13C6
R13C5
R13C4
R13C3
R13C2
R13C1
R12C10
R12C9
R12C8
R12C7
R12C6
R12C5
R12C4
R12C3
R12C2
R12C1
R11C10
R11C9
R11C8
R11C7
R11C6
R11C5
R11C4
R11C3
R11C2
R11C1
hIQ
TMID
LM
I
D
Lucent Technologies Inc.
11
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
The programmable logic cell (PLC) consists of a pro-
grammable function unit (PFU), a supplemental logic
and interconnect cell (SLIC), and routing resources. All
PLCs in the array are functionally identical with only
minor differences in routing connectivity for improved
routability. The PFU, which contains eight 4-input LUTs,
eight latches/FFs, and one FF for logic implementation,
is discussed in the next section, followed by discus-
sions of the SLIC and PLC routing resources.
Programmable Function Unit
The PFUs are used for logic. Each PFU has 50 external
inputs and 18 outputs and can operate in several
modes. The functionality of the inputs and outputs
depends on the operating mode.
The PFU uses 36 data input lines for the LUTs, eight
data input lines for the latches/FFs, five control inputs
(ASWE, CLK, CE, LSR, SEL), and a carry input (CIN)
for fast arithmetic functions and general-purpose data
input for the ninth FF. There are eight combinatorial data
outputs (one from each LUT), eight latched/registered
outputs (one from each latch/FF), a carry-out (COUT),
and a registered carry-out (REGCOUT) that comes from
the ninth FF. The carry-out signals are used principally
for fast arithmetic functions.
Figure 2 and Figure 3 show high-level and detailed
views of the ports in the PFU, respectively. The eight
sets of LUT inputs are labeled as K
0
through K
7
with
each of the four inputs to each LUT having a suffix of
_x, where x is a number from 0 to 3. There are four F5
inputs labeled A through D. These inputs are used for a
fifth LUT input for 5-input LUTs or as a selector for multi-
plexing two 4-input LUTs. The eight direct data inputs to
the latches/FFs are labeled as DIN[7:0]. Registered LUT
outputs are shown as Q
[7:0], and combinatorial LUT
outputs are labeled as F
[7:0].
The PFU implements combinatorial logic in the LUTs
and sequential logic in the latches/FFs. The LUTs are
static random access memory (SRAM) and can be used
for read/write or read-only memory.
Each latch/FF can accept data from its associated LUT.
Alternatively, the latches/FFs can accept direct data
from DIN[7:0], eliminating the LUT delay if no combina-
torial function is needed. Additionally, the CIN input can
be used as a direct data source for the ninth FF. The
LUT outputs can bypass the latches/FFs, which reduces
the delay out of the PFU. It is possible to use the LUTs
and latches/FFs more or less independently, allowing,
for instance, a comparator function in the LUTs simulta-
neously with a shift register in the FFs.
5-5752(F)
Figure 2. PFU Ports
The PFU can be configured to operate in four modes:
logic mode, half-logic mode, ripple mode, and memory
(RAM/ROM) mode. In addition, ripple mode has four
submodes and RAM mode can be used in either a
single- or dual-port memory fashion. These submodes
of operation are discussed in the following sections.
5-5752(F)
F5D
K
7
_0
K
7
_1
K
7
_2
K
7
_3
K
6
_0
K
6
_1
K
6
_2
K
6
_3
K
5
_0
K
5
_1
K
5
_2
K
5
_3
K
4
_0
K
4
_1
K
4
_2
K
4
_3
F5C
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
CIN
F5B
K
3
_0
K
3
_1
K
3
_2
K
3
_3
K
2
_0
K
2
_1
K
2
_2
K
2
_3
K
1
_0
K
1
_1
K
1
_2
K
1
_3
K
0
_0
K
0
_1
K
0
_2
K
0
_3
F5A
LSR
CLK
CE
SEL
ASWE
PROGRAMMABLE
FUNCTION UNIT
(PFU)
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
COUT
REGCOUT
F7
F6
F5
F4
F3
F2
F1
F0
12
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
5-5743(F)
Note: All multiplexers without select inputs are configuration selector multiplexers.
Figure 3. Simplified PFU Diagram
SEL
CIN
D
CE
CK
S/R
FF8
REGCOUT
COUT
1
ASWE
LSR
K7_3
K6_0
K6_1
K6_2
K6_3
K5_0
K5_1
K5_2
F5D
K7_0
K7_1
K7_2
K5_3
K4_0
K4_1
K4_2
K4_3
F5C
CLK
A
B
C
D
A
B
C
D
A
B
C
D
K4
K5
K6
K7
DIN7
DIN6
DIN5
DIN4
REG5
D0
D1
CE
CK
S/R
DSEL
Q5
F5
REG6
D0
D1
CE
CK
S/R
DSEL
Q6
F6
REG7
D0
D1
CE
CK
S/R
DSEL
Q7
F7
REG4
D0
D1
CE
CK
S/R
DSEL
Q4
F4
A
B
C
D
F5MODE45
K3_3
K2_0
K2_1
K2_2
K2_3
K1_0
K1_1
K1_2
F5B
K3_0
K3_1
K3_2
K1_3
K0_0
K0_1
K0_2
K0_3
F5A
A
B
C
D
A
B
C
D
A
B
C
D
K0
K1
K2
K3
DIN3
DIN2
DIN1
DIN0
REG1
D0
D1
CE
CK
S/R
DSEL
Q1
F1
REG2
D0
D1
CE
CK
S/R
DSEL
Q2
F2
REG3
D0
D1
CE
CK
S/R
DSEL
Q3
F3
REG0
D0
D1
CE
CK
S/R
DSEL
Q0
F0
A
B
C
D
F5MODE01
F5MODE67
F5MODE23
0
0
0
0
0
0
0
0
0
0
0
0
CE
0
0
0
1
1
1
0
0
0
0
1
0
1
0
1
0
1
0
Lucent Technologies Inc.
13
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
Look-Up Table Operating Modes
The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For exam-
ple, in some operating modes, the DIN[7:0] inputs are direct data inputs to the PFU latches/FFs. In memory mode,
the same DIN[7:0] inputs are used as a 4-bit write data input bus and a 4-bit write address input bus into LUT
memory.
Table 3 lists the basic operating modes of the LUT. Figure 4--Figure 10 show block diagrams of the LUT operating
modes. The accompanying descriptions demonstrate each mode's use for generating logic.
PFU Control Inputs
Each PFU has five routable control inputs and an active-low, asynchronous global set/reset (GSRN) signal that
affects all latches and FFs in the device. The five control inputs are CLK, LSR, CE, ASWE, and SEL, and their
functionality for each logic mode of the PFU (discussed subsequently) is shown in Table 4. The clock signal to the
PFU is CLK, CE stands for clock enable, which is its primary function. LSR is the local set/reset signal that can be
configured as synchronous or asynchronous. The selection of set or reset is made for each latch/FF and is not a
function of the signal itself. ASWE stands for add/subtract/write enable, which are its functions, along with being an
optional clock enable, and SEL is used to dynamically select between direct PFU input and LUT output data as the
input to the latches/FFs.
All of the control signals can be disabled and/or inverted via the configuration logic. A disabled clock enable indi-
cates that the clock is always enabled. A disabled LSR indicates that the latch/FF never sets/resets (except from
GSRN). A disabled SEL input indicates that DIN[7:0] PFU inputs are routed to the latches/FFs. For logic and ripple
modes of the PFU, the LSR, CE, and ASWE (as a clock enable) inputs can be disabled individually for each nibble
(latch/FF[3:0], latch/FF[7:4]) and for the ninth FF.
Table 3. Look-Up Table Operating Modes
Mode
Function
Logic
4- and 5-input LUTs; softwired LUTs; latches/FFs with direct input or LUT input; CIN as direct input to
ninth FF or as pass through to COUT.
Half Logic/
Half Ripple
Upper four LUTs and latches/FFs in logic mode; lower four LUTs and latches/FFs in ripple mode; CIN
and ninth FF for logic or ripple functions.
Ripple
All LUTs combined to perform ripple-through data functions. Eight LUT registers available for direct-in
use or to register ripple output. Ninth FF dedicated to ripple out, if used. The submodes of ripple mode
are adder/subtractor, counter, multiplier, and comparator.
Memory
All LUTs and latches/FFs used to create a 32 x 4 synchronous dual-port RAM. Can be used as single-
port or as ROM.
14
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
Table 4. Control Input Functionality
Mode
CLK
LSR
CE
ASWE
SEL
Logic
CLK to all latches/
FFs
LSR to all latches/
FFs, enabled per nib-
ble and for ninth FF
CE to all latches/FFs,
selectable per nibble
and for ninth FF
CE to all latches/FFs,
selectable per nibble
and for ninth FF
Select between LUT
input and direct input
for eight latches/FFs
Half Logic/
Half Ripple
CLK to all latches/
FFs
LSR to all latches/FF,
enabled per nibble
and for ninth FF
CE to all latches/FFs,
selectable per nibble
and for ninth FF
Ripple logic control
input
Select between LUT
input and direct input
for eight latches/FFs
Ripple
CLK to all latches/
FFs
LSR to all latches/
FFs, enabled per nib-
ble and for ninth FF
CE to all latches/FFs,
selectable per nibble
and for ninth FF
Ripple logic control
input
Select between LUT
input and direct input
for eight latches/FFs
Memory
(RAM)
CLK to RAM
Port enable 2
Port enable 1
Write enable
Not used
Memory
(ROM)
Optional for sync.
outputs
Not used
Not used
Not used
Not used
Logic Mode
The PFU diagram of Figure 3 represents the logic
mode of operation. In logic mode, the eight LUTs are
used individually or in flexible groups to implement user
logic functions. The latches/FFs may be used in con-
junction with the LUTs or separately with the direct
PFU data inputs. There are three basic submodes of
LUT operation in PFU logic mode: F4 mode, F5 mode,
and softwired LUT (SWL) mode. Combinations of these
submodes are possible in each PFU.
F4 mode, shown simplified in Figure 4, illustrates the
uses of the basic 4-input LUTs in the PFU. The output
of an F4 LUT can be passed out of the PFU, captured
at the LUTs associated latch/FF, or multiplexed with the
adjacent F4 LUT output using one of the F5[A:D] inputs
to the PFU. Only adjacent LUT pairs (K
0
and K
1
, K
2
and K
3
, K
4
and K
5
, K
6
and K
7
) can be multiplexed, and
the output always goes to the even-numbered output of
the pair.
The F5 submode of the LUT operation, shown simpli-
fied in Figure 4, indicates the use of 5-input LUTs to
implement logic. 5-input LUTs are created from two
4-input LUTs and a multiplexer. The F5 LUT is the
same as the multiplexing of two F4 LUTs described
previously with the constraint that the inputs to the F4
LUTs be the same. The F5[A:D] input is then used as
the fifth LUT input. The equations for the two F4 LUTs
will differ by the assumed value for the F5[A:D] input,
one F4 LUT assuming that the F5[A:D] input is zero,
and the other assuming it is a one. The selection of the
appropriate F4 LUT output in the F5 MUX by the
F5[A:D] signal creates a 5-input LUT. Any combination
of F4 and F5 LUTs is allowed per PFU using the eight
16-bit LUTs. Examples are eight F4 LUTs, four F5
LUTs, and a combination of four F4 plus two F5 LUTs.
5-5970(F)
Figure 4. Simplified F4 and F5 Logic Modes
K
7
F7
K
7
F6
K
6
F5D
K
6
F6
K
5
F5
K
5
F4
K
4
F5C
K
4
F4
K
3
F3
K
3
F2
K
2
F5B
K
2
F2
K
1
F1
K
1
F0
K
0
F5A
K
0
F0
K
7
/K
6
F6
K
5
/K
4
F4
K
3
/K
2
F2
K
1
/K
0
F0
F5 MODE
MULTIPLEXED F4 MODE
F4 MODE
Lucent Technologies Inc.
15
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
Softwired LUT submode uses F4 and F5 LUTs and internal PFU feedback routing to generate complex logic func-
tions up to three LUT-levels deep. Figure 3 shows multiplexers between the K
Z
[3:0] inputs to the PFU and the
LUTs. These multiplexers can be independently configured to route certain LUT outputs to the input of other LUTs.
In this manner, very complex logic functions, some of up to 21 inputs, can be implemented in a single PFU at
greatly enhanced speeds.
Figure 5 shows several softwired LUT topologies. In this figure, each circle represents either an F4 or F5 LUT. It is
important to note that an LUT output that is fed back for softwired use is still available to be registered or output
from the PFU. This means, for instance, that a logic equation that is needed by itself and as a term in a larger
equation need only be generated once and PLC routing resources will not be required to use it in the larger equa-
tion.
Figure 5. Softwired LUT Topology Examples
5-5753(F)
F4
KEY:
F5
4-INPUT LUT
5-INPUT LUT
5-5754(F)
F4
F4
F4
F4
F4
F4
F4
F4
FOUR 7-INPUT FUNCTIONS IN ONE PFU
F5
F5
F5
F5
TWO 9-INPUT FUNCTIONS IN ONE PFU
F5
F5
F5
F5
ONE 17-INPUT FUNCTION IN ONE PFU
F5
F5
F4
ONE 21-INPUT FUNCTION IN ONE PFU
F4
F4
F4
F4
F4
F4
F4
TWO OF FOUR 10-INPUT FUNCTIONS IN ONE PFU
F4
F4
F4
F4
3
ONE OF TWO 12-INPUT FUNCTIONS IN ONE PFU
16
16
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
Half-Logic Mode
Series 3 FPGAs are based upon a twin-quad architec-
ture in the PFUs. The byte-wide nature (eight LUTs,
eight latches/FFs) may just as easily be viewed as two
nibbles (two sets of four LUTs, four latches/FFs). The
two nibbles of the PFU are organized so that any nib-
ble-wide feature (excluding some softwired LUT topolo-
gies) can be swapped with any other nibble-wide
feature in another PFU. This provides for very flexible
use of logic and for extremely flexible routing. The half-
logic mode of the PFU takes advantage of the twin-
quad architecture and allows half of a PFU, K
[7:4]
and
associated latches/FFs, to be used in logic mode while
the other half of the PFU, K
[3:0]
and associated latches/
FFs, is used in ripple mode. In half-logic mode, the
ninth FF may be used as a general-purpose FF or as a
register in the ripple mode carry chain.
Ripple Mode
The PFU LUTs can be combined to do byte-wide ripple
functions with high-speed carry logic. Each LUT has a
dedicated carry-out net to route the carry to/from any
adjacent LUT. Using the internal carry circuits, fast
arithmetic, counter, and comparison functions can be
implemented in one PFU. Similarly, each PFU has
carry-in (CIN, FCIN) and carry-out (COUT, FCOUT)
ports for fast-carry routing between adjacent PFUs.
The ripple mode is generally used in operations on two
data buses. A single PFU can support an 8-bit ripple
function. Data buses of 4 bits and less can use the
nibble-wide ripple chain that is available in half-logic
mode. This nibble-wide ripple chain is also useful for
longer ripple chains where the length modulo 8 is four
or less. For example, a 12-bit adder (12 modulo 8 = 4)
can be implemented in one PFU in ripple mode (8 bits)
and one PFU in half-logic mode (4 bits), freeing half of
a PFU for general logic mode functions.
Each LUT has two operands and a ripple (generally
carry) input, and provides a result and ripple (generally
carry) output. A single bit is rippled from the previous
LUT and is used as input into the current LUT. For LUT
K
0
, the ripple input is from the PFU CIN or FCIN port.
The CIN/FCIN data can come from either the fast-carry
routing (FCIN) or the PFU input (CIN), or it can be tied
to logic 1 or logic 0.
In the following discussions, the notations LUT K
7
/K
3
and F[7:0]/F[3:0]
are used to denote the LUT that pro-
vides the carry-out and the data outputs for full PFU
ripple operation (K
7
, F[7:0]) and half-logic ripple
operation (K
3
, F[3:0]), respectively. The ripple mode
diagram in Figure 6 shows full PFU ripple operation,
with half-logic ripple connections shown as dashed
lines.
The result output and ripple output are calculated by
using generate/propagate circuitry. In ripple mode, the
two operands are input into K
Z
[1] and K
Z
[0] of each
LUT. The result bits, one per LUT, are F[7:0]/F[3:0]
(see
Figure 6). The ripple output from LUT K
7
/K
3
can be
routed on dedicated carry circuitry into any of four adja-
cent PLCs, and it can be placed on the PFU COUT/
FCOUT outputs. This allows the PLCs to be cascaded
in the ripple mode so that nibble-wide ripple functions
can be expanded easily to any length.
Result outputs and the carry-out may optionally be reg-
istered within the PFU. The capability to register the
ripple results, including the carry output, provides for
improved counter performance and simplified pipelin-
ing in arithmetic functions.
Figure 6. Ripple Mode
5-5755(F)
F7
K
7
[1]
K
7
[0]
K
7
D
Q
C
C
D Q
Q7
REGCOUT
COUT
F6
K
6
[1]
K
6
[0]
K
6
D
Q
Q6
F4
K
4
[1]
K
4
[0]
K
4
D
Q
Q4
F3
K
3
[1]
K
3
[0]
K
3
D
Q
Q3
F2
K
2
[1]
K
2
[0]
K
2
D
Q
Q2
F1
K
1
[1]
K
1
[0]
K
1
D
Q
Q1
F5
K
5
[1]
K
5
[0]
K
5
D
Q
Q5
F0
K
0
[1]
K
0
[0]
K
0
D
Q
Q0
CIN/FCIN
FCOUT
Lucent Technologies Inc.
17
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
The ripple mode can be used in one of four submodes.
The first of these is adder-subtractor submode. In
this submode, each LUT generates three separate out-
puts. One of the three outputs selects whether the
carry-in is to be propagated to the carry-out of the cur-
rent LUT or if the carry-out needs to be generated. If
the carry-out needs to be generated, this is provided by
the second LUT output. The result of this selection is
placed on the carry-out signal, which is connected to
the next LUT carry-in or the COUT/FCOUT signal, if it
is the last LUT (K
7
/K
3
). Both of these outputs can be
any equation created from K
Z
[1] and K
Z
[0], but in this
case, they have been set to the propagate and gener-
ate functions.
The third LUT output creates the result bit for each LUT
output connected to F[7:0]/F[3:0]. If an adder/subtrac-
tor is needed, the control signal to select addition or
subtraction is input on ASWE, with a logic 0 indicating
subtraction and a logic 1 indicating addition. The result
bit is created in one-half of the LUT from a single bit
from each input bus K
Z
[1:0], along with the ripple input
bit.
The second submode is the counter submode (see
Figure 7). The present count, which may be initialized
via the PFU DIN inputs to the latches/FFs, is supplied
to input K
Z
[0], and then output F[7:0]/F[3:0] will either
be incremented by one for an up counter or decre-
mented by one for a down counter. If an up/down
counter is needed, the control signal to select the direc-
tion (up or down) is input on ASWE with a logic 1 indi-
cating an up counter and a logic 0 indicating a down
counter. Generally, the latches/FFs in the same PFU
are used to hold the present count value.
Figure 7. Counter Submode
5-5756(F)
F7
K
7
[0]
K
7
D
Q
C
C
D
Q
Q7
REGCOUT
COUT
F6
K
6
[0]
K
6
D
Q
Q6
F4
K
4
[0]
K
4
D
Q
Q4
F3
K
3
[0]
K
3
D
Q
Q3
F2
K
2
[0]
K
2
D
Q
Q2
F1
K
1
[0]
K
1
D
Q
Q1
F5
K
5
[0]
K
5
D
Q
Q5
F0
K
0
[0]
K
0
D
Q
Q0
CIN/FCIN
FCOUT
18
18
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
In the third submode, multiplier submode, a single
PFU can affect an 8 x 1 bit (4 x 1 for half-ripple mode)
multiply and sum with a partial product (see Figure 8).
The multiplier bit is input at ASWE, and the multiplicand
bits are input at K
Z
[1], where K
7
[1] is the most signifi-
cant bit (MSB). K
Z
[0] contains the partial product (or
other input to be summed) from a previous stage. If
ASWE is logical 1, the multiplicand is added to the par-
tial product. If ASWE is logical 0, 0 is added to the par-
tial product, which is the same as passing the partial
product. CIN/FCIN can bring the carry-in from the less
significant PFUs if the multiplicand is wider than 8 bits,
and COUT/FCOUT holds any carry-out from the multi-
plication, which may then be used as part of the prod-
uct or routed to another PFU in multiplier mode for
multiplicand width expansion.
Ripple mode's fourth submode features equality
comparators.
The functions that are explicitly available
are A
>
B, A
B, and A
<
B, where the value for A is
input on K
Z
[0], and the value for B is input on K
Z
[1]. A
value of 1 on the carry-out signals valid argument. For
example, a carry-out equal to 1 in AB submode indi-
cates that the value on K
Z
[0] is greater than or equal to
the value on K
Z
[1]. Conversely, the functions A < B, A +
B, and A > B are available using the same functions but
with a 0 output expected. For example, A
>
B with a 0
output indicates A < B. Table 5 shows each function
and the output expected.
If larger than 8 bits, the carry-out signal can be cas-
caded using fast-carry logic to the carry-in of any adja-
cent PFU. The use of this submode could be shown
using Figure 6, except that the CIN/FCIN input for the
least significant PFU is controlled via configuration.
Key: C = configuration data.
Figure 8. Multiplier Submode
Table 5. Ripple Mode Equality Comparator
Functions and Outputs
Equality
Function
ORCA
Foundry
Submode
True, if
Carry-Out Is:
A
>
B
A
>
B
1
A
<
B
A
<
B
1
A
B
A
B
1
A < B
A
>
B
0
A > B
A
<
B
0
A = B
A
B
0
5-5757(F)
K
7
[1]
K
7
[0]
+
D Q
C
C
D Q
1
0
0
K
7
ASWE
K
4
[1]
K
4
[0]
+
D Q
1
0
0
K
4
K
3
[1]
K
3
[0]
+
D Q
1
0
0
K
3
K
2
[1]
K
2
[0]
+
D Q
1
0
0
K
2
K
1
[1]
K
1
[0]
+
D Q
1
0
0
K
1
K
6
[1]
K
6
[0]
+
D Q
1
0
0
K
6
K
5
[1]
K
5
[0]
+
D Q
1
0
0
K
5
K
0
[1]
K
0
[0]
+
D Q
1
0
0
K
0
F7
Q7
REGCOUT
COUT
F6
Q6
F4
Q4
F3
Q3
F2
Q2
F1
Q1
F5
Q5
F0
Q0
Lucent Technologies Inc.
19
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
Memory Mode
The Series 3 PFU can be used to implement a 32 x 4 (128-bit) synchronous, dual-port random access memory
(RAM). A block diagram of a PFU in memory mode is shown in Figure 9. This RAM can also be configured to work
as a single-port memory and because initial values can be loaded into the RAM during configuration, it can also be
used as a read-only memory (ROM).
Figure 9. Memory Mode
The PFU memory mode uses all LUTs and latches/FFs including the ninth FF in its implementation as shown in
Figure 9. The read address is input at the K
Z
[3:0] and F5[A:D] inputs where K
Z
[0] is the LSB and F5[A:D] is the
MSB, and the write address is input on CIN (MSB) and DIN[7, 5, 3, 1], with DIN[1] being the LSB. Write data is
input on DIN[6, 4, 2, 0], where DIN[6] is the MSB, and read data is available combinatorially on F[6, 4, 2, 0] and
registered on Q[6, 4, 2, 0] with F[6] and Q[6] being the MSB. The write enable signal is input at ASWE, and two
write port enables are input on CE and LSR. The PFU CLK signal is used to synchronously write the data. The
polarities of the clock, write enable, and port enables are all programmable. Write-port enables may be disabled if
they are not to be used.
5-5969(F)
Q6
Q4
Q2
Q0
D
5
Q
CIN(WA4)
K
Z
[3:0]
4
F5[A:D]
D Q
DIN7(WA3)
D Q
DIN5(WA2)
D Q
DIN3(WA1)
D Q
DIN1(WA0)
D Q
DIN6(WD3)
D Q
DIN4(WD2)
D Q
DIN2(WD1)
D Q
DIN0(WD0)
D Q
ASWE(WREN)
EN
S/R
CE(WPE1)
LSR(WPE2)
CLK
4
WRITE
WRITE
READ
READ
4
F6
F4
F2
F0
D Q
D Q
D Q
D Q
WRITE
RAM CLOCK
ADDRESS[4:0]
ADDRESS[4:0]
DATA[3:0]
DATA[3:0]
ENABLE
20
20
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
Data is written to the write data, write address, and
write enable registers on the active edge of the clock,
but data is not written into the RAM until the next clock
edge one-half cycle later. The read port is actually
asynchronous, providing the user with read data very
quickly after setting the read address, but timing is also
provided so that the read port may be treated as fully
synchronous for write then read applications. If the
read and write address lines are tied together (main-
taining MSB to MSB, etc.), then the dual-port RAM
operates as a synchronous single-port RAM. If the
write enable is disabled, and an initial memory contents
is provided at configuration time, the memory acts as a
ROM (the write data and write address ports and write
port enables are not used).
Wider memories can be created by operating two or
more memory mode PFUs in parallel, all with the same
address and control signals, but each with a different
nibble of data. To increase memory word depth above
32, two or more PLCs can be used. Figure 10 shows a
128 x 8 dual-port RAM that is implemented in eight
PLCs. This figure demonstrates data path width expan-
sion by placing two memories in parallel to achieve an
8-bit data path. Depth expansion is applied to achieve
128 words deep using the 32-word deep PFU memo-
ries. In addition to the PFU in each PLC, the SLIC
(described in the next section) in each PLC is used for
read address decodes and 3-state drivers. The 128 x 8
RAM shown could be made to operate as a single-port
RAM by tying (bit-for-bit) the read and write addresses.
To achieve depth expansion, one or two of the write
address bits (generally the MSBs) are routed to the
write port enables as in Figure 10. For 2 bits, the bits
select which 32-word bank of RAM of the four available
from a decode of two WPE inputs is to be written. Simi-
larly, 2 bits of the read address are decoded in the
SLIC and are used to control the 3-state buffers
through which the read data passes. The write data
bus is common, with separate nibbles for width expan-
sion, across all PLCs, and the read data bus is com-
mon (again, with separate nibbles) to all PLCs at the
output of the 3-state buffers.
Figure 10 also shows a new optional capability to pro-
vide a read enable for RAMs/ROMs in Series 3 using
the SLIC cell. The read enable will 3-state the read
data bus when inactive, allowing the write data and
read data buses to be tied together if desired.
Figure 10. Memory Mode Expansion Example--128 x 8 RAM
5-5749(F)
RD[7:0]
WE
WA[6:0]
RA[6:0]
CLK
WA
RA
WPE0
WPE1
WE
WD[7:4]
5
5
4
PLC
8
WD[7:0]
8
7
7
WA
RA
WPE0
WPE1
WE
RD[3:0]
WD[3:0]
5
5
4
PLC
RD[7:4]
WA
RA
WPE0
WPE1
WE
WD[7:4]
5
5
4
PLC
WA
RA
WPE0
WPE1
WE
RD[3:0]
WD[3:0]
5
5
4
PLC
RD[7:4]
RE
4
4
4
4
PFU
PFU
PFU
PFU
SLIC
SLIC
SLIC
SLIC
Lucent Technologies Inc.
21
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
Supplemental Logic and Interconnect Cell
(SLIC)
Each PLC contains a supplemental logic and intercon-
nect cell (SLIC) embedded within the PLC routing, out-
side of the PFU. As its name indicates, the SLIC
performs both logic and interconnect (routing) func-
tions. Its main features are 3-statable, bidirectional buff-
ers, and a
PAL
-like decoder capability. Figure 11 shows
a diagram of a SLIC with all of its features shown. All
modes of the SLIC are not available at one time.
Each SLIC contains ten bidirectional (BIDI) buffers,
each buffer capable of driving left and/or right out of the
SLIC. These BIDI buffers are twin-quad in nature and
are segregated into two groups of four (nibbles) and a
third group of two for control. Each of these groups of
BIDIs can drive from the left (BLI[9:0]) to the right
(BRO[9:0]), the right (BRI[9:0]) to the left (BLO[9:0]), or
from the central input (I[9:0]) to the left and/or right.
This central input comes directly from the PFU outputs
(O[9:0]). Each of the BIDIs in the nibble-wide groups
also has a 3-state buffer capability, but not the third
group.
There is one 3-state control (TRI) for each SLIC, with
the capability to invert or disable the 3-state control for
each group of four BIDIs. Separate 3-state control for
each nibble-wide group is achievable by using the
SLIC's decoder (DEC) output, driven by the group of
two BIDIs, to control the 3-state of one BIDI nibble
while using the TRI signal to control the 3-state of the
other BIDI nibble. Figure 12 and Figure 13 show the
SLIC in buffer mode with available 3-state control from
the TRI and DEC signals. If the entire SLIC is acting in
a buffer capacity, the DEC output may be used to gen-
erate a constant logic 1 (VHI) or logic 0 (VLO) signal for
general use.
The SLIC may also be used to generate
PAL
-like AND-
OR with optional INVERT (AOI) functions or a decoder
of up to 10 bits. Each group of buffers can feed into an
AND gate (4-input AND for the nibble groups and 2-
input AND for the other two buffers). These AND gates
then feed into a 3-input gate that can be configured as
either an AND gate or an OR gate. The output of the 3-
input gate is invertible and is output at the DEC output
of the SLIC. Figure 16 shows the SLIC in full decoder
mode.
The functionality of the SLIC is parsed by the two
nibble-wide groups and the 2-bit buffer group. Each of
these groups may operate independently as BIDI buff-
ers (with or without 3-state capability for the nibble-
wide groups) or as a
PAL
/decoder.
As discussed in the memory mode section, if the SLIC
is placed into one of the modes where it contains both
buffers and a decode or AOI function (e.g.,
BUF_BUF_DEC mode), the DEC output can be gated
with the 3-state input signal. This allows up to a 6-input
decode (e.g., BUF_DEC_DEC mode) plus the 3-state
input to control the enable/disable of up to four buffers
per SLIC. Figure 12--Figure 16 show several configu-
rations of the SLIC, while Table 6 shows all of the possi-
ble modes.
Table 6. SLIC Modes
Mode
#
Mode
BUF
[3:0]
BUF
[7:4]
BUF
[9:8]
1
BUFFER
Buffer
Buffer
Buffer
2
BUF_BUF_DEC
Buffer
Buffer
Decoder
3
BUF_DEC_BUF
Buffer
Decoder
Buffer
4
BUF_DEC_DEC
Buffer
Decoder Decoder
5
DEC_BUF_BUF
Decoder
Buffer
Buffer
6
DEC_BUF_DEC Decoder
Buffer
Decoder
7
DEC_DEC_BUF
Decoder Decoder
Buffer
8
DECODER
Decoder Decoder Decoder
22
22
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
Figure 11. SLIC All Modes Diagram
Figure 12. Buffer Mode
5-5744(F)
BRI9
I9
BLI9
BRI8
I8
BLI8
BRI7
I7
BLI7
BRI6
I6
BLI6
BRI5
I5
BLI5
BRI4
I4
BLI4
BRI3
I3
BLI3
BRI2
I2
BLI2
BRI1
I1
BLI1
BRI0
I0
BLI0
BL09
BR09
BL08
BR08
BL07
BR07
BL06
BR06
BL05
BR05
BL04
BR04
BL03
BR03
BL02
BR02
BL01
BR01
BL00
BR00
DEC
DEC
0/1
0/1
TRI
0/1
0/1
HIGH Z WHEN LOW
5-5745(F)
BRI9
I9
BLI9
BRI8
I8
BLI8
BRI7
I7
BLI7
BRI6
I6
BLI6
BRI5
I5
BLI5
BRI4
I4
BLI4
BRI3
I3
BLI3
BRI2
I2
BLI2
BRI1
I1
BLI1
BRI0
I0
BLI0
BL09
BR09
BL08
BR08
BL07
BR07
BL06
BR06
BL05
BR05
BL04
BR04
BL03
BR03
BL02
BR02
BL01
BR01
BL00
BR00
TRI
0/1
0/1
1
0
DEC
THIS CAN BE USED
A VHI OR VLO
HIGH Z WHEN LOW
TO GENERATE
Lucent Technologies Inc.
23
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
Figure 13. Buffer-Buffer-Decoder Mode
Figure 14. Buffer-Decoder-Buffer Mode
5-5746(F)
BRI9
BLI9
BRI8
BLI8
BRI7
I7
BLI7
BRI6
I6
BLI6
BRI5
I5
BLI5
BRI4
I4
BLI4
BRI3
I3
BLI3
BRI2
I2
BLI2
BRI1
I1
BLI1
BRI0
I0
BLI0
BL07
BR07
BL06
BR06
BL05
BR05
BL04
BR04
BL03
BR03
BL02
BR02
BL01
BR01
BL00
BR00
TRI
DEC
1
1
1
1
HIGH Z
WHEN LOW
HIGH Z
WHEN LOW
5-5747(F)
BRI7
BLI7
BRI6
BLI6
BRI5
BLI5
BRI4
BLI4
BRI3
I3
BLI3
BRI2
I2
BLI2
BRI1
I1
BLI1
BRI0
I0
BLI0
BL03
BR03
BL02
BR02
BL01
BR01
BL00
BR00
TRI
DEC
BRI9
I9
BLI9
BRI8
I8
BLI8
BL09
BR09
BL08
BR08
1
1
HIGH Z WHEN LOW
24
24
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
Figure 15. Buffer-Decoder-Decoder Mode
Figure 16. Decoder Mode
5-5750(F)
BRI7
BLI7
BRI6
BLI6
BRI5
BLI5
BRI4
BLI4
BRI3
I3
BLI3
BRI2
I2
BLI2
BRI1
I1
BLI1
BRI0
I0
BLI0
BL03
BR03
BL02
BR02
BL01
BR01
BL00
BR00
TRI
DEC
BRI9
BLI9
BRI8
BLI8
1
1
HIGH Z WHEN LOW
5-5748(F)
BRI7
BLI7
BRI6
BLI6
BRI5
BLI5
BRI4
BLI4
BRI3
BLI3
BRI2
BLI2
BRI1
BLI1
BRI0
BLI0
DEC
BRI9
BLI9
BRI8
BLI8
Lucent Technologies Inc.
25
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
PLC Latches/Flip-Flops
The eight general-purpose latches/FFs in the PFU can
be used in a variety of configurations. In some cases,
the configuration options apply to all eight latches/FFs in
the PFU and
some apply to the latches/FFs on a nibble-
wide basis where the ninth FF is considered indepen-
dently. For other options, each latch/FF is independently
programmable. In addition, the ninth FF can be used for
a variety of functions.
Table 7 summarizes these latch/FF options. The
latches/FFs can be configured as either positive- or
negative-level sensitive latches, or positive or negative
edge-triggered flip-flops (the ninth register can only be
FF). All latches/FFs in a given PFU share the same
clock, and the clock to these latches/FFs can be
inverted. The input into each latch/FF is from either the
corresponding LUT output (F[7:0]) or the direct data
input (DIN[7:0]). The latch/FF input can also be tied to
logic 1 or to logic 0, which is the default.
* Not available for FF[8].
The eight latches/FFs in a PFU share the clock (CLK)
and options for clock enable (CE), local set/reset (LSR),
and front-end data select (SEL) inputs. When CE is dis-
abled, each latch/FF retains its previous value when
clocked. The clock enable, LSR, and SEL inputs can be
inverted to be active-low.
The set/reset operation of the latch/FF is controlled by
two parameters: reset mode and set/reset value. When
the global set/reset (
GSRN) and local set/reset (LSR)
signals are not asserted, the latch/FF operates normally.
The reset mode is used to select a synchronous or
asynchronous LSR operation. If synchronous, LSR has
the option to be enabled only if clock enable (CE or
ASWE) is active or for LSR to have priority over the
clock enable input, thereby setting/resetting the FF inde-
pendent of the state of the clock enable. The clock
enable is supported on FFs, not latches. It is imple-
mented by using a 2-input multiplexer on the FF input,
with one input being the previous state of the FF and the
other input being the new data applied to the FF. The
select of this 2-input multiplexer is clock enable (CE or
ASWE), which selects either the new data or the previ-
ous state. When the clock enable is inactive, the FF out-
put does not change when the clock edge arrives.
Table 7. Configuration RAM Controlled Latch/
Flip-Flop Operation
Function Options
Common to All Latches/FFs in PFU
LSR Operation
Asynchronous or synchronous
Clock Polarity
Noninverted or inverted
Front-end Select*
Direct (DIN[7:0]) or from LUT (F[7:0])
LSR Priority
Either LSR or CE has priority
Latch/FF Mode
Latch or flip-flop
Enable GSRN
GSRN enabled or has no effect on
PFU latches/FFs
Set Individually in Each Latch/FF in PFU
Set/Reset Mode
Set or reset
By Group (Latch/FF[3:0], Latch/FF[7:4], and FF[8])
Clock Enable
CE or ASWE or none
LSR Control
LSR or none
26
26
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
The GSRN signal is only asynchronous, and it sets/
resets all latches/FFs in the FPGA based upon the set/
reset configuration bit for each latch/FF. The set/reset
value determines whether GSRN and LSR are set or
reset inputs. The set/reset value is independent for
each latch/FF. A new option is available to disable the
GSRN function per PFU after initial device configura-
tion.
The latch/FF can be configured to have a data front-
end select. Two data inputs are possible in the front-
end select mode, with the SEL signal used to select
which data input is used. The data input into each
latch/FF is from the output of its associated LUT, F[7:0],
or direct from DIN[7:0], bypassing the LUT. In the front-
end data select mode, both signals are available to the
latches/FFs.
If either or both of these inputs is unused or is unavail-
able, the latch/FF data input can be tied to a logic 0 or
logic 1 instead (the default is logic 0).
The latches/FFs can be configured in three basic
modes:
1. Local synchronous set/reset: the input into the
PFU's LSR port is used to synchronously set or
reset each latch/FF.
2. Local asynchronous set/reset: the input into LSR
asynchronously sets or resets each latch/FF.
3. Latch/FF with front-end select, LSR either synchro-
nous or asynchronous: the data select signal
selects the input into the latches/FFs between the
LUT output and direct data in.
For all three modes, each latch/FF can be indepen-
dently programmed as either set or reset. Figure 17
provides the logic functionality of the front-end select,
global set/reset, and local set/reset operations.
The ninth PFU FF, which is generally associated with
registering the carry-out signal in ripple mode func-
tions, can be used as a general-purpose FF. It is only
an FF and is not capable of being configured as a latch.
Because the ninth FF is not associated with an LUT,
there is no front-end data select. The data input to the
ninth FF is limited to the CIN input, logic 1, logic 0, or
the carry-out in ripple and half-logic modes.
Key: C = configuration data.
Figure 17. Latch/FF Set/Reset Configurations
DIN
LOGIC 0
LOGIC 1
F
CE
D
s_set
s_reset
CLK
SET RESET
Q
LSR
GSRN
CD
CE/ASWE
D
CLK
SET RESET
LSR
CD
CE
CE/ASWE
D
CLK
SET RESET
CD
CE
CE/ASWE
DIN
SEL
GSRN
DIN
LOGIC 0
LOGIC 1
F
DIN
LOGIC 0
LOGIC 1
F
LSR
GSRN
Q
Q
Lucent Technologies Inc.
27
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
PLC Routing Resources
Generally, the
ORCA
Foundry
Development System is
used to automatically route interconnections. Interac-
tive routing with the
ORCA
Foundry design editor
(EPIC) is also available for design optimization. To use
EPIC for interactive layout, an understanding of the
routing resources is needed and is provided in this sec-
tion.
The routing resources consist of switching circuitry and
metal interconnect segments. Generally, the metal lines
which carry the signals are designated as routing seg-
ments. The switching circuitry connects the routing
segments, providing one or more of three basic func-
tions: signal switching, amplification, and isolation. A
net running from a PFU or PIC output (source) to a
PLC or PIC input (destination) consists of one or more
routing segments, connected by switching circuitry
called configurable interconnect points (CIPs).
The following sections discuss PLC, PIC, and interquad
routing resources. This section discusses the PLC
switching circuitry, intra-PLC routing, inter-PLC routing,
and clock distribution.
Configurable Interconnect Points
The process of connecting routing segments uses
three basic types of switching circuits: two types of con-
figurable interconnect points (CIPs) and bidirectional
buffers (BIDIs). The basic element in CIPs is one or
more pass transistors, each controlled by a configura-
tion RAM bit. The two types of CIPs are the mutually
exclusive (or multiplexed) CIP and the independent CIP.
A mutually exclusive set of CIPs contains two or more
CIPs, only one of which can be on at a time. An inde-
pendent CIP has no such restrictions and can be on
independent of the state of other CIPs. Figure 18
shows an example of both types of CIPs.
Key: C = configuration data.
5-5973(C)
Figure 18. Configurable Interconnect Point
3-Statable Bidirectional Buffers
Bidirectional buffers, previously described in the SLIC
section of the programmable logic cell discussion, pro-
vide isolation as well as amplification for signals routed
a long distance. Bidirectional buffers are also used to
route signals diagonally in the PLC (described later in
the subsection entitled Intra-PLC Routing), and BIDIs
can be used to indirectly route signals through the
switching routing (xSW) segments. Any number from
zero to ten BIDIs can be used in a given PLC.
MULTIPLEXED CIP
A
B
C
O
A
B
C
O
CD
INDEPENDENT CIP
A
B
CD
B
A
=
2
28
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
General Routing Structure
Routing resources in Series 3 FPGAs generally consist of routing segments in groups of ten, with varying lengths
and connectivity to logic and other routing resources. The varying lengths of routing segments provides a hierarchy
of routing capability from chip-length routes to routes within a PLC. The hierarchical nature of the routing provides
the
ORCA
Foundry development tools with the necessary resources to route a design completely and to optimize
the routing for system speed while reducing the overall power required by the device.
Within each group of ten routing segments there is an equivalency of connectivity between pairs of segments.
These pairs are segments: [0, 4] and [1, 5] and [2, 6] and [3, 7] and [8, 9]. The equivalency in connectivity ensures
that signals on either segment in a pair have the same capability to get to a given destination. This, in turn, allows
for signal distribution from a source to varying destinations without using special routing. It also provides for routing
flexibility by ensuring that one segment position will not become so congested as to preclude routing a bus or group
of signals and allows easy connectivity from either of the twin quads in a source PFU to either of the twin quads in
any destination PFU.
Having ten segments in a group is significant in that it provides for routing a byte of data and two control signals or
parity. Due to the equivalent pairs of segments, this can also be viewed as routing two nibbles each with a control
signal. Figure 19 is an overview of the routing for a single PLC.
5-5766(F)
Figure 19. Single PLC View of Inter-PLC Route Segments
2 OF 5
LINE-BY-LINE
FINS
PFU
OUTPUT
SLIC
SWITCHING
SUR[9:0]
BL[
9:
0]
vxL
[9
:0
]
vx5
[9
:0
]
v
x
1L[
9:
0]
SU
L[
9
:
0]
vx1
R[9
:0
]
FC
LC
K
VC
K
vxH
[9
:0
]
BL[
9:
0]
hxH[9:0]
hx1U[9:0]
hCK
FC
SLL[9:0]
hx1B[9:0]
hx5[9:0]
hxL[9:0]
BR[9:0]
SUL[9:0]
BL[9:0]
FC
SUL[9:0]
BR[9:0]
LCK
SLL[9:0]
FC
SLR[9:0]
5
2
5
2
5
2
KEY: CONFIGURABLE SIGNAL LINE BREAKS
Lucent Technologies Inc.
29
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
Intra-PLC Routing
The function of the intra-PLC routing resources is to
connect the PFU's input and output ports to the routing
resources used for entry to and exit from the PLC. This
routing provides PFU feedback, corner turning, or
switching from one type of routing resource to another.
Flexible Input Structure (FINS)
The flexible input switching structure (FINS) in each
PLC of the
ORCA
Series 3 provides for the flexibility of
a crossbar switch from the routing resources to the
PFU inputs while taking advantage of the routability of
shared inputs. Connectivity between the PLC routing
resources and the PFU inputs is provided in two
stages. The primary FINS switch has 50 inputs that
connect the PLC routing to the 35 inputs on the sec-
ondary switch. The outputs of the second switch con-
nect to the 50 PFU inputs. The switches are
implemented to provide connectivity for bused signals
and individual connections.
PFU Output Switching
The PFU outputs are switched onto PLC routing
resources via the PFU output multiplexer (OMUX). The
PFU output switching segments from the output multi-
plexer provide ten connections to the PLC routing out
of 18 possible PFU outputs (F[7:0], Q[7:0], DOUT,
REGCOUT). These output switching segments con-
nect segment for segment to the SUR, SUL, SLR, and
SLL switching segments described below (e.g., O4
connects only to SUR4, not SUR5). The output switch-
ing segments also feed directly into the SLIC on a seg-
ment-by-segment basis. This connectivity is also
described below.
Switching Routing Segments (xSW)
There are four sets of switching routing segments in
each PLC. Each set consists of ten switching elements:
SUL[9:0], SUR[9:0], SLL[9:0], and SLR[9:0], tradition-
ally labeled for the upper-left, upper-right, lower-left,
and lower-right sections of the PFUs, respectively. The
xSW routing segments connect to the PFU inputs and
outputs as well as the BIDI routing segments, to be
described later. They also connect to both the horizon-
tal and vertical x1 and x5 routing segments (inter-PLC
routing resources, described later) in their specific cor-
ner. xSW segments can be used for fast connections
between adjacent PLCs or PICs without requiring the
use of inter-PLC routing resources. This capability not
only increases signal speed on adjacent PLC routing,
but also reduces routing congestion on the principal
inter-PLC routing resources. The SLL and SUR seg-
ments combine to provide connectivity to the PLCs to
the left and right of the current PLC; the SLR and SUL
segments combine to provide connectivity to the PLCs
above and below the current PLC.
Fast routes on switching segments to diagonally adja-
cent PLCs/PICs are possible using the BIDI routing
segments (discussed below) and the SLL and SLR
switching segments. The BR BIDI routing segments
combine with the SUL switching segments of the PLC
below and to the right of the current PLC to connect to
that PLC. The BL BIDI routing segments combine with
the SLL switching segments of the PLC above and to
the right of the current PLC to connect to that PLC.
These fast diagonal connections provide a great
amount of flexibility in routing congested areas of logic
and in shifting data on a per-PLC basis such as per-
forming implicit multiplications/divisions in routing
between functional logic elements.
Switching routing segments are also the chief means
by which signals are transferred between the inter-PLC
routing resources and the PFU. Each set of switching
segments has connectivity to the x1 routing segments,
and there is varying connectivity to the x5, xH, and xL
inter-PLC routing segments. Detailed information on
switching segment/inter-PLC routing connectivity is
provided later in this section in the Inter-PLC Routing
Resources subsection.
30
30
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
BIDI Routing and SLIC Connectivity
The SLIC is connected to the rest of the PLC by the
bidirectional (BIDI) routing segments and the PFU out-
put switching segments coming from the PFU output
multiplexer. The BIDI routing segments (xBID) are
labeled as BL for BIDI-left and BR for BIDI-right. Each
set of BR and BL xBID segments is composed of ten
bidirectional lines (note that these lines are diagramed
as ten input lines to the SLIC and ten output lines from
the SLIC that can be used in a mutually exclusive fash-
ion). Because the SLIC is connected directly to the out-
puts of the PFU, it provides great flexibility in routing via
the xBID segments. The PFU routing segments, O[9:0],
only connect to their respective line in the SLL, SUL,
SUR, and SLR switching segment groups. That is, O9
only connects to SLL9, SUL9, SUR9, and SLR9. The
BIDI lines provide the capability to connect to the other
member of the routing set. That means, for example,
that O9 can be routed to BR8 or BL8. This connectivity
can be used as a means to distribute or gather signals
on intra-PLC routing without disturbing inter-PLC
resources. As described in the Switching Routing Seg-
ments subsection, the BIDI routing segments are also
used for routes to a diagonally adjacent PFU.
In addition to the intra-PLC connections, the xBID and
output switching segments also have connectivity to
the x1, x5, and xL inter-PLC routing resources, provid-
ing an alternate routing path rather than using PLC
xSW segments. These connections also provide a path
to the 3-state buffers in the SLIC without encumbering
the xSW segments. In this manner, buffering or 3-state
control can be added to inter-PLC routing without dis-
turbing local functionality within a PFU.
Control Signal and Fast-Carry Routing
PFU control signal and the fast-carry routing are per-
formed using the FINS structure and several dedicated
routing paths. The fast-carry (FC) routing resources
consist of a dedicated bidirectional segment between
each orthogonal pair of PLCs. This means that a fast-
carry can go to or come from each PLC to the right or
left, above or below the subject PLC. The FINS struc-
ture is used to control the switching of these fast-carry
paths between the fast-carry input (FCIN) and fast-
carry output (FCOUT) ports of the PFU.
The PFU control inputs (CE, SEL, LSR, ASWE) and
CIN can be reached via the FINS by two special routing
segments, E1 and E2. The E1 routing segment pro-
vides connectivity between all of the xBID routing seg-
ments and the FINS. It is unidirectional from the BIDI
routing to the FINS. E1 also provides connectivity to the
PFU clock input via FINS for a local clock signal. The
E2 segment connects the SLIC DEC output to the FINS
and to a group of CIPS that provide bidirectional con-
nectivity with all of the BIDI routing segments. This
allows the DEC signal to be used in the PFU and/or
routed on the BIDI segments. It also allows signals to
be routed to the PFU on the xBID segments if the SLIC
DEC output is not used.
There is also a dedicated routing segment from the
FINS
to the SLIC TRI input used for BIDI buffer 3-state
control.
Lucent Technologies Inc.
31
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
Inter-PLC Routing Resources
The inter-PLC routing is used to route signals between
PLCs. The routing segments occur in groups of ten,
and differ in the numbers of PLCs spanned. The x1
routing segments span one PLC, the x5 routing seg-
ments span five PLCs, the xH routing segments span
one-half the width (height) of the PLC array, and the xL
routing segments span the width (height) of the PLC
array. All types of routing segments run in both horizon-
tal and vertical directions.
Table 8 shows the groups of inter-PLC routing seg-
ments in each PLC. In the table, there are two rows/col-
umns for x1 lines. They are differentiated by a T for top,
B for bottom, L for left, and R for right. In the
ORCA
Foundry design editor representation, the horizontal x1
routing segments are located above and below the
PFU. The two groups of vertical segments are located
on the left side of the PFU. The xL and x5 routing seg-
ments only run below and to the left of the PFU, while
the xH segments only run above and to the right of the
PFU. The indexes specify individual routing segments
within a group. For example, the vx5[2] segment runs
vertically to the left of the PFU, spans five PLCs, and is
the third line in the 10-bit wide group.
PLCs are arranged like tiles on the
ORCA
device.
Breaks in routing occur at the middle of the tile (e.g., x1
lines break in the middle of each PLC) and run across
tiles until the next break.
Figure 20 provides a global view of inter-PLC routing
resources across multiple PLCs.
x1 Routing Segments. There are a total of 40 x1 rout-
ing segments per PLC: 20 vertical and 20 horizontal.
Each of these are subdivided into two, 10-bit wide
buses: hx1T[9:0], hx1B[9:0], vx1L[9:0], and vx1R[9:0].
An x1 segment is one PLC long. If a signal net is longer
than one PLC, an x1 segment can be lengthened to n
times its length by turning on n 1 CIPs. A signal is
routed onto an x1 route segment via the switching rout-
ing segments or BIDI routing segments which also
allows the x1 route segment to be connected to other
inter-PLC segments of different lengths. Corner turning
between x1 segments is provided through direct con-
nections, xSW segments, and xBID segments.
x5 Routing Segments. There are two sets of ten x5
routing segments per PLC. One set (vx5[9:0]) runs ver-
tically, and the other (hx5[9:0]) runs horizontally. Each
x5 segment traverses five PLCs before it is broken by a
CIP. Two x5 segments in each group break in each
PLC. The two that break are in an equivalent pair; for
example, x5[0] and x5[4]. The x5 segments that break
shift by one at the next PLC. For example, if hx5[0] and
hx5[4] are broken at the current PLC, hx5[1] and hx5[5]
will be broken at the PLC to the right of the current
PLC. There are direct connections to the BIDI routing
segments in the PLC at which the x5 segments break,
on both sides of the break. Signal corner turning is
enabled by CIPs in each PLC that allow the broken x5
segments to directly connect to the broken x5 seg-
ments that run in the orthogonal direction. x5 corner
turning can also be accomplished via the xSW and
xBID segments in a PLC. In addition, the x5 segments
are connected to the FINS and PFU outputs on a bit-
by-bit basis by the xSW segments. x5 segments can be
connected for signal runs in multiples of five PLCs, or
they can be combined with x1 and xH routing segments
for runs of varying distances.
Table 8. Inter-PLC Routing Resources
Horizontal
Routing
Segments
Vertical
Routing
Segments
Distance
Spanned
hx1U[9:0]
vx1R[9:0]
One PLC
hx1B[9:0]
vx1L[9:0]
One PLC
hx5[9:0]
vx5[9:0]
Five PLCs
hx5[9:0]
vx5[9:0]
Five PLCs
hxL[9:0]
vxL[9:0]
PLC Array
hxH[9:0]
vxH[9:0]
1/2 PLC Array
hCLK
vCLK
PLC Array
32
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
5-5767(F)
Figure 20. Multiple PLC View of Inter-PLC Routing
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
hxH[9:0]
hx1[9:0]
hCLK
hx1[9:0]
hx5[9:0]
hxL[9:0]
hxH[9:0]
hx1[9:0]
hCLK
hx1[9:0]
hx5[9:0]
hxL[9:0]
hx1[9:0]
hx5[9:0]
hxL[9:0]
hxH[9:0]
hx1[9:0]
hCLK
vx1L[
9:0]
vx5[9
:0]
vCLK
vxH[9:0
]
vx1[9
:0]
vxL[9
:0]
vx5[9
:0]
vCLK
vxH[9:0
]
vxL[9
:0]
vx5[9
:0]
vx1[9
:0]
vCLK
vxH[9:0
]
vx1[9
:0]
vx1[9
:0]
vx1[9
:0]
vx1[9:0
]
10
2
2
10
2
10
2
10
2
10
2
10
2
10
2
10
2
10
2
10
10
2
10
2
10
2
10
2
10
2
10
2
10
2
10
2
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
SLIC
PLC BOUNDARY
2 OF 10
LINE-BY-LINE
10
2
KEY: CONFIGURABLE SIGNAL-LINE BREAKS:
Lucent Technologies Inc.
33
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
xL Routing Lines. The xL routing lines run vertically
and horizontally the height and width of the array,
respectively. There are a total of 20 xL routing lines per
PLC: ten horizontal (hxL[9:0]) and ten vertical
(vxL[9:0]). Each of the xL lines connects to the PIC
routing at either end. The xL lines are intended prima-
rily for global signals that must travel long distances
and require minimum delay and/or skew, such as
clocks or 3-state buses.
Each xL line (also called a long line) drives a buffer in
each PLC that can drive onto the horizontal and verti-
cal local clock routing segments (lCLK) in the PLC.
Also, two out of each group of ten xL segments in each
PLC can be driven by a buffer attached to a clock spine
(described later) allowing local distribution of global
clock signals. More general-purpose connections to the
long lines can be made through the xBID segments in a
PLC. Each long line is connected to an xBID segment
on a bit-by-bit basis. These BIDI connections allow cor-
ner turning from horizontal to vertical long lines, and
connection between long lines and x1 or x5 segments.
xH Routing Segments. Ten by-half (xH) routing seg-
ments run horizontally (hxH[9:0]) and ten xH routing
segments run vertically (vxH[9:0]) in each row and col-
umn in the array. These routing segments travel a dis-
tance of one-half the PLC array before being broken in
the middle of the array in the interquad area (discussed
later). They also connect at the periphery of the FPGA
to the PICs, like the xL lines. xH routing segments con-
nect to the PLCs only by switching segments. They are
intended for fast signal interconnect.
Clock (and Global CE and LSR) Routing Segments.
For a very fast and low-skew clock (or other global sig-
nal tree), clock routing segments run the entire height
and width of the PLC array. There are two clock routing
segments per PLC: one horizontal (hCLK) and one ver-
tical (vCLK). The source for these clock routing seg-
ments can be any of the I/O buffers in the PIC, the
Series 3 ExpressCLK inputs, user logic, or the pro-
grammable clock manager (PCM). The horizontal clock
routing segments (hCLK) are alternately driven by the
left and right PICs. The vertical clock routing segments
(vCLK) are alternately driven by the top and bottom
PICs.
The clock routing segments are designed to be a clock
spine. In each PLC, there is a fast connection available
from the clock segment to a long-line driver (described
earlier). With this connection, one of the clock routing
segments in each PLC can be used to drive one of the
ten xL routing segments perpendicular to it, which, in
turn, creates a clock spine tree. This feature is dis-
cussed in detail in the Clock Distribution Network sec-
tion.
Special connectivity is provided in each PLC to connect
the clock enable signals (CE and ASWE) and the LSR
signal to the clock network for fast global control signal
distribution. CE and ASWE have a special connection
to the horizontal clock spine, and LSR has a special
connection to the vertical clock spine. This allows both
signals to be routed globally within the same PLC, if
desired; however, this will consume some of the
resources available for clock signal routing.
If using these spines, the clock enable signal must
come from the right or left edge of the device, and the
LSR signal must come from the top or bottom of the
device due to their horizontal and vertical connectivity,
respectively, to the clock network.
Minimizing Routing Delay
The CIP is an active element used to connect two rout-
ing segments. As an active element, it adds signifi-
cantly to the resistance and capacitance of a routing
network (net), thus increasing the net's delay. The
advantage of the x1 segment over an x5 segment is
routing flexibility. A net from one PLC to the next is eas-
ily routed by using x1 routing segments. As more CIPs
are added to a net, the delay increases. To increase
speed, routes that are greater than two PLCs away are
routed on the x5 routing segments because a CIP is
located only in every fifth PLC. A net that spans eight
PLCs requires seven x1 routing segments and six
CIPs. Using x5 routing segments, the same net uses
two routing segments and one CIP.
34
34
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
PLC Architectural Description
Figure 21 is an architectural drawing of the PLC (as
seen in
ORCA
Foundry) that reflects the PFU, the rout-
ing segments, and the CIPs. A discussion of each of
the letters in the drawing follows.
A. These are switching routing segments (xSW) that
give the router flexibility. In general switching theory,
the more levels of indirection there are in the routing,
the more routable the network is. The xSW seg-
ments can also connect to the xSW lines in adjacent
PLCs.
B. These CIPs connect the x1 routing. These are
located in the middle of the PLC to allow the block to
connect to either the left end of the horizontal x1
segment from the right or the right end of the hori-
zontal x1 segment from the left, or both. By symme-
try, the same principle is used in the vertical
direction.
C. This set of CIPs is used to connect the x1 and x5
nets to the xSW segments or to other x1 and x5
nets. The CIPs on the major diagonal allow data to
be transmitted on a bit-by-bit basis from x1 nets to
the xSW segments and between the x1 and x5 nets.
D. This structure is the supplemental logic and inter-
connect cell, or SLIC. It contains 3-statable bidirec-
tional buffers and logic for building decoders and
AND-OR-INVERT type structures.
E. These are the primary and secondary elements of
the flexible input structure or FINS. FINS is a switch
matrix that provides high connectivity while retaining
routing capability. FINS also includes feedback
paths for softwired LUT implementation.
F. This is the PFU output switch matrix. It is a complex
switch network which, like the FINS at the input, pro-
vides high connectivity and maintains routability.
G. This set of CIPs allows an xBID segment to transfer
a signal to/from xSW segments on each side. The
BIDIs can access the PFU through the xSW seg-
ments. These CIPs allow data to be routed through
the BIDIs for amplification or 3-state control and
continue to another PLC. They also provide an alter-
native routing resource to improve routability.
H. These CIPs are used to transfer data from/to the
xBID segments to/from the x1 and xL routing seg-
ments. These CIPs have been optimized to allow
the BIDI buffers to drive the loads usually seen
when using each type of routing segment.
I. Clock input to PFU.
J. These are the ten switched output routing segments
from the PFU. They connect to the PLC switching
segments and are input to the SLIC.
K. These lines deliver the auxiliary signals clock enable
(CE), local set/reset (LSR), front-end select (SEL),
add/subtract/write enable (ASWE), as well as the
carry signals (CIN and FCIN) to the latches/FFs.
L. This is the local clock buffer. Any of the horizontal
and vertical xL lines can drive the clock input of the
PLC latches/FFs. The clock routing segments
(vCLK and hCLK) and multiplexers/drivers are used
to connect to the xL routing segments for low-skew,
low-delay global signals.
M. These routing segments are used to route the fast-
carry signal to/from the neighboring four PLCs. The
carry-out (COUT) and registered carry-out (REG-
COUT) can also be routed out of the PFU.
N. This is the E2 control routing segment. It runs from
the SLIC DEC output to the FINS and also provides
connectivity to all xBID segments.
O. The xH routing segments run one-half the length
(width) of the array before being broken by a CIP.
P. These CIPs connect the xH segments to the xSW
segments.
Q. The xBID segments are used to connect the SLIC to
the xSW segments, x1 segments, x5 segments, and
xL lines, as well as providing for diagonal PLC to
PLC connections.
R. These CIPs provide connections from the xBID seg-
ments to the E1/E2 routing segments that feed PFU
control inputs CE, LSR, CIN, ASWE, SEL, and the
clock input. Alternatively, these CIPs connect the
BIDI lines to the decoder (DEC) output of the SLIC,
for routing the DEC signal.
S. These are clock spines (vCLK and hCLK) with the
multiplexers and drivers to connect to the xL routing
segments.
T. These CIPs connect xBID segments to switching
segments in diagonally and orthogonally adjacent
PFUs.
U. These CIPs connect xSW segments to the PFU out-
put segments.
V. These CIPS connect xSW segments in orthogonally
adjacent PFUs.
W.This is the SLIC 3-state control routing segment
from the FINS to the SLIC 3-state control.
X. This is the E1 control routing segment. It provides a
PFU input path from all xBID segments.
Y. These CIPs are used to select which xBID segments
are connected to the E1/E2 signal as described in
(R).
Lucent Technologies Inc.
35
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
(continued)
5-5758(F)
Figure 21. PLC Architecture
H
S
M
G
R
L
H
H
D
R
SLIC
OUTPUT
SWITCHING
PFU
P
R
I
M
ARY
F
I
N
S
SE
CON
DAR
Y F
I
N
S
B
W
Y
A
B
P
M
O
Q
M
O
F
P
V
K
J
U
U
U
X
A
B
H
B
G
C
H
Q
Q
T
M
S
Q
Q
L
H
T
E
E
N
Q
C
C
C
A
C
C
C
A
A
A
A
C
A
A
C
C
C
C
A
36
36
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
The programmable input/output cells (PICs) are
located along the perimeter of the device. The PIC's
name is represented by a two-letter designation to indi-
cate on which side of the device it is located followed by
a number to indicate in which row or column it is
located. The first letter, P, designates that the cell is a
PIC and not a PLC. The second letter indicates the side
of the array where the PIC is located. The four sides
are left (L), right (R), top (T), and bottom (B). The indi-
vidual I/O pad is indicated by a single letter (either A, B,
C, or D) placed at the end of the PIC name. As an
example, PL10A indicates a pad located on the left
side of the array in the tenth row.
Each PIC interfaces to four bond pads and contains the
necessary routing resources to provide an interface
between I/O pads and the PLCs. Each PIC is com-
posed of four programmable I/Os (PIOs) and significant
routing resources. Each PIO contains input buffers,
output buffers, routing resources, latches/FFs, and
logic and can be configured as an input, output, or
bidirectional I/O.
PICs in the Series 3 FPGAs have significant local rout-
ing resources, similar to routing in the PLCs. This new
routing increases the ability to fix user pinouts prior to
placement and routing of a design and still maintain
routability. The flexibility provided by the routing also
provides for increased signal speed due to a greater
variety of signal paths possible.
Included in the PIC routing is a fast path from the input
pins to the SLICs in each of the three adjacent PLCs
(one orthogonal and two diagonal). This feature allows
for input signals to be very quickly processed by the
SLIC decoder function and used on-chip or sent back
off of the FPGA. Also new to the Series 3 PIOs are
latches and FFs and options for using fast, dedicated
clocks called ExpressCLKs. These features will all be
discussed in subsequent sections.
A diagram of a single PIO (one of four in a PIC) is
shown in Figure 22. Table 9 provides an overview of the
programmable functions in an I/O cell.
5-5805(F).c
Figure 22. OR3C/Txxx Programmable Input/Output (PIO) Image from
ORCA
Foundry
IN2
IN1
D0
D1
CK
SP
SD
LSR
INREGMODE
LATCHFF
LATCH
FF
D
CK
NORMAL
INVERTED
RESET
SET
LEVEL MODE
TTL
CMOS
UP
DOWN
NONE
PULL-MODE
BUFFER
TS
FAST
SLEW
SINK
RESET
SET
LSR
SP
CK
D
OUT1
OUT2
ECLK
SCLK
CE
CE_OVER_LSR
LSR_OVER_CE
ASYNC
LSR
ENABLE_GSR
DISABLE_GSR
OUT1OUTREG
OUT2OUTREG
OUT1OUT2
NOR
XOR
XNOR
AND
NAND
OR
PIO LOGIC
CLKIN
0
0
1
0
PAD
Q
Q
1
PD
TO
RO
U
TIN
G
Q
1
ECLK
SCLK
PMUX
F
R
O
M
ROU
T
IN
G
MODE
LSR
CK
D0 Q
Lucent Technologies Inc.
37
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
(continued)
5 V Tolerant I/O
The I/O on the OR3Txxx Series devices allow intercon-
nection to both 3.3 V and 5 V devices (selectable on a
per-pin basis).
The OR3Txxx devices will drive the pin to the 3.3 V lev-
els when the output buffer is enabled. If the other
device being driven by the OR3Txxx device has TTL-
compatible inputs, then the device will not dissipate
much input buffer power. This is because the OR3Txxx
output is being driven to a higher level than the TTL
level required. If the other device has a CMOS-compat-
ible input, the amount of input buffer power will also be
small. Both of these power values are dependent upon
the input buffer characteristics of the other device when
driven at the OR3Txxx output buffer voltage levels.
The OR3Txxx device has internal programmable pull-
ups on the I/O buffers. These pull-up voltages are
always referenced to V
DD
and are always sufficient to
pull the input buffer of the OR3Txxx device to a high
state. The pin on the OR3Txxx device will be at a level
1.0 V below V
DD
(minimum of 2.0 V with a minimum
V
DD
of 3.0 V). This voltage is sufficient to pull the exter-
nal pin up to a 3.3 V CMOS high input level (1.8 V, min)
or a TTL high input level (2.0 V, min) in a 5 V tolerant
system. Therefore, in a 5 V tolerant system using 5 V
CMOS parts, care must be taken to evaluate the use of
these pull-ups to pull the pin of the OR3Txxx device to
a typical 5 V CMOS high input level (2.2 V, min).
PCI Compliant I/O
The I/O on the OR3Txxx Series devices allows compli-
ance with PCI Local Bus (Rev. 2.2) 5 V and 3.3 V sig-
naling environments. The signaling environment used
for each input buffer can be selected on a per-pin basis.
The selection provides the appropriate I/O clamping
diodes for PCI compliance. Choosing an IBT input
buffer will provide PCI compliance in OR3Txxx devices.
OR3Cxx devices have PCI Local Bus compliant I/Os for
5 V signaling.
Table 9. PIO Options
Input
Option
Input Level
TTL, OR3Cxx only
CMOS, OR3Cxx or OR3Txxx
3.3 V PCI Compliant, OR3Txxx
5 V PCI Compliant, OR3Txxx
Input Speed
Fast, Delayed
Float Value
Pull-up, Pull-down, None
Register Mode
Latch, FF, Fast Zero Hold FF,
None (direct input)
Clock Sense
Inverted, Noninverted
Input Selection
Input 1, Input 2, Clock Input
Output
Option
Output Drive
Current
12 mA/6 mA or 6 mA/3 mA
Output Function
Normal, Fast Open Drain
Output Speed
Fast, Slewlim, Sinklim
Output Source
FF Direct-out, General Routing
Output Sense
Active-high, Active-low
3-State Sense
Active-high, Active-low (3-state)
FF Clocking
ExpressCLK
, System Clock
Clock Sense
Inverted, Noninverted
Logic Options
See Table 10.
I/O Controls
Option
Clock Enable
Active-high, Active-low,
Always Enabled
Set/Reset Level
Active-high, Active-low,
No Local Reset
Set/Reset Type
Synchronous, Asynchronous
Set/Reset Priority
CE over LSR, LSR over CE
GSR Control
Enable GSR, Disable GSR
38
38
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
(continued)
Inputs
As outlined earlier in Table 9, there are six major
options on the PIO inputs that can be selected in the
ORCA
Foundry tools. For OR3Cxx devices, the inputs
and bidirectional buffers can be configured as either
TTL or CMOS compatible. OR3Txxx devices support
CMOS levels only for input or bidirectional buffers, have
5 V tolerant I/Os as previously explained, but can
optionally be selected on a pin-by-pin basis to be PCI
bus 3.3 V signaling compliant (PCI bus 5 V signaling
compliance occurs in 5 V tolerant operation). The
default buffer upon powerup for the unused sites is 5 V
tolerant/5 V PCI compliant. Consult the
ORCA
macro
library, Series 3 I/O cells, for the appropriate buffers.
Inputs may have a pull-up or pull-down resistor
selected on an input for signal stabilization and power
management. Input signals in a PIO can be passed to
PIC routing on any of three paths, two general signal
paths into PIC routing, and/or a fast route into the clock
routing system.
There is also a programmable delay available on the
input. When enabled, this delay affects the IN1 and IN2
signals of each PIO, but not the clock input. The delay
allows any signal to have a guaranteed zero hold time
when input. This feature is discussed subsequently.
Inputs should have transition times of less than 500 ns
and should not be left floating. If any pin is not used, it
is 3-stated with an internal pull-up resistor enabled
automatically after configuration.
Warning: During configuration, all OR3Txxx inputs
have internal pull-ups enabled. If these inputs are
driven to 5 V, they will draw substantial current
(
5 mA). This is due to the fact that the inputs are
pulled up to 3 V.
Floating inputs increase power consumption, produce
oscillations, and increase system noise. The OR3Cxx
inputs have a typical hysteresis of approximately 280
mV (200 mV for the OR3Txxx) to reduce sensitivity to
input noise. The PIC contains input circuitry which pro-
vides protection against latch-up and electrostatic dis-
charge.
The other features of the PIO inputs relate to the new
latch/FF structure in the input path. As shown in
Figure 23, the input is optionally passed to a register or
latch/register pair. These structures can operate in the
modes listed in Table 9. In latch mode, the input signal
is fed to a latch that is clocked by a system clock signal.
The clock may be inverted or noninverted from its
sense in the PIC routing. There is also a local set/reset
signal to the latch from the PIC routing. The senses of
these signals are also programmable as well as the
capability to enable or disable the global set/reset sig-
nal and select the set/reset priority. The same control
signals may also be used to control the input latch/FF
when it is configured as a FF instead of a latch, with the
addition of another control signal used as a clock
enable.
Lucent Technologies Inc.
39
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
(continued)
Zero-Hold Input
There are two options for zero-hold input capture in the PIO. If input delay mode is selected to delay the signal from
the input pin, data can be either registered or latched with guaranteed zero-hold time in the PIO using a system
clock.
To guarantee zero hold, the system clock spine structure must be used for clocking, as will be discussed later. The
fast zero-hold mode of the PIO input takes advantage of the latch/FF combination and sources the input FF data
from a dedicated latch that is clocked by the ExpressCLK from the PIC. The ExpressCLK is a clock from a dedi-
cated input pin designed for fast, low-skew operation at the I/Os and is described more fully in the Clock Distribu-
tion Network and PIC Interquad (MID) Routing sections that follow. The combination of ExpressCLK latch and
system clock FF guarantees a zero-hold capture of input data in the PIO FF, while at the same time reducing input
setup time. Figure 23 shows a schematic of the fast-capture latch/FF and a sample timing diagram.
5-5974(F)
Note: CE and LSR signals not shown.
Figure 23. Fast-Capture Latch and Timing
D Q
INPUT DATA
LATCH
CLK
O
I
EXPRESSCLK
O
I
SYSTEM CLK
CD = 1
CLOCK ENABLE
LOCAL SET/RESET
D
Q
FF
S/R
CE
DATA OUT
TO PIC ROUTING
EXPRESSCLK
SYSTEM CLK
INPUT DATA
Q
LATCH
Q
FF
B
A
C
D
E
B
A
C
D
E
A
B
C
D
40
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
(continued)
Input Demultiplexing
The combination of input register capability and the two inputs, IN1 and IN2, from each PIO to the internal routing
provides for input signal demultiplexing without any additional resources. Figure 24 shows the input configuration
and general timing for demultiplexing a multiplexed address and data signal. The PIO input signal is sent to both
the input latch and directly to IN2. The signal is latched on the falling edge of the clock and output to routing at IN1.
The address and data are then both available at the rising edge of the system clock. These signals may be regis-
tered or otherwise processed in the PLCs at that clock edge. Figure 24 also shows the possible use of the SLIC
decoder to perform an address decode to enable which registers are to receive the input data. Although the timing
shown is for using the input register as a latch, it may also be used in the same way as an FF. Also note that the sig-
nals found in PIO inputs IN1 and IN2 can be interchanged.
5-5798(F)
Figure 24. PIO Input Demultiplexing
DEC
D
Q
PAD
PIO
D
Q
CE
SLIC
OTHER ADDRESS
LINES
SCLK
IN1
IN2
SCLK
PIO LATCH
PLC FF
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
DATA1
DATA2
DATA3
DATA4
DATA1
DATA2
DATA3
ADDR2
ADDR3
ADDR4
ADDR5
DATA0
DATA4
OUTPUT
OUTPUT
PIO INPUT
PLC
Lucent Technologies Inc.
41
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
(continued)
Outputs
The PIC's output drivers have programmable drive
capability and slew rates. Three propagation delays
(fast, slewlim, sinklim) are available on output drivers.
The sinklim mode has the longest propagation delay
and is used to minimize system noise and minimize
power consumption. The fast and slewlim modes allow
critical timing to be met.
The drive current is 12 mA sink/6 mA source for the
slewlim and fast output speed selections and
6 mA sink/3 mA source for the sinklim output. Two adja-
cent outputs can be interconnected to increase the out-
put sink/source current to 24 mA/12 mA.
All outputs that are not speed critical should be config-
ured as sinklim to minimize power and noise. The num-
ber of outputs that switch simultaneously in the same
direction should be limited to minimize ground bounce.
To minimize ground bounce problems, locate heavily
loaded output buffers near the ground pads. Ground
bounce is generally a function of the driving circuits,
traces on the printed-circuit board, and loads and is
best determined with a circuit simulation.
At powerup, the output drivers are in slewlim mode,
and the input buffers are configured as TTL-level com-
patible (CMOS for OR3Txxx) with a pull-up. If an output
is not to be driven in the selected configuration mode, it
is 3-stated.
The output buffer signal can be inverted, and the
3-state control signal can be made active-high, active-
low, or always enabled. In addition, this 3-state signal
can be registered or nonregistered. Additionally, there
is a fast, open-drain output option that directly connects
the output signal to the 3-state control, allowing the out-
put buffer to either drive to a logic 0 or 3-state, but
never to drive to a logic 1. Because there is no explicit
route required to create the open-drain output, its
response is very fast. Like the input side of the PIO,
there are two output connections from PIC routing to
the output side of the PIO, OUT1, and OUT2. These
connections provide for flexible routing and can be
used in data manipulation in the PIO as described in
subsequent paragraphs.
An FF has been added to the output path of the PIO.
The register has a local set/reset and clock enable. The
LSR has the option to be synchronous or asynchro-
nous and have priority set as clock enable over LSR or
LSR over clock enable. Clocking to the output FF can
come from either the system clock or the ExpressCLK
associated with the PIC. The input to the FF can come
from either OUT1 or OUT2, or it can be tied to V
DD
or
GND. Additionally, the input to the FF can be inverted.
Output Multiplexing
The Series 3 PIO output FF can be combined with the
new PIO logic block to perform output data multiplexing
with no PLC resources required. The PIO logic block
has three multiplexing modes: OUT1OUTREG,
OUT2OUTREG, and OUT1OUT2. OUT1OUTREG and
OUT2OUTREG are equivalent except that either OUT1
or OUT2 is MUXed with the FF, where the FF data is
output on the clock phase after the active edge. The
simplest multiplexing mode is OUT1OUT2. In this
mode, the signal at OUT1 is output to the pad while the
clock is low, and the signal on OUT2 is output to the
pad when the clock is high. Figure 25 shows a simple
schematic of a PIO in OUT1OUT2 mode and a general
timing diagram for multiplexing an address and data
signal.
Often an address will be used to generate or read a
data sample from memory with the goal of multiplexing
the data onto a single line. In this case, the address
often precedes the data by one clock cycle.
OUT1OUTREG and OUT2OUTREG modes of the PIO
logic can be used to address this situation.
Because OUT1OUTREG mode is equivalent to
OUT2OUTREG, only OUT2OUTREG mode is
described here. Figure 26 shows a simple PIO sche-
matic in OUT2OUTREG mode and general timing for
multiplexing data with a leading address. The address
signal on OUT1 is registered in the PIO FF. This delays
the address so that it aligns with the data signal. The
PIO logic block then sends the OUTREG signal
(address) to the pad when the clock is high and the
OUT2 signal (data) to the pad when the clock is low,
resulting in an aligned, multiplexed signal.
42
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
(continued)
NOTE: PIO LOGIC MODE, OUT1OUT2
5-5799(F)
Figure 25. Output Multiplexing (OUT1OUT2 Mode)
NOTE: PIO LOGIC MODE, OUT1OUT2
5-5797(F)
Figure 26. Output Multiplexing (OUT2OUTREG Mode)
CLK
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
DATA2
DATA3
DATA4
DATA5
ADDR1
ADDR2
ADDR3
DATA1
DATA2
DATA3
DATA4
DATA1
ADDR4
OUT1
OUT2
PIC OUTPUT
PLC
ADDRESS
PAD
PIO
LOGIC
OUT1
OUT2
CLK
FROM
ROUTING
DATA
FROM
ROUTING
PIC
PLC
D
Q
CLK
PAD
P/O
LOGIC
OUT1
OUT2
PIC
DATA
CLK
REG ADDRESS
DATA
ADDR1
ADDR2
ADDR3
ADDR4
DATA1
DATA2
DATA3
DATA4
DATA1
DATA2
ADDR1
ADDR2
ADDR3
ADDR4
DATA3
PAD
ADDR ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
FROM
ROUTING
ADDRESS
FROM
ROUTING
Lucent Technologies Inc.
43
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
(continued)
PIO Logic Function Generator
The PIO logic block can also generate logic functions
based on the signals on the OUT2 and CLK ports of
the PIO. The functions are AND, NAND, OR, NOR,
XOR, and XNOR. Table 10 is provided as a summary
of the PIO logic options.
PIO Register Control Signals
As discussed in the Inputs and Outputs subsections,
the PIO latches/FFs have various clock, clock enable
(CE), local set/reset (LSR), and global set/reset
(GSRN) controls. Table 11 provides a summary of
these control signals and their effect on the PIO
latches/FFs. Note that all control signals are optionally
invertible.
Table 10. PIO Logic Options
Option
Description
OUT1OUTREG
Data at OUT1 output when clock
low, data at FF out when clock
high.
OUT2OUTREG
Data at OUT2 output when clock
low, data at FF out when clock
high.
OUT1OUT2
Data at OUT1 output when clock
low, data at OUT2 when clock
high.
AND
Output logical AND of signals on
OUT2 and clock.
NAND
Output logical NAND of signals
on OUT2 and clock.
OR
Output logical OR of signals on
OUT2 and clock.
NOR
Output logical NOR of signals on
OUT2 and clock.
XOR
Output logical XOR of signals on
OUT2 and clock.
XNOR
Output logical XNOR of signals
on OUT2 and clock.
Table 11. PIO Register Control Signals
Control Signal
Effect/Functionality
ExpressCLK
Clocks input fast-capture latch;
optionally clocks output FF, or
3-state FF.
System Clock
(SCLK)
Clocks input latch/FF; optionally
clocks output FF, or 3-state FF.
Clock Enable
(CE)
Optionally enables/disables input
FF (not available for input latch
mode); optionally enables/dis-
ables output FF; separate CE
inversion capability for input and
output.
Local Set/Reset
(LSR)
Option to disable; affects input
latch/FF, output FF, and 3-state
FF if enabled.
Global Set/Reset
(GSRN)
Option to enable or disable per
PIO after initial configuration.
Set/Reset Mode
The input latch/FF, output FF, and
3-state FF are individually set or
reset by both the LSR and GSRN
inputs.
44
44
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
(continued)
PIC Routing Resources
The PIC routing borrows many of the concepts and
constructs from the PLC routing. It is designed to be
able to gather an 8-bit bidirectional bus from any eight
consecutive I/O pads and route them to either or both
of the two adjacent PLCs. The eight I/O bits do not
need to start at a PIC boundary; that is, they may start
at one of the middle two PIOs in a PIC and span three
PICs.
Substantial routing has been added to the PIC to off-
load PLC routing from being used to move signals
around the PLC array perimeter. This saves PLC rout-
ing for logic purposes and provides greater flexibility for
locking design pinouts prior to final placement and rout-
ing of the device, or allowing a change in the pinout late
in the design cycle. The PIC routing has also been
increased substantially to allow routing to the complex
PIO cells that now allow multiple inputs and outputs per
device pin, along with new sequential control signals,
such as clock enable, LSR, and clock.
PICs are grouped in pairs for purposes of discussing
PIC routing. On the sides of a device, the PICs in a pair
are referred to as top and bottom. On the top or bottom
of a device, the PICs in a pair are referred to as left or
right. For example, on the top edge of the device, the
leftmost PIC, PT1, is the left PIC of a pair, and PIC PT2
is the right PIC of that pair. The next PIC to the right,
PT3, is the left PIC of the next pair, and so on.
The need for PIC pairs stems from the routing of
switching segments and PLC half- and long-line driv-
ers. As described below, the connectivity for these
types of routing is grouped across pairs of PICs to pro-
vide complete and fast routing of I/O signals between a
given PIC and the three adjacent PLCs: one orthogonal
and two diagonal.
PIC routing segments use the same terminology as
PLC routing segments, but are prefixed with a p to dis-
tinguish them as belonging to the PICs.
PIC Switching Segments. Each PIC has two groups
of switching segments (pSW), each group having eight
lines with connectivity to the PIOs in groups of four.
One set of switching segments connects to the PIC to
the left (above), and the other set connects to the
switching segments of the PIC to the right (below). This
means of connectivity between PICs using staggered
connections of groups of switching segments allows a
given PIC to route signals to both adjacent PICs and all
adjacent PLCs efficiently. This provides single signal
routing flexibility and routing of multiple buses on
groups of I/Os without tying up global routing
resources.
px1 Routing Segments. There are five px1 routing
segments in each PIC that run parallel to the edge of
the chip on which the PIC resides, each broken by a
CIP in each PIC. The px1 segments have connectivity
to the pSW segments and to the x1 routing segments
of the two adjacent PLCs.
px2 Routing Segments. There are five px2 routing
segments in each PIC that run parallel to the edge of
the chip on which the PIC resides. To provide greater
routing flexibility, the CIPs that break the px2 segments
every two PICs are staggered across the two PICs in a
pair. One PIC of the pair has break CIPs on the even-
numbered px2 segments, and the other has them on
the odd-numbered px2 segments. The px2 segments
have connectivity to the pSW segments and to the x1
routing segments of the two adjacent PLCs.
px5 Routing Segments. There are ten px5 routing
segments in each PIC that run parallel to the edge of
the chip on which the PIC resides. Two of the ten seg-
ments are broken in each PIC so that each segment is
broken every five PICs. All ten px5 segments break at
the corners of the chip, allowing independent px5 rout-
ing on each edge of the chip. The px5 routing seg-
ments connect to the pSW segments and the x5 and
xH routing segments of the two adjacent PLCs.
pxH Routing Segments. Each PIC contains eight pxH
routing segments that run parallel to the edge of the
chip on which the PIC resides. The pxH segments have
connectivity with the xL, xH, and one set of xBID rout-
ing segments in the immediately adjacent PLC.
pxL Routing Segments. There are ten pxL routing
segments in each PIC that run parallel to the edge of
the chip on which the PIC resides. Each of the xL lines
makes a connection to an xL line from the adjacent
PLC. PIC long lines (xL) can be used for global signal
distribution just as PLC xL lines can.
Lucent Technologies Inc.
45
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
(continued)
PIC Architectural Description
The PIC architecture as seen in
ORCA
Foundry is
shown in Figure 27. The figure is the left PIC of a PIC
pair on the top edge of a Series 3 array. Both PICs in a
pair are similar, with the differences mainly lying in the
connections between the PIC switching segments
(pSW), the IN2 connections across PIC boundaries,
and the system clock spine driver residing in only one
PIC of a pair.
A. This is a programmable input/output (PIO). There
are four PIOs per PIC. The PIOs contain the PIC
logic and I/O buffers.
B. This is the PIC output switching block. It connects
the PIC switching segments and local clock lines to
the PIO output and control signals.
C. This is the system clock spine switching block and
buffer. There is only one system clock spine per pair
of PICs. Its inputs can come from the PIC switching
segments or any of the eight PIO inputs in a PIC
pair.
D. PIC switching segments (pSW). These routing seg-
ments are used to interconnect routing resources
within the PIC and to a lesser degree, between
PICs.
E. px1 routing segments. The PIC x1 routing seg-
ments traverse one PIC and break at a CIP in the
middle of each PIC.
F. px2 routing segments. The PICs have routing that
traverses two PICs between breaks. The breaks are
staggered among the five px2 segments.
G. px5 routing segments. Each of the ten PIC x5 rout-
ing segments traverses five PICs in between breaks
at a CIP. Two px5 segments break in each PIC.
H. pxH routing segments. The eight PIC xH routing
segments traverse half of the array and break at
CIPs in the interquad routing region that is in the
middle of the array.
I.
(Not used intentionally for clarity.)
J. pxL routing segments. The PIC long lines run the
entire length of the side of the array.
K. x5 routing segments from the adjacent PLC routing.
L. xL routing segments from the adjacent PLC routing.
M. x1 routing segments from the adjacent PLC routing.
N. Switching segments from the adjacent PLC routing.
O. xH routing segments from the adjacent PLC routing.
P. BIDI routing segments from the adjacent PLC rout-
ing.
Q. These are the IN2 routing segments. There is one
IN2 line from each PIO, and all eight IN2 lines from
each PIC pair are present in both PICs of a pair.
R. These CIPs connect the IN1 and IN2 routing seg-
ments from the PIOs to the PIC switching seg-
ments.
S. These CIPs break the PIC switching segments at
the interface between a PIC pair.
T. These CIPs connect adjacent PLC routing
resources to the PIC switching segments.
U. These CIPs connect inter-PIC routing with the PIC
switching segments.
V. These CIPs break the px1, px2, and px5 routing at
the middle of a PIC. The px2 and px5 CIP place-
ment varies depending on the PLC.
W. These mutually exclusive buffers can drive one long
line signal onto a PIC local clock routing segment.
X. These mutually exclusive buffers can select a
source from one of the local system clock routes to
drive the PIO 3-state control signal.
Y. These are the four local system clock routing seg-
ments. Two come from connections within the PIC,
one from the other PIC in the pair, and one from the
adjacent PLC.
Z. These mutually exclusive buffers allow a signal on
the PIC switching segments to be routed to a sys-
tem clock spine or to a PIO system clock.
AA. ExpressCLK routing line.
AB. System clock spine.
AC. These various groups of CIPs connect routing
resources from the adjacent PLC to the inter-PIC
routing resources.
AD. These buffers provide connectivity between the
PLC xL (xH) lines and the PIC xL (xH) lines or
connectivity between one of the IN2 routing seg-
ments and the PIC and/or PLC xL (xH) routing
segments.
AE. These mutually exclusive buffers and CIPs provide
connectivity to the PLC xL and xH lines from one
of the IN2 input segments.
AF. These buffers allow the IN2 signals to drive onto
the BIDI routing of the adjacent PLC, or the BIDI
routing of the adjacent PLC, and the PIC switching
segments and/or PIC half lines may be connected.
46
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells
(continued)
5-5823(F)
Figure 27. PIC Architecture
AA
AA
AA
B
Y
D
D
D
D
E
F
H
J
Z
X
AC
G
AE
AD
T
W
R
T
V
U
U
AC
J
Q
Q
R
R
C
P
O
N
M
AD
M
K
L
K
S
AF
W
T
H
AE
AC
AB
Lucent Technologies Inc.
47
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
High-Level Routing Resources
The high-level routing resources in the
ORCA
Series 3 devices are interquad routing, corner cell routing, and PIC
interquad routing. These resources and their related structures are discussed in the following subsections.
Interquad Routing
In the
ORCA
Series 3 devices, the PLC array is split into four equal quadrants. In between these quadrants, routing
has been added to route signals between the quadrants and distribute clocks. In addition to general routing, there
are four specialized clock routing spines. The general routing is discussed below, followed by the special clock rout-
ing.
One of the main purposes of interquad routing is to distribute internally generated signals, such as clocks and con-
trol signals. There are two types of interquad blocks: vertical and horizontal. Vertical interquad blocks (vIQ) run
between quadrants on the left and right, while horizontal interquad blocks (hIQ) run between top and bottom quad-
rants. Interquad lines begin and end in the MID cells that are discussed later. Since hIQ and vIQ blocks have the
same logic, only the hIQ block is described below. The interquad routing connects to x5 and xH segments. It does
not affect other local routing (xsw, x1, fast carry), so local routing is the same, whether PLC-PLC connections cross
quadrants or not. Figure 28 presents a (not to scale) view of interquad routing.
5-4538(F)
Figure 28. Interquad Routing
TMID
BMID
5
5
5
5
vIQ2
[4:0]
vIQ4
[4:0]
vIQ6
[4:0]
vIQ8[4
:0]
vIQ0[4
:0]
vIQ3
[4:0]
vIQ5
[4:0]
vIQ7
[4:0]
vIQ9[4
:0]
vIQ1[4
:0]
5
5
5
5
5
5
LMID
RMID
hIQ7[4:0]
hIQ5[4:0]
hIQ3[4:0]
hIQ1[4:0]
hIQ9[4:0]
hIQ6[4:0]
hIQ4[4:0]
hIQ2[4:0]
hIQ0[4:0]
hIQ8[4:0]
5
5
5
5
5
5
5
5
5
5
FAST CLOCK R
FAST CLOCK L
F
A
S
T
CL
OCK
T
F
AST
CL
O
C
K B
48
48
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
High-Level Routing Resources
(continued)
Figure 29 shows the connections from the interquad
routing to the inter-PLC routing for a block of the hori-
zontal interquad. The vertical interquad has similar
connections. The connections shown in Figure 29 are
made with PLCs located above and below the routing
shown in the figure. The interquad routing segments,
prefixed IH for interquad horizontal, are in ten groups of
five lines. Any one line from each group can be routed
to one of the xH segments from the top of the device
(left for vertical interquad), one of the xH segments
from the bottom of the device (right for vertical inter-
quad), and one of the x5 segments crossing the inter-
quad.
Figure 28 shows four fast middle clock (fast clock) sig-
nals with the suffixes T (top), B (bottom), R (right), and
L (left), respectively. Figure 29 also shows the fast
clock R and fast clock L lines; these are dedicated
interquad clock spines. They originate in the CLKCN-
TRL special function blocks in the middle of each edge
of the device, with the name referencing the edge of
origin. For example, fast clock R originates in the
CLKCNTRL block on the right edge of a device. Fast
clock spines traverse the entire PLC array but do not
connect to the PICs on the edge of the device opposite
to the source. Each fast clock line connects to two of
the xL lines in each PLC that run orthogonally to the
fast clock. These connections allow the fast clock lines
to generate a clock tree that can reach any PLC in the
device. Fast clocks and other clock resources are dis-
cussed in the Clock Distribution Network section.
Programmable Corner Cell Routing
Programmable Routing
The programmable corner cell (PCC) contains the cir-
cuitry to connect the routing of the two PICs in each
corner of the device. The PIC px1 and px2 segments
and eight PIC switching segments are directly con-
nected together from one PIC to another. The px5 lines
are all broken with CIPs and the PIC pxL and pxH
segments are connected from one block to another
through programmable buffers.
Corner Cell Special Functions
In addition to routing functions, special-purpose func-
tions are located in each FPGA corner. The upper-left
PCC contains connections to the boundary-scan logic
and microprocessor interface. The upper-right PCC
contains connections to the readback logic, connectiv-
ity to the global 3-state signal (TS_ALL), and a pro-
grammable clock manager. The lower-left PCC
contains connections to the internal oscillator and a
programmable clock manager. The lower-right PCC
contains connections to the start-up and global reset
logic. These functions are all more completely
described in the Special Function Blocks section of this
data sheet.
5-5821(F)
Figure 29. hIQ Block Detail
IH 0[4:0]
IH 1[4:0]
IH 2[4:0]
IH 3[4:0]
IH 4[4:0]
F A S T C LO C K R
IH 5[4:0]
IH 6[4:0]
IH 7[4:0]
IH 8[4:0]
IH 9[4:0]
F A S T C LO C K L
B L[9:0] vxL[9:0] vx5[9:0] vx1[9:0]
S U L[9:0]
vx1[9:0]
vxH [9:0] B L[9:0]
F A S T
vck
C A R R Y
Lucent Technologies Inc.
49
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
High-Level Routing Resources
(continued)
PIC Interquad (MID) Routing
There is also connectivity between the PICs in each
quadrant, as well as a clock control (CLKCNTRL) mod-
ule (discussed in the Special Function Blocks section)
between the PIC routing and the interquad routing.
These blocks are called LMID (left), TMID (top), RMID
(right), and BMID (bottom). The TMID routing is shown
in Figure 30. As with the hIQ and vIQ blocks, the only
connectivity to the PIC routing is to the global pxH and
px5 segments.
The pxH segments from the one quadrant can be con-
nected through a CIP to its counterpart in the opposite
quadrant, providing a path that spans the array of
PICs. Since a passive CIP is used to connect the two
pxH segments, a 3-state signal can be routed on the
two pxH segments in the opposite quadrants, and then
connected through this CIP. As with the hIQ and vIQ
blocks, CIPs and buffers allow nibble-wide connections
between the interquad segments, the xH segments,
and the x5 segments.
5-5822(F)
Figure 30. Top (TMID) Routing
EXPRESSCLK RIGHT
PIC LOCAL CLOCKS
PIC LOCAL CLOCKS
pxL[9:0]
pxH[7:0]
px5[9:0]
px1[4:0]
pSW[7:4]
pSW[3:0]
pSW[7:4]
pSW[3:0]
px2[4:0]
1v
9x
L
[
4]
1v
8x
L
[
3]
I
v
7x
L
[
2]
FA
S
T
CL
O
C
K
I
v
7x
L
[
0]
I
v
6x
L
[
3]
I
v
6x
L
[
1]
I
v
5x
L
[
2]
I
v
5x
L
[
0]
I
v
4x
L
[
3]
I
v
3x
L
[
3]
I
v
3x
L
[
1]
I
v
2x
L
[
2]
I
v
2x
L
[
0]
I
v
1x
L
[
3]
I
v
1x
L
[
1]
1v
0x
L
[
2]
1v
0x
L
[
0]
Iv4
xL
1
]
in2[A:D] FROM LEFT
in[A:D] FROM RIGHT
CORNER ExpressCLK
FROM RIGHT
FROM LEFT
EXPRESSCLK LEFT
SHUTOFF
50
50
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Clock Distribution Network
The Series 3 FPGAs provide three types of high-
speed, low-skew clock distributions: system clock, fast
middle clock (fast clock), and ExpressCLK. Because of
the great variety of sources and distribution for clock
signals in the
ORCA
Series 3, the clock mechanisms
will be described here from the inside out. The clock
connections to the PFU will be described, followed by
clock distribution to the PLC array, clock sources to the
PLC array, and finally ending with clock sources and
distribution in the PICs. The ExpressCLK inputs are
new, dedicated clock inputs in Series 3 FPGAs. They
are mentioned in several of the clock network descrip-
tions and are described fully later in this section.
PFU Clock Sources
Within a PLC there are five sources for the clock signal
of the latches/FFs in the PFU. Two of the signals are
generated off of the long lines (xL) within the PLC: one
from the set of vertical long lines and one from the set
of horizontal long lines. For each of these signals, any
one of the ten long lines of each set, vertical or horizon-
tal, can generate the clock signal. Two of the five PFU
clock sources come from neighboring PLCs. One clock
is generated from the PLC to the left or right of the cur-
rent PLC, and one is generated from the PLC above or
below the current PLC. The selection decision as to
where these signals come from, above/below and left/
right, is based on the position of the PLC in the array
and has to do with the alternating nature of the source
of the system clock spines (discussed later). The last of
the five clock sources is also generated within the PLC.
The E1 control signal, described in the PLC Routing
Resources section, can drive the PFU clock. The E1
signal can come from any xBID routing resource in the
PLC. The selection and switching of clock signals in a
PLC is performed in the FINS. Figure 31 shows the
PFU clock sources for a set of four adjacent PLCs.
Global Control Signals
The four clock signals in each PLC that are generated
from the long lines (xL) in the current PLC or an adja-
cent PLC can also be used to drive the PFU clock
enable (CE), local set/reset (LSR) and add/subtract/
write enable (ASWE) signals. The clock signals gener-
ated from vertical long lines can drive CE and ASWE,
and the clocks generated from horizontal long lines can
drive LSR. This allows for low-skew global distribution
of two of these three control signals with the clock rout-
ing while still allowing a global clock route to occur.
5-6054(F)
Figure 31. PFU Clock Sources
PFU
PLC
PFU
PLC
PFU
PLC
PFU
PLC
E1
E1
E1
E1
hxL[9:0]
hxL[9:0]
vxL[9:0]
vxL[9:0]
Lucent Technologies Inc.
51
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Clock Distribution Network
(continued)
Clock Distribution in the PLC Array
System Clock (SCLK)
The clock distribution network, or clock spine network,
within the PLC array is designed to minimize clock skew
while maximizing clock flexibility. Clock flexibility is
expressed in two ways: the ease with which a single
clock is routed to the entire array, and the capability to
provide multiple clocks to the PLC array.
There is one horizontal and one vertical clock spine
passing through each PLC. The horizontal clock spine
is sourced from the PIC in the same row on either the
left- or right-hand side of the array, with the source side
(left or right) alternating for each row. The vertical clock
spines are similarly sourced from the PICs alternating
from the top or bottom of a column. Each clock spine is
capable of driving one of the ten xL routing segments
that run orthogonal to it within each PLC. Full connec-
tivity to all PFUs is maintained due to the connectivity
from the xL lines to the PFU clock signals described in
the previous section; however, only an xL line in every
other row (column) needs to be driven to allow the
given clock signal to be distributed to every PFU.
Figure 32 is a high-level diagram of the Series 3 system
clock spine network with sample xL line
connections for a 4 x 4 array of PLCs.
The clock spine structure previously described pro-
vides for complete distribution of a clock from any I/O
pin to the entire PLC array by means of a single clock
spine and long lines (xL). This distribution system also
provides a means to have many different clocks routed
to many different and dispersed locations in the PLC
array. Each spine can carry a different clock signal, so
for the OR3C/T55 (which has an 18 x 18 array of PLCs,
implying nine clock spines per side), 36 input clock sig-
nals can be supported using the system clock network.
Fast Clock
Fast clocks are high-speed, low-skew clock spines that
originate from the CLKCNTRL special function blocks
(described later). There are four fast clock spines--one
originating on the middle of each edge of the array. The
spines run in the interquad region of the PLC array
from their source side of the device to the last row or
column on the opposite side of the device. The fast
clocks connect to two long lines, xL[8] and xL[9], that
run orthogonal to the spine direction in each PLC.
These long lines can then be connected to the PFU
clock input in the same manner as the general system
clocks, and, like the system clock connections, xL lines
are only needed in every other row (column) to distrib-
ute a clock to every PFU. The limited number of long-
line connections and the low skew of the CLKCNTRL
source combine to make the fast clocks a very robust,
low-skew clock source.
5-5801(F).a
Figure 32.
ORCA
Series 3 System Clock Distribution Overview
(xL)
HORIZONTAL
(xL)
UNUSED
(xL)
(xL)
UNUSED
SCLK SPINE
(xL)
UNUSED
SCLK SPINE
VERTICAL
SCLK SPINE
SCLK SPINE
SCLK SPINE
UNUSED
SCLK SPINE
UNUSED
SCLK SPINE
UNUSED
SCLK SPINE
UNUSED
SCLK SPINE
UNUSED
SCLK SPINE
52
52
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Clock Distribution Network
(continued)
Clock Sources to the PLC Array
The source of a clock that is globally available to the
PLC array can be from any user I/O pad, any of the
ExpressCLK
pads, or an internally generated source.
System Clock
As described in the Programmable Input/Output Cells
section, PICs are grouped in adjacent pairs. Any one of
the eight pads in a PIC pair can drive a clock spine in a
row or column. For PIC pairs on the top of the chip, the
column associated with the left PIC has the clock
spine, for pairs on the bottom, the right PIC column has
the spine. The top PIC of the pair sources the spine
from the left side of the array, and the bottom PIC of the
pair sources the spine from the right side of the array.
Clock delay and skew are minimized by having a single
clock buffer per pair of PICs. The clock spine for each
pair can also be driven by one of the four PIC switching
segments (pSW) in each PIC of the pair. This allows a
signal generated in the PLC array to be routed onto the
global clock spine network. The system clock output of
the programmable clock manager (PCM) may also be
routed to the global system clock spines via the pSW
segments. Figure 33 shows the clock spine multiplex-
ing structure for a pair of PICs on the top of the array.
Fast Clock
The fast clock spines are sourced to the PLC array
from each side of the device by the ExpressCLK pads
via the CLKCNTRL function block (described in the
Special Function Blocks section). The ExpressCLK and
fast clock source from the pads is shown in Figure 34
and will be described further in the ExpressCLK Inputs
subsection.
5-5800(F)
Figure 33. PIC System Clock Spine Generation
Clocks in the PICs
Because the Series 3 FPGAs have latches and FFs in
the I/Os, it is necessary to have clock signal distribution
to the PIOs as well as in the PLC array. The system
clock, the fast clock, and the ExpressCLK are available
for PIO clocking.
PIC System Clock
There are five local system clock lines in each PIC.
Much like the sources for a clock in the PFU, two of the
local PIC clocks are generated within the PIC from long
lines. One is generated from the set of ten PIC long
lines (pxL) that runs parallel to the PICs on a side, and
the other is generated from the set of ten long lines (xL)
from the PLC array that terminate in the PIC. Another
local PIC system clock route comes from the set of ten
xL lines in the adjacent PLC that is parallel to the side
of the array on which the PIC resides. The fourth local
PIC system clock route comes from the set of ten long
lines (xL) from the PLC array that terminate in the adja-
cent PIC that is not part of the same PIC pair. Much like
the E1 signals in the PLCs that are used to distribute a
local clock to the PFU source, the fifth local clock line in
each PIC comes from local pSW signals. This clock
signal for each PIC is shown in Figure 33. One of these
five local PIC system clocks is selected for the system
clock signal in the PIO. It is used as the PIO system
clock for both input and output clocking as selected
within the PIO. All PIOs in a PIC share the same sys-
tem clock.
PIC ExpressCLK
The ExpressCLK signal used at the PIC latches/FFs
comes from the CLKCNTRL function block that resides
in the middle of the side on which the PIC resides. A
single signal comes from the CLKCNTRL and is driven
by separate buffers onto two ExpressCLK long wires.
One of these ExpressCLK signals goes to the PICs on
the right of (above) the CLKCNTRL block, and the
other ExpressCLK signal goes to the PICs on the left of
(below) the CLKCNTRL block on that side.
PAD A
PAD B
PAD C
PAD D
pSW[4]
pSW[5]
pSW[6]
pSW[7]
PA
D
A
PA
D
B
PAD
C
PA
D
D
pS
W
[
4]
pS
W
[
5]
pS
W
[
6]
pS
W
[
7]
SPINE
TO LOCAL CLOCKS
TO LOCAL CLOCKS
TPICL
TPICR
Lucent Technologies Inc.
53
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Clock Distribution Network
(continued)
ExpressCLK Inputs
There are four dedicated ExpressCLK pads on each
Series 3 device: one in the middle of each side. Two
other user I/O pads can also be used as corner
ExpressCLK
inputs, one on the lower-left corner, and
one on the upper-right corner. The corner ExpressCLK
pads feed the ExpressCLK to the two sides of the array
that are adjacent to that corner, always driving the
same signal in both directions. The ExpressCLK route
from the middle pad and from the corner pad associ-
ated with that side are multiplexed and can be glitch-
lessly stopped/started under user control using the
StopCLK
feature of the CLKCNTRL function block
(described under Special Function Blocks) on that side.
The ExpressCLK output of the programmable clock
manager (PCM) is programmably connected to the cor-
ner ExpressCLK routes. PCM blocks are found in the
same corners as the corner ExpressCLK signals and
are described in the Special Function Blocks section.
The ExpressCLK structure is shown in Figure 34 (PCM
blocks are not shown).
5-5802(F)
Note: All multiplexers are set during configuration.
Figure 34. ExpressCLK and Fast Clock Distribution
Selecting Clock Input Pins
Any user I/O pin on an
ORCA
FPGA can be used as a
fast, low-skew system clock input. Since the four dedi-
cated ExpressCLK inputs can only be used to distribute
global signals into the FPGA, these pins should be
selected first as clock pins. Within the interquad region
of the device, these clocks sourced by the ExpressCLK
inputs are called fast clocks. Choosing the next clock
pin is completely arbitrary, but using a pin that is near
the center of an edge of the device will provide the low-
est skew system clock network. The pin-to-pin timing
numbers in the Timing Characteristics section assume
that the clock pin is in one of the PICs at the center of
any side of the device next to an ExpressCLK pad. For
actual timing characteristics for a given clock pin, use
the timing analyzer results from
ORCA
Foundry.
To select subsequent clock pins, certain rules should
be followed. As discussed in the Programmable Input/
Output Cells section, PICs are grouped into adjacent
pairs. Each of these pairs contains eight I/Os, but only
one of the eight I/Os in a PIC pair can be routed directly
onto a system clock spine. Therefore, to achieve top
performance, the next clock input chosen should not be
one of the pins from a PIC pair previously used for a
clock input. If it is necessary to have a second input in
the same PIC pair route onto global system clock rout-
ing, the input can be routed to a free clock spine using
the PIC switching segment (pSW) connections to the
clock spine network at some small sacrifice in speed.
Alternatively, if global distribution of the secondary
clock is not required, the signal can be routed on long
lines (xL) and input to the PFU clock input without
using a clock spine.
Another rule for choosing clock pins has to do with the
alternating nature of clock spine connections to the xL
and pxL routing segments. Starting at the left side of
the device, the first vertical clock spine from the top
connects to hxL[0] (horizontal xL[0]), and the first verti-
cal clock spine from the bottom connects to hxL[5] in all
PLC rows. The next vertical clock spine from the top
connects to hxL[1], and the next one from the bottom
connects to hxL[6]. This progression continues across
the device, and after a spine connects to hxL[9], the
next spine connects to hxL[0] again. Similar connec-
tions are made from horizontal clock spines to vxL (ver-
tical xL) lines from the top to the bottom of the device.
Because the
ORCA
Series 3 clock routing only
requires the use of an xL line in every other row or col-
umn, even two inputs chosen 20 PLCs apart on the
same xL line will not conflict, but it is always better to
avoid these choices, if possible. The fast clock spines
in the interquad routing region also connect to xL[8]
and xL[9] for each set of xL lines, so it is better to avoid
user I/Os that connect to xL[8] or xL[9] when a fast
clock is used that might share one of these connec-
tions. Another reason to use the fast clock spines is
that since they use only the xL[9:8] lines, they will not
conflict with internal data buses which typically use
xL[7:0]. For more details on clock selection, refer to
application notes on clock distribution in
ORCA
Series
3 devices.
EX PR ES SC LKS TO PIO s
FAST C LO C KS
E XPR ES SC LK PAD S
C LKC N TR L
B LOC K
54
54
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Special Function Blocks
Special function blocks in the Series 3 provide extra
capabilities beyond general FPGA operation. These
blocks reside in the corners and MIDs (middle inter-
quad areas) of the FPGA array.
Single Function Blocks
Most of the special function blocks perform a specific
dedicated function. These functions are data/configura-
tion readback control, global 3-state control (TS_ALL),
internal oscillator generation, global set/reset (GSRN),
and start-up logic.
Readback Logic
The readback logic is located in the upper right corner
of the FPGA and can be enabled via a bit stream option
or by instantiation of a library readback component.
Readback is used to read back the configuration data
and, optionally, the state of the PFU outputs. A read-
back operation can be done while the FPGA is in nor-
mal system operation. The readback operation cannot
be daisy-chained. To use readback, the user selects
options in the bit stream generator in the
ORCA
Foundry Development System.
Table 12 provides readback options selected in the bit
stream generator tool. The table provides the number
of times that the configuration data can be read back.
This is intended primarily to give the user control over
the security of the FPGA's configuration program. The
user can prohibit readback (0), allow a single readback
(1), or allow unrestricted readback (U).
Readback can be performed via the Series 3 micropro-
cessor interface (MPI) or by using dedicated FPGA
readback controls. If the MPI is enabled, readback via
the dedicated FPGA readback logic is disabled. Read-
back using the MPI is discussed in the Microprocessor
Interface (MPI) section.
The pins used for dedicated readback are readback
data (RD_DATA), read configuration (
RD_CFG
), and
configuration clock (CCLK). A readback operation is ini-
tiated by a high-to-low transition on
RD_CFG
. The
RD_CFG
input must remain low during the readback
operation. The readback operation can be restarted at
frame 0 by driving the
RD_CFG
pin high, applying at
least two rising edges of CCLK, and then driving
RD_CFG
low again. One bit of data is shifted out on
RD_DATA at the rising edge of CCLK. The first start bit
of the readback frame is transmitted out several cycles
after the first rising edge of CCLK after
RD_CFG
is input
low (see the Readback Timing Characteristics table in
the Timing Characteristics section). To be certain of the
start of the readback frame, the data can be monitored
for the 01 frame start bit pair.
Readback can be initiated at an address other than
frame 0 via the new microprocessor interface (MPI)
control registers (see the Microprocessor Interface
(MPI) section for more information). In all cases, read-
back is performed at sequential addresses from the
start address.
It should be noted that the RD_DATA output pin is also
used as the dedicated boundary-scan output pin, TDO.
If this pin is being used as TDO, the RD_DATA output
from readback can be routed internally to any other pin
desired. The
RD_CFG
input pin is also used to control
the global 3-state (TS_ALL) function. Before and during
configuration, the TS_ALL signal is always driven by
the
RD_CFG
input and readback is disabled. After con-
figuration, the selection as to whether this input drives
the readback or global 3-state function is determined
by a set of bit stream options. If used as the
RD_CFG
input for readback, the internal TS_ALL input can be
routed internally to be driven by any input pin.
Table 12. Readback Options
Option
Function
0
Prohibit Readback
1
Allow One Readback Only
U
Allow Unrestricted Number of Readbacks
Lucent Technologies Inc.
55
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Special Function Blocks
(continued)
The readback frame contains the configuration data
and the state of the internal logic. During readback, the
value of all registered PFU and PIC outputs can be
captured. The following options are allowed when
doing a capture of the PFU outputs.
1. Do not capture data (the data written to the RAMs,
usually 0, will be read back).
2. Capture data upon entering readback.
3. Capture data based upon a configurable signal
internal to the FPGA. If this signal is tied to
logic 0, capture RAMs are written continuously.
4. Capture data on either options 2 or 3 above.
The readback frame has an identical format to that of
the configuration data frame, which is discussed later in
the Configuration Data Format section. If LUT memory
is not used as RAM and there is no data capture, the
readback data (not just the format) will be identical to
the configuration data for the same frame. This eases a
bitwise comparison between the configuration and
readback data. The configuration header, including the
length count field, is not part of the readback frame.
The readback frame contains bits in locations not used
in the configuration. These locations need to be
masked out when comparing the configuration and
readback frames. The development system optionally
provides a readback bit stream to compare to readback
data from the FPGA. Also note that if any of the LUTs
are used as RAM and new data is written to them,
these bits will not have the same values as the original
configuration data frame either.
Global 3-State Control (TS_ALL)
To increase the testability of the
ORCA
Series FPGAs,
the global 3-state function (TS_ALL) disables the
device. The TS_ALL signal is driven from either an
external pin or an internal signal. Before and during
configuration, the TS_ALL signal is driven by the input
pad
RD_CFG
. After configuration, the TS_ALL signal
can be disabled, driven from the
RD_CFG
input pad, or
driven by a general routing signal in the upper right cor-
ner. Before configuration, TS_ALL is active-low; after
configuration, the sense of TS_ALL can be inverted.
The following occur when TS_ALL is activated:
1. All of the user I/O output buffers are 3-stated, the
user I/O input buffers are pulled up (with the pull-
down disabled), and the input buffers are configured
with TTL input thresholds (OR3Cxx only).
2. The TDO/RD_DATA output buffer is 3-stated.
3. The
RD_CFG
,
RESET
, and
PRGM
input buffers remain
active with a pull-up.
4. The DONE output buffer is 3-stated, and the input
buffer is pulled up.
Internal Oscillator
The internal oscillator resides in the lower left corner of
the FPGA array. It has output clock frequencies of
1.25 MHz and 10 MHz. The internal oscillator is the
source of the internal CCLK used for configuration. It
may also be used after configuration as a general-
purpose clock signal.
Global Set/Reset (GSRN)
The GSRN logic resides in the lower right corner of the
FPGA. GSRN is an invertible, default, active-low signal
that is used to reset all of the user-accessible latches/
FFs on the device. GSRN is automatically asserted at
powerup and during configuration of the device.
The timing of the release of GSRN at the end of config-
uration can be programmed in the start-up logic
described below. Following configuration, GSRN may
be connected to the
RESET
pin via dedicated routing, or
it may be connected to any signal via normal routing.
Within each PFU and PIO, individual FFs and latches
can be programmed to either be set or reset when
GSRN is asserted. A new option in Series 3 allows indi-
vidual PFUs and PIOs to turn off the GSRN signal to its
latches/FFs after configuration.
The
RESET
input pad has a special relationship to
GSRN. During configuration, the
RESET
input pad
always initiates a configuration abort, as described in
the FPGA States of Operation section. After configura-
tion, the global set/reset signal (GSRN) can either be
disabled (the default), directly connected to the
RESET
input pad, or sourced by a lower-right corner signal. If
the
RESET
input pad is not used as a global reset after
configuration, this pad can be used as a normal input
pad.
56
56
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Special Function Blocks
(continued)
Start-Up Logic
The start-up logic block is located in the lower right cor-
ner of the FPGA. This block can be configured to coor-
dinate the relative timing of the release of GSRN, the
activation of all user I/Os, and the assertion of the
DONE signal at the end of configuration. If a start-up
clock is used to time these events, the start-up clock
can come from CCLK, or it can be routed into the start-
up block using lower right corner routing resources.
These signals are described in the Start-Up subsection
of the FPGA States of Operation section.
Clock Control (CLKCNTRL) and StopCLK
There is one CLKCNTRL block in the MID section of
the interquad routing on each side of the FPGA. This
block is used to selectively distribute the fast clock to
the PLC array and the left (top) and right (bottom)
ExpressCLKs (ECKL and ECKR) to the side of the
array on which the CLKCNTRL block resides.
The source clock for the CLKCNTRL block comes
either from the ExpressCLK pad at the middle of the
side of the FPGA or from the corner ExpressCLK route
that comes from the corner ExpressCLK pad (at the
lower left or upper right of the device, whichever is
closer). The programmable clock manager ExpressCLK
output can also be sourced to this corner routing for
distribution at the two closest CLKCNTRL blocks.
Each CLKCNTRL block also features an invertible
StopCLK
shutoff input that is available from local rout-
ing. This feature may be used to glitchlessly stop and
start the clock at the three outputs of each CLKCNTRL
block and has the option of doing so on either the rising
or falling edge of the clock. When the clock is halted
based on its rising edge, it stops and stays at V
DD
.
When it is stopped based on its falling edge, it stops
and stays at GND. If the StopCLK shutoff signal meets
the CLKCNTRL setup and hold times, the clock is
stopped on the second clock cycle after the shutoff sig-
nal. A diagram of the bottom CLKCNTRL block and
StopCLK
timing is shown in Figure 35.
5-5981(F)
Notes:
CLKCNTRL output clocks are ExpressCLK left and right and fast clock.
Clock shutoff shown active-high acting on clock falling edge.
Figure 35. Top CLKCNTRL Function Block
CORNER EXPRESSCLK
CLOCK SHUTOFF
EXPRESSCLK RIGHT
EXPRESSCLK LEFT
FAST CLOCK
CLOCK SHUTOFF
OFF_SET
OFF_HLD
OFF_SET
OFF_HLD
CLKCNTRL OUTPUT
CLOCKS
Lucent Technologies Inc.
57
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Special Function Blocks
(continued)
Boundary Scan
The increasing complexity of integrated circuits (ICs)
and IC packages has increased the difficulty of testing
printed-circuit boards (PCBs). To address this testing
problem, the
IEEE
standard 1149.1/D1 (
IEEE
Standard
Test Access Port and Boundary-Scan Architecture) is
implemented in the
ORCA
series of FPGAs. It allows
users to efficiently test the interconnection between
integrated circuits on a PCB as well as test the inte-
grated circuit itself. The
IEEE
1149.1/D1 standard is a
well-defined protocol that ensures interoperability
among boundary-scan (BSCAN) equipped devices
from different vendors.
The
IEEE
1149.1/D1 standard defines a test access
port (TAP) that consists of a four-pin interface with an
optional reset pin for boundary-scan testing of inte-
grated circuits in a system. The
ORCA
Series FPGA
provides four interface pins: test data in (TDI), test
mode select (TMS), test clock (TCK), and test data out
(TDO). The
PRGM
pin used to reconfigure the device
also resets the boundary-scan logic.
The user test host serially loads test commands and
test data into the FPGA through these pins to drive out-
puts and examine inputs. In the configuration shown in
Figure 36, where boundary scan is used to test ICs,
test data is transmitted serially into TDI of the first
BSCAN device (U1), through TDO/TDI connections
between BSCAN devices (U2 and U3), and out TDO of
the last BSCAN device (U4). In this configuration, the
TMS and TCK signals are routed to all boundary-scan
ICs in parallel so that all boundary-scan components
operate in the same state. In other configurations, mul-
tiple scan paths are used instead of a single ring. When
multiple scan paths are used, each ring is indepen-
dently controlled by its own TMS and TCK signals.
Figure 37 provides a system interface for components
used in the boundary-scan testing of PCBs. The three
major components shown are the test host, boundary-
scan support circuit, and the devices under test
(DUTs). The DUTs shown here are
ORCA
Series
FPGAs with dedicated boundary-scan circuitry. The
test host is normally one of the following: automatic test
equipment (ATE), a workstation, a PC, or a micropro-
cessor.
5-5972(F)
Key: BSC = boundary-scan cell, BDC = bidirectional data cell,
and DCC = data control cell.
Figure 36. Printed-Circuit Board with Boundary-
Scan Circuitry
TDI
TMS
TCK
TDO
TDI
TDO
TMS
TCK
U2
net a
net b
net c
PLC
ARRAY
BDC
BSC
p_in
p_ts
SCAN
OUT
SCAN
IN
PR[ij]
DCC
p_out
BDC
BSC
p_in
p_out
p_ts
PL[ij]
DCC
SCAN
IN
SCAN
OUT
BDC
DCC
BSC
p_in
p_out
p_ts
SCAN
OUT
PB[ij]
SCAN
IN
TDO TCK TMS TDI
TAPC
BYPASS
REGISTER
INSTRUCTION
REGISTER
BDC
DCC
BSC
p_in
p_out
p_ts
SCAN
OUT
SCAN
IN
PT[ij]
SEE ENLARGED VIEW BELOW
s
TDI
TDO
TMS
TCK
U3
TDI
TDO
TMS
TCK
U4
TDI
TDO
TMS
TCK
U2
58
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Special Function Blocks
(continued)
5-6765(F)
Figure 37. Boundary-Scan Interface
D[7:0]
INTR
MICRO-
PROCESSOR
D[7:0]
CE
RA
R/W
DAV
INT
SP
TMS0
TCK
TDI
TDO
TDI
TMS
TCK
TDO
ORCA
SERIES
FPGA
TDI
ORCA
SERIES
FPGA
TMS
TCK
TDO
TDI
TMS
TCK
TDO
ORCA
SERIES
FPGA
LUCENT
BOUNDARY-
SCAN
MASTER
(BSM)
(DUT)
(DUT)
(DUT)
The boundary-scan support circuit shown in Figure 37
is the 497AA Boundary-Scan Master (BSM). The BSM
off-loads tasks from the test host to increase test
throughput. To interface between the test host and the
DUTs, the BSM has a general microprocessor interface
and provides parallel-to-serial/serial-to-parallel conver-
sion, as well as three 8K data buffers. The BSM also
increases test throughput with a dedicated automatic
test-pattern generator and with compression of the test
response with a signature analysis register. The PC-
based boundary-scan test card/software allows a user
to quickly prototype a boundary-scan test setup.
Boundary-Scan Instructions
The
ORCA
Series boundary-scan circuitry is used for
three mandatory
IEEE
1149.1/D1 tests (EXTEST,
SAMPLE/PRELOAD, BYPASS), the optional
IEEE
1149.1/D1 IDCODE instruction, and five
ORCA
-defined
instructions. The 3-bit wide instruction register sup-
ports the nine instructions listed in Table 13, where the
use of PSR1 or USERCODE is selectable by a bit
stream option.
Table 13. Boundary-Scan Instructions
Code
Instruction
000
EXTEST
001
PLC Scan Ring 1 (PSR1)/USERCODE
010
RAM Write (RAM_W)
011
IDCODE
100
SAMPLE/PRELOAD
101
PLC Scan Ring 2 (PSR2)
110
RAM Read (RAM_R)
111
BYPASS
Lucent Technologies Inc.
59
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Special Function Blocks
(continued)
The external test (EXTEST) instruction allows the inter-
connections between ICs in a system to be tested for
opens and stuck-at faults. If an EXTEST instruction is
performed for the system shown in Figure 36, the con-
nections between U1 and U2 (shown by nets a, b, and
c) can be tested by driving a value onto the given nets
from one device and then determining whether the
same value is seen at the other device. This is deter-
mined by shifting 2 bits of data for each pin (one for the
output value and one for the 3-state value) through the
BSR until each one aligns to the appropriate pin. Then,
based upon the value of the 3-state signal, either the
I/O pad is driven to the value given in the BSR, or the
BSR is updated with the input value from the I/O pad,
which allows it to be shifted out TDO.
The SAMPLE/PRELOAD instruction is useful for sys-
tem debugging and fault diagnosis by allowing the data
at the FPGA's I/Os to be observed during normal
operation or written during test operation. The data for
all of the I/Os is captured simultaneously into the BSR,
allowing them to be shifted-out TDO to the test host.
Since each I/O buffer in the PICs is bidirectional, two
pieces of data are captured for each I/O pad: the value
at the I/O pad and the value of the 3-state control sig-
nal. For preload operation, data is written from the BSR
to all of the I/Os simultaneously.
There are five
ORCA
-defined instructions. The PLC
scan rings 1 and 2 (PSR1, PSR2) allow user-defined
internal scan paths using the PLC latches/FFs. The
RAM_Write Enable (RAM_W) instruction allows the
user to serially configure the FPGA through TDI. The
RAM_Read Enable (RAM_R) allows the user to read
back RAM contents on TDO after configuration. The
IDCODE instruction allows the user to capture a 32-bit
identification code that is unique to each device and
serially output it at TDO. The IDCODE format is shown
in Table 14.
Table 14. Boundary-Scan ID Code
* PLC array size of FPGA, reverse bit order.
Note: Table assumes version 0.
Device
Version
(4 bits)
Part*
(10 bits)
Family
(6 bits)
Manufacturer
(11 bits)
LSB
(1 bit)
OR3T20
0000
0011000000 110000
00000011101
1
OR3T30
0000
0111000000 110000
00000011101
1
OR3C/T55
0000
0100100000 110000
00000011101
1
OR3C/T80
0000
0110100000 110000
00000011101
1
OR3T125
0000
0011100000 110000
00000011101
1
OR3T165
0000
0000010000 110000
00000011101
1
60
60
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Special Function Blocks
(continued)
ORCA
Boundary-Scan Circuitry
The
ORCA
Series boundary-scan circuitry includes a
test access port controller (TAPC), instruction register
(IR), boundary-scan register (BSR), and bypass regis-
ter. It also includes circuitry to support the four pre-
defined instructions.
Figure 38 shows a functional diagram of the boundary-
scan circuitry that is implemented in the
ORCA
Series.
The input pins' (TMS, TCK, and TDI) locations vary
depending on the part, and the output pin is the dedi-
cated TDO/RD_DATA output pad. Test data in (TDI) is
the serial input data. Test mode select (TMS) controls
the boundary-scan test access port controller (TAPC).
Test clock (TCK) is the test clock on the board.
The BSR is a series connection of boundary-scan cells
(BSCs) around the periphery of the IC. Each I/O pad on
the FPGA, except for CCLK, DONE, and the boundary-
scan pins (TCK, TDI, TMS, and TDO), is included in
the BSR. The first BSC in the BSR (connected to TDI)
is located in the first PIC I/O pad on the left of the top
side of the FPGA (PTA PIC). The BSR proceeds clock-
wise around the top, right, bottom, and left sides of the
array. The last BSC in the BSR (connected to TDO) is
located on the top of the left side of the array (PL1D).
The bypass instruction uses a single FF, which resyn-
chronizes test data that is not part of the current scan
operation. In a bypass instruction, test data received on
TDI is shifted out of the bypass register to TDO. Since
the BSR (which requires a two FF delay for each pad)
is bypassed, test throughput is increased when devices
that are not part of a test operation are bypassed.
The boundary-scan logic is enabled before and during
configuration. After configuration, a configuration
option determines whether or not boundary-scan logic
is used.
The 32-bit boundary-scan identification register con-
tains the manufacturer's ID number, unique part num-
ber, and version (as described earlier). The
identification register is the default source for data on
TDO after RESET if the TAP controller selects the shift-
data-register (SHIFT-DR) instruction. If boundary scan
is not used, TMS, TDI, and TCK become user I/Os,
and TDO is 3-stated or used in the readback operation.
An optional USERCODE is available if the boundary-
scan PSR1 instruction is not used. The selection
between PSR1 and USERCODE is a configuration
option and can be performed in
ORCA
Foundry. The
USERCODE is an 11-bit value that the user can set
during device configuration and can be written to and
read from the FPGA via the boundary-scan logic. The
USERCODE value replaces the manufacturer field of
the boundary-scan ID code when the USERCODE
instruction is issued, allowing users to have configured
devices identified in a user-defined manner. The manu-
facturer ID field remains available when the IDCODE
instruction is issued.
5-5768(F)
Figure 38.
ORCA
Series Boundary-Scan Circuitry Functional Diagram
TAP
CONTROLLER
TMS
TCK
BOUNDARY-SCAN REGISTER
PSR2 REGISTER (PLCs)
BYPASS REGISTER
DATA
MUX
INSTRUCTION DECODER
INSTRUCTION REGISTER
M
U
X
RESET
CLOCK IR
SHIFT-IR
UPDATE-IR
PUR
TDO
SELECT
ENABLE
RESET
CLOCK DR
SHIFT-DR
UPDATE-DR
TDI
DATA REGISTERS
PSR1 REGISTER (PLCs)
CONFIGURATION REGISTER
(RAM_R, RAM_W)
PRGM
I/O BUFFERS
V
DD
V
DD
V
DD
V
DD
IDCODE REGISTER
Lucent Technologies Inc.
61
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Special Function Blocks
(continued)
ORCA
Series TAP Controller (TAPC)
The
ORCA
Series TAP controller (TAPC) is a 1149.1/
D1 compatible test access port controller. The 16 JTAG
state assignments from the
IEEE
1149.1/D1 specifica-
tion are used. The TAPC is controlled by TCK and
TMS. The TAPC states are used for loading the IR to
allow three basic functions in testing: providing test
stimuli (Update-DR), test execution (Run-Test/Idle),
and obtaining test responses (Capture-DR). The TAPC
allows the test host to shift in and out both instructions
and test data/results. The inputs and outputs of the
TAPC are provided in the table below. The outputs are
primarily the control signals to the instruction register
and the data register.
Table 15. TAP Controller Input/Outputs
The TAPC generates control signals that allow capture,
shift, and update operations on the instruction and data
registers. In the capture operation, data is loaded into
the register. In the shift operation, the captured data is
shifted out while new data is shifted in. In the update
operation, either the instruction register is loaded for
instruction decode, or the boundary-scan register is
updated for control of outputs.
The test host generates a test by providing input into
the
ORCA
Series TMS input synchronous with TCK.
This sequences the TAPC through states in order to
perform the desired function on the instruction register
or a data register. Figure 39 provides a diagram of the
state transitions for the TAPC. The next state is deter-
mined by the TMS input value.
5-5370(F)
Figure 39. TAP Controller State Transition Diagram
Symbol
I/O
Function
TMS
I
Test Mode Select
TCK
I
Test Clock
PUR
I
Powerup Reset
PRGM
I
BSCAN Reset
TRESET
O
Test Logic Reset
Select
O
Select IR (High); Select-DR (Low)
Enable
O
Test Data Out Enable
Capture-DR
O
Capture/Parallel Load-DR
Capture-IR
O
Capture/Parallel Load-IR
Shift-DR
O
Shift Data Register
Shift-IR
O
Shift Instruction Register
Update-DR
O
Update/Parallel Load-DR
Update-IR
O
Update/Parallel Load-IR
SELECT-
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
1
1
0
0
1
0
RUN-TEST/
IDLE
1
TEST-LOGIC-
RESET
SELECT-
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
1
0
1
0
0
0
0
0
1
0
1
1
1
0
1
1
0
0
0
0
1
1
1
0
62
62
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Special Function Blocks
(continued)
Boundary-Scan Cells
Figure 40 is a diagram of the boundary-scan cell (BSC)
in the
ORCA
series PICs. There are four BSCs in each
PIC: one for each pad, except as noted above. The
BSCs are connected serially to form the BSR. The
BSC controls the functionality of the in, out, and 3-state
signals for each pad.
The BSC allows the I/O to function in either the normal
or test mode. Normal mode is defined as when an out-
put buffer receives input from the PLC array and pro-
vides output at the pad or when an input buffer
provides input from the pad to the PLC array. In the test
mode, the BSC executes a boundary-scan operation,
such as shifting in scan data from an upstream BSC in
the BSR, providing test stimuli to the pad, capturing
test data at the pad, etc.
The primary functions of the BSC are shifting scan data
serially in the BSR and observing input (p_in), output
(p_out), and 3-state (p_ts) signals at the pads. The
BSC consists of two circuits: the bidirectional data cell
is used to access the input and output data, and the
direction control cell is used to access the 3-state
value. Both cells consist of a flip-flop used to shift scan
data which feeds a flip-flop to control the I/O buffer. The
bidirectional data cell is connected serially to the direc-
tion control cell to form a boundary-scan shift register.
The TAPC signals (capture, update, shiftn, treset, and
TCK) and the MODE signal control the operation of the
BSC. The bidirectional data cell is also controlled by
the high out/low in (HOLI) signal generated by the
direction control cell. When HOLI is low, the bidirec-
tional data cell receives input buffer data into the BSC.
When HOLI is high, the BSC is loaded with functional
data from the PLC.
The MODE signal is generated from the decode of the
instruction register. When the MODE signal is high
(EXTEST), the scan data is propagated to the output
buffer. When the MODE signal is low (BYPASS or
SAMPLE), functional data from the FPGA's internal
logic is propagated to the output buffer.
The boundary-scan description language (BSDL) is
provided for each device in the
ORCA
Series of FPGAs
on the
ORCA
Foundry CD. The BSDL is generated
from a device profile, pinout, and other boundary-scan
information.
5-2844(F
Figure 40. Boundary-Scan Cell
D
Q
D
Q
D
Q
D
Q
SCAN IN
p_out
HOLI
BIDIRECTIONAL DATA CELL
I/O BUFFER
DIRECTION CONTROL CELL
MODE
UPDATE/TCK
SCAN OUT
TCK
SHIFTN/CAPTURE
p_ts
p_in
PAD_IN
PAD_TS
PAD_OUT
0
1
0
1
0
1
0
1
0
1
Lucent Technologies Inc.
63
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Special Function Blocks
(continued)
Boundary-Scan Timing
To ensure race-free operation, data changes on specific clock edges. The TMS and TDI inputs are clocked in on
the rising edge of TCK, while changes on TDO occur on the falling edge of TCK. In the execution of an EXTEST
instruction, parallel data is output from the BSR to the FPGA pads on the falling edge of TCK. The maximum fre-
quency allowed for TCK is 10 MHz.
Figure 41 shows timing waveforms for an instruction scan operation. The diagram shows the use of TMS to
sequence the TAPC through states. The test host (or BSM) changes data on the falling edge of TCK, and it is
clocked into the DUT on the rising edge.
5-5971(F)
Figure 41. Instruction Register Scan Timing Diagram
TCK
TMS
TDI
RUN-
T
E
ST/
I
DLE
RU
N-TEST/I
DLE
EX
IT
1-
I
R
EX
IT
2-
I
R
UP
DATE
-I
R
S
E
LE
CT-DR-S
C
AN
CA
PTURE
-I
R
S
E
LE
CT-I
R-
SCA
N
T
E
ST
-LO
G
I
C-R
ESE
T
SHI
FT-
I
R
P
A
US
E-I
R
SHI
FT-
I
R
EX
IT
1-
I
R
64
64
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Microprocessor Interface (MPI)
The Series 3 FPGAs have a dedicated synchronous
microprocessor interface function block (see
Figure 42). The MPI is programmable to operate with
PowerPC
MPC800 series microprocessors and
Intel
*
i960
* J core processors; see Table 16 and Table 17,
respectively, for compatible processors. The MPI imple-
ments an 8-bit interface to the host processor (
Pow-
erPC
or
i960
) that can be used for configuration and
readback of the FPGA as well as for user-defined data
processing and general monitoring of FPGA function.
In addition to dedicated-function registers, the micro-
processor interface allows for the control of up to 16
user registers (RAM or flip-flops) in the FPGA logic. A
synchronous/asynchronous handshake procedure is
used to control transactions with user logic in the FPGA
array. There is also capability for the FPGA logic to
interrupt the host processor either by a hard interrupt or
by having the host processor poll the microprocessor
interface.
The control portion of the microprocessor interface is
available following powerup of the FPGA if the mode
pins specify MPI mode, even if the FPGA is not yet con-
figured. The mode pin (M[2:0]) settings can be found in
the FPGA Configuration Modes section of this data
sheet, and the setup and use of the MPI for configura-
tion is discussed in the MPI Setup and Control subsec-
tion. For postconfiguration use, the MPI must be
included in the configuration bit stream by using an MPI
library element in your design from the
ORCA
macro
library, or by setting the MP_USER bit of the MPI con-
figuration control register prior to the start of configura-
tion (MPI registers are discussed later).
*
Intel
and
i960
are registered trademarks of Intel Corporation.
5-5806(F)
Figure 42. MPI Block Diagram
DONE
RD_DATA
INIT
D7
D7IN
D7OUT
D6
D6IN
D6OUT
D5
D5IN
D5OUT
D4
D4IN
D4OUT
D3
D3IN
D3OUT
D2
D2IN
D2OUT
D1
D1IN
D1OUT
D0
D0IN
D0OUT
ORCA 3C/Txxx MPI
STATUS
REGISTER
SCRATCHPAD
REGISTER
READBACK
DATA REGISTER
READBACK
ADDR REGISTER
CONTROL
REGISTERS
PART ID
REGISTERS
RESET
RD_CFG
PRGM
GSR
IRQ
TO GSR BLOCK
TO FPGA
ROUTING
USER_START
USER_END
WR_CTRL
A[3:0]
RDYRCV
CLK
ADS
ALE
W/R
i960 LOGIC
RD/WR
BT
TS
CLKOUT
TA
POWERPC LOGIC
DE
CODE
/
C
ONT
R
OL
PO
W
E
R
P
C
ONL
Y
A4
A3
A2
A1
A0
RD
CS0
CS1
CCLK
M3
M2
M1
M0
MPI_IRQ
MPI_ACK
MPI_CLK
MPI_STRB
MPI_ALE
MPI_RW
MPI_B1
TO FPGA
ROUTING
D[7:0]IN
D[7:0]OUT
DEVICE PAD
I/O BUFFER
Lucent Technologies Inc.
65
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Microprocessor Interface (MPI)
(continued)
PowerPC System
In Figure 43, the
ORCA
FPGA is a memory-mapped
peripheral to the
PowerPC
processor. The
PowerPC
interface uses separate address and data buses and
has several control lines. The
ORCA
chip select lines,
CS0
and CS1, are each connected to an address line
coming from the
PowerPC
. In this manner, the FPGA is
capable of a transaction with the
PowerPC
whenever
the address line connected to
CS0
is low, the address
line for CS1 is high, and there is a valid address on
PowerPC
address lines A[27:31]. Other forms of selec-
tion are possible by using the FPGA chip selects in a
different way. For example,
PowerPC
address bits
A[0:26] could be decoded to select
CS0
and CS1, or if
the FPGA is the only peripheral to the
PowerPC
, CS0
and CS1 could be tied low and high, respectively, to
cause them to always be selected. If the MPI is not
used for FPGA configuration, decoding logic can be
implemented internal or external to the FPGA. If logic
internal to the FPGA is used, the chip selects must be
routed out on an output pin and then connected exter-
nally to
CS0
and/or CS1. If the MPI is to be used for
configuration, any decode logic used must be imple-
mented external to the FPGA since the FPGA logic has
not been configured yet.
5-5761(F)
Note: FPGA shown as a memory-mapped peripheral using
CS0
and
CS1. Other decoding schemes are possible using
CS0
and/or
CS1.
Figure 43.
PowerPC
/MPI
The basic flow of a transaction on the
PowerPC
/MPI
interface is given below. Pin descriptions are shown in
Table 16 and timing is shown in the Timing Characteris-
tics section of this data sheet. For both read and write
transactions, the address, chip select, and read/write
(read high, write low) signals are set up at the FPGA
pins by the
PowerPC
. The
PowerPC
then asserts its
transfer start signal (
TS
) low. Data is available to the
MPI
during a write at the rising clock edge after the
clock cycle during which
TS
is low. The transfer is
acknowledged to the
PowerPC
by the low asser tion of
the
TA
signal. The MPI
PowerPC
interface does not
support burst transfers, so the burst inhibit signal,
BI
, is
also asserted low during the transfer acknowledge . The
same process applies to a read from the MPI except
that the read data is expected at the FPGA data pins by
the
PowerPC
at the rising edge of the clock when
TA
is
low. The MPI only drives
TA
low for one clock cycle.
Interrupt requests can be sent to the
PowerPC
asyn-
chronously to the read/write process. Interrupt requests
are sourced by the user-logic in the FPGA. The MPI will
assert the request to the
PowerPC
as a direct interrupt
signal and/or a pollable bit in the MPI status register
(discussed in the MPI Setup and Control section). The
MPI
will continue to assert the interrupt request until
the user-logic deasserts its interrupt request signal.
Table 16.
PowerPC
/MPI Configuration
DOUT
CCLK
D[7:0]
A[4:0]
MPI_CLK
MPI_RW
MPI_ACK
MPI_BI
MPI_IRQ
MPI_STRB
CS0
CS1
HDC
LDC
D[7:0]
A[27:31]
CLKOUT
RD/WR
TA
BI
IRQx
TS
A26
A25
TO DAISY-
CHAINED
DEVICES
POWERPC
ORCA
8
FPGA
SERIES 3
DONE
INIT
PowerPC
Signal
ORCA Pin
Name
MPI
I/O
Function
D[0:7]
D[7:0]
I/O
8-bit data bus
A[27:31]
A[4:0]
I
5-bit
MPI
address
bus
TS
RD/MPI_STRB
I
Transfer start signal
--
CS0
I
Active-low
MPI
select
--
CS1
I
Active-high
MPI
select
CLKOUT
A7/MPI_CLK
I
PowerPC interface
clock
RD/
WR
A8/MPI_RW
I
Read (high)/write
(low) signal
TA
A9/
MPI_ACK
O
Active-low transfer
acknowledge signal
BI
A10/
MPI_BI
O
Active-low burst
transfer inhibit
signal
Any of
IRQ
[7:0]
A11/
MPI_IRQ
O
Active-low interrupt
request signal
66
66
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Microprocessor Interface (MPI)
(continued)
i960 System
Figure 44 shows a schematic for connecting the
ORCA
MPI
to supported
i960
processors. In the figure, the
FPGA is shown as the only peripheral, with the FPGA
chip select lines,
CS0
and CS1, tied low and high,
respectively. The
i960
address and data are multi-
plexed onto the same bus. This precludes memory
mapping of the FPGA in the
i960
memory space of a
multiperipheral system without some form of address
latching to capture and hold the address signals to
drive the
CS0
and/or CS1 signals. Multiple address sig-
nals could also be decoded and latched to drive the
CS0
and/or CS1 signals. If the MPI is not used for
FPGA configuration, decoding/latching logic can be
implemented internal or external to the FPGA. If logic
internal to the FPGA is used, the chip selects must be
routed out an output pin and then connected externally
to
CS0
and/or CS1. If the MPI is to be used for configu-
ration, any decode/latch logic used must be imple-
mented external to the FPGA since the FPGA logic has
not been configured yet.
5-5762(F)
Note: FPGA shown as only system peripheral with fixed-chip select
signals. For multiperipheral systems, address decoding and/
or latching can be used to implement chip selects.
Figure 44.
i960
/MPI
The basic flow of a transaction on the
i960
/MPI inter-
face is given below. Pin descriptions are shown in
Table 17, and timing is shown in the
ORCA
Timing
Characteristics section of this data sheet. For both read
and write transactions, the address latch enable (ALE)
is set up by the
i960
at the FPGA to the falling edge of
the clock. The address, byte enables, chip selects, and
read/write (read low, write high) signals are normally
set up at the FPGA pins by the
i960
at the next rising
edge of the clock. At this same rising clock edge, the
i960
asserts its address/data strobe (
ADS
) low. Data is
available to the MPI during a write at the rising clock
edge of the following clock cycle. The transfer is
acknowledged to the
i960
by the low assertion of the
ready/recover (
RDYRCV
) signal. The same process
applies to a read from the MPI except that the read
data is expected at the FPGA data pins by the
i960
at
the rising edge of the clock when
RDYRCV
is low. The
MPI
only drives
RDYRCV
low for one clock cycle.
Interrupts can be sent to the
i960
asynchronously to
the read/write process. Interrupt requests are sourced
by the user-logic in the FPGA. The MPI will assert the
request to the
i960
as a direct interrupt signal and/or a
pollable bit in the MPI status register (discussed in the
MPI
Setup and Control section). The MPI will continue
to assert the interrupt request until the user-logic deas-
serts its interrupt request signal.
Table 17.
i960
/MPI Configuration
DOUT
CCLK
D[7:0]
MPI_CLK
MPI_RW
MPI_ACK
MPI_IRQ
MPI_ALE
MPI_BE1
HDC
LDC
TO DAISY-
CHAINED
DEVICES
ORCA
8
FPGA
SERIES 3
DONE
INIT
AD[7:0]
CLKIN
W/R
RDYRCV
XINTx
ALE
BE1
i960
CS1
CS0
i960 SYSTEM CLOCK
V
DD
MPI_BE0
BE0
MPI_STRB
ADS
i960
Signal
ORCA
Pin
Name
MPI
I/O
Function
AD[7:0]
D[7:0]
I/O
Multiplexed 5-bit address/
8-bit data bus. The
address appears on D[4:0].
ALE
RDY/RCLK/
MPI_ALE
I
Address latch enable used
to capture address from
AD[4:0] on falling edge of
clock.
ADS
RD
/
MPI_STRB
I
Address/data strobe to
indicate start of transac-
tion.
--
CS0
I
Active-low
MPI
select.
--
CS1
I
Active-high
MPI
select.
System
Clock
A7/
MPI_CLK
I
i960 system clock. This
clock is sourced by the
system and not the
i960.
W/
R
A8/MPI_RW
I
Write (high)/read (low)
signal.
RDYRCV
A9/
MPI_ACK
O
Active-low ready/recover
signal indicating acknowl-
edgment of the transac-
tion.
Any of
XINT
[7:0]
A11/
MPI_IRQ
O
Active-low interrupt
request signal.
BE0
A0/
MPI_BE0
I
Byte-enable 0 used as
address bit 0 in
i960 8-bit
mode.
BE1
A1/
MPI_BE1
I
Byte-enable 1 used as
address bit 1 in
i960 8-bit
mode.
Lucent Technologies Inc.
67
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Microprocessor Interface (MPI)
(continued)
MPI Interface to FPGA
The MPI interfaces to the user-programmable FPGA
logic using a 4-bit address, read/write control signal,
interrupt request signal, and user start and user end
handshake signals. Timing numbers are provided so
that the user-logic data transfers can be performed syn-
chronously with the host processor (
PowerPC
or
i960
)
interface clock or asynchronously. Table 18 shows the
internal interface signals between the MPI and the
FPGA user-programmable logic. All of the signals are
connected to the MPI in the upper-left corner of the
device except for the D[7:0] and CLK signals that come
directly from the I/O pin.
The 4-bit addressing from the MPI to the PLCs allows
for up to 16 locations to be addressed by the host pro-
cessor. The user address space of the MPI does not
address any hard register. Rather, the user is free to
construct registers from FFs, latches, or RAM that can
be selected by the addressing. Alternately, the decoded
address signals may be used as control signals for
other functions such as state machines or timers.
The transaction sequence between the MPI and the
user-logic is as follows. When the host processor ini-
tiates a transaction as discussed in the preceding sec-
tions, the MPI outputs the 4-bit user address (UA[3:0])
and the read/write control signal (
URDWR
, which is
read-high, write-low regardless of host processor), and
then asserts the user start signal, USTART. During a
write from the host processor, the user logic can accept
data written by the host processor from the D[7:0] pins
once the USTART signal is asserted. The user logic
ends a transaction by asserting an active-high user
end (UEND) signal to the MPI.
The MPI will insert wait-states in the host processor
bus cycles, holding the host processor until the user-
logic completes its task and returns a UEND signal,
upon which the MPI generates an acknowledge signal.
If the host processor is reading from the FPGA, the
user logic must have the read data available on the
D[7:0] pins of the FPGA when the UEND signal is
asserted. If the user logic is fast or if the MPI user
address is being decoded for use as a control signal,
the MPI transaction time can be minimized by routing
the USTART signal directly to the UEND input of the
MPI
. The timing section of this data sheet contains a
parameter table with delay, setup, and hold timing
requirements to operate the user-logic either synchro-
nously or asynchronously with the MPI host interface
clock.
The user-logic may also assert an active-low interrupt
request (
UIRQ
) to the MPI, which, in turn, asserts an
interrupt to the host processor. Assertion of an inter-
rupt request is asynchronous to the host processor
clock and any read or write transaction occurring in the
MPI
. The user-logic is responsible for providing any
required interrupt vectors for the host processor, and
the user-logic must deassert the interrupt request once
serviced. If the interrupt request is not deasserted in
the user logic, it will continue to be asserted to the host
processor via the MPI_IRQ pin.
Table 18. MPI Internal Interface Signals
Signal
MPI
I/O
Function
UA[3:0]
O
User Logic Address. Addresses up to 16 unique user registers or use as control
signals.
URDWRN
O
User Logic Read/Write Control Signal. High indicates a read from user logic by
the host processor, low indicates a write to user-logic by the host processor.
USTART
O
Active-High User Start Signal. Indicates the start of an MPI transaction between
the host processor and the user logic.
UEND
I
Active-High User End Signal. Indicates that the user-logic is finished with the
current MPI transaction.
UIRQ
I
Active-Low Interrupt. Sends request from the user-logic to the host processor.
D[7:0]
FPGA I/O
User Data. Eight data bits come directly from the FPGA pins--not through the
MPI
.
MPI_CLK
FPGA I
MPI
Clock. The MPI clock is sourced by the host processor and comes directly
from the FPGA pin--not through the MPI.
68
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Microprocessor Interface (MPI)
(continued)
MPI
Setup and Control
The MPI has a series of addressable registers that provide MPI control and status, configuration and readback data
transfer, FPGA device identification, and a dedicated user scratchpad register. All registers are 8 bits wide. The
address map for these registers and the user-logic address space are shown in Table 19, followed by descriptions
of the register and bit functions. Note that for all registers, the most significant bit is bit 7, and the least significant bit
is bit 0.
Table 19. MPI Setup and Control Registers
Control Register 1
The MPI control register 1 is a read/write register. The host processor writes a control byte to configure the MPI. It
is readable by the host processor to verify the status of control bits previously written.
Table 20. MPI Setup and Control Registers Descriptions
Address
(Hex)
Register
00
Control Register 1.
01
Control Register 2.
02
Scratchpad Register.
03
Status Register.
04
Configuration/Readback Data Register.
05
Readback Address Register 1 (bits [7:0]).
06
Readback Address Register 2 (bits [15:8]).
07
Device ID Register 1 (bits [7:0]).
08
Device ID Register 2 (bits [15:8]).
09
Device ID Register 3 (bits [23:16]).
0A
Device ID Register 4 (bits [31:24]).
0B--0F
Reserved.
10--1F
User-definable Address Space.
Bit #
Description
Bit 0
GSR Input. Setting this bit to a 1 invokes a global set/reset on the FPGA. The host processor must
return this bit to a 0 to remove the GSR signal. GSR does not affect the registers at MPI addresses 0
through F hexadecimal or any configuration registers. Default state = 0.
Bit 1
Reserved.
Bit 2
Reserved.
Bit 3
Reserved.
Bit 4
Reserved.
Bit 5
RD_CFG
Input. Changing this bit to a 0 after configuration will initiate readback. The host processor
must return this bit to a 1 to remove the
RD_CFG
signal. Since this bit works exactly like the
RD_CFG
input pin, please see the FPGA pin descriptions for more information on this signal. Default state = 1.
Bit 6
Reserved.
Bit 7
PRGM
Input. Setting this bit to a 0 causes the FPGA to begin configuration and resets the boundary-
scan circuitry. The host processor must return this bit to a 1 to remove the
PRGM
signal. Since this bit
works exactly like the
PRGM
input pin (except that it does not reset the MPI), please see the FPGA pin
descriptions for more information on this signal. Default state = 1.
Lucent Technologies Inc.
69
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Microprocessor Interface (MPI)
(continued)
Scratchpad Register
The MPI scratchpad register is an 8-bit read/write register with no defined operation. It may be used for any user-
defined function.
Control Register 2
The MPI control register 2 is a read/write register. The host processor writes a control byte to configure the MPI. It
is readable by the host processor to verify the status of control bits it had previously written.
Table 21. MPI Control Register 2
Bit #
Bit Name
Description
Bit 0
EN_IRQ_CFG
Enable
IRQ
for Configuration Data Request in Daisy-Chain Configuration
Mode. Setting this bit to a 1 prior to configuration enables the
IRQ
signal to go active
when new data is requested for configuration writes or is available for configuration
reads to/from the configuration data register. A 0 clears the
IRQ
enable. This bit is
only valid for daisy-chain configuration. Default = 0.
Bit 1
EN_IRQ_ERR
Enable
IRQ
for Bit Stream Error. Setting this bit to a 1 prior to configuration
enables the
IRQ
signal to go active on the occurrence of a bit stream error during
configuration. A 0 clears the
IRQ
enable. This bit only has effect while in configura-
tion mode. Default = 0.
Bit 2
EN_IRQ_USR
Enable
IRQ
from the User FPGA Space. Setting this bit to a 1 allows user-defined
circuitry in the FPGA to generate an interrupt to the host processor by sourcing a
logic low on the
UIRQ
signal in the user logic. Default = 0.
Bit 3
MP_DAISY
MPI
Daisy-Chain Output Enable. Setting this bit to a 1 enables daisy-chain output
of the configuration data. See the Configuration section of this data sheet for daisy-
chain configuration details. Default = 0.
Bit 4
MP_HOLD_BUS Enable Bus Holding During Daisy-Chain Configuration Mode. Setting this bit to
a 1 will cause the MPI to wait until the FPGA configuration logic has serialized a
byte of configuration data before acknowledging the transaction. The data is only
serialized if the MP_DAISY (bit 3 above) control bit is set to 1. If MP_HOLD_BUS is
set to 0, the MPI will immediately acknowledge a configuration data byte transfer.
Immediate acknowledgment allows the host processor to perform other tasks during
FPGA configuration by polling the MPI status register (or by interrupt) and only write
configuration data when the FPGA is ready. Default = 0.
Bit 5
MP_USER
MPI
User Mode Enable. Setting this bit to a 1 will enable the MPI for user mode
operation. MP_USER must be set prior to the FPGA DONE signal going high during
configuration. The MPI may also be enabled for user operation via the configuration
bit stream. Default = 0.
Bit 6
Reserved
--
Bit 7
Reserved
--
70
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Microprocessor Interface (MPI)
(continued)
Status Register
The microprocessor interface status register is a read-only register, providing information to the host processor.
Table 22. Status Register
Configuration Data Register
The MPI configuration data register is a writable register in configuration mode and a readable register in readback
mode. For FPGA configuration, this is where the configuration data bytes are sequentially written by the host pro-
cessor. Similarly, for readback mode, the MPI provides the readback data bytes in this register for the host proces-
sor.
Readback Address Register 1
The MPI readback address register 1 is a writable register used to accept the least significant address byte
(bits [7:0]) of the configuration data location to be read back.
Readback Address Register 2
The MPI readback address register 2 is a writable register used to accept the most significant address byte
(bits [15:8]) of the configuration data location to be read back.
Bit #
Description
Bit 0
Reserved.
Bit 1
Data Ready. Set by the MPI, a 1 on this bit during configuration alerts the host processor that the FPGA
is ready for another byte of configuration data. During byte-wide readback, the MPI sets this bit to a 1 to
tell the host processor that a byte of configuration data is available for reading. This bit is cleared by a
host processor access (read or write) to the configuration data register.
Bit 2
IRQ
Pending. The MPI sets this bit to 1 to indicate to the host processor that the FPGA has a pending
interrupt request. This bit may be used for the host processor to poll for interrupts if the
MPI_IRQ
pin out-
put of the FPGA has been masked at the host processor. This bit is set to 0 when the status register is
read. Interrupt requests from the FPGA user space must be cleared in FPGA user logic in addition to
reading this bit.
Bits
[4:3]
Bit Stream Error Flags. Bits 3 and 4 are set by the MPI to indicate any error during FPGA configura-
tion. See bit 2 of control register 2 for the capability to alert the host processor of an error via the
IRQ
signal during configuration. In the truth table below, bit 3 is the LSB (bit on right). These bits are cleared
to 0 when
PRGM
goes active:
00 = No error
01 = ID error
10 = Checksum error
11 = Stop-bit/alignment error
Bit 5
Reserved.
Bit 6
INIT.
This bit reflects the binary value of the FPGA
INIT
pin.
Bit 7
DONE. This bit reflects the binary value of the FPGA DONE pin.
Lucent Technologies Inc.
71
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Microprocessor Interface (MPI)
(continued)
Device ID Registers
The MPI device ID is broken into four registers holding 1 byte each. The device ID that is available through the MPI
is the same as the boundary-scan ID code, except that the device ID in the MPI has a reverse bit order. There is no
means to overwrite any of the device ID as can be done with the boundary-scan ID, but the MPI scratchpad register
can be used as a personalization register. The format for the entire device ID is shown below followed by family and
device values and the partitioning of the device ID into the four device ID registers.
Table 23. Device ID Code
* PLC array size of FPGA.
Table 24 shows the family and device values for all parts covered by this data sheet.
Table 24. Series 3 Family and Device ID Values
Table 25 describes the device IDs for all parts covered by this data sheet as they are partitioned into the four regis-
ters found in the MPI.
Table 25.
ORCA
Series 3 Device ID Descriptions
Version
Part*
Family
Manufacturer
MSB
4 bits
10 bits
6 bits
11 bits
1 bit
Example: (First version of Lucent's OR3C55)
0000 0100100000 110000 00000011101 1
Part Name
Family ID
(Hex)
Device ID
(Hex)
OR3T20
03
0C
OR3T30
03
0E
OR3C/T55
03
12
OR3C/T80
03
16
OR3T125
03
1C
Device ID Register 1
Bit 0
Logic 1. This bit is always a one.
Bits [7:1]
0011101, the 7 least significant bits of the Lucent Technologies manufacturer ID.
Device ID Register 2
Bits [3:0]
0000, the 4 most significant bits of the Lucent Technologies manufacturer ID.
Bits [7:4]
The 4 least significant bits of the 10-bit part number.
Device ID Register 3
Bits [5:0]
The 6 most significant bits of the 10-bit part number.
Bits [7:6]
The 2 least significant bits of the device family code.
Device ID Register 4
Bits [3:0]
The 4 most significant bits of the device family code.
Bits [7:4]
The 4-bit device version code.
72
72
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
The
ORCA
programmable clock manager (PCM) is a
special function block that is used to modify or condi-
tion clock signals for optimum system performance.
Some of the functions that can be performed with the
PCM
are clock skew reduction (both internal and board
level), duty-cycle adjustment, clock delay reduction,
clock phase adjustment, and clock frequency multipli-
cation/division. Due to the different capabilities required
by customer application, each PCM contains both a
PLL (phase-locked loop) and a DLL (delayed-locked
loop) mode. By using PLC logic resources in conjunc-
tion with the PCM, many other functions, such as fre-
quency synthesis, are possible.
There are two PCMs on each Series 3 device, one in
the lower left corner and one in the upper right corner.
Each can drive two different, but interrelated clock net-
works inside the FPGA. Each PCM can take a clock
input from the ExpressCLK pad in its corner or from
general routing resources. There are also two input
sources that provide feedback to the PCM from the
PLC array. One of these is a dedicated corner Express-
CLK
feedback, and the other is from general routing.
Each PCM sources two clock outputs, one to the corner
ExpressCLK
that feeds the CLKCNTRL blocks on the
two sides adjacent to the PCM, and one to the system
clock spine network through general routing. Figure 45
shows a high-level block diagram of the PCM.
Functionality of the PCM is programmed during opera-
tion through a read/write interface internal to the FPGA
array or via the configuration bit stream. The internal
FPGA interface comprises write enable and read
enable signals, a 3-bit address bus, an 8-bit input (to
the PCM) data bus, and an 8-bit output data bus. There
is also a PCM output signal, LOCK, that indicates a sta-
ble output clock state. These signals are used to pro-
gram a series of registers to configure the PCM
functional core for the desired functionality.
Operation of the PCM is divided into two modes, delay-
locked loop (DLL) and phase-locked loop (PLL). Some
operations can be performed by either mode and some
are specific to a particular mode. These will be
described in each individual mode section. In general,
DLL mode is preferable to PLL mode for the same func-
tion because it is less sensitive to input clock noise.
In the discussions that follow, the duty cycle is the per-
cent of the clock period during which the output clock is
high.
5-5828(F)
Figure 45. PCM Block Diagram
USER CONTROL SIGNALS
PCM-FPGA
INTERFACE
PCM CORE
FUNCTIONS
CORNER EXPRESSCLK IN
GENERAL CLOCKIN
FEEDBACK
ExpressCLK
FEEDBACK CLOCK
FROM ROUTING
EXPRESSCLK OUT
SYSTEM CLOCK OUT
(FROM GENERAL ROUTING)
(TO GENERAL ROUTING)
Lucent Technologies Inc.
73
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
PCM Registers
The PCM contains eight user-programmable registers used for configuring the PCM's functionality. Table 26 shows
the mapping of the registers and their functions. See Figure 46 for more information on the location of PCM ele-
ments that are discussed in the table. The PCM registers are referenced in the discussions that follow. Detailed
explanations of all register bits are supplied following the functional description of the PCM.
Table 26. PCM Registers
Address
Function
0
Divider 0 Programming. Programmable divider, DIV0, value and DIV0 reset bit. DIV0 can
divide the input clock to the PCM or can be bypassed.
1
Divider 1 Programming. Programmable divider, DIV1, value and DIV1 reset bit. DIV1 can
divide the feedback clock input to the PCM or can be bypassed. Valid only in PLL mode.
2
Divider 2 Programming. Programmable divider, DIV2, value and DIV2 reset bit. DIV2 can
divide the output of the tapped delay line or can be bypassed and is only valid for the
ExpressCLK
output.
3
DLL 2x Duty-Cycle Programming. DLL mode clock doubler (2x) duty-cycle selection.
4
DLL 1x Duty-Cycle Programming. Depending on the settings in other registers, this regis-
ter is for:
a. PLL mode phase/delay selection;
b. DLL mode 1x duty cycle selection; and
c. DLL mode programmable delay.
5
Mode Programming. DLL/PLL mode selection, DLL 1x/2x clock selection, phase detector
feedback selection.
6
Clock Source Status/Output Clock Selection Programming. Input clock selection, feed-
back clock selection, ExpressCLK output source selection, system clock output source selec-
tion.
7
PCM Control Programming. PCM power, reset, and configuration control.
74
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
5-5829(F)
Figure 46. PCM Functional Block Diagram
EXPRESSCLK
FROM
PROGRAMMABLE
DIVIDER
DIV0
REGISTER 7
REGISTER 6
REGISTER 5
REGISTER 4
REGISTER 3
REGISTER 2
REGISTER 1
REGISTER 0
FPGA-PCM INTERFACE
COMBINATORIAL
LOGIC
PROGRAMMABLE
DIVIDER
DIV2
0
1
2
3
S4
0
1
2
3
S10
0
SYSTEM CLOCK
OUTPUT
EXPRESSCLK
OUTPUT
FROM
EXPRESSCLK
FEEDBACK
FEEDBACK
CLOCK
PROGRAMMABLE
DIVIDER
DIV1
0
1
S2
PHASE
DETECTOR
PROGRAMMABLE DELAY
LINES (32 TAPS)
CHARGE PUMP
AND
LOW-PASS FILTER
1
0
S4
1...7
S5
1...7
1...7
1...7
S6
S7
S8
0
1
2
3
S4
0
1
2
3
S3
PCM
INPUT
CLOCK
DAT
A
_
I
N[7
:
0
]
A
D
DR_IN[2
:0]
DA
T
A
_
O
UT
[7
:0
]
WE
RE
LO
C
K
PAD
ROUTING
0
1
2
3
S0
ROUTING
Lucent Technologies Inc.
75
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
Delay-Locked Loop (DLL) Mode
DLL mode is used for implementing a delayed clock
(phase adjustment), clock doubling, and duty cycle
adjustment. All DLL functions stem from a delay line
with 32 taps. The delayed input clock is pulled from var-
ious taps and processed to implement the desired
result. There is no feedback clock in DLL mode, provid-
ing a very stable output and a fast lock time for the out-
put clock.
DLL mode is selected by setting bit 0 in PCM register
five to a 0. The settings for the various submodes of
DLL mode are described in the following paragraphs.
Divider DIV0 may be used with any of the DLL modes
to divide the input clock by an integer factor of 1 to 8
prior to implementation of the DLL process.
Delayed Clock
A delayed version of the input clock can be constructed
in DLL mode. The output clock can be delayed by
increments of 1/32 of the input clock period. Express
CLK and system CLK outputs in delay modes are
selected by setting register six, bits [5:4] to 10 or 11 for
ExpressCLK
output, and/or bits [7:6] to 10 for system
clock output. The delay value is entered in register four.
See register four programming details for more infor-
mation. Delay values are also shown in the second col-
umn of Table 27.
Note that when register six, bits [5:4] are set to 11, the
ExpressCLK
output is divided by an integer factor from
1 to 8 while the system clock cannot be divided. The
ExpressCLK
divider is provided so that the I/O clocking
provided by the ExpressCLK can operate slower than
the internal system clock. This allows for very fast inter-
nal processing while maintaining slower interface
speeds off-chip for improved noise and power perfor-
mance or to interoperate with slower devices in the sys-
tem. The divisor of the ExpressCLK frequency is
selected in register two. See the register two program-
ming details for more information.
1x Clock Duty-Cycle Adjustment
A duty-cycle adjusted replica of the input clock can be
constructed in DLL mode. The duty cycle can be
adjusted in 1/32 (3.125%) increments of the input clock
period. DLL 1x clock mode is selected by setting bit 4
of register five to a 1, and output clock source selection
is selected by setting register six, bits [5:4] to 01 for
ExpressCLK
output, and/or bits [7:6] to 01 for system
clock output. The duty-cycle percentage value is
entered in register four. See register four programming
details for more information. Duty cycle values are also
shown in the third column of Table 27.
Table 27. DLL Mode Delay/1x Duty Cycle
Programming Values
Register 4 [7:0]
7 6 5 4 3 2 1 0
Delay
(CLK_IN/32)
Duty Cycle
(% of CLK_IN)
0 0 X X X 0 0 0
1
3.125
0 0 X X X 0 0 1
2
6.250
0 0 X X X 0 1 0
3
9.375
0 0 X X X 0 1 1
4
12.500
0 0 X X X 1 0 0
5
15.625
0 0 X X X 1 0 1
6
18.750
0 0 X X X 1 1 0
7
21.875
0 0 X X X 1 1 1
8
25.000
0 1 X X X 0 0 0
9
28.125
0 1 X X X 0 0 1
10
31.250
0 1 X X X 0 1 0
11
34.375
0 1 X X X 0 1 1
12
37.500
0 1 X X X 1 0 0
13
40.625
0 1 X X X 1 0 1
14
43.750
0 1 X X X 1 1 0
15
46.875
0 1 1 1 1 X X X
16
50.000
1 0 0 0 0 X X X
17
53.125
1 0 0 0 1 X X X
18
56.250
1 0 0 1 0 X X X
19
59.375
1 0 0 1 1 X X X
20
62.500
1 0 1 0 0 X X X
21
65.625
1 0 1 0 1 X X X
22
68.750
1 0 1 1 0 X X X
23
71.875
1 0 1 1 1 X X X
24
75.000
1 1 0 0 0 X X X
25
78.125
1 1 0 0 1 X X X
26
81.250
1 1 0 1 0 X X X
27
84.375
1 1 0 1 1 X X X
28
87.500
1 1 1 0 0 X X X
29
90.625
1 1 1 0 1 X X X
30
93.750
1 1 1 1 0 X X X
31
96.875
76
76
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
2x Clock Duty-Cycle Adjustment
A doubled-frequency, duty-cycle adjusted version of the
input clock can be constructed in DLL mode. The first
clock cycle of the 2x clock output occurs when the input
clock is high, and the second cycle occurs when the
input clock is low. The duty cycle can be adjusted in
1/32 (6.25%) increments of the input clock period.
Additionally, each of the two doubled-clock cycles that
occurs in a single input clock cycle may be adjusted to
have different duty cycles. DLL 2x clock mode is
selected by setting bit 4 of register five to a 1, and by
setting register six, bits [5:4] to 01 for ExpressCLK out-
put, and/or bits [7:6] to 01 for system clock output. The
duty-cycle percentage value is entered in register
three. See register three programming details for more
information. Duty-cycle values where both cycles of the
doubled clock have the same duty cycle are also shown
in Table 28.
Table 28. DLL Mode Delay/2x Duty Cycle
Programming Values
Phase-Locked Loop (PLL) Mode
The PLL mode of the PCM is used for clock multiplica-
tion (1/8x to 64x) and clock delay minimization func-
tions. PLL functions make use of the PCM dividers and
use feedback signals, often from the FPGA array. The
use of feedback is discussed with each PLL submode.
PLL mode is selected by setting bit 0 of register five to
1.
Clock Delay Minimization
PLL mode can be used to minimize the effects of the
input buffer and input routing delay on the clock signal.
PLL mode causes a feedback clock signal to align in
phase with the input clock (refer back to the block dia-
gram in Figure 45) so that the delay between them is
effectively eliminated.
There is a dedicated feedback path from an adjacent
middle CLKCNTRL block to the PCM. Using the corner
ExpressCLK
pad as the input to the PCM and using this
dedicated feedback path, the clock from the Express-
CLK
output of the PCM, as viewed at the CLKCNTRL
block, will be phase-aligned with the ExpressCLK input
to the PCM. These relationships are diagrammed in
Figure 47.
A feedback clock can also be input to the PCM from
general routing. This allows for compensating for delay
between the PCM input and a point in the general rout-
ing. The use of this routed-feedback path is not gener-
ally recommended. Because compensation is based
on the programmable routing, the amount of clock
delay compensation can vary between FPGA lots and
fabrication processes, and will vary each time that the
feedback line is routed using different resources. Con-
tact Lucent Technologies for application notes regard-
ing the use of routed-feedback delay compensation.
5-5980(F)
Figure 47. ExpressCLK Delay Minimization
Using the PCM
Register 3 [7:0]
7 6 5 4 3 2 1 0
Duty Cycle
(%)
0 0 0 0 0 0 0 0
6.25
0 0 0 0 1 0 0 1
12.50
0 0 0 1 0 0 1 0
18.75
0 0 0 1 1 0 1 1
25.00
0 0 1 0 0 1 0 0
31.25
0 0 1 0 1 1 0 1
37.50
0 0 1 1 0 1 1 0
43.75
0 0 1 1 1 1 1 1
50.00
1 1 0 0 0 0 0 0
56.25
1 1 0 0 1 0 0 1
62.50
1 1 0 1 0 0 1 0
68.75
1 1 0 1 1 0 1 1
75.00
1 1 1 0 0 1 0 0
81.25
1 1 1 0 1 1 0 1
87.50
1 1 1 1 0 1 1 0
93.75
CORNER
CLKCNTRL
CLKCNTRL
DELAY
DELAY IS COMPENSATED
INPUT
OUTPUT WITHOUT
USING PCM
OUTPUT
EXPRESSCLK
EXPRESSCLK
USING PCM
EXPRESSCLK
COMPENSATION EQUALS DELAY
Lucent Technologies Inc.
77
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
Clock Multiplication
An output clock that is a multiple (not necessarily an
integer multiple) of the input clock can be generated in
PLL mode. The multiplication ratio is programmed in
the division registers DIV0, DIV1, and DIV2. Note that
DIV2 applies only to the ExpressCLK output of the
PCM
and any reference to DIV2 is implicitly 1 for the
system clock output of the PCM. The clock multiplica-
tion formulas when using ExpressCLK feedback are:
Where the values of DIV0, DIV1, and DIV2 range from
1 to 8.
The ExpressCLK multiplication range of output clock
frequencies is, therefore, from 1/8x up to 8x, with the
system clock range up to 8x the ExpressCLK frequency
or 64x the input clock frequency. If system clock feed-
back is used, the formulas are:
The divider values, DIV0, DIV1, and DIV2 are pro-
grammed in registers zero, one, and two, respectively.
The multiplied output is selected by setting register six,
bits [5:4] to 10 or 11 for ExpressCLK output and/or bits
[7:6] to 10 for system clock output. Note that when reg-
ister six, bits [5:4] are set to 11, the ExpressCLK output
is divided by DIV2, while the system clock cannot be
divided. The ExpressCLK divider is provided so that the
I/O clocking provided by the ExpressCLK can operate
slower than the internal system clock. This allows for
very fast internal processing while maintaining slower
interface speeds off-chip for improved noise and power
performance or to interoperate with slower devices in
the system.
It is also necessary to configure the internal PCM oscil-
lator for operation in the proper frequency range.
Table 29 and Table 30 show the settings required for
register four for a given frequency range for Series 3C
and 3T devices. In addition, the acquisition time is
shown for each frequency range. This is the time that is
required for the PCM to acquire LOCK. The PCM oscil-
lator frequency range is chosen based on the desired
output frequency at the system clock output. If using
the ExpressCLK output, the equivalent system clock
frequency can be selected by multiplying the expected
ExpressCLK
output frequency by the value for DIV2.
Choose the nominal frequency from the table that is
closest to the desired frequency, and use that value to
program register four. Minor adjustments to match the
exact input frequency are then performed automatically
by the PCM.
F
ExpressCLK_OUT
= F
INPUT_CLOCK
DIV1
DIV0
F
SYSTEM_CLOCK_OUT
= F
ExpressCLK_OUT
DIV2
F
SYSTEM_CLOCK_OUT
= F
INPUT_CLOCK
DIV1
DIV0
F
ExpressCLK_OUT
= F
SYSTEM_CLOCK
/
DIV2
78
78
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
Table 29. PCM Oscillator Frequency Range 3Txxx
Note: Use of settings in the first three rows is not recommended.
X means don't care.
Table 30. PCM Oscillator Frequency Range 3Cxx
Note: Use of settings in the first three rows is not recommended.
X means don't care.
Register 4
76543210
Min
(MHz)
System
Clock
Output
Frequency
(MHz)
NOM
Max
(MHz)
T
Acquisition
(s)
00XXX010
17.00
58.50
100.00
36.00
00XXX011
16.10
52.50
89.00
37.00
00XXX100
15.17
49.00
82.80
38.00
00XXX101
14.25
45.00
76.50
39.00
00XXX110
13.33
41.50
70.30
40.00
00XXX111
12.40
38.00
64.00
41.00
01XXX000
12.20
36.75
61.30
43.75
01XXX001
12.10
35.00
58.00
46.50
01XXX010
11.90
33.00
54.30
49.25
01XXX011
11.70
31.30
51.00
52.00
01XXX100
11.10
30.00
49.40
54.75
01XXX101
10.50
29.15
47.80
57.50
01XXX110
10.00
28.10
46.20
60.25
01XXX111
9.40
27.00
44.60
63.00
10000XXX
9.20
26.25
43.30
65.40
10001XXX
9.00
25.65
42.30
67.80
10010XXX
8.80
25.00
41.30
70.10
10011XXX
8.60
24.45
40.30
72.50
10100XXX
8.40
23.70
39.00
74.90
10101XXX
8.10
22.90
37.70
77.30
10110XXX
7.90
22.20
36.50
79.60
10111XXX
7.70
21.50
35.20
82.00
11000XXX
7.60
20.80
34.00
84.30
11001XXX
7.45
20.10
32.80
86.50
11010XXX
7.30
19.45
31.60
88.80
11011XXX
7.20
18.85
30.50
91.00
11100XXX
6.60
18.30
30.00
93.30
11101XXX
6.00
17.70
29.40
95.50
11110XXX
5.50
17.10
28.60
97.80
11111XXX
5.00
16.50
28.00
100.00
Register 4
76543210
Min
(MHz)
System
Clock
Output
Frequency
(MHz)
NOM
Max
(MHz)
T
Acquisition
(s)
00XXX010 10.50
73.00
135.00
36.00
00XXX011 10.00
68.00
126.00
37.00
00XXX100
9.50
63.00
117.00
38.00
00XXX101
9.10
58.50
108.00
39.00
00XXX110
8.60
53.80
99.00
40.00
00XXX111
8.10
49.00
90.00
41.00
01XXX000
7.80
47.70
87.50
43.80
01XXX001
7.60
46.30
85.00
46.50
01XXX010
7.30
45.00
82.50
49.30
01XXX011
7.10
43.60
80.00
52.00
01XXX100
6.80
42.10
77.50
55.00
01XXX101
6.50
40.75
75.00
57.50
01XXX110
6.30
39.40
72.50
60.30
01XXX111
6.00
38.00
70.00
63.00
10000XXX
5.90
37.40
68.80
65.40
10001XXX
5.90
36.70
67.50
67.80
10010XXX
5.80
36.00
66.30
70.10
10011XXX
5.80
35.40
65.00
72.50
10100XXX
5.70
35.00
63.80
74.90
10101XXX
5.60
34.10
62.50
77.30
10110XXX
5.60
33.50
61.30
79.60
10111XXX
5.50
32.80
60.00
82.00
11000XXX
5.40
32.10
58.80
84.30
11001XXX
5.40
31.50
57.50
86.50
11010XXX
5.30
30.70
56.30
88.80
11011XXX
5.30
30.10
55.00
91.00
11100XXX
5.20
29.50
53.80
93.30
11101XXX
5.10
28.80
52.50
95.50
11110XXX
5.10
28.20
51.30
97.80
11111XXX
5.00
27.50
50.00
100.00
Lucent Technologies Inc.
79
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
PCM/FPGA Internal Interface
Writing and reading the PCM registers is done through
a simple asynchronous interface that connects with the
FPGA routing resources. Reads from the PCM by the
FPGA logic are accomplished by setting up the 3-bit
address, A[2:0], and then applying an active-high read
enable (RE) pulse. The read data will be available as
long as RE is held high. The address may be changed
while RE is high, to read other addresses. When RE
goes low, the data output bus is 3-stated.
Writes to the PCM by the FPGA logic are performed by
applying the write data to the data input bus of the
PCM
, applying the 3-bit address to write to, and assert-
ing the write enable (WE) signal high. Data will be writ-
ten by the high-going transition of the WE pulse.
The read enable (RE) and write enable (WE) signals
may not be active at the same time. For detailed timing
information and specifications, see the Timing Charac-
teristics section of this data sheet.
The LOCK signal output from the PCM to the FPGA
routing indicates a stable output clock signal from the
PCM
. The LOCK signal is high when the PCM output
clock parameters fall within the programmed values
and the PCM specifications for jitter. Due to phase cor-
rections that occur internal to the PCM, the LOCK sig-
nal might occasionally pulse low when the output clock
is out of specification for only one or two clock cycles
(high jitter due to temperature, voltage fluctuation, etc.)
To accommodate these pulses, it is suggested that the
user integrate the LOCK signal over a period suitable to
their application to achieve the desired usage of the
LOCK signal.
The LOCK signal will also pulse high and low during
the acquisition time as the output clock stabilizes. True
LOCK is only achieved when the LOCK signal is a solid
high. Again, it is suggested that the user integrate the
LOCK signal over a time period suitable to the subject
application.
PCM Operation
Several features are available for the control of the
PCM
's overall operation. The PCM may be programma-
bly enabled/disabled via bit 0 of register 7. When dis-
abled, the analog power supply of the PCM is turned
off, conserving power and eliminating the possibility of
inducing noise into the system power buses. Individual
bits (register 7, bits [2:1]) are provided to reset the DLL
and PLL functions of the PCM. These resets affect only
the logic generating the DLL or PLL function; they do
not reset the divider values (DIV0, DIV1, DIV2) or reg-
isters [7:0]. The global set/reset (GSRN) is also pro-
grammably controlled via register 7, bit 7. If register 7,
bit 7 is set to 1, GSRN will have no effect on the PCM
logic, allowing the clock to operate during a global
set/reset. This function allows the FPGA to be reset
without affecting a clock that is sent off-chip and used
elsewhere in the system. Bit 6 of register 7 affects the
functionality of the PCM during configuration. If set to 1,
this bit enables the PCM to operate during configura-
tion, after the PCM has been configured. The PCM
functionality is programmed via the bit stream. If regis-
ter 7, bit 6 is 0, the PCM cannot function and its power
supply is disabled until after the configuration DONE
signal goes high.
When the PCM is powered up via register 7, bit 0, there
is a wake-up time associated with its operation. Follow-
ing the wake-up time, the PCM will begin to fully func-
tion, and, following an acquisition time during which the
output clock may be unstable, the PCM will be in
steady-state operation. There is also a shutdown time
associated with powering off the PCM. The output
clock will be unstable during this period. Waveforms
and timing parameters can be found in the Timing
Characteristics section of this data sheet.
80
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
PCM Detailed Programming
Descriptions of bit fields and individual control bits in the PCM control registers are provided in Table 31. Refer to
Figure 46 for more information on the location of the PCM elements that are discussed. In the following discussion,
the duty cycle is in the percentage of the clock period where the clock is high.
Table 31
.
PCM Control Registers
Bit #
Function
Register 0--Divider 0 Programming
Bits [3:0]
4-Bit Divider, DIV0, Value. This value enables the input clock to immediately be divided by a
value from 1 to 8. A 0 value (the default) indicates that DIV0 is bypassed (no division). Bypass
incurs less delay than dividing by 1. Hexadecimal values greater than 8 for bits [3:0] yield their
modulo 8 value. For example, if bits [3:0] are 1001 (9 hex), the result is divide by 1 (remainder
9/8 = 1).
Bits [6:4]
Reserved.
Bit 7
DIV 0 Reset Bit. DIV0 may not be reset by GSRN depending on the value of register 7, bit 7.
This bit may be set to 1 to reset DIV0 to its default value. Bit 0 must be set to 0 (the default) to
remove the reset.
Register 1--Divider 1 Programming
Bits [3:0]
4-Bit Divider, DIV1, Value. This value enables the feedback clock to be divided by a value from
1 to 8. A 0 value (the default) indicates that DIV1 is bypassed (no division). Bypass incurs less
delay than dividing by 1. Hexadecimal values greater than 8 for bits [3:0] yield their modulo 8
value. For example, if bits [3:0] are 1001 (9 hex), the result is divide by 1 (remainder 9/8 = 1).
Bits [6:4]
Reserved.
Bit 7
DIV1 Reset Bit. DIV1 may not be reset by GSRN, depending on the value of register 7, bit 7.
This bit may be set to 1 to reset DIV1 to its default value. Bit 0 must be set to 0 (the default) to
remove the reset.
Register 2--Divider 2 Programming
Bits [3:0]
4-Bit Divider, DIV2, Value. This value enables the tapped delay line output clock driven onto
ExpressCLK
to be divided by a value from 1 to 8. A 0 value (the default) indicates that DIV2 is
bypassed (no division). Bypass incurs less delay than dividing by 1. Hexadecimal values greater
than 8 for bits [3:0] yield their modulo 8 value. For example, if bits [3:0] are 1001 (9 hex), the
result is divide by 1 (remainder 9/8 = 1).
Bits [6:4]
Reserved.
Bit 7
DIV2 Reset Bit. DIV2 may not be reset by GSRN, depending on the value of register 7, bit 7.
This bit may be set to 1 to reset DIV2 to its default value. Bit 7 must be set to 0 (the default) to
remove the reset.
Register 3--DLL 2x Duty-Cycle Programming
Bits [2:0]
Duty-cycle selection for the doubled clock period associated with the input clock high. The duty
cycle is (value of bit 6) * 50% + ((value of bits [2:0]) + 1) * 6.25%. See the description for bit 6.
Bits [5:3]
Duty-cycle selection for the doubled clock period associated with the input clock low. The duty
cycle is (value of bit 7) * 50% + ((value of bits [2:0]) + 1) * 6.25%. See the description for bit 7.
Bit 6
Master duty-cycle control for the first clock period of the doubled clock: 0 = less than or equal to
50%, 1 = greater than 50%.
Bit 7
Master duty-cycle control for the second clock period of the doubled clock: 0 = less than or equal
to 50%, 1 = greater than 50%. Example: Both clock periods having a 62.5% duty cycle, bits [7:0]
are 11 001 001.
Lucent Technologies Inc.
81
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
Table 31. PCM Control Registers (continued)
Bit #
Function
Register 4--DLL 1x Duty-Cycle Programming
Bits [2:0]
Duty-Cycle/Delay Selection for Duty Cycle/Delays Less Than or Equal to 50%. The duty-
cycle/delay is (value of bits [7:6]) * 25% + ((value of bits [2:0]) + 1) * 3.125%. See the description
for bits [7:6].
Bits [5:3]
Duty-Cycle/Delay Selection for Duty Cycle/Delays Greater Than 50%. The duty-cycle/delay
is (value of bits [7:6]) * 25% + ((value of bits [5:3]) + 1) * 3.125%. See the description for bits [7:6].
Bits [7:6]
Master Duty Cycle Control:
00: duty cycle 3.125% to 25%
01: duty cycle 28.125% to 50%
10: duty cycle 53.125% to 75%
11: duty cycle 78.125% to 96.875%
Example: A 40.625% duty cycle, bits [7:0] are 01 XXX 100, where X is a don't care because the
duty cycle is not greater than 50%.
Example: The PCM output clock should be delayed 96.875% (31/32) of the input clock period.
Bits [7:0] are 11110XXX, which is 78.125% from bits [7:6] and 18.75% from bits [5:3]. Bits [2:0]
are don't care (X) because the delay is greater than 50%.
Register 5--Mode Programming
Bit 0
DLL/PLL Mode Selection Bit. 0 = DLL, 1 = PLL. Default is DLL mode.
Bit 1
Reserved.
Bit 2
PLL Phase Detector Feedback Input Selection Bit. 0 = feedback signal from routing/
ExpressCLK
, 1 = feedback from programmable delay line output. Default is 0. Has no effect in
DLL mode.
Bit 3
Reserved.
Bit 4
1x/2x Clock Selection Bit for DLL Mode. 0 = 1x clock output, 1 = 2x clock output. Default is 1x
clock output. Has no effect in PLL mode.
Bits [7:5]
Reserved.
82
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
Table 31. PCM Control Registers (continued)
Bit #
Function
Bits [5:4]


ExpressCLK
Output Source Selector. Default is 00.
00: PCM input clock, bypass path through PCM
01: DLL output
10: tapped delay line output
11: divided (DIV2) delay line output
Bits [7:6]


System Clock Output Source Selector. Default is 00.
00: PCM input clock, bypass path through PCM
01: DLL output
10: tapped delay line output
11: reserved
Register 7--PCM Control Programming
Bit 0
PCM Analog Power Supply Switch. 1 = power supply on, 0 = power supply off.
Bit 1
PCM Reset. A value of 1 resets all PCM logic for PLL and DLL modes.
Bit 2
DLL Reset. A value of 1 resets the clock generation logic for DLL mode. No dividers or user reg-
isters are affected.
Bits [5:3]
Reserved.
Bit 6
PCM Configuration Operation Enable Bit. 0 = normal configuration operation. During configu-
ration (DONE = 0), the PCM analog power supply will be off, the PCM output data bus is 3-stated,
and the LOCK signal is asserted to logic 0. The PCM will power up when DONE = 1.
1 = PCM operation during configuration. The PCM may be powered up (see bit 0) and begin
operation, or continue operation. The setup of the PCM can be performed via the configuration
bit stream.
Bit 7
PCM GSRN Enable Bit. 0 = normal GSRN operation. 1 = GSRN has no effect on PCM logic, so
clock processing will not be interrupted by a chip reset. Default is 0.
Lucent Technologies Inc.
83
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
PCM Applications
The applications discussed below are only a small
sampling of the possible uses for the PCM. Check the
Lucent Technologies
ORCA
FPGA Internet website
(listed at the end of this data sheet) for additional appli-
cation notes.
Clock Phase Adjustment
The PCM may be used to adjust the phase of the input
clock. The result is an output clock which has its active
edge either preceding or following the active edge of
the input clock. Clock phase adjustment is accom-
plished in DLL mode by delaying the clock. This is dis-
cussed in the Delay-Locked Loop (DLL) Mode section.
Examples of using the delayed clock as an early or late
phase-adjusted clock are outlined in the following para-
graphs.
An output clock that precedes the input clock can be
used to compensate for clock delay that is largely due
to excessive loading. The preceding output clock is
really not early relative to the input clock, but is delayed
almost a full cycle. This is shown in Figure 48A. The
amount of delay that is being compensated for, plus
clock setup time and some margin, is the amount less
than one full clock cycle that the output clock is delayed
from the input clock.
In some systems, it is desirable to operate logic from
several clocks that operate at different phases. This
technique is often used in microprocessor-based sys-
tems to transfer and process data synchronously
between functional areas, but without incurring exces-
sive delays. Figure 48B shows an input clock and an
output clock operating 180 out of phase. It also shows
a version of the input clock that was shifted approxi-
mately 180 using logic gates to create an inverter.
Note that the inverted clock is really shifted more than
180 due to the propagation delay of the inverter. The
PCM
output clock does not suffer from this delay. Addi-
tionally, the 180 shifted PCM output could be shifted
by some smaller amount to effect an early 180 shifted
clock that also accounts for loading effects.
In terms of degrees of phase shift, the phase of a clock
is adjustable in DLL mode with resolution relative to the
delay increment (see Table 27):
Phase Adjustment = (Delay)* 11.25,
Delay
<
16
Phase Adjustment = ((Delay)* 11.25) 360,
Delay > 16
5-5979(F)
Figure 48. Clock Phase Adjustment Using the PCM
INPUT CLOCK
OUTPUT CLOCK
INPUT CLOCK
PCM OUTPUT CLOCK
INVERTED INPUT CLOCK
A. Generating an Early Clock
B. Multiphase Clock Generation Using the DLL
UNINTENDED PHASE
SHIFT DUE TO
INVERTER DELAY
DLL DELAY
DLL DELAY
CLOCK DELAY AND SETUP
BEING COMPENSATED
84
84
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
High-Speed Internal Processing with Slow I/Os
The PCM PLL mode provides two outputs, one sent to
the global system clock routing of the FPGA and the
other to the ExpressCLK(s) that serve the FPGA I/Os.
The ExpressCLK output of the PCM has a divide capa-
bility (DIV2) that the system clock output does not. This
feature allows an input clock to be multiplied up to a
higher frequency for high-speed internal processing,
and also allows the ExpressCLK output to be divided
down to a lower frequency to accommodate off-FPGA
data transfers. For example, a 10 MHz input clock may
be multiplied (see Clock Multiplication in the Phase-
Locked Loop (PLL) Mode subsection) to 25 MHz (DIV0
= 4, DIV1 = 5, DIV2 = 2) and output to the FPGA
ExpressCLK
. This allows the I/Os of the circuit to run at
25 MHz ((2 * 5)/4 * 10 MHz). The system clock will run
at DIV2 times the ExpressCLK rate, which is 2 times
25 MHz, or 50 MHz. This setup allows for internal pro-
cessing to occur at twice the rate of on/off device I/O
transfers.
PCM Cautions
Cautions do apply when using the PCM. There are a
number of configurations that are possible in the PCM
that are theoretically valid, but may not produce viable
results. This section describes some of those situa-
tions, and should leave the user with an understanding
of the types of pitfalls that must be avoided when modi-
fying clock signals.
Resultant signals from the PCM must meet the FPGA
timing specifications. It is possible to specify pulses by
using duty-cycle adjustments that are too narrow to
function in the FPGA. For instance, if a 40 MHz clock is
doubled to 80 MHz and a 6.25% duty cycle is selected,
the result will be a 780 ps pulse that repeats every
12.5 ns. This pulse falls outside of the clock pulse width
specification and is not valid.
Using divider DIV2, it is possible to specify a clock mul-
tiplication factor of 64 between the input clock and the
output system clock. As mentioned above, the resultant
frequency must meet all FPGA timing specifications.
The input clock must also meet the minimum specifica-
tions. An input clock rate that is below the PCM clock
minimum cannot be used even if the multiplied output is
within the allowable range.
The use of the PCM to tweak a clock signal to eliminate
a particular problem, such as a single setup time viola-
tion, is discouraged. A small shift in delay, duty cycle, or
phase to correct a single-point problem is in essence
an asynchronous patch to a synchronous system, mak-
ing the system less stable. This type of local problem,
as opposed to a global clock control issue like device-
wide clock delay, can usually be eliminated through
more robust design practices. If this type of change is
made, the designer must be aware that depending on
the extent of the change made, the design may fail to
operate correctly in a different speed grade or voltage
grade (e.g., 3C vs. 3T), or even in a different production
lot of the same device.
Divider DIV2 is available in DLL mode for the Express-
CLK
output, but its use is not recommended with duty-
cycle adjusted clocks.
Lucent Technologies Inc.
85
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
FPGA States of Operation
Prior to becoming operational, the FPGA goes through
a sequence of states, including initialization, configura-
tion, and start-up. Figure 49 outlines these three FPGA
states.
Figure 49. FPGA States of Operation
Initialization
Upon powerup, the device goes through an initialization
process. First, an internal power-on-reset circuit is trig-
gered when power is applied. When V
DD
reaches the
voltage at which portions of the FPGA begin to operate
(2.5 V to 3 V for the OR3Cxx, 2.2 V to 2.7 V for the
OR3Txxx), the I/Os are configured based on the con-
figuration mode, as determined by the mode select
inputs M[2:0]. A time-out delay is initiated when V
DD
reaches between 3.0 V and 4.0 V (OR3Cxx) or 2.7 V to
3.0 V (OR3Txxx) to allow the power supply voltage to
stabilize. The
INIT
and DONE outputs are low. At pow-
erup, if V
DD
does not rise from 2.0 V to V
DD
in less than
25 ms, the user should delay configuration by inputting
a low into
INIT
,
PRGM
, or
RESET
until V
DD
is greater
than the recommended minimum operating voltage
(4.75 V for OR3Cxx commercial devices and 3.0 V for
OR3Txxx devices).
At the end of initialization, the default configuration
option is that the configuration RAM is written to a low
state. This prevents shorts prior to configuration. As a
configuration option, after the first configuration (i.e., at
reconfiguration), the user can reconfigure without
clearing the internal configuration RAM first. The
active-low, open-drain initialization signal
INIT
is
released and must be pulled high by an external resis-
tor when initialization is complete. To synchronize the
configuration of multiple FPGAs, one or more
INIT
pins
should be wire-ANDed. If
INIT
is held low by one or
more FPGAs or an external device, the FPGA remains
in the initialization state.
INIT
can be used to signal that
the FPGAs are not yet initialized. After
INIT
goes high
for two internal clock cycles, the mode lines (M[3:0])
are sampled, and the FPGA enters the configuration
state.
The high during configuration (HDC), low during config-
uration (
LDC
), and DONE signals are active outputs in
the FPGA's initialization and configuration states. HDC,
LDC
, and DONE can be used to provide control of
external logic signals such as reset, bus enable, or
PROM enable during configuration. For parallel master
configuration modes, these signals provide PROM
enable control and allow the data pins to be shared
with user logic signals.
5-4529(F)
ACTIVE I/O
RELEASE INTERNAL RESET
DONE GOES HIGH
START-UP
INITIALIZATION
CONFIGURATION
RESET
OR
PRGM
LOW
PRGM
LOW
CLEAR CONFIGURATION
INIT LOW, HDC HIGH, LDC LOW
OPERATION
POWERUP
POWER-ON TIME DELAY
M[3:0] MODE IS SELECTED
CONFIGURATION DATA FRAME
INIT HIGH, HDC HIGH, LDC LOW
DOUT ACTIVE
YES
NO
NO
RESET,
INIT,
OR
PRGM
LOW
BIT
ERROR
YES
WRITTEN
MEMORY
86
86
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
FPGA States of Operation
(continued)
If configuration has begun, an assertion of
RESET
or
PRGM
initiates an abort, returning the FPGA to the ini-
tialization state. The
PRGM
and
RESET
pins must be
pulled back high before the FPGA will enter the config-
uration state. During the start-up and operating states,
only the assertion of
PRGM
causes a reconfiguration.
In the master configuration modes, the FPGA is the
source of configuration clock (CCLK). In this mode, the
initialization state is extended to ensure that, in daisy-
chain operation, all daisy-chained slave devices are
ready. Independent of differences in clock rates, master
mode devices remain in the initialization state an addi-
tional six internal clock cycles after
INIT
goes high.
When configuration is initiated, a counter in the FPGA
is set to 0 and begins to count configuration clock
cycles applied to the FPGA. As each configuration data
frame is supplied to the FPGA, it is internally assem-
bled into data words. Each data word is loaded into the
internal configuration memory. The configuration load-
ing process is complete when the internal length count
equals the loaded length count in the length count field,
and the required end of configuration frame is written.
All OR3Cxx I/Os operate as TTL inputs during configu-
ration (OR3Txxx I/Os are CMOS-only). All I/Os that are
not used during the configuration process are
3-stated with internal pull-ups.
Warning: During configuration, all OR3Txxx inputs
have internal pull-ups enabled. If these inputs are
driven to 5V, they will draw substantial current (
5 ma).
This is due to the fact that the inputs are pulled up to
3V.
During configuration, the PIC and PLC latches/FFs are
held set/reset and the internal BIDI buffers are 3-
stated. The combinatorial logic begins to function as
the FPGA is configured. Figure 50 shows the general
waveform of the initialization, configuration, and start-
up states.
Configuration
The
ORCA
Series FPGA functionality is determined by
the state of internal configuration RAM. This configura-
tion RAM can be loaded in a number of different
modes. In these configuration modes, the FPGA can
act as a master or a slave of other devices in the sys-
tem. The decision as to which configuration mode to
use is a system design issue. Configuration is dis-
cussed in detail, including the configuration data format
and the configuration modes used to load the configu-
ration data in the FPGA, following a description of the
start-up state.
5-4482(F)
Figure 50. Initialization/Configuration/Start-Up Waveforms
V
DD
M[3:0]
CCLK
HDC
LDC
DONE
USER I/O
INTERNAL
RESET
(gsrn)
CONFIGURATION
OPERATION
INITIALIZATION
START-UP
RESET
PRGM
INIT
Lucent Technologies Inc.
87
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
FPGA States of Operation
(continued)
Start-Up
After configuration, the FPGA enters the start-up
phase. This phase is the transition between the config-
uration and operational states and begins when the
number of CCLKs received after
INIT
goes high is equal
to the value of the length count field in the configuration
frame and when the end of configuration frame has
been written. The system design issue in the start-up
phase is to ensure the user I/Os become active without
inadvertently activating devices in the system or caus-
ing bus contention. A second system design concern is
the timing of the release of global set/reset of the PLC
latches/FFs.
There are configuration options that control the relative
timing of three events: DONE going high, release of the
set/reset of internal FFs, and user I/Os becoming
active. Figure 51 shows the start-up timing for
ORCA
FPGAs. The system designer determines the relative
timing of the I/Os becoming active, DONE going high,
and the release of the set/reset of internal FFs. In the
ORCA
Series FPGA, the three events can occur in any
arbitrary sequence. This means that they can occur
before or after each other, or they can occur simulta-
neously.
There are four main start-up modes: CCLK_NOSYNC,
CCLK_SYNC, UCLK_NOSYNC, and UCLK_SYNC.
The only difference between the modes starting with
CCLK and those starting with UCLK is that for the
UCLK modes, a user clock must be supplied to the
start-up logic. The timing of start-up events is then
based upon this user clock, rather than CCLK. The dif-
ference between the SYNC and NOSYNC modes is
that for SYNC mode, the timing of two of the start-up
events, release of the set/reset of internal FFs, and the
I/Os becoming active is triggered by the rise of the
external DONE pin followed by a variable number of ris-
ing clock edges (either CCLK or UCLK). For the
NOSYNC mode, the timing of these two events is
based only on either CCLK or UCLK.
DONE is an open-drain bidirectional pin that may
include an optional (enabled by default) pull-up resistor
to accommodate wired ANDing. The open-drain DONE
signals from multiple FPGAs can be tied together
(ANDed) with a pull-up (internal or external) and used
as an active-high ready signal, an active-low PROM
enable, or a reset to other portions of the system.
When used in SYNC mode, these ANDed DONE pins
can be used to synchronize the other two start-up
events, since they can all be synchronized to the same
external signal. This signal will not rise until all FPGAs
release their DONE pins, allowing the signal to be
pulled high.
The default for
ORCA
is the CCLK_SYNC synchro-
nized start-up mode where DONE is released on the
first CCLK rising edge, C1 (see Figure 51). Since this is
a synchronized start-up mode, the open-drain DONE
signal can be held low externally to stop the occurrence
of the other two start-up events. Once the DONE pin
has been released and pulled up to a high level, the
other two start-up events can be programmed individu-
ally to either happen immediately or after up to four ris-
ing edges of CCLK (Di, Di + 1, Di + 2, Di + 3, Di + 4).
The default is for both events to happen immediately
after DONE is released and pulled high.
A commonly used design technique is to release
DONE one or more clock cycles before allowing the I/O
to become active. This allows other configuration
devices, such as PROMs, to be disconnected using the
DONE signal so that there is no bus contention when
the I/Os become active. In addition to controlling the
FPGA during start-up, other start-up techniques that
avoid contention include using isolation devices
between the FPGA and other circuits in the system,
reassigning I/O locations, and maintaining I/Os as 3-
stated outputs until contentions are resolved.
Each of these start-up options can be selected during
bit stream generation in
ORCA
Foundry, using
Advanced Options. For more information, please see
the
ORCA
Foundry documentation.
88
88
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
FPGA States of Operation
(continued)
Note: F = finished, no more CLKs required.
5-2761(F)
Figure 51. Start-Up Waveforms
Reconfiguration
To reconfigure the FPGA when the device is operating
in the system, a low pulse is input into
PRGM
. The con-
figuration data in the FPGA is cleared, and the I/Os not
used for configuration are 3-stated. The FPGA then
samples the mode select inputs and begins reconfigu-
ration. When reconfiguration is complete, DONE is
released, allowing it to be pulled high.
Partial Reconfiguration
All
ORCA
device families have been designed to allow
a partial reconfiguration of the FPGA at any time. This
is done by setting a bit stream option in the previous
configuration sequence that tells the FPGA to not reset
all of the configuration RAM during a reconfiguration.
Then only the configuration frames that are to be modi-
fied need to be rewritten, thereby reducing the configu-
ration time.
Other bit stream options are also available that allow
one portion of the FPGA to remain in operation while a
partial reconfiguration is being done. If this is done, the
user must be careful to not cause contention between
the two configurations (the bit stream resident in the
FPGA and the partial reconfiguration bit stream) as the
second reconfiguration bit stream is being loaded.
Other Configuration Options
There are many other configuration options available to
the user that can be set during bit stream generation in
ORCA
Foundry. These include options to enable
boundary scan and/or the microprocessor interface
(MPI) and/or the programmable clock manager (PCM),
readback options, and options to control and use the
internal oscillator after configuration.
Other useful options that affect the next configuration
(not the current configuration process) include options
to disable the global set/reset during configuration, dis-
able the 3-state of I/Os during configuration, and dis-
able the reset of internal RAMs during configuration to
allow for partial configurations (see above). For more
information on how to set these and other configuration
options, please see the
ORCA
Foundry documenta-
tion.
Di
C1
C2
C3
C4
F
C1
C2
C3
C4
C1
C2
C3
C4
C1, C2, C3, OR C4
Di + 1
Di
Di + 2
Di + 3
Di + 4
Di + 1
Di
Di + 2
Di + 3
Di + 4
CCLK_SYNC
DONE IN
U1
U2
U3
U4
F
U1
U2
U3
U4
U1
U2
U3
U4
UCLK_NOSYNC
Di + 1
Di
Di + 2
Di + 3
Di + 4
Di + 1
Di + 2
Di + 3
UCLK_SYNC
UCLK PERIOD
SYNCHRONIZATION UNCERTAINTY
DONE IN
F
C1
C1
U1, U2, U3, OR U4
DONE
I/O
GSRN
ACTIVE
DONE
I/O
GSRN
ACTIVE
DONE
I/O
GSRN
ACTIVE
DONE
I/O
GSRN
ACTIVE
UCLK
F
CCLK_NOSYNC
Lucent Technologies Inc.
89
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Configuration Data Format
The
ORCA
Foundry Development System interfaces
with front-end design entry tools and provides tools to
produce a fully configured FPGA. This section dis-
cusses using the
ORCA
Foundry Development System
to generate configuration RAM data and then provides
the details of the configuration frame format.
The
ORCA
OR3Cxx and OR3Txxx Series FPGAs are
bit stream compatible.
Using
ORCA Foundry
to Generate
Configuration RAM Data
The configuration data bit stream defines the I/O func-
tionality, logic, and interconnections within the FPGA.
The bit stream is generated by the development sys-
tem. The bit stream created by the bit stream genera-
tion tool is a series of 1s and 0s used to write the FPGA
configuration RAM. It can be loaded into the FPGA
using one of the configuration modes discussed later.
In the bit stream generator, the designer selects
options that affect the FPGA's functionality. Using the
output of the bit stream generator, circuit_name.bit,
the development system's download tool can load the
configuration data into the
ORCA
series FPGA evalua-
tion board from a PC or workstation.
Alternatively, a user can program a PROM (such as a
Serial ROM or a standard EPROM) and load the FPGA
from the PROM. The development system's PROM
programming tool produces a file in .mks or .exo for-
mat.
Configuration Data Frame
Configuration data can be presented to the FPGA in
two frame formats: autoincrement and explicit. A
detailed description of the frame formats is shown in
Figure 52, Figure 53, and Table 32. The two modes are
similar except that autoincrement mode uses assumed
address incrementation to reduce the bit stream size,
and explicit mode requires an address for each data
frame. In both cases, the header frame begins with a
series of 1s and a preamble of 0010, followed by a
24-bit length count field representing the total number
of configuration clocks needed to complete the loading
of the FPGAs.
Following the header frame is a mandatory ID frame.
(Note that the ID frame was optional in the
ORCA
2C
and 2C/TxxA Series.)
The ID frame contains data used to determine if the bit
stream is being loaded to the correct type of
ORCA
FPGA (i.e., a bit stream generated for an OR3C55 is
being sent to an OR3C55). Error checking is always
enabled for Series 3 devices, through the use of an
8-bit checksum. One bit in the ID frame also selects
between the autoincrement and explicit address modes
for this load of the configuration data.
A configuration data frame follows the ID frame. A data
frame starts with a 01-start bit pair and ends with
enough 1-stop bits to reach a byte boundary. If using
autoincrement configuration mode, subsequent data
frames can follow. If using explicit mode, one or more
address frames must follow each data frame, telling the
FPGA at what addresses the preceding data frame is
to be stored (each data frame can be sent to multiple
addresses).
Following all data and address frames is the postam-
ble. The format of the postamble is the same as an
address frame with the highest possible address value
with the checksum set to all ones.
90
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Configuration Data Format
(continued)
5-5759(F)
Figure 52. Serial Configuration Data Format--Autoincrement Mode
5-5760(F)
Figure 53. Serial Configuration Data Format--Explicit Mode
Table 32. Configuration Frame Format and Contents
* In MPI configuration mode, the number of stop bits = 32.
Note: For slave parallel mode, the byte containing the preamble must be 11110010. The number of leading header dummy bits must
be (n
*
8) + 4, where n is any nonnegative integer and the number of trailing dummy bits must be (n
*
8), where n is any positive
integer. The number of stop bits/frame for slave parallel mode must be (x
*
8), where x is a positive integer. Note also that the bit
stream generator tool supplies a bit stream that is compatible with all configuration modes, including slave parallel mode.
Header
11110010
Preamble
24-bit Length Count
Configuration frame length.
11111111
Trailing header--8 bits.
ID Frame
0101 1111 1111 1111
ID frame header.
Configuration Mode
00 = autoincrement, 01 = explicit.
Reserved [41:0]
Reserved bits set to 0.
ID
20-bit part ID.
Checksum
8-bit checksum.
11111111
Eight stop bits (high) to separate frames.
Configuration
Data
Frame
(repeated for each
data frame)
01
Data frame header.
Data Bits
Number of data bits depends upon device.
Alignment Bits = 0
String of 0 bits added to bit stream to make frame header, plus data
bits reach a byte boundary.
Checksum
8-bit checksum.
11111111
Eight stop bits (high) to separate frames.
Configuration
Address
Frame
00
Address frame header.
14 Address Bits
14-bit address of location to start data storage.
Checksum
8-bit checksum.
11111111
Eight stop bits (high) to separate frames.
Postamble
00
Postamble header.
11111111 111111
Dummy address.
1111111111111111
16 stop bits.*
CONFIGURATION DATA
CONFIGURATION DATA
1 0
0 1
0 1
PREAMBLE LENGTH
ID FRAME
CONFIGURATION
CONFIGURATION
POSTAMBLE
CONFIGURATION HEADER
0 0
0 0
COUNT
DATA FRAME 1
DATA FRAME 2
PREAMBLE LENGTH
ID FRAME
CONFIGURATION CONFIGURATION
POSTAMBLE
CONFIGURATION HEADER
ADDRESS
ADDRESS
0 0
COUNT
DATA FRAME 1
DATA FRAME 2
FRAME 2
FRAME 1
CONFIGURATION DATA
CONFIGURATION DATA
1 0
0 1
0 1
0 0
0 0
0 0
Lucent Technologies Inc.
91
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Configuration Data Format
(continued)
The length and number of data frames and information on the PROM size for the Series 3 FPGAs are given in
Table 33.
Table 33. Configuration Frame Size
Bit Stream Error Checking
There are three different types of bit stream error checking performed in the
ORCA
Series 3 FPGAs:
ID frame, frame alignment, and CRC checking.
The ID data frame is sent to a dedicated location in the FPGA. This ID frame contains a unique code for the device
for which it was generated. This device code is compared to the internal code of the FPGA. Any differences are
flagged as an ID error. This frame is automatically created by the bit stream generation program in
ORCA
Foundry.
Each data and address frame in the FPGA begins with a frame start pair of bits and ends with eight stop bits set to
1. If any of the previous stop bits were a 0 when a frame start pair is encountered, it is flagged as a frame align-
ment error.
Error checking is also done on the FPGA for each frame by means of a checksum byte. If an error is found on eval-
uation of the checksum byte, then a checksum/parity error is flagged. The checksum is the XOR of all the data
bytes, from the start of frame up to and including the bytes before the checksum. It applies to the ID, address, and
data frames.
When any of the three possible errors occur, the FPGA is forced into an idle state, forcing INIT low. The FPGA will
remain in this state until either the
RESET
or
PRGM
pins are asserted.
If using either of the MPI modes to configure the FPGA, the specific type of bit stream error is written to one of the
MPI
registers by the FPGA configuration logic. The
PGRM
bit of the MPI control register can also be used to reset
out of the error condition and restart configuration.
Devices
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
# of Frames
856
984
1240
1496
1880
Data Bits/Frame
202
232
292
352
442
Configuration Data (# of frames x # of data
bits/frame)
172,912
228,288
362,080
526,592
830,960
Maximum Total # Bits/Frame (align bits, 01
frame start, 8-bit checksum, 8 stop bits)
224
256
312
376
464
Maximum Configuration Data (# bits/frame
x # of frames)
191,744
251,904
386,880
562,496
872,320
Maximum PROM Size (bits)
(add configuration header and postamble)
191,912
252,072
387,048
562,664
872,488
92
92
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
FPGA Configuration Modes
There are eight methods for configuring the FPGA.
Seven of the configuration modes are selected on the
M0, M1, and M2 inputs. The eighth configuration mode
is accessed through the boundary-scan interface. A
fourth input, M3, is used to select the frequency of the
internal oscillator, which is the source for CCLK in
some configuration modes. The nominal frequencies of
the internal oscillator are 1.25 MHz and 10 MHz. The
1.25 MHz frequency is selected when the M3 input is
unconnected or driven to a high state.
There are three basic FPGA configuration modes:
master, slave, and peripheral. The configuration data
can be transmitted to the FPGA serially or in parallel
bytes. As a master, the FPGA provides the control sig-
nals out to strobe data in. As a slave device, a clock is
generated externally and provided into the CCLK input.
In the three peripheral modes, the FPGA acts as a
microprocessor peripheral. Table 34 lists the functions
of the configuration mode pins. Note that two configura-
tion modes previously available on the OR2Cxx and
OR2C/TxxA devices (master parallel down and syn-
chronous peripheral) have been removed for Series 3
devices.
Table 34. Configuration Modes
*
Motorola
is a registered trademark of Motorola, Inc.
Master Parallel Mode
The master parallel configuration mode is generally
used to interface to industry-standard, byte-wide mem-
ory, such as the 2764 and larger EPROMs. Figure 54
provides the connections for master parallel mode. The
FPGA outputs an 18-bit address on A[17:0] to memory
and reads 1 byte of configuration data on the rising
edge of RCLK. The parallel bytes are internally serial-
ized starting with the least significant bit, D0. D[7:0] of
the FPGA can be connected to D[7:0] of the micropro-
cessor only if a standard prom file format is used. If a
.bit or .rbt file is used from
ORCA
Foundry, then the
user must mirror the bytes in the .bit or .rbt file OR
leave the .bit or .rbt file unchanged and connect D[7:0]
of the FPGA to D[0:7] of the microprocessor.
Figure 54. Master Parallel Configuration Schematic
In master parallel mode, the starting memory address
is 00000 Hex, and the FPGA increments the address
for each byte loaded.
One master mode FPGA can interface to the memory
and provide configuration data on DOUT to additional
FPGAs in a daisy-chain. The configuration data on
DOUT is provided synchronously with the falling edge
of CCLK. The frequency of the CCLK output is eight
times that of RCLK.
M2
M1
M0
CCLK
Configuration
Mode
Data
0
0
0
Output
Master Serial
Serial
0
0
1
Input
Slave Parallel
Parallel
0
1
0
Output
Microprocessor:
Motorola
*
Pow-
erPC
Parallel
0
1
1
Output
Microprocessor:
Intel i960
Parallel
1
0
0
Output
Master Parallel
Parallel
1
0
1
Output
Async Peripheral
Parallel
1
1
0
Reserved
1
1
1
Input
Slave Serial
Serial
EPROM
A[17:0]
DONE
M2
M1
M0
HDC
ORCA
SERIES
FPGA
RCLK
LDC
V
DD
D[7:0]
DOUT
CCLK
TO DAISY-
CHAINED
DEVICES
V
DD
OR GND
PRGM
PROGRAM
A[17:0]
D[7:0]
OE
CE
Lucent Technologies Inc.
93
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
FPGA Configuration Modes
(continued)
Master Serial Mode
In the master serial mode, the FPGA loads the configu-
ration data from an external serial ROM. The configura-
tion data is either loaded automatically at start-up or on
a
PRGM
command to reconfigure. The ATT1700A
Series Serial PROMs can be used to configure the
FPGA in the master serial mode. This provides a sim-
ple 4-pin interface in a compact package.
Configuration in the master serial mode can be done at
powerup and/or upon a configure command. The sys-
tem or the FPGA must activate the serial ROM's
RESET
/OE and
CE
inputs. At powerup, the FPGA and
serial ROM each contain internal power-on reset cir-
cuitry that allows the FPGA to be configured without
the system providing an external signal. The power-on
reset circuitry causes the serial ROM's internal address
pointer to be reset. After powerup, the FPGA automati-
cally enters its initialization phase.
The serial ROM/FPGA interface used depends on such
factors as the availability of a system reset pulse, avail-
ability of an intelligent host to generate a configure
command, whether a single serial ROM is used or mul-
tiple serial ROMs are cascaded, whether the serial
ROM contains a single or multiple configuration pro-
grams, etc. Because of differing system requirements
and capabilities, a single FPGA/serial ROM interface is
generally not appropriate for all applications.
Data is read in the FPGA sequentially from the serial
ROM. The DATA output from the serial ROM is con-
nected directly into the DIN input of the FPGA. The
CCLK output from the FPGA is connected to the CLK
input of the serial ROM. During the configuration pro-
cess, CCLK clocks one data bit on each rising edge.
Since the data and clock are direct connects, the
FPGA/serial ROM design task is to use the system or
FPGA to enable the
RESET
/OE and
CE
of the serial
ROM(s). There are several methods for enabling the
serial ROM's
RESET
/OE and
CE
inputs. The serial
ROM's
RESET
/OE is programmable to function with
RESET active-high and
OE
active-low or
RESET
active-
low and OE active-high.
In Figure 55, serial ROMs are cascaded to configure
multiple daisy-chained FPGAs. The host generates a
500 ns low pulse into the FPGA's
PRGM
input. The
FPGA's
INIT
input is connected to the serial ROMs'
RESET
/OE input, which has been programmed to
function with
RESET
active-low and OE active-high.
The FPGA DONE is routed to the
CE
pin. The low on
DONE enables the serial ROMs. At the completion of
configuration, the high on the FPGA's DONE disables
the serial ROM.
Serial ROMs can also be cascaded to support the con-
figuration of multiple FPGAs or to load a single FPGA
when configuration data requirements exceed the
capacity of a single serial ROM. After the last bit from
the first serial ROM is read, the serial ROM outputs
CEO
low and 3-states the DATA output. The next serial
ROM recognizes the low on
CE
input and outputs con-
figuration data on the DATA output. After configuration
is complete, the FPGA's DONE output into
CE
disables
the serial ROMs.
This FPGA/serial ROM interface is not used in applica-
tions in which a serial ROM stores multiple configura-
tion programs. In these applications, the next
configuration program to be loaded is stored at the
ROM location that follows the last address for the previ-
ous configuration program. The reason the interface in
Figure 55 will not work in this application is that the low
output on the
INIT
signal would reset the serial ROM
address pointer, causing the first configuration to be
reloaded.
In some applications, there can be contention on the
FPGA's DIN pin. During configuration, DIN receives
configuration data, and after configuration, it is a user
I/O. If there is contention, an early DONE at start-up
(selected in
ORCA
Foundry) may correct the problem.
An alternative is to use
LDC
to drive the serial ROM's
CE
pin. In order to reduce noise, it is generally better to
run the master serial configuration at 1.25 MHz (M3 pin
tied high), rather than 10 MHz, if possible.
Figure 55. Master Serial Configuration Schematic
ATT1700A
DIN
M2
M1
M0
ORCA
SERIES
FPGA
CCLK
DOUT
TO DAISY-
CHAINED
DEVICES
DATA
CLK
CE
CEO
ATT1700A
DATA
CLK
RESET/OE
CEO
CE
TO MORE
SERIAL ROMs
AS NEEDED
DONE
INIT
PROGRAM
RESET/OE
PRGM
5-4456.1(F)
94
94
Lucent Technologies Inc.
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
FPGA Configuration Modes
(continued)
Asynchronous Peripheral Mode
Figure 56 shows the connections needed for the asyn-
chronous peripheral mode. In this mode, the FPGA
system interface is similar to that of a microprocessor-
peripheral interface. The microprocessor generates the
control signals to write an 8-bit byte into the FPGA. The
FPGA control inputs include active-low
CS0
and active-
high CS1 chip selects and
WR
and
RD
inputs. The chip
selects can be cycled or maintained at a static level
during the configuration cycle. Each byte of data is writ-
ten into the FPGA's D[7:0] input pins. D[7:0] of the
FPGA can be connected to D[7:0] of the microproces-
sor only if a standard prom file format is used. If a .bit or
.rbt file is used from
ORCA
Foundry, then the user must
mirror the bytes in the .bit or .rbt file OR leave the .bit or
.rbt file unchanged and connect D[7:0] of the FPGA to
D[0:7] of the microprocessor.
The FPGA provides an RDY/
BUSY
status output to indi-
cate that another byte can be loaded. A low on RDY/
BUSY
indicates that the double-buffered hold/shift reg-
isters are not ready to receive data, and this pin must
be monitored to go high before another byte of data
can be written. The shortest time RDY/
BUSY
is low
occurs when a byte is loaded into the hold register and
the shift register is empty, in which case the byte is
immediately transferred to the shift register. The long-
est time for RDY/
BUSY
to remain low occurs when a
byte is loaded into the holding register and the shift
register has just started shifting configuration data into
configuration RAM.
The RDY/
BUSY
status is also available on the D7 pin by
enabling the chip selects, setting
WR
high, and apply-
ing
RD
low, where the
RD
input provides an output
enable for the D7 pin when
RD
is low. The D[6:0] pins
are not enabled to drive when
RD
is low and, therefore,
only act as input pins in asynchronous peripheral
mode. Optionally, the user can ignore the RDY/
BUSY
status and simply wait until the maximum time it would
take for the RDY/
BUSY
line to go high, indicating the
FPGA is ready for more data, before writing the next
data byte.
Figure 56. Asynchronous Peripheral Configuration
Microprocessor Interface
(MPI)
Mode
The built-in MPI in Series 3 FPGAs is designed for use
in configuring the FPGA. Figure 57 and Figure 58 show
the glueless interface for FPGA configuration and read-
back from the
PowerPC
and
i960
processors, respec-
tively. When enabled by the mode pins, the MPI
handles all configuration/readback control and hand-
shaking with the host processor. For single FPGA con-
figuration, the host sets the configuration control
register
PRGM
bit to zero then back to a one and, after
reading that the
INIT
signal is high in the MPI status
register, transfers data 8 bits at a time to the FPGA's
D[7:0] input pins.
If configuring multiple FPGAs through daisy-chain
operation is desired, the MP_DAISY bit must be set in
the configuration control register of the MPI. Because
of the latency involved in a daisy-chain configuration,
the MP_HOLD_BUS bit may be set to zero rather than
one for daisy-chain operation. This allows the MPI to
acknowledge the data transfer before the configuration
information has been serialized and transferred on the
FPGA daisy-chain. The early acknowledgment frees
the host processor to perform other system tasks. Con-
figuring with the MP_HOLD_BUS bit at zero requires
that the host microprocessor poll the RDY/
BUSY
bit of
the MPI status register and/or use the MPI interrupt
capability to confirm the readiness of the MPI for more
configuration data.
MICRO-
PROCESSOR
D[7:0]
CS1
M2
M1
M0
HDC
ORCA
SERIES
FPGA
8
LDC
V
DD
DONE
CS0
DOUT
CCLK
TO DAISY-
CHAINED
DEVICES
BUS
CONTROLLER
ADDRESS
DECODE LOGIC
RD
WR
RDY/BUSY
INIT
PRGM
Lucent Technologies Inc.
95
Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
FPGA Configuration Modes
(continued)
There are two options for using the host interrupt
request in configuration mode. The configuration con-
trol register offers control bits to enable the interrupt on
either a bit stream error or to notify the host processor
when the FPGA is ready for more configuration data.
The MPI status register may be used in conjunction
with, or in place of, the interrupt request options. The
status register contains a 2-bit field to indicate the bit
stream error status. As previously mentioned, there is
also a bit to indicate the MPI's readiness to receive
another byte of configuration data. A flow chart of the
MPI
configuration process is shown in Figure 59. The
MPI
status and configuration register bit maps can be
found in the Special Function Blocks section and MPI
configuration timing information is available in the Tim-
ing Characteristics section of this data sheet.
5-5761(F)
Note: FPGA shown as a memory-mapped peripheral using
CS0
and
CS1. Other decoding schemes are possible using
CS0
and/or
CS1.
Figure 57.
PowerPC
/MPI Configuration Schematic
5-5762(F)
Note: FPGA shown as only system peripheral with fixed chip select
signals. For multiperipheral systems, address decoding and/
or latching can be used to implement chip selects.
Figure 58.
i960
/MPI Configuration Schematic
Configuration readback can also be performed via the
MPI
when it is in user mode. The MPI is enabled in user
mode by setting the MP_USER bit to 1 in the configura-
tion control register prior to the start of configuration or
through a configuration option. To perform readback,
the host processor writes the 14-bit readback start
address to the readback address registers and sets the
RD_CFG
bit to 0 in the configuration control register.
Readback data is returned 8 bits at a time to the read-
back data register and is valid when the DATA_RDY bit
of the status register is 1. There is no error checking
during readback. A flow chart of the MPI readback
operation is shown in Figure 60. The RD_DATA pin
used for dedicated FPGA readback is invalid during
MPI
readback.
5-5763(F)
Figure 59. Configuration Through MPI
DOUT
CCLK
D[7:0]
A[4:0]
MPI_CLK
MPI_RW
MPI_ACK
MPI_BI
MPI_IRQ
MPI_STRB
CS0
CS1
HDC
LDC
D[7:0]
A[27:31]
CLKOUT
RD/WR
TA
BI
IRQx
TS
A26
A25
TO DAISY-
CHAINED
DEVICES
POWERPC
ORCA
8
FPGA
SERIES 3
DONE
INIT
DOUT
CCLK
D[7:0]
MPI_CLK
MPI_RW
MPI_ACK
MPI_IRQ