Preliminary Data Sheet
December 2000

ORCA

Series 4

Field-Programmable Gate Arrays

Programmable Features

High-performance platform design.
-- 0.13 µm seven-level metal technology.
-- Internal performance of >250 MHz

(four logic levels).

-- I/O performance of >416 MHz for all user I/Os.
-- Over 1.5 million usable system gates.
-- Meets multiple I/O interface standards.
-- 1.5 V operation (30% less power than 1.8 V oper-

ation) translates to greater performance.

-- Embedded block RAM (EBR) for onboard stor-

age and buffer needs.

-- Built-in system components including an internal

system bus, eight PLLs, and microprocessor
interface.

Traditional I/O selections.
-- LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V)

I/Os.

-- Per pin-selectable I/O clamping diodes provide

3.3 V PCI compliance.

-- Individually programmable drive capability.

24 mA sink/12 mA source, 12 mA sink/6 mA
source, or 6 mA sink/3 mA source.

-- Two slew rates supported (fast and slew-limited).
-- Fast-capture input latch and input flip-flop (FF)/

latch for reduced input setup time and zero hold
time.

-- Fast open-drain drive capability.
-- Capability to register 3-state enable signal.
-- Off-chip clock drive capability.
-- Two-input function generator in output path.

New programmable high-speed I/O.
-- Single-ended: GTL, GTL+, PECL, SSTL3/2

(class I & II), HSTL (Class I, III, IV), zero-bus
turn-around (ZBT*), and double data rate (DDR).

-- Double-ended: LDVS, bused-LVDS, LVPECL.
-- Customer defined: Ability to substitute arbitrary

standard-cell I/O to meet fast moving standards.

New capability to (de)multiplex I/O signals.
-- New DDR on both input and output at rates up to

311 MHz (622 MHz effective rate).

-- Used to implement emerging RapidIO

back-

plane interface specification.

-- New 2x and 4x downlink and uplink capability per

I/O (i.e., 104 MHz internal to 416 MHz I/O).

Enhanced twin-quad programmable function unit
(PFU).
-- Eight 16-bit look-up tables (LUTs) per PFU.
-- Nine user registers per PFU, one following each

LUT and organized to allow two nibbles to act
independently, plus one extra for arithmetic
carry/borrow operations.

* ZBT is a trademark of Integrated Device Technologies Inc.
RapidIO is a trademark of Motorola, Inc.

Table 1. ORCA Series 4--Available FPGA Logic

The usable gate counts range from a logic-only gate count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The

logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and
12 gates per SLIC/FF pair (one per PFU). Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic,
CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or
512 gates) per PFU. Embedded block RAM (EBR) is counted as four gates per bit plus each block has an additional 25k gates. 7k gates
are used for each PLL and 50k gates for the embedded system bus and microprocessor interface logic. Both the EBR and PLLs are con-
servatively utilized in the gate count calculations.

Note: Devices are not pinout compatible with ORCA Series 2/3.

Device

Columns

Rows

PFUs

User I/O

LUTs

EBR

Blocks

EBR Bits (k)

Usable

Gates (k)

OR4E2

624

400

4992

260--470

OR4E4

1296

576

10368

111

400--720

OR4E6

2024

720

16,192

148

530--970

OR4E10

3360

928

26,880

185

740--1350

OR4E14

4620

1088

36,960

222

930--1700

Table of Contents

Contents

Page

Contents

Page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Features............................................. 1
System Features .........................................................4
Product Description .....................................................6

Architecture Overview .............................................6

Programmable Logic Cells ..........................................7

Programmable Function Unit ...................................8
Look-Up Table Operating Modes ..........................11
Supplemental Logic and Interconnect Cell ............21
PLC Latches/Flip-Flops .........................................25

Embedded Block RAM ..............................................27

EBR Features ........................................................27

Routing Resources ...................................................31
Clock Distribution Network ........................................31

Primary Clock Nets ................................................31
Secondary Clock and Control Nets .......................31
Edge Clock Nets ....................................................31

Programmable Input/Output Cells .............................31

Programmable I/O .................................................31
Inputs .....................................................................34

Special Function Blocks ............................................38
Microprocessor Interface (MPI) .................................48
Embedded System Bus (ESB) ..................................49
Phase-Locked Loops.................................................52
FPGA States of Operation.........................................55

Initialization ............................................................56
Configuration .........................................................56
Start-Up .................................................................56
Reconfiguration .....................................................60
Partial Reconfiguration ..........................................60
Other Configuration Options ..................................60
Bit Stream Error Checking .....................................62

FPGA Configuration Modes.......................................62

Master Parallel Mode.............................................63
Master Serial Mode ...............................................64
Asynchronous Peripheral Mode ............................65
Microprocessor Interface Mode .............................66
Slave Serial Mode .................................................70
Slave Parallel Mode...............................................70
Daisy Chaining ......................................................71
Daisy-Chaining with Boundary Scan .....................72

Absolute Maximum Ratings.......................................72
Recommended Operating Conditions .......................73
Electrical Characteristics ...........................................73
Pin Information ..........................................................75

Pin Descriptions.....................................................75
Package Compatibility ...........................................78

Package Thermal Characteristics Summary ...........118

......................................................................118

Package Thermal Characteristics............................119

Package Coplanarity ...............................................119
Package Parasitics ..................................................119
Package Outline Diagrams......................................120

Terms and Definitions..........................................120

Package Outline Drawings ......................................121

352-Pin PBGA .....................................................121
432-Pin EBGA .....................................................122
680-Pin PBGAM ..................................................123

Ordering Information................................................124

Figure

Page

Figure 1. Series 4 Top-Level Diagram ........................7
Figure 2. PFU Ports .....................................................9
Figure 3. Simplified PFU Diagram .............................10
Figure 4. Simplified F4 and F5 Logic Modes .............12
Figure 5. Simplified F6 Logic Modes .........................13
Figure 6. MUX 4 x 1...................................................13
Figure 7. MUX 8 x 1...................................................14
Figure 8. Softwired LUT Topology Examples.............15
Figure 9. Ripple Mode ...............................................16
Figure 10. Counter Submode ....................................17
Figure 11. Multiplier Submode...................................18
Figure 12. Memory Mode ..........................................19
Figure 13. Memory Mode Expansion

Example--128 x 8 RAM ........................................21

Figure 14. SLIC All Modes Diagram ..........................22
Figure 15. Buffer Mode ..............................................23
Figure 16. Buffer-Buffer-Decoder Mode ....................23
Figure 17. Buffer-Decoder-Buffer Mode ....................24
Figure 18. Buffer-Decoder-Decoder Mode ................24
Figure 19. Decoder Mode ..........................................25
Figure 20. Latch/FF Set/Reset Configurations ..........26
Figure 21. EBR Read and Write Cycles

with Write Through ................................................29

Figure 22. Series 4 PIO Image from

ORCA Foundry ......................................................33

Figure 23. ORCA High-Speed I/O Banks ..................36
Figure 24. PIO Shift Register.....................................38
Figure 25. Printed-Circuit Board with Boundary-

Scan Circuitry ........................................................39

Figure 26. Boundary-Scan Interface..........................40
Figure 27. ORCA Series Boundary-Scan

Circuitry Functional Diagram .................................43

Figure 28. TAP Controller State Transition

Diagram .................................................................44

Figure 29. Boundary-Scan Cell .................................45
Figure 30. Instruction Register Scan Timing

Diagram .................................................................46

Figure 31. PLL_VF External Requirements...............53
Figure 32. PLL Naming Scheme ...............................54

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Contents

Page

Contents

Page

Table of Contents

(continued)

Figure 33. FPGA States of Operation ....................... 55
Figure 34. Initialization/Configuration/Start-Up

Waveforms............................................................. 57

Figure 35. Start-Up Waveforms................................. 59
Figure 36. Serial Configuration Data

Format--Autoincrement Mode .............................. 60

Figure 37. Serial Configuration Data

Format--Explicit Mode .......................................... 60

Figure 38. Master Parallel

Configuration Schematic ....................................... 63

Figure 39. Master Serial Configuration Schematic.... 65
Figure 40. Asynchronous Peripheral Configuration... 66
Figure 41. PowerPC/MPI Configuration Schematic... 67
Figure 42. Configuration Through MPI ...................... 68
Figure 43. Readback Through MPI ........................... 69
Figure 44. Slave Serial Configuration Schematic ...... 70
Figure 45. Slave Parallel Configuration Schematic ... 71
Figure 46. Daisy-Chain Configuration Schematic ..... 72
Figure 47. Package Parasitics ................................. 120

Table

Page

Table 1. ORCA Series 4--Available FPGA Logic ....... 1
Table 2. System Performance .................................... 5
Table 3. Look-Up Table Operating Modes ................ 11
Table 4. Control Input Functionality .......................... 11
Table 5. Ripple Mode Equality Comparator

Functions and Outputs .......................................... 18

Table 6. SLIC Modes ................................................ 22
Table 7. Configuration RAM Controlled Latch/

Flip-Flop Operation................................................ 25

Table 8. ORCA Series 4-- Available

Embedded Block RAM .......................................... 27

Table 9. RAM Signals ............................................... 28
Table 10. FIFO Signals ............................................ 29
Table 11. Constant Multiplier Signals ....................... 30
Table 12. 8 x 8 Multiplier Signals.............................. 30
Table 13. CAM Signals ............................................. 30
Table 14. Series 4 Programmable I/O Standards ..... 32
Table 15. PIO Options .............................................. 35
Table 16. PIO Register Control Signals .................... 35

Table 17. PIO Logic Options..................................... 36
Table 18. Compatible Mixed I/O Standards .............. 36
Table 19. LVDS I/O Specifications........................... 37
Table 20. LVDS Termination Pin ............................. 37
Table 21. Dedicated Temperature Sensing.............. 39
Table 22. Boundary-Scan Instructions ..................... 40
Table 23. Series 4E Boundary-Scan

Vendor-ID Codes................................................... 41

Table 24. TAP Controller Input/Outputs ................... 43
Table 25. Readback Options .................................... 46
Table 26. MPC 860 to ORCA MPI Interconnection .. 48
Table 27. Embedded System Bus/MPI Registers..... 50
Table 28. Interrupt Register Space Assignments ..... 50
Table 29. Status Register Space Assignments ........ 51
Table 30. Command Register Space Assignments .. 51
Table 31. PPLL Specifications.................................. 52
Table 32. DPLL DS-1/E-1 Specifications.................. 53
Table 33. Dedicated Pin Per Package ...................... 53
Table 34. STS-3/STM-1 DPLL Specifications........... 54
Table 35. Phase-Lock Loops Index .......................... 54
Table 36A. Configuration Frame Format

and Contents ......................................................... 61

Table 36B. Configuration Frame Format

and Contents for Embedded Block RAM............... 61

Table 37. Configuration Frame Size ......................... 62
Table 38. Configuration Modes................................. 63
Table 39. Absolute Maximum Ratings ...................... 73
Table 40. Recommended Operating Conditions....... 73
Table 41. Electrical Characteristics .......................... 73
Table 42. Pin Descriptions........................................ 75
Table 43. ORCA I/Os Summary ............................... 78
Table 44. 352-Pin PBGA Pinout ............................... 79
Table 45. 432-Pin EBGA .......................................... 89
Table 46. 680-Pin PBGAM Pinout ............................ 99
Table 47. ORCA Series 4 FPGAs Plastic

Package Thermal Guidelines .............................. 119

Table 48. ORCA Series 4 FPGAs

Package Parasitics .............................................. 119

Table 49. Series 4 Package Matrix

(Speed Grades)................................................... 124

Table 50. Package Options..................................... 124

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Features

(continued)

-- New register control in each PFU has two inde-

pendent programmable clocks, clock enables,
local set/reset, and data selects.

-- New LUT structure allows flexible combinations of

LUT4, LUT5, new LUT6, 4-to-1 MUX, new
8-to-1 MUX, and ripple mode arithmetic functions
in the same PFU.

-- 32 x 4 RAM per PFU, configurable as single- or

dual-port. Create large, fast RAM/ROM blocks
(128 x 8 in only eight PFUs) using the supplemen-
tal logic and interconnect cell (SLIC) decoders as
bank drivers.

-- Softwired LUTs (SWL) allow fast cascading of up

to three levels of LUT logic in a single PFU
through fast internal routing which reduces routing
congestion and improves speed.

-- Flexible fast access to PFU inputs from routing.
-- Fast-carry logic and routing to all four adjacent

PFUs for nibble-, bytewide, or longer arithmetic
functions, with the option to register the PFU
carry-out.

Abundant high-speed buffered and nonbuffered rout-
ing resources provide 2x average speed improve-
ments over previous architectures.

Hierarchical routing optimized for both local and glo-
bal routing with dedicated routing resources. This
results in faster routing times with predictable and
efficient performance.

SLIC provides eight 3-statable buffers, up to 10-bit
decoder, and PAL

-like and-or-invert (AOI) in each

programmable logic cell.

New 200 MHz embedded quad-port RAM blocks, two
read ports, two write ports, and two sets of byte lane
enables. Each embedded RAM block can be config-
ured as:
-- One 512 x 18 (quad-port, two read/two write) with

optional built-in arbitration.

-- One 256 x 36 (dual-port, one read/one write).
-- One 1K x 9 (dual-port, one read/one write).
-- Two 512 x 9 (dual-port, one read/one write for

each).

-- Two RAMs with arbitrary number of words whose

sum is 512 or less by 18 (dual-port, one read/one
write).

-- Supports joining of RAM blocks.
-- Two 16 x 8-bit content addressable memory

(CAM) support.

-- FIFO 512 x 18, 256 x 36, 1K x 9 or dual 512 x 9.
-- Constant multiply (8 x 16 or 16 x 8).
-- Dual-variable multiply (8 x 8).

Built-in testability.
-- Full boundary-scan (IEEE

1149.1 and Draft

1149.2 joint test access group (JTAG)).

-- Programming and readback through boundary-

scan port compliant to IEEE Draft 1532:D1.7.

-- TS_ALL testability function to 3-state all I/O pins.
-- New temperature-sensing diode used to deter-

mine device junction temperature.

System Features

PCI local bus compliant.

Improved PowerPC

860 and PowerPC II high-speed

(66 MHz) synchronous MPI interface can be used for
configuration, readback, device control, and device
status, as well as for a general-purpose interface to
the FPGA logic, RAMs, and embedded standard-cell
blocks. Glueless interface to synchronous PowerPC
processors with user-configurable address space
provided.

New embedded AMBA

specification 2.0 AHB sys-

tem bus (ARM

processor) facilitates communication

among the microprocessor interface, configuration
logic, EBR, FPGA logic, and embedded standard-cell
blocks. Embedded 32-bit internal system bus plus
4-bit parity interconnects FPGA logic, microproces-
sor interface (MPI), embedded RAM blocks, and
embedded standard-cell blocks with 100 MHz bus
performance. Included are built-in system registers
that act as the control and status center for the
device.

New network phase-locked loops (PLLs) meet ITU-T
G.811 specifications and provide clock conditioning
for DS-1/E-1 and STS-3/STM-1 applications.

Flexible general-purpose programmable PLLs offer
clock multiply (up to 8x), divide (down to 1/8x), phase
shift, delay compensation, and duty cycle adjustment
combined. Improved built-in clock management with
programmable phase-locked loops (PPLLs) provide
optimum clock modification and conditioning for
phase, frequency, and duty cycle from 20 MHz up to
420 MHz. Each PPLL provides two separate clock
outputs.

1. PAL is a trademark of Advanced Micro Devices, Inc.
2. IEEE a is registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

3. PowerPC is a registered trademark of International Business

Machines, Corporation.

4. AMBA and ARM are trademarks of ARM Limited.

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

System Features

(continued)

Variable-size bused readback of configuration data capability with the built-in MPI and system bus.

Internal, 3-state, bidirectional buses with simple control provided by the SLIC.

Meets universal test and operations PHY interface for ATM (UTOPIA) Levels 1, 2, and 3. Also meets proposed
specifications for UTOPIA Level 4 for 10 Gbits/s interfaces.

New clock routing structures for global and local clocking significantly increases speed and reduces skew
(<200 ps for OR4E4).

New local clock routing structures allow creation of localized clock trees anywhere on the device.

New DDR, QDR, and ZBT memory interfaces support the latest high-speed memory interfaces.

New 2x/4x uplink and downlink I/O shift registers capabilities interface high-speed external I/Os to reduced inter-
nal logic speed.

ORCA Foundry 2000 development system software. Supported by industry-standard CAE tools for design entry,
synthesis, simulation, and timing analysis.

Table 2. System Performance

1. Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 32 x 4 RAMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (seven of 15 PFUs

contain only pipelining registers).

4. Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.
5. Implemented using 32 x 4 dual-port RAM mode.
6. Implemented in one partially occupied SLIC, with decoded output setup to CE in the same PLC.
7. Implemented in five partially occupied SLICs.

Function No.

PFUs

Unit

16-bit loadable up/down counter

282

MHz

16-bit accumulator

282

MHz

8 x 8 Parallel Multiplier

Multiplier mode, unpipelined

11.5

MHz

ROM mode, unpipelined

175

MHz

Multiplier mode, pipelined

197

MHz

32 x 16 RAM (synchronous)

Single port, 3-state bus

264

MHz

Dual-port

340

MHz

128 x 8 RAM (synchronous)

Single port, 3-state bus

264

MHz

Dual-port, 3-state bus

264

MHz

Address Decode

8-bit internal, LUT-based

0.25

1.37

8-bit internal, SLIC-based

0.73

32-bit internal, LUT-based

4.68

32-bit internal, SLIC-based

2.08

36-bit Parity Check (internal)

4.68

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Product Description

Architecture Overview

The ORCA Series 4 architecture is a new generation of
SRAM-based programmable devices from Lucent
Technologies Microelectronics Group. It includes
enhancements and innovations geared toward today's
high-speed systems on a single chip. Designed with
networking applications in mind, the Series 4 family
incorporates system-level features that can further
reduce logic requirements and increase system speed.
ORCA Series 4 devices contain many new patented
enhancements and are offered in a variety of packages
and speed grades.

The hierarchical architecture of the logic, clocks, rout-
ing, RAM, and system-level blocks create a seamless
merge of FPGA and ASIC designs. Modular hardware
and software technologies enable system-on-chip inte-
gration with true plug-and-play design implementation.

The architecture consists of four basic elements: pro-
grammable logic cells (PLCs), programmable input/out-
put cells (PIOs), embedded block RAMs (EBRs), and
system-level features. These elements are intercon-
nected with a rich routing fabric of both global and local
wires. An array of PLCs and its associated resources
are surrounded by common interface blocks (CIBs) that
provide an abundant interface to the adjacent PIOs or

system blocks. Routing congestion around these criti-
cal blocks is eliminated by the use of the same routing
fabric implemented within the programmable logic core.
PICs provide the logical interface to the PIOs which
provide the boundary interface off and onto the device.
Also, the interquad routing blocks (hIQ, vIQ) separate
the quadrants of the PLC array and provide the global
routing and clocking elements. Each PLC contains a
PFU, SLIC, local routing resources, and configuration
RAM. Most of the FPGA logic is performed in the PFU,
but decoders, PAL-like functions, and 3-state buffering
can be performed in the SLIC. The PIOs provide device
inputs and outputs and can be used to register signals
and to perform input demultiplexing, output multiplex-
ing, uplink and downlink functions, and other functions
on two output signals.

The Series 4 architecture integrates macrocell blocks
of memory known as EBR. The blocks run horizontally
across the PLC array and provide flexible memory
functionality. Large blocks of 512 x 18 quad-port RAM
complement the existing distributed PFU memory. The
RAM blocks can be used to implement RAM, ROM,
FIFO, multiplier, and CAM.

System-level functions such as a microprocessor inter-
face, PLLs, embedded system bus elements (located in
the corners of the array), the routing resources, and
configuration RAM are also integrated elements of the
architecture.

Preliminary Data Sheet
December 2000

Lucent Technologies Inc.

ORCA Series 4 FPGAs

Product Description

(continued)

5-7536 (F)a

Figure 1. Series 4 Top-Level Diagram

EMBEDDED

SYSTEM BUS

PLC

MICROPROCESSOR

INTERFACE (MPI)

PFU

SLIC

FPGA/SYSTEM

BUS INTERFACE

PLLs

EMBEDDED

BLOCK RAM

HIGH-SPEED I/Os

CLOCK PINS

PIO

Programmable Logic Cells

The PLCs are arranged in an array of rows and col-
umns. The location of a PLC is indicated by its row and
column so that a PLC in the second row and the third
column is R2C3. The array of actual PLCs for every
device begins with R3C2 in all Series 4 generic
FPGAs.

The PLC consists of a PFU, SLIC, and routing
resources. Each PFU within a PLC contains eight
4-input (16-bit) LUTs, eight latches/FFs, and one addi-
tional FF that may be used independently or with arith-
metic functions. The PFU is the main logic element of
the PLC, containing elements for both combinatorial

and sequential logic. Combinatorial logic is done in
LUTs located in the PFU. The PFU can be used in dif-
ferent modes to meet different logic requirements. The
LUTs twin-quad architecture provides a configurable
medium-/large-grain architecture that can be used to
implement from one to eight independent combinatorial
logic functions or a large number of complex logic func-
tions using multiple LUTs. The flexibility of the LUT to
handle wide input functions, as well as multiple smaller
input functions, maximizes the gate count per PFU
while increasing system speed.

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Logic Cells

(continued)

The PFU is organized in a twin-quad fashion: two sets
of four LUTs and FFs that can be controlled indepen-
dently. Each PFU has two independent programmable
clocks, clock enables, local set/reset, and data selects
with one available per set of quad FFs.

LUTs may also be combined for use in arithmetic func-
tions using fast-carry chain logic in either 4-bit or 8-bit
modes. The carry-out of either mode may be registered
in the ninth FF for pipelining. Each PFU may also be
configured as a synchronous 32 x 4 single- or dual-port
RAM or ROM. The FFs (or latches) may obtain input
from LUT outputs or directly from invertible PFU inputs,
or they can be tied high or tied low. The FFs also have
programmable clock polarity, clock enables, and local
set/reset.

The LUTs can be programmed to operate in one of
three modes: combinatorial, ripple, or memory. In com-
binatorial mode, the LUTs can realize any 4-, 5-, or
6-input logic function and many multilevel logic func-
tions using ORCA's SWL connections. In ripple mode,
the high-speed carry logic is used for arithmetic func-
tions, comparator functions, or enhanced data path
functions. In memory mode, the LUTs can be used as a
32 x 4 synchronous RAM or ROM, in either single- or
dual-port mode.

The SLIC is connected from PLC routing resources
and from the outputs of the PFU. It contains eight
3-state, bidirectional buffers and logic to perform up to
a 10-bit AND function for decoding, or an AND-OR with
optional INVERT to perform PAL-like functions. The
3-state drivers in the SLIC and their direct connections
from the PFU outputs make fast, true 3-state buses
possible within the FPGA.

Programmable Function Unit

The PFUs are used for logic. Each PFU has 53 exter-
nal inputs and 20 outputs and can operate in several
modes. The functionality of the inputs and outputs
depends on the operating mode.

The PFU uses 36 data input lines for the LUTs, eight
data input lines for the latches/FFs, eight control inputs
(CLK[1:0], CE[1:0], LSR[1:0], SEL[1:0]), and a carry
input (CIN) for fast arithmetic functions and general-
purpose data input for the ninth FF. There are eight
combinatorial data outputs (one from each LUT), eight
latched/registered outputs (one from each latch/FF), a
carry-out (COUT), and a registered carry-out (REG-
COUT) that comes from the ninth FF. The carry-out sig-
nals are used principally for fast arithmetic functions.
There are also two dedicated F6 mode outputs which
are for the 6-input LUT function and 8-to-1 MUX.

Figure 2 and Figure 3 show high-level and detailed
views of the ports in the PFU, respectively. The eight
sets of LUT inputs are labeled as K0 through K7 with
each of the four inputs to each LUT having a suffix
of _x, where x is a number from 0 to 3.

There are four F5 inputs labeled A through D. These
are used for additional LUT inputs for 5- and 6-input
LUTs or as a selector for multiplexing two 4-input LUTs.
Four adjacent LUT4s can also be multiplexed together
with a 4-to-1 MUX to create a 6-input LUT. The eight
direct data inputs to the latches/FFs are labeled as
DIN[7:0]. Registered LUT outputs are shown as Q[7:0],
and combinatorial LUT outputs are labeled as F[7:0].

The PFU implements combinatorial logic in the LUTs
and sequential logic in the latches/FFs. The LUTs are
static random access memory (SRAM) and can be
used for read/write or ROM.

Each latch/FF can accept data from its associated LUT.
Alternatively, the latches/FFs can accept direct data
from DIN[7:0], eliminating the LUT delay if no combina-
torial function is needed. Additionally, the CIN input can
be used as a direct data source for the ninth FF. The
LUT outputs can bypass the latches/FFs, which
reduces the delay out of the PFU. It is possible to use
the LUTs and latches/FFs more or less independently,
allowing, for instance, a comparator function in the
LUTs simultaneously with a shift register in the FFs.

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Logic Cells

(continued)

5-9714(F)

Note: All multiplexers without select inputs are configuration selector multiplexers.

Figure 3. Simplified PFU Diagram

K3_0MUX

K7_0MUX

D0
D1
SD
SP
CK
LSR

REG7

RESET
SET

DIN7

DIN7MUX

D0
D1
SD
SP
CK
LSR

REG6

RESET
SET

DIN6

DIN6MUX

D0
D1
SD
SP
CK
LSR

REG5

RESET
SET

DIN5

DIN5MUX

D0
D1
SD
SP
CK
LSR

REG4

RESET
SET

DIN4

DIN4MUX

LUT647

A
B
C
D

FSDMUX

K7_2MUX

K6_0MUX

K6_2MUX

AMUX

H7H6MUX

FSCMUX

H5H4MUX

LUT6MUX

F5D

K7_0

K7_1
K7_2

K7_3
K6_0

K6_1
K6_2

K6_3

K5_0
K5_1
K5_2
K5_3

K4_0
K4_1
K4_2

F5C

K4_3

D0
D1
SD
SP
CK
LSR

REG3

RESET
SET

DIN3

DIN3MUX

D0
D1
SD
SP
CK
LSR

REG2

RESET

SET

DIN2

DIN2MUX

D0
D1
SD
SP
CK
LSR

REG1

RESET
SET

DIN1

DIN1MUX

D0
D1
SD
SP
CK
LSR

REG0

RESET
SET

DEL0
DEL1
DEL2

DIN0

DIN0MUX

LUT603

A
B
C
D

FSBMUX

K3_2MUX

K2_0MUX

K2_2MUX

BMUX

H3H2MUX

F5AMUX

H1H0MUX

LUT6MUX

F5B

K3_0

K3_1
K3_2

K3_3
K2_0

K2_1
K2_2

K2_3

K1_0
K1_1
K1_2
K1_3

K0_0
K0_1
K0_2

F5A

K0_3

CLK1

CLK1MUX

SEL1

SEL1MUX

CE1

CE1MUX

CE47MUX

LSR1

LSR1MUX

LSR47MUX

CIN

CLK0

CLK0MUX

SEL0

SEL0MUX

CE0

CE0MUX

CEBMUX

LSR0

LSR0MUX

CE03MUX

LSRBMUX

LSR03MUX

D0
SP
CK
LSR

REG8

RESET
SET

RECCOUT

COUT

SR1MODEATTR

SR1MODE

CE1_OVER_LSR1
LSR1_OVER_CE1
RSYNC1

SR0MODEATTR

SR0MODE

CE0_OVER_LSR0
LSR0_OVER_CE0
ASYNC0

REGMODE_TOP

FF
LATCH

REG 4 THROUGH 7

THIS IS ALWAYS A FLIPFLOP

REGMODE_BOT

FF
LATCH

REG 0 THROUGH 3

LOGIC
MLOGIC
RIPPLE
RAM
ROM

ENABLED
DISABLED

GSR

PFU MODES

CINMUX

DEL3

DEL0
DEL1
DEL2
DEL3

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Programmable Logic Cells

(continued)

Look-Up Table Operating Modes

The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For exam-
ple, in some operating modes, the DIN[7:0] inputs are direct data inputs to the PFU latches/FFs. In memory mode,
the same DIN[7:0] inputs are used as a 4-bit write data input bus and a 4-bit write address input bus
into LUT memory.

Table 3 lists the basic operating modes of the LUT. Figure 4--Figure 7 show block diagrams of the LUT operating
modes. The accompanying descriptions demonstrate each mode's use for generating logic.

Table 3. Look-Up Table Operating Modes

PFU Control Inputs

Each PFU has eight routable control inputs and an active-low, asynchronous global set/reset (GSRN) signal that
affects all latches and FFs in the device. The eight control inputs are CLK[1:0], LSR[1:0], CE[1:0], and SEL[1:0],
and their functionality for each logic mode of the PFU is shown in Table 4. The clock signal to the PFU is CLK, CE
stands for clock enable, which is its primary function. LSR is the local set/reset signal that can be configured as syn-
chronous or asynchronous. The selection of set or reset is made for each latch/FF and is not a function of the signal
itself. SEL is used to dynamically select between direct PFU input and LUT output data as the input to
the latches/FFs.

All of the control signals can be disabled and/or inverted via the configuration logic. A disabled clock enable
indicates that the clock is always enabled. A disabled LSR indicates that the latch/FF never sets/resets (except from
GSRN). A disabled SEL input indicates that DIN[7:0] PFU inputs or the LUT outputs are always input to the latches/
FFs.

Table 4. Control Input Functionality

Mode

Function

Logic

4-, 5-, and 6-input LUTs; softwired LUTs; latches/FFs with direct input or LUT input; CIN as direct
input to ninth FF or as pass through to COUT.

Half Logic/

Half Ripple

Upper four LUTs and latches/FFs in logic mode; lower four LUTs and latches/FFs in ripple mode;
CIN and ninth FF for logic or ripple functions.

Ripple

All LUTs combined to perform ripple-through data functions. Eight LUT registers available for
direct-in use or to register ripple output. Ninth FF dedicated to ripple out, if used. The submodes of
ripple mode are adder/subtractor, counter, multiplier, and comparator.

Memory

All LUTs and latches/FFs used to create a 32x4 synchronous dual-port RAM. Can be used as
single-port or as ROM.

Mode

CLK[1:0]

LSR[1:0]

CE[1:0]

SEL[1:0]

Logic

CLK to all latches/
FFs

LSR to all latches/FFs,
enabled per nibble and
for ninth FF

CE to all latches/FFs,
selectable per nibble
and for ninth FF

Select between LUT
input and direct input for
eight latches/FFs

Half Logic/

Half Ripple

CLK to all latches/
FFs

LSR to all latches/FF,
enabled per nibble and
for ninth FF

CE to all latches/FFs,
selectable per nibble
and for ninth FF

Select between LUT
input and direct input for
eight latches/FFs

Ripple

CLK to all latches/
FFs

LSR to all latches/FFs,
enabled per nibble and
for ninth FF

CE to all latches/FFs,
selectable per nibble
and for ninth FF

Select between LUT
input and direct input for
eight latches/FFs

Memory

(RAM)

CLK to RAM

LSR0 port enable 2

CE1 RAM write enable
CE0 Port enable 1

Not used

Memory

(ROM)

Optional for
synchronous outputs

Not used

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Logic Cells

(continued)

Logic Mode

The PFU diagram of Figure 3 represents the logic
mode of operation. In logic mode, the eight LUTs are
used individually or in flexible groups to implement user
logic functions. The latches/FFs may be used in con-
junction with the LUTs or separately with the direct
PFU data inputs. There are three basic submodes of
LUT operation in PFU logic mode: F4 mode, F5 mode,
and the F6 mode. Combinations of the submodes are
possible in each PFU.

F4 mode, shown simplified in Figure 4, illustrates the
uses of the basic 4-input LUTs in the PFU. The output
of an F4 LUT can be passed out of the PFU, captured
at the LUTs associated latch/FF, or multiplexed with the
adjacent F4 LUT output using one of the F5[A:D] inputs
to the PFU (not shown). Only adjacent LUT pairs (K

and K

, K

and K

, K

and K

, K

and K

) can be multi-

plexed, and the output always goes to the even-num-
bered output of the pair.

The F5 submode of the LUT operation, shown simpli-
fied in Figure 4, indicates the use of 5-input LUTs to
implement logic. 5-input LUTs are created from two
4-input LUTs and a multiplexer. The F5 LUT is the
same as the multiplexing of two F4 LUTs described
previously with the constraint that the inputs to both F4
LUTs be the same. The F5[A:D] input is then used as
the fifth LUT input. The equations for the two F4 LUTs
will differ by the assumed value for the F5[A:D] input,
one F4 LUT assuming that the F5[A:D] input is zero,
and the other assuming it is a one. The selection of the
appropriate F4 LUT output in the F5 MUX by the
F5[A:D] signal creates a 5-input LUT.

Two 6-input LUTs are created by shorting together the
inputs of four 4-input LUTs (K0:3 and K4:7) which are
multiplexed together. The F5 inputs of the adjacent F4
LUTs derive the fifth and sixth inputs of the F6 mode as
shown in Figure 5. The F6 outputs, LUT603 and
LUT647, are dedicated to the F6 mode or can be used
as the outputs of MUX8x1. MUX8x1 modes as shown
in Figure 7 are created by programming adjacent
4-input LUTs to 2x1 MUXs and multiplexing down to
create MUX8x1. Other functions can be implemented
from the configuration shown in Figure 5 where the four
LUT4s drive the 4x1 MUX in each half of the PFU if the
LUT4 inputs are not tied to the same inputs. Both F6
mode and MUX8x1 are available in the upper and
lower PFU nibbles.

Any combination of F4 and F5 LUTs is allowed per
PFU using the eight 16-bit LUTs. Examples are eight
F4 LUTs, four F5 LUTs, a combination of four F4 plus
two F5 LUTs, a combination of two F4, one F5, plus
one F6, or a combination of one F5, one MUX21 of two
LUT4s, and one MUX41 of four LUT4s.

5-9733(F)

Figure 4. Simplified F4 and F5 Logic Modes

K7_0
K7_1
K7_2

F5D

LUT4

2x1

MUX

K7_3

K6_0
K6_1
K6_2
K6_3

K5_0
K5_1
K5_2

F5C

LUT4

2x1

MUX

K5_3

K4_0
K4_1
K4_2
K4_3

K3_0
K3_1
K3_2

F5B

LUT4

2x1

MUX

K3_3

K2_0
K2_1
K2_2
K2_3

K1_0
K1_1
K1_2

F5A

LUT4

2x1

MUX

K1_3

K0_0
K0_1
K0_2
K0_3

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Logic Cells

(continued)

Half-Logic Mode

Series 4 FPGAs are based upon a twin-quad architec-
ture in the PFUs. The bytewide nature (eight LUTs,
eight latches/FFs) may just as easily be viewed as two
nibbles (two sets of four LUTs, four latches/FFs). The
two nibbles of the PFU are organized so that any nib-
blewide feature (excluding some softwired LUT topolo-
gies) can be swapped with any other nibblewide feature
in another PFU. This provides for very flexible use of
logic and for extremely flexible routing. The half-logic
mode of the PFU takes advantage of the twin-quad
architecture and allows half of a PFU, K

[7:4]

and associ-

ated latches/FFs, to be used in logic mode while the
other half of the PFU, K

[3:0]

and associated

latches/FFs, is used in ripple mode. In half-logic mode,
the ninth FF may be used as a general-purpose FF or
as a register in the ripple mode carry chain.

Ripple Mode

The PFU LUTs can be combined to do bytewide ripple
functions with high-speed carry logic. Each LUT has a
dedicated carry-out net to route the carry to/from any
adjacent LUT. Using the internal carry circuits, fast
arithmetic, counter, and comparison functions can be
implemented in one PFU. Similarly, each PFU has
carry-in (CIN, FCIN) and carry-out (COUT, FCOUT)
ports for fast-carry routing between adjacent PFUs.

The ripple mode is generally used in operations on two
data buses. A single PFU can support an 8-bit ripple
function. Data buses of 4 bits and less can use the
nibblewide ripple chain that is available in half-logic
mode. This nibblewide ripple chain is also useful for
longer ripple chains where the length modulo 8 is four
or less. For example, a 12-bit adder (12 modulo 8 = 4)
can be implemented in one PFU in ripple mode (8 bits)
and one PFU in half-logic mode (4 bits), freeing half of
a PFU for general logic mode functions.

Each LUT has two operands and a ripple (generally
carry) input, and provides a result and ripple (generally
carry) output. A single bit is rippled from the previous
LUT and is used as input into the current LUT. For LUT
K

, the ripple input is from the PFU CIN or FCIN port.

The CIN/FCIN data can come from either the fast-carry
routing (FCIN) or the PFU input (CIN), or it can be tied
to logic 1 or logic 0.

In the following discussions, the notations LUT K

and F[7:0]/F[3:0]

are used to denote the LUT that pro-

vides the carry-out and the data outputs for full PFU
ripple operation (K

, F[7:0]) and half-logic ripple

operation (K

, F[3:0]), respectively. The ripple mode

diagram (Figure 9) shows full PFU ripple operation,
with half-logic ripple connections shown as dashed
lines.

The result output and ripple output are calculated by
using generate/propagate circuitry. In ripple mode, the
two operands are input into K

[1] and K

[0] of each

LUT. The result bits, one per LUT, are F[7:0]/F[3:0]

(see

Figure 9). The ripple output from LUT K

can be

routed on dedicated carry circuitry into any of four adja-
cent PLCs, and it can be placed on the PFU COUT/
FCOUT outputs. This allows the PLCs to be cascaded
in the ripple mode so that nibblewide ripple functions
can be expanded easily to any length.

Result outputs and the carry-out may optionally be reg-
istered within the PFU. The capability to register the
ripple results, including the carry output, provides for
improved counter performance and simplified pipelin-
ing in arithmetic functions.

5-5755(F).

Figure 9. Ripple Mode

[1]

[0]

REGOUT

COUT

[1]

[0]

[1]

[0]

[1]

[0]

[1]

[0]

[1]

[0]

[1]

[0]

[1]

[0]

IN/FCIN

FCOUT

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Programmable Logic Cells

(continued)

The ripple mode can be used in one of four submodes.
The first of these is adder-subtractor submode. In
this submode, each LUT generates three separate out-
puts. One of the three outputs selects whether the
carry-in is to be propagated to the carry-out of the cur-
rent LUT or if the carry-out needs to be generated. If
the carry-out needs to be generated, this is provided by
the second LUT output. The result of this selection is
placed on the carry-out signal, which is connected to
the next LUT carry-in or the COUT/FCOUT signal, if it
is the last LUT (K

). Both of these outputs can be

any equation created from K

[1] and K

[0], but in this

case, they have been set to the propagate and gener-
ate functions.

The third LUT output creates the result bit for each LUT
output connected to F[7:0]/F[3:0]. If an adder/subtrac-
tor is needed, the control signal to select addition or
subtraction is input on F5A/F5C inputs. These inputs
generate the controller input AS. When AS = 0, this
function performs the adder, A + B. When AS = 1, the
function performs the subtractor, A B. The result bit is
created in one-half of the LUT from a single bit from
each input bus K

[1:0], along with the ripple input bit.

The second submode is the counter submode (see
Figure 10). The present count, which may be initialized
via the PFU DIN inputs to the latches/FFs, is supplied
to input K

[0], and then output F[7:0]/F[3:0] will either

be incremented by one for an up counter or decre-
mented by one for a down counter. If an up/down
counter is needed, the control signal to select the direc-
tion (up or down) is input on F5A and F5C. When
F5[A:C], respectively per nibble, is a logic 1, this indi-
cates a down counter and a logic 0 indicates an up
counter.

5-5756(F)

Figure 10. Counter Submode

[0]

REGCOUT

COUT

[0]

CIN/FCIN

FCOUT

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Logic Cells

(continued)

In the third submode, multiplier submode, a single
PFU can affect an 8x1 bit (4x1 for half-ripple mode)
multiply and sum with a partial product (see Figure 11).
The multiplier bit is input at F5[A:C], respectively per
nibble, and the multiplicand bits are input at K

[1],

where K

[1] is the most significant bit (MSB). K

[0] con-

tains the partial product (or other input to be summed)
from a previous stage. If F5[A:C] is logical 1, the multi-
plicand is added to the partial product. If F5[A:C] is log-
ical 0, 0 is added to the partial product, which is the
same as passing the partial product. CIN/FCIN can
bring the carry-in from the less significant PFUs if the
multiplicand is wider than 8 bits, and COUT/FCOUT
holds any carry-out from the multiplication, which may
then be used as part of the product or routed to another
PFU in multiplier mode for multiplicand width expan-
sion.

Ripple mode's fourth submode features equality
comparators. The functions that are explicitly available
are A

B, A

B, and A

B, where the value for A is

input on K

[0], and the value for B is input on K

[1]. A

value of 1 on the carry-out signals valid argument. For
example, a carry-out equal to 1 in AB submode indi-
cates that the value on K

[0] is greater than or equal to

the value on K

[1]. Conversely, the functions A

A + B, and A > B are available using the same functions
but with a 0 output expected. For example, A

B with a

0 output indicates A

B. Table 5 shows each function

and the output expected.

If larger than 8 bits, the carry-out signal can be cas-
caded using fast-carry logic to the carry-in of any adja-
cent PFU. The use of this submode could be shown
using Figure 9, except that the CIN/FCIN input for the
least significant PFU is controlled via configuration.

Table 5. Ripple Mode Equality Comparator

Functions and Outputs

5-5757(F)

Key: C = configuration data.
Note: F5[A:C] shorted together.

Figure 11. Multiplier Submode

Equality

Function

ORCA Foundry

Submode

True, if

Carry-Out Is:

A < B

A > B

A < B

A = B

K7[1]

K7[0]

F5[A:C]

K4[1]

K4[0]

K3[1]

K3[0]

K2[1]

K2[0]

K1[1]

K1[0]

K6[1]

K6[0]

K5[1]

K5[0]

K0[1]

K0[0]

COUT

REGCOUT

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Logic Cells

(continued)

The PFU memory mode uses all LUTs and latches/FFs
including the ninth FF in its implementation as shown in
Figure 12. The read address is input at the K

[3:0] and

F5[A:D] inputs where K

[0] is the LSB and F5[A:D] is

the MSB, and the write address is input on CIN (MSB)
and DIN[7, 5, 3, 1], with DIN[1] being the LSB. Write
data is input on DIN[6, 4, 2, 0], where DIN[6] is the
MSB, and read data is available combinatorially on
F[6, 4, 2, 0] and registered on Q[6, 4, 2, 0] with F[6] and
Q[6] being the MSB. The write enable controlling ports
are input on CE0, CE1, and LSR0. CE1 is the active-
high write enable (CE1 = 1, RAM is write enabled). The
first write port is enabled by CE0. The second write
port is enabled with LSR0. The PFU CLK (CLK0) signal
is used to synchronously write the data. The polarities
of the clock, write enable, and port enables are all pro-
grammable. Write-port enables may be disabled if they
are not to be used.

Data is written to the write data, write address, and
write enable registers on the active edge of the clock,
but data is not written into the RAM until the next clock
edge one-half cycle later. The read port is actually
asynchronous, providing the user with read data very
quickly after setting the read address, but timing is also
provided so that the read port may be treated as fully
synchronous for write then read applications. If the
read and write address lines are tied together (main-
taining MSB to MSB, etc.), then the dual-port RAM
operates as a synchronous single-port RAM. If the
write enable is disabled, and an initial memory contents
are provided at configuration time, the memory acts as
a ROM (the write data and write address ports and
write port enables are not used).

Wider memories can be created by operating two or
more memory mode PFUs in parallel, all with the same
address and control signals, but each with a different
nibble of data. To increase memory word depth above
32, two or more PLCs can be used. Figure 10 shows a
128 x 8 dual-port RAM that is implemented in eight
PLCs. This figure demonstrates data path width expan-
sion by placing two memories in parallel to achieve an
8-bit data path. Depth expansion is applied to achieve
128 words deep using the 32-word deep PFU memo-
ries. In addition to the PFU in each PLC, the SLIC
(described in the next section) in each PLC is used for
read address decodes and 3-state drivers. The 128 x 8
RAM shown could be made to operate as a single-port
RAM by tying (bit-for-bit) the read and write addresses.

To achieve depth expansion, one or two of the write
address bits (generally the MSBs) are routed to the
write port enables as in Figure 10. For 2 bits, the bits
select which 32-word bank of RAM of the four available
from a decode of two WPE inputs is to be written. Simi-
larly, 2 bits of the read address are decoded in the
SLIC and are used to control the 3-state buffers
through which the read data passes. The write data
bus is common, with separate nibbles for width expan-
sion, across all PLCs, and the read data bus is com-
mon (again, with separate nibbles) to all PLCs at the
output of the 3-state buffers.

Figure 13 also shows the capability to provide a read
enable for RAMs/ROMs using the SLIC cell. The read
enable will 3-state the read data bus when inactive,
allowing the write data and read data buses to be tied
together if desired.

Preliminary Data Sheet
December 2000

Lucent Technologies Inc.

ORCA Series 4 FPGAs

Programmable Logic Cells

(continued)

5-5749(F)

Figure 13. Memory Mode Expansion Example--128 x 8 RAM

RD[7:0]

WA[6:0]

RA[6:0]

CLK

WPE 1

WPE 2

WD[7:4]

PLC

WD[7:0]

WPE 1

WPE 2

RD[3:0]

WD[3:0]

PLC

RD[7:4]

WPE 1

WPE 2

WD[7:4]

PLC

WPE 1

WPE 2

RD[3:0]

WD[3:0]

PLC

RD[7:4]

Supplemental Logic and Interconnect Cell

Each PLC contains a SLIC embedded within the PLC
routing, outside of the PFU. As its name indicates, the
SLIC performs both logic and interconnect (routing)
functions. Its main features are 3-statable, bidirectional
buffers, and a PAL-like decoder capability. Figure 14
shows a diagram of a SLIC with all of its features
shown. All modes of the SLIC are not available at one
time.

The ten SLIC inputs can be sourced directly from the
PFU or from the general routing fabric. SI[0:9] inputs
can come from the horizontal or vertical routing, and
I[0:9} comes from the PFU outputs O[9:0]. These
inputs can also be tied to a logical 1 or 0 constant. The
inputs are twin-quad in nature and are segregated into
two groups of four nibbles and a third group of two
inputs for control. Each input nibble groups also have
3-state capability; however, the third pair does not.

There is one 3-state control (TRI) for each SLIC, with
the capability to invert or disable the 3-state control for
each group of four BIDIs. Separate 3-state control for
each nibblewide group is achievable by using the
SLICs decoder (DEC) output, driven by the group of

two BIDIs, to control the 3-state of one BIDI nibble
while using the TRI signal to control the 3-state of the
other BIDI nibble. Figure 15

shows the SLIC in buffer

mode with available 3-state control from the TRI and
DEC signals. If the entire SLIC is acting in a buffer
capacity, the DEC output may be used to generate a
constant logic 1 (V

) or logic 0 (V

) signal for general

use.

The SLIC may also be used to generate PAL-like AND-
OR with optional INVERT (AOI) functions or a decoder
of up to 10 bits. Each group of buffers can feed into an
AND gate (4-input AND for the nibble groups and
2-input AND for the other two buffers). These AND
gates then feed into a 3-input gate that can be config-
ured as either an AND gate or an OR gate. The output
of the 3-input gate is invertible and is output at the DEC
output of the SLIC. Figure 19 shows the SLIC in full
decoder mode.

The functionality of the SLIC is parsed by the two
nibblewide groups and the 2-bit buffer group. Each of
these groups may operate independently as BIDI buff-
ers (with or without 3-state capability for the nibblewide
groups) or as a PAL/decoder.

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Logic Cells

(continued)

As discussed in the Memory Mode section on page 19,
if the SLIC is placed into one of the modes where it
contains both buffers and a decode or AOI function
(e.g., BUF_BUF_DEC mode), the DEC output can be
gated with the 3-state input signal. This allows up to a
6-input decode (e.g., BUF_DEC_DEC mode) plus the
3-state input to control the enable/disable of up to four
buffers per SLIC. Figure 15--Figure 19 show several
configurations of the SLIC, while Table 6 shows all of
the possible modes.

Table 6. SLIC Modes

5-5744(F).a.

Figure 14. SLIC All Modes Diagram

Mode

No.

Mode

BUF

[3:0]

BUF

[7:4]

BUF

[9:8]

BUFFER

Buffer

BUF_BUF_DEC

Buffer

Decoder

BUF_DEC_BUF

Buffer

Decoder

Buffer

BUF_DEC_DEC

Buffer

Decoder Decoder

DEC_BUF_BUF Decoder

Buffer

DEC_BUF_DEC Decoder

Buffer

Decoder

DEC_DEC_BUF Decoder Decoder

Buffer

DECODER

Decoder Decoder Decoder

SIN9

SOUT09

DEC

0/1

TRI

0/1

SOUT08

SOUT07

SOUT06

SOUT05

SOUT04

SOUT03

SOUT02

SOUT01

SOUT00

LOGIC 1 OR 0

SIN8

LOGIC 1 OR 0

SIN7

LOGIC 1 OR 0

SIN6

LOGIC 1 OR 0

SIN5

LOGIC 1 OR 0

SIN4

LOGIC 1 OR 0

SIN3

LOGIC 1 OR 0

SIN2

LOGIC 1 OR 0

SIN1

LOGIC 1 OR 0

SIN0

LOGIC 1 OR 0

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Programmable Logic Cells

(continued)

5-5748(F)

Figure 19. Decoder Mode

PLC Latches/Flip-Flops

The eight general-purpose latches/FFs in the PFU can
be used in a variety of configurations. In some cases,
the configuration options apply to all eight latches/FFs
in the PFU and some apply to the latches/FFs on a nib-
blewide basis where the ninth FF is considered inde-
pendently. For other options, each latch/FF is
independently programmable. In addition, the ninth FF
can be used for a variety of functions.

Table 7 summarizes these latch/FF options. The
latches/FFs can be configured as either positive- or
negative-level sensitive latches, or positive or negative
edge-triggered FFs (the ninth register can only be a
FF). All latches/FFs in a given nibble of a PFU share
the same clock, and the clock to these latches/FFs can
be inverted. The input into each latch/FF is from either
the corresponding LUT output (F[7:0]) or the direct data
input (DIN[7:0]). The latch/FF input can also be tied to
logic 1 or to logic 0, which is the default.

Table 7. Configuration RAM Controlled Latch/

Flip-Flop Operation

* Not available for FF[8].

Each PFU has two independent programmable clocks,
clock enable CE[1:0], local set/reset LSR[1:0], and
front-end data selects SEL[1:0]. When CE is disabled,
each latch/FF retains its previous value when clocked.
The clock enable, LSR, and SEL inputs can be inverted
to be active-low.

DEC

SIN7

LOGIC 1 OR 0

SIN6

LOGIC 1 OR 0

SIN5

LOGIC 1 OR 0

SIN4

LOGIC 1 OR 0

SIN9

LOGIC 1 OR 0

SIN8

LOGIC 1 OR 0

SIN3

LOGIC 1 OR 0

SIN1

LOGIC 1 OR 0

SIN2

LOGIC 1 OR 0

SIN0

LOGIC 1 OR 0

Function Options

Common to All Latches/FFs in PFU

Enable GSRN

GSRN enabled or has no effect on
PFU latches/FFs.

Set Individually in Each Latch/FF in PFU

Set/Reset Mode

Set or reset.

By Group (Latch/FF[3:0], Latch/FF[7:4], and FF[8])

Clock Enable

CE or none.

LSR Control

LSR or none.

Clock Polarity

Noninverted or inverted.

Latch/FF Mode

Latch or FF.

LSR Operation

Asynchronous or synchronous.

Front-end Select* Direct (DIN[7:0]) or from LUT

(F[7:0]).

LSR Priority

Either LSR or CE has priority.

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Logic Cells

(continued)

The set/reset operation of the latch/FF is controlled by
two parameters: reset mode and set/reset value. When
the GSRN and local set/reset (LSR) signals are not
asserted, the latch/FF operates normally. The reset
mode is used to select a synchronous or asynchronous
LSR operation. If synchronous, LSR has the option to
be enabled only if clock enable (CE) is active or for LSR
to have priority over the clock enable input, thereby set-
ting/resetting the FF independent of the state of the
clock enable. The clock enable is supported on FFs,
not latches. It is implemented by using a 2-input multi-
plexer on the FF input, with one input being the previ-
ous state of the FF and the other input being the new
data applied to the FF. The select of this 2-input multi-
plexer is clock enable (CE), which selects either the
new data or the previous state. When the clock enable
is inactive, the FF output does not change when the
clock edge arrives.

The GSRN signal is only asynchronous, and it sets/
resets all latches/FFs in the FPGA based upon the set/
reset configuration bit for each latch/FF. The set/reset
value determines whether GSRN and LSR are set or
reset inputs. The set/reset value is independent for
each latch/FF. An option is available to disable the
GSRN function per PFU after initial device configura-
tion.

The latch/FF can be configured to have a data front-
end select. Two data inputs are possible in the front-
end select mode, with the SEL signal used to select
which data input is used. The data input into each
latch/FF is from the output of its associated LUT,

F[7:0], or direct from DIN[7:0], bypassing the LUT. In
the front-end data select mode, both signals are avail-
able to the latches/FFs.

If either or both of these inputs is unused or is unavail-
able, the latch/FF data input can be tied to a logic 0 or
logic 1 instead (the default is logic 0).

The latches/FFs can be configured in three basic
modes:

Local synchronous set/reset: the input into the PFU's
LSR port is used to synchronously set or reset each
latch/FF.

Local asynchronous set/reset: the input into LSR
asynchronously sets or resets each latch/FF.

Latch/FF with front-end select, LSR either synchro-
nous or asynchronous: the data select signal selects
the input into the latches/FFs between the LUT out-
put and direct data in.

For all three modes, each latch/FF can be indepen-
dently programmed as either set or reset. Figure 20
provides the logic functionality of the front-end select,
global set/reset, and local set/reset operations.

The ninth PFU FF, which is generally associated with
registering the carry-out signal in ripple mode func-
tions, can be used as a general-purpose FF. It is only
an FF and is not capable of being configured as a latch.
Because the ninth FF is not associated with an LUT,
there is no front-end data select. The data input to the
ninth FF is limited to the CIN input, logic 1, logic 0, or
the carry-out in ripple and half-logic modes.

5-9737(F).a

Key: CD = configuration data.

Figure 20. Latch/FF Set/Reset Configurations

S_SET

S_RESET

CLK

SET RESET

DIN

LOGIC 1
LOGIC 0

LSR

GSRN

CLK

SET RESET

DIN

LOGIC 1
LOGIC 0

GSRN

LSR

CLK

SET RESET

DIN

LOGIC 1
LOGIC 0

GSRN

LSR

DIN

SEL

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Embedded Block RAM

The ORCA Series 4 devices complement the distrib-
uted PFU RAM with large blocks of memory macro-
cells. The memory is available in 512 words by 18 bits/
word blocks with two write and two read ports. Two byte
lane enables also operate with quad-port functionality.
Additional logic has been incorporated for FIFO, multi-
plier, and CAM implementations. The RAM blocks are
organized along the PLC rows and are added in pro-
portion to the FPGA array sizes as shown in Table 8.
The contents of the RAM blocks may be optionally ini-
tialized during FPGA configuration.

Table 8. ORCA Series 4-- Available Embedded

Block RAM

Each highly flexible 512 x 18 (quad-port, two read/two
write) RAM block can be programmed by the user to
meet their particular function. Each of the EBR configu-
rations use the physical signals as shown in
Table 9. Quad-port addressing permits simultaneous
read and write operations.

The EBR ports are written synchronously on the posi-
tive edge of CKW. Synchronous read operations use
the positive edge of CKR. Options are available to use
synchronous read address registers and read output
registers, or to bypass these registers and have the
RAM read operate asynchronously.

EBR Features

Quad-Port Modes (Two Read/Two Write)

512 x 18 with optional built-in arbitration between
write ports.

1024 x 18 built on two blocks with built-in decode
logic for simplified implementation and increased
speed.

Dual-Port Modes (One Read/One Write)

One 256 x 36.

One 1K x 9.

Two 512 x 9 built in one EBR with two separate read,
write clocks and enables for independent operation.

Two RAMs with a user customized number of words
whose sum is 512 (or less) by 18.

The joining of RAM blocks is supported to create wider
and deeper memories. The adjacent routing interface
provided by the CIBs allow the cascading of blocks
together with minimal penalties due to routing delays.

FIFO Modes

FIFOs can be configured to 256, 512, or 1K depths and
36, 18, or 9 widths respectively or two-512 x 9 but also
can be expanded using multiple blocks. FIFO works
synchronously with the same read and write clock
where the read port can be registered on the output or
not registered. It can also be optionally configured
asynchronously with different read and write clocks.

Integrated flags allow the user the ability to fully utilize
the EBR for FIFO, without the need to dedicate an
address for providing distinct full/empty status. There
are four programmable flags provided for each FIFO:
Empty, partially empty, full, and partially full FIFO sta-
tus. The partially empty and partially full flags are pro-
grammable with the flexibility to program the flags to
any value from the full or empty threshold. The pro-
grammed values can be set to a fixed value through the
bit stream, or a dynamic value can be controlled by
input pins of the EBR FIFO.

Multiplier Modes

The ORCA EBR supports two variations of multiplier
functions. Constant coefficient MULTIPLY [KCM] mode
will produce a 24-bit output of a fixed 8-bit constant
multiply of a 16-bit number or a fixed 16-bit constant
multiply of an 8-bit number. This KCM multiplies a con-
stant times a 16- or 8-bit number and produces a prod-
uct as a 24-bit result. The coefficient and multiplication
tables are stored in memory. Both the input and outputs
can be configured to be registered for pipelining. Both
write ports are available during MULTIPLY mode so
that the user logic can update and modify the coeffi-
cients for dynamic coefficient updates.

An 8 x 8 MULTIPLY mode is configurable to either a
pipelined or combinatorial multiplier function of two
8-bit numbers. Two 8-bit operands are multiplied to
yield a 16-bit product. The input and outputs can be
registered in pipeline mode.

Device

Number of

Blocks

Number of

EBR Bits

OR4E2

74K

OR4E4

111K

OR4E6

148K

OR4E10

185K

OR4E14

222K

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Embedded Block RAM

(continued)

CAM Mode

The CAM block is a content address memory that pro-
vides fast address searches by receiving data input
and returning addresses that contain the data. Imple-
mented in each EBR are two 16-word x 8-bit CAM
function blocks.

The CAM has three modes: single match, multiple
match, and clear, which are all achieved in one clock
cycle. In single-match mode, an 8-bit data input is inter-
nally decoded and reports a match when data is
present in a particular RAM address. Its result is
reported by a corresponding single address bit. In mul-
tiple match, the same occurs with the exception of mul-
tiple address lines report the match. Clear mode is
used to clear the CAM contents in one clock cycle by
erasing all locations.)

Arbitration logic is optionally programmed by the user
to signal occurrences of data collisions as well as to
block both ports from writing at the same time. The
arbitration logic prioritizes PORT1. When utilizing the
arbiter, the signal BUSY indicates data is being written
to PORT1. This BUSY output signals PORT1 activity by
driving a high output. The arbitration default is enabled;
however, the user may disable the arbiter in configura-
tion. If the arbiter is turned off, both ports could be writ-
ten at the same time and the data would be corrupt. In
this scenario, the BUSY signal will indicate a possible
error.

There is also a user option which dedicates PORT 1 to
communications to the system bus. In this mode, the
user logic only has access to PORT0 and arbitration
logic is enabled. The system bus utilizes the priority
given to it by the arbiter; therefore, the system bus will
always be able to write to the EBR.

Table 9. RAM Signals

Port Signals

I/O

Function

PORT 0

AR0[#:0]

Address to be read.

AW0[#:0]

Address to be written.

BW0<1:0>

Byte-write enable.
Byte = 8 bits + parity bit.
<1> = bits[17, 15:9] <0> = bits[16, 7:0]

CKR0

Positive-edge asynchronous read clock.

CKW0

Positive-edge synchronous write clock.

CSR0

Enables read to output. Active-high.

CSW0

Enables write to occur. Active-high.

D [#:0]

Input data to be written to RAM.

Q [#:0]

Output data of memory contents at referenced address.

PORT 1

AR1[#:0]

Address to be read.

AW1[#:0]

Address to be written.

BW1<1:0>

Byte-write enable.
Byte = 8 bits + parity bit.
<1> = bits[17, 15:9] <0> = bits[16, 7:0]

CKR1

Positive-edge asynchronous read clock.

CKW1

Positive-edge synchronous write clock.

CSR1

Enables read to output. Active-high.

CSW1

Enables write to occur. Active-high.

D [#:0]

Input data to be written to RAM.

Q [#:0]

Output data of memory contents at referenced address.

Control

BUSY

PORT1 writing. Active-high.

RESET

Data output registers cleared. Memory contents unaffected. Active-low.

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Embedded Block RAM

(continued)

Table 11. Constant Multiplier Signals

Table 12. 8 x 8 Multiplier Signals

Table 13. CAM Signals

Port Signals

I/O

Function

AR0[15:0]

Data input--operand.

AW(1:0)[8:0]

Address bits.

D(1:0)[17:0]

Data inputs to load memory or change coefficient.

CKW[0:1]

Positive-edge write port clock.

CKR[0:1]

Positive-edge read port clock. Used for synchronous multiply mode.

CSW[1:0]

Active-high write enable.

CSR[1:0]

Active-high read enable.

Q[23:0]

Data outputs--product result.

Port Signals

I/O

Function

AR0[7:0]

Data input--multiplicand.

AR1[7:0]

Data input--multiplier.

AW(1:0)[8:0]

Address bits for memory.

D(1:0)[17:0]

Data inputs to load memory.

CKW[0:1]

Positive-edge write port clock.

CKR[0:1]

Positive-edge read port clock. Used for synchronous multiply mode.

CSW[1:0]

Active-high write enable.

CSR[1:0]

Active-high enables. For enabling address registers.

BW(1:0)[1:0]

Byte-lane write for loading memory.

Q[15:0]

Data outputs--product.

Port Signals

I/O

Function

AR(1:0)[7:0]

Data match.

AW(1:0)[8:0]

Data write.

D(1:0)[17]

Clear data active-high.

D(1:0)[16]

Single match active-high.

D(1:0)[3:0]

CAM address for data write.

CSW[1:0]

Active-high write enable. Enable for CAM data write.

CSR[1:0]

Active-high enable data registers. Enable for CAM data registers.

Q(1:0)15:0]

Decoded data outputs. 1 corresponds to a data match at that address location.

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Routing Resources

The abundant routing resources of the Series 4 archi-
tecture are organized to route signals individually or as
buses with related control signals. Both local and global
signals utilize high-speed buffered and nonbuffered
routes. One PLC segmented (x1), six PLC segmented
(x6), and bused half-chip (xHL) routes are patterned
together to provide high connectivity with fast software
routing times and high-speed system performance.

x1 routes cross width of one PLC and provide local
connectivity to PFU and SLIC inputs and outputs. x6
lines cross width of six PLCs and are unidirectional and
buffered with taps in the middle and on the end. Seg-
ments allow connectivity to PFU/SLIC outputs (driven
at one endpoint), other x6 lines (at endpoints), and
x1 lines for access to PFU/SLIC inputs. xH lines run
vertically and horizontally the distance of half the
device and are useful for driving medium-/long-dis-
tance 3-state routing.

The improved routing resources offer great flexibility in
moving signals to and from the logic core. This flexibil-
ity translates into an improved capability to route
designs at the required speeds even when the I/O sig-
nals have been locked to specific pins.

Generally, the ORCA Foundry Development System is
used to automatically route interconnections. Interac-
tive routing with the ORCA Foundry design editor
(EPIC) is also available for design optimization.

The routing resources consist of switching circuitry and
metal interconnect segments. Generally, the metal lines
which carry the signals are designated as routing seg-
ments. The switching circuitry connects the routing
segments, providing one or more of three basic func-
tions: signal switching, amplification, and isolation. A
net running from a PFU or PIO output (source) to a
PLC or PIO input (destination) consists of one or more
routing segments, connected by switching circuitry
called configurable interconnect points (CIPs).

Clock Distribution Network

Primary Clock Nets

The Series 4 FPGAs provide eight fully distributed glo-
bal primary net routing resources. These eight primary
nets can only drive clock signals. The scheme dedi-
cates four of the eight resources to provide fast primary
nets and four are available for general primary nets.
The fast primary nets are targeted toward low-skew
and small injection times while the general primary
nets are also targeted toward low-skew but have more
source location flexibility. Fast access to the global pri-
mary nets can be sourced from two pairs of pads

located in the center of each side of the device, from
the programmable PLLs, and dedicated network PLLs
located in the corners, or from PLC logic. The I/O pads
are dedicated in pairs for use of differential I/O clocking
or single-ended I/O clock sources. However, if these
pads are not needed to source the clock network, they
can be utilized for general I/O. The clock routing
scheme is patterned using vertical and horizontal
routes which provide connectivity to all PLC columns.

Secondary Clock and Control Nets

Secondary spines provide flexible clocking and control
signaling for local regions. Secondary nets usually
have high fan-outs. The Series 4 utilizes a spine and
branches that use additional x6 segments. This strat-
egy provides a flexible connectivity and routes can be
sourced from any I/O pin, all PLLs, or from PLC logic.

Edge Clock Nets

Routes are distributed around the edges and are avail-
able for every four PIOs (one per PIC). All PIOs and
PLLs can drive the edge clocks and are used in con-
junction with the secondary spines discussed above to
drive the same edge clock signal into the internal logic
array. The edge clocks provide fast injection to the PLC
array and I/O registers. Many edge clock nets are pro-
vided on each side of the device.

Programmable Input/Output Cells

Programmable I/O

The Series 4 PIO addresses the demand for the flexi-
bility to select I/O that meets system interface require-
ments. I/Os can be programmed in the same manner
as in previous ORCA devices with the addition of new
features that allow the user the flexibility to select new
I/O types that support high-speed interfaces.

Each PIC contains up to four programmable I/O pads
and are interfaced through a common interface block to
the FPGA array. The PIO group is split into two pairs of
I/O pads with each pair having independent clock
enables, local set/reset, and global set/reset.

On the input side, each PIO contains a programmable
latch/FF which enables very fast latching of data from
any pad. The combination provides for very low setup
requirements and zero hold times for signals coming
on-chip. It may also be used to demultiplex an input sig-
nal, such as a multiplexed address/data signal, and
register the signals without explicitly building a demulti-
plexer with a PFU.

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Input/Output Cells

(continued)

On the output side of each PIO, an output from the PLC
array can be routed to each output FF, and logic can be
associated with each I/O pad. The output logic associ-
ated with each pad allows for multiplexing of output sig-
nals and other functions of two output signals.

The output FF, in combination with output signal multi-
plexing, is particularly useful for registering address
signals to be multiplexed with data, allowing a full clock
cycle for the data to propagate to the output. The out-
put buffer signal can be inverted, and the 3-state con-
trol can be made active-high, active-low, or always
enabled. In addition, this 3-state signal can be regis-
tered or nonregistered.

The Series 4 I/O logic has been enhanced to include
modes for speed uplink and downlink capabilities.
These modes are supported through shift register logic
which divides down incoming data rates or multiplies
up outgoing data rates. This new logic block also sup-
ports high-speed DDR mode requirements where data
is clocked into and out of the I/O buffers on both edges
of the clock.

The new programmable I/O cell allows designers to
select I/Os that meet many new communication stan-
dards permitting the device to hook up directly without
any external interface translation. They support tradi-
tional FPGA standards as well as high-speed single-
ended and differential pair signaling (as shown in
Table 14). Based on a programmable, bank-oriented
I/O ring architecture, designs can be implemented
using 3.3 V, 2.5 V, 1.8 V, and 1.5 V output levels.

Table 14. Series 4 Programmable I/O Standards

Note: Interfaces to DDR and ZBT memories are supported through the interface standards shown above.

Standard

DDIO

(V) V

REF

(V)

Interface Usage

LVTTL

3.3

General purpose.

LVCMOS2

2.5

LVCMOS1.8

1.8 NA

PCI

3.3

PCI.

LVDS

2.5

Point to point and multidrop backplanes, high noise immunity.

Bused-LVDS

2.5

Network backplanes, high noise immunity, bus architecture
backplanes.

LVPECL

2.5

Network backplanes, differential 100 MHz+ clocking, optical
transceiver, high-speed networking.

PECL

3.3

2.0

Backplanes.

GTL

3.3

0.8

Backplane or processor interface.

GTL+

3.3

1.0

HSTL-Class I

1.5

0.75

High-speed SRAM and networking interfaces.

HTSL-Class III and IV

1.5

0.9

STTL3-Class I and II

3.3

1.5

Synchronous DRAM interface.

SSTL2-Class I and II

2.5

1.25

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Programmable Input/Output Cells

(continued)

The PIOs are located along the perimeter of the device.
The PIO name is represented by a two-letter designa-
tion to indicate on which side of the device it is located
followed by a number to indicate in which row or column
it is located. The first letter, P, designates that the cell is
a PIO and not a PLC. The second letter indicates the
side of the array where the PIO is located. The four
sides are left (L), right (R), top (T), and bottom (B). The
individual I/O pad is indicated by a single letter (either
A, B, C, or D) placed at the end of the PIO name. As an
example, PL10A indicates a pad located on the left side
of the array in the tenth row.

Each PIC interfaces to four bond pads and contains the
necessary routing resources to provide an interface
between I/O pads and the PLCs. Each PIC is com-
posed of four programmable I/Os and significant routing
resources. Each PIC contains input buffers, output buff-
ers, routing resources, latches/FFs, and logic and can
be configured as an input, output, or bidirectional
I/O. Any PIO is capable of supporting the I/O standard
listed in Table 12 and supporting DDR and ZBT specifi-
cations.

The I/O on the OR4Exxx Series devices allows compli-
ance with PCI Local Bus (Rev. 2.2) 3.3 V signaling
environments. The signaling environment used for
each input buffer can be selected on a per-pin basis.
The selection provides the appropriate I/O clamping
diodes for PCI compliance.

The CIBs that bound the PIOs have significant local
routing resources, similar to routing in the PLCs. This
new routing increases the ability to fix user pinouts
prior to placement and routing of a design and still
maintain routability. The flexibility provided by the rout-
ing also provides for increased signal speed due to a
greater variety of optimal signal paths.

Included in the PIO routing interface is a fast path from
the input pins to the PFU logic. This feature allows for
input signals to be very quickly processed by the SLIC
decoder function and used on-chip or sent back off of
the FPGA. Also, the Series 4 PIOs include latches and
FFs and options for using fast, dedicated secondary,
and edge clocks.

A diagram of a single PIO is shown in Figure 22, and
Table 15 provides an overview of the programmable
functions in an I/O cell.

5-9732(F)

Figure 22. Series 4 PIO Image from ORCA Foundry

OUTSH

OUTDDMUX

OUTDD

OUTFFMUX

OUTFF

CLK4MUX

LSRMUX

LSR

GSR

ENABLED

DISABLED

SRMODE

CE_OVER_LSR

LSR_OVER_CE

ASYNC

CEMUX0

OUTDD

CLK

OUTSH

CLK

OUTDD

OUTREG

LSR

AND

NAND

NOR

XOR

XNOR

PLOGIC

PMUX

OUTSHMUX

BUFMODE

SLEW

FAST

LEVELMODE

PCI

SSTL2

SSTL3

HSTL1

HSTL3

GTL

GTLPLUS

PECL

LVPECL

LVDS

P2MUX

OUTDD

TSMUX

USRTS

TSREG

LSR

RESET
SET

PULLMODE

DOWN
NONE

INMUX

CEMUXI

NORMAL

INVERTED

LATCHFF

LSR

LATCHFF
LATCH
FF

INDDMUX

INDD

INCK

INFF

RESET
SET

DELAY

IOPAD

OUTMUX

CELL

LVCMOS2

LVCMOS18

DEL0
DEL1
DEL2
DEL3

MILLIAMPS

SIX

TWELVE

TWENTYFOUR

RESISTOR

OFF

KEEPERMODE

OFF

LATCH
FF

OUTPUT SIDE

INPUT SIDE

LVTTL

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Input/Output Cells

(continued)

Inputs

There are many major options on the PIO inputs that
can be selected in the ORCA Foundry tools listed in
Table 15. Inputs may have a pull-up or pull-down resis-
tor selected on an input for signal stabilization and
power management. A weak keeper circuit is also
available on inputs. Input signals in a PIO are passed to
CIB routing and/or a fast route into the clock routing
system.

There is also a programmable delay available on the
input. When enabled, this delay affects the INFF and
INDD signals of each PIO, but not the clock input. The
delay allows any signal to have a guaranteed zero hold
time when input. This feature is discussed subse-
quently.

Inputs should have transition times of less than 500 ns
and should not be left floating. If any pin is not used, it
is 3-stated with an internal pull-up resistor enabled
automatically after configuration.

Floating inputs increase power consumption, produce
oscillations, and increase system noise. The inputs
have a typical hysteresis of approximately 250 mV to
reduce sensitivity to input noise. The PIC contains
input circuitry that provides protection against latch-up
and electrostatic discharge.

The other features of the PIO inputs relate to the latch/
FF structure in the input path. In latch mode, the input
signal is fed to a latch that is clocked by either the pri-
mary, secondary, or edge clock signal. The clock may
be inverted or noninverted. There is also a local set/
reset signal to the latch. The senses of these signals
are also programmable and have the capability to
enable or disable the global set/reset signal and select
the set/reset priority. The same control signals may

also be used to control the input latch/FF when it is
configured as a FF instead of a latch, with the addition
of another control signal used as a clock enable. The
PIOs are paired together and have independent CE,
set/reset, and GSRN control signals for the pair. Note
that these control signals are paired to the same pair of
pins used for differential signaling.

The input path is also capable of accepting data from
any pad using a fast capture feature. This feature can
be programmed as a latch or FF referenced to any
clock. There are two options for zero-hold input capture
in the PIO. If input delay mode is selected to delay the
signal from the input pin, data can be either registered
or latched with guaranteed zero-hold time in the PIO
using a system clock. To further improve setup time,
the fast zero-hold mode of the PIO input takes advan-
tage of the latch/FF combination and sources the input
FF data from a dedicated latch that is clocked by a fast
edge clock

from the dedicated clock pads or any local

pad. The input FF is then driven by a primary clock
sourced from a dedicated input pin designed for fast,
low-skew operation at the I/Os. These dedicated pads
are located in pairs in the center of each side of the
array and if not utilized by the clock spine can be used
as general user I/O. The clock inputs to both the dedi-
cated fast capture latch and the input FF can also be
driven by the on-chip PLLs.

The combination of input register capability provides for
input signal demultiplexing without any additional
resources such as for address and data arriving on the
same pins. On the positive edge of the clock, the data
would come from the pad to latch. The PIO input signal
is sent to both the input latch and directly to INDD. The
signal is latched on the falling edge of the clock and
output to routing at INFF. The address and data are
then both available at the rising edge of the clock.
These signals may be registered or otherwise pro-
cessed in the PLCs.

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Programmable Input/Output Cells

(continued)

Table 15. PIO Options

Outputs

The PIO's output drivers for TTL/CMOS outputs have
programmable drive capability and slew rates. Two
propagation delays (fast, slewlim) are available on out-
put drivers. There are three combinations of program-
mable drive currents (24 mA sink/12 mA source, 12 mA
sink/6 mA, and 6 mA sink/3 mA source). At powerup,
the output drivers are in slewlim mode and
12 mA sink/6 mA source. If an output is not to be driven
in the selected configuration mode, it is 3-stated.

The output buffer signal can be inverted, and the
3-state control signal can be made active-high, active-
low, or always enabled. In addition, this 3-state signal
can be registered or nonregistered. Additionally, there

is a fast, open-drain output option that directly connects
the output signal to the 3-state control, allowing the out-
put buffer to either drive to a logic 0 or 3-state, but
never to drive to a logic 1.

The PIO has both input and output shift register capa-
bilities. This ability allows the data rate to be reduced
from the pad or increased to the pad by two or four
times. The shift register block (SRB) is available in
groups of four PIO. Both the input and output shift reg-
isters are controlled by the same clock and can operate
at the same time at the same speed as long as the
SRB is not connected to the same pads.The output
control signals are similar to the input control signals in
that they are per pair of PIOs.

Bus Hold

Each PIO can be programmed with a KEEPERMODE
feature. This element is user programmed for bus hold
requirements. This mode retains the last known state of
a bus when the bus goes into 3-state. It prevents float-
ing buses and saves system power.

PIO Register Control Signals

The PIO latches/FFs have various clock, clock enable
(CE), local set/reset (LSR), and GSRN controls. Table
16 provides a summary of these control signals and
their effect on the PIO latches/FFs. Note that all control
signals are optionally invertible. The output control sig-
nals are similar to the input control signals in that they
are per pair of PIOs.

Table 16. PIO Register Control Signals

Input

Option

Input Level

LVTTL, LVCMOS 2,
LVCMOS 1.8, 3.3 V PCI Compliant.

Input Speed

Fast, Delayed.

Float Value

Pull-up, Pull-down, None.

Latch, FF, Fast Zero Hold FF, None
(direct input).

Clock Sense

Inverted, Noninverted.

Input Selection

Input 1, Input 2, Clock Input.

Keeper Mode

On, Off.

LVDS Resistor

On, Off.

Output

Option

Output Drive

Current

12 mA/6 mA or 6 mA/3 mA
24 mA/12 mA.

Output Function Normal, Fast Open Drain.

Output Speed

Fast, Slew.

Output Source

FF Direct-out, General Routing.

Output Sense

Active-high, Active-low.

3-State Sense

Active-high, Active-low (3-state).

FF Clocking

Edge Clock, System Clock.

Clock Sense

Inverted, Noninverted.

Logic Options

See Table 17.

I/O Controls

Option

Clock Enable

Active-high, Active-low, Always
Enabled.

Set/Reset Level

Active-high, Active-low, No Local
Reset.

Set/Reset Type

Synchronous, Asynchronous.

Set/Reset Priority CE over LSR, LSR over CE.

GSR Control

Enable GSR, Disable GSR.

Control Signal

Effect/Functionality

Edge Clock

(ECLK)

Clocks input fast-capture latch;
optionally clocks output FF, or
3-state FF.

System Clock

(SCLK)

Clocks input latch/FF; optionally
clocks output FF, or 3-state FF.

Clock Enable

(CE)

Optionally enables/disables input FF
(not available for input latch mode);
optionally enables/disables output
FF; separate CE inversion capability
for input and output.

Local Set/Reset

(LSR)

Option to disable; affects input latch/
FF, output FF, and 3-state FF if
enabled.

Global Set/Reset

(GSRN)

Option to enable or disable per PIO
(the input FF, output FF, and
3-state FF) after initial configuration.

Set/Reset Mode The input latch/FF, output FF, and

3-state FF are individually set or
reset by both the LSR and GSRN
inputs.

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Input/Output Cells

(continued)

The PIO output FF can perform output data multiplex-
ing with no PLC resources required. This type of
scheme is necessary for DDR applications which
require data clocking out of the I/O on both edges of
the clock. In this scheme, the output of OUTFF and
OUTDD are serialized and shifted out on both the posi-
tive and negative edges of the clock using the shift reg-
isters.

The PIC logic block can also generate logic functions
based on the signals on the OUTDD and CLK ports of
the PIO. The functions are AND, NAND, OR, NOR,
XOR, and XNOR. Table 17 is provided as a summary
of the PIO logic options.

Table 17. PIO Logic Options

Flexible I/O features allow the user to select I/O to meet
different high-speed interface requirements. These I/Os
require different input references or supply voltages.
The perimeter of the device is divided into groups of
PIOs or buffer banks. For each bank, there is a sepa-
rate V

IO. Every device is equally broken up into eight

I/O banks. The V

IO supplies the correct output volt-

age for a particular standard. The user must supply the
appropriate power supply to the V

IO pin. Within a

bank, several I/O standards may be mixed as long as
they use a common V

IO. Also, some interface stan-

dards require a specified threshold voltage known as
V

REF

. In these modes, where a particular V

REF

required, the device is automatically programmed to
dedicate a pin for the appropriate V

REF

which must be

supplied by the user. The V

REF

is dedicated exclusively

to the bank and cannot be intermixed with other signal-
ing requiring other V

REF

voltages. However, pins not

requiring V

REF

can be mixed in the bank. The V

REF

pad

is then no longer available to the user for general use.
See Table 14 for a list of the I/O standards supported.

Table 18. Compatible Mixed I/O Standards

0205(F).

Figure 23. ORCA High-Speed I/O Banks

High-Speed Memory Interfaces

PIO features allow high-speed interfaces to external
SRAM and/or DRAM devices. Series 4 I/Os provide
200 MHz ZBT requirements when switching between
write and read cycles. ZBT allows 100% use of bus
cycles during back-to-back read/write and write/read
cycles. However, this maximum utilization of the bus
increases probability of bus contention when the inter-
faced devices attempt to drive the bus to opposite logic
values. The LVTTL I/O interfaces directly with commer-
cial ZBT SRAMs signaling and allows the versatility to
program the FPGA drive strengths from 6 mA to
24 mA.

DDR allows data to be read or written on both the rising
and the falling edge of the clock which delivers twice
the bandwidth. QDR (quad data rate) are similar, but
have separate read and write parts for over double the
bandwidth. The DDR capability in the PIO also allows
double the bandwidth per pin for generic transfer of
data between two devices. DDR doubles the memory
speed from SDRAMs without the need to increase
clock frequency. The flexibility of the PIO allows
133 MHz/266 Mbits per second performance using the
SSTL I/O features of the Series 4. All DDR interface
functions are built into the PIO.

Option

Description

AND

Output logical AND of signals
on OUTFF and clock.

NAND

Output logical NAND of signals
on OUTFF and clock.

Output logical OR of signals on
OUTFF and clock.

NOR

Output logical NOR of signals
on OUTFF and clock.

XOR

Output logical XOR of signals
on OUTFF and clock.

XNOR

Output logical XNOR of signals
on OUTFF and clock.

IO BANK

Voltage

Compatible Standards

3.3 V

LVTTL, SSTL3-I, SSTL3-II, GTL, GTL+,
PECL

2.5 V

LVCMOS2, SSTL2-I, SSTL2-II, LVDS,
LVPECL

1.8 V

LVCMOS18

1.5 V

HSTL I, HSTL III, HSTL IV

PLC ARRAY

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Programmable Input/Output Cells

(continued)

LVDS I/O

The LVDS differential pair I/O standard allows for high-speed, low-voltage swing and low-power interfaces defined
by industry standards: ANSI*/TIA/EIA

-644 and IEEE 1596.3 SSI-LVDS. The general-purpose standard is supplied

without the need for an input reference supply and uses a low switching voltage which translates to low ac power
dissipation.

The ORCA LVDS I/O provides an integrated 100

matching resistor used to provide a differential voltage across

the inputs of the receiver. The on-chip integration provides termination of the LVDS receiver without the need of dis-
crete external board resistors. The user has the programmable option to enable termination per receiver pair for
point-to-point applications or, in multipoint interfaces, limit the use of termination to bused pairs. If the user chooses
to terminate any differential receiver, a single LVDS_R pin is dedicated to connect a single 100

resistor to V

which will provide a balance termination to all of the LVDS receiver pairs programmed to termination. See Table 20
for the LVDS termination pin location.

Table 19 provides the dc specifications for the ORCA LVDS solution.

Table 19. LVDS I/O Specifications

Table 20. LVDS Termination Pin

PIO Downlink/Uplink

Each group of four PIO have access to an input/output shift register as shown in Figure 24. This feature allows high-
speed input data to be divided down by 1/2 or 1/4, and output data can be multiplied by 2x or 4x its internal speed.
Both the input and output shift can be programmed to operate at the same time. However, the same PIO cannot be
used for both input and output shift registers at the same time.

For input shift mode, the data from INDD from the PIO is connected to the input shift register. The input data is
divided down and is returned to the routing through the INSH nodes. In 4x mode, all the INSH nodes are used. 2x
mode uses INSH4 and INSH3. Similarly, the output shift register brings data into the register from dedicated
OUTSH nodes. 4x mode uses all the OUTSH signals. However, only OUTSH2 and OUTSH1 are used for 2x mode.

* ANSI is a registered trademark of American National Standards Institute, Inc.
EIA is a registered trademark of Electronic Industries Association.

Parameter

Min

Typical

Max

Unit

Built-in Receiver Differential Input Resistor

100

105

Receiver Input Voltage

0.0

2.4

Differential Input Threshold

100

Output Common-mode Voltage

1.125

1.25

1.375

Input Common-mode Voltage

0.2

1.25

2.2

Dedicated Chip LVDS External Termination Pin (LVDS_R) Per Package

BA352

BC432

BM680

AC3

AH29

AL1

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Input/Output Cells

(continued)

0204(F).

Figure 24. PIO Shift Register

I
NDD

PIO

I
NDD

PIO

I
NDD

PIO

I
NDD

PIO

SHIFT REGISTER
OUT FROM FPGA

SHIFT REGISTER

INTO FPGA

CLK

Special Function Blocks

Internal Oscillator

The internal oscillator resides in the upper left corner of
the FPGA array. It has output clock frequencies of
1.25 MHz and 10 MHz. The internal oscillator is the
source of the internal CCLK used for configuration. It
may also be used after configuration as a general-
purpose clock signal.

Global Set/Reset (GSRN)

The GSRN logic resides in the lower-right corner of the
FPGA. GSRN is an invertible (default active-low) signal
that is used to reset all of the user-accessible latches/
FFs on the device. GSRN is automatically asserted at
powerup and during configuration of the device.

The timing of the release of GSRN at the end of config-
uration can be programmed in the start-up logic
described below. Following configuration, GSRN may
be connected to the

RESET

pin via dedicated routing, or

it may be connected to any signal via normal routing.
Within each PFU and PIO, individual FFs and latches

can be programmed to either be set or reset when
GSRN is asserted. Series 4 allows individual PFUs and
PIOs to turn off the GSRN signal to its latches/FFs
after configuration.

The

RESET

input pad has a special relationship to

GSRN. During configuration, the

RESET

input pad

always initiates a configuration abort, as described in
the FPGA States of Operation section. After configura-
tion, the GSRN can either be disabled (the default),
directly connected to the

RESET

input pad, or sourced

by a lower-right corner signal. If the

RESET

input pad is

not used as a global reset after configuration, this pad
can be used as a normal input pad.

Start-Up Logic

The start-up logic block can be configured to coordi-
nate the relative timing of the release of GSRN, the
activation of all user I/Os, and the assertion of the
DONE signal at the end of configuration. If a start-up
clock is used to time these events, the start-up clock
can come from CCLK, or it can be routed into the start-
up block using lower-right corner routing resources.

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Special Function Blocks

(continued)

Temperature Sensing

The built-in temperature-sensing diodes allow junction
temperature to be measured during device operation. A
physical pin (PTEMP) is dedicated for monitoring
device junction temperature. PTEMP works by forcing a
10 µA current in the forward direction, and then mea-
suring the resulting voltage. The voltage decreases
with increasing temperature at approximately
1.69 mV/°C. A typical device with a 85 °C device tem-
perature will measure approximately 630 mV.

Table 21. Dedicated Temperature Sensing

Boundary-Scan

The IEEE standards 1149.1 and 1149.2 (IEEE Stan-
dard test access port and boundary-scan architecture)
are implemented in the ORCA series of FPGAs. It
allows users to efficiently test the interconnection
between integrated circuits on a PCB as well as test the
integrated circuit itself. The IEEE 1149 standard is a
well-defined protocol that ensures interoperability
among boundary-scan (BSCAN) equipped devices
from different vendors.

Series 4 FPGAs are also compliant to IEEE standard
1532/D1. This standard for boundary-scan based in-
system configuration of programmable devices pro-
vides a standardized programming access and method-
ology for FPGAs. A device, or set of devices,
implementing this standard may be programmed, read
back, erased verified, singly or concurrently, with a
standard set of resources.

The IEEE 1149 standards define a test access port
(TAP) that consists of a four-pin interface with an
optional reset pin for boundary-scan testing of inte-
grated circuits in a system. The ORCA Series FPGA
provides four interface pins: test data in (TDI), test
mode select (TMS), test clock (TCK), and test data out
(TDO). The

PRGM

pin used to reconfigure the device

also resets the boundary-scan logic.

The user test host serially loads test commands and
test data into the FPGA through these pins to drive out-
puts and examine inputs. In the configuration shown in
Figure 26, where boundary-scan is used to test ICs,
test data is transmitted serially into TDI of the first
BSCAN device (U1), through TDO/TDI connections

between BSCAN devices (U2 and U3), and out TDO of
the last BSCAN device (U4). In this configuration, the
TMS and TCK signals are routed to all boundary-scan
ICs in parallel so that all boundary-scan components
operate in the same state. In other configurations, mul-
tiple scan paths are used instead of a single ring. When
multiple scan paths are used, each ring is indepen-
dently controlled by its own TMS and TCK signals.

Figure 26 provides a system interface for components
used in the boundary-scan testing of PCBs. The three
major components shown are the test host, boundary-
scan support circuit, and the devices under test
(DUTs). The DUTs shown here are ORCA Series
FPGAs with dedicated boundary-scan circuitry. The
test host is normally one of the following: automatic test
equipment (ATE), a workstation, a PC, or a micropro-
cessor.

5-5972(F)

Key: BSC = boundary-scan cell, BDC = bidirectional data cell, and

DCC = data control cell.

Figure 25. Printed-Circuit Board with Boundary-

Scan Circuitry

Dedicated Temperature Sensing

Diode Pin Per Package

BA352

BC432

BM680

AB3

AH31

AK4

INSTRUCTION

TDO

BYPASS

TCK TMS TDI

SCAN

OUT

SCAN

SCAN
OUT

SCAN

OUT

BSC

BDC

DCC

SCAN

OUT

SCAN
IN

TAPC

p_in

p_out

p_in

p_ts

p_out

p_ts

p_in

p_out

p_ts

p_out

p_ts

PL[ij]

PT[ij]

PR[ij]

PB[ij]

BDC

DCC

PLC

ARRAY

BDC

DCC

BDC

DCC

BSC

SEE ENLARGED VIEW BELOW.

TMS TDI
TCK
TDO

TDI

TCK

TDO

TMS

net a

net b

net c

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Special Function Blocks

(continued)

5-6765(F)

Figure 26. Boundary-Scan Interface

D[7:0]

INTR

MICRO-

PROCESSOR

D[7:0]

CE
RA

R/W

DAV
INT

TMS0

TCK

TDI

TDO

TDI

TMS

TCK

TDO

ORCA

SERIES

FPGA

TDI

ORCA

SERIES

FPGA

TMS

TCK

TDO

TDI

TMS

TCK

TDO

ORCA

SERIES

FPGA

LUCENT

BOUNDARY-

SCAN

MASTER

(BSM)

(DUT)

The boundary-scan support circuit shown in Figure 26
is the 497Aa boundary-scan master (BSM). The BSM
off-loads tasks from the test host to increase test
throughput. To interface between the test host and the
DUTs, the BSM has a general MPI and provides paral-
lel-to-serial/serial-to-parallel conversion, as well as
three 8K data buffers. The BSM also increases test
throughput with a dedicated automatic test-pattern
generator and with compression of the test response
with a signature analysis register. The PC-based
boundary-scan test card/software allows a user to
quickly prototype a boundary-scan test setup.

Boundary-Scan Instructions

The Series 4 boundary-scan circuitry includes ten
IEEE 1149.1, 1149.2, and 1532/D1 instructions and six
ORCA-defined instructions. These also include one
IEEE 1149.3 optional instruction. A 6-bit wide instruc-
tion register supports all the instructions listed in
Table 22. The BYPASS instruction passes data inter-
nally from TDI to TDO after being clocked by TCK.

Table 22. Boundary-Scan Instructions

Code

Instruction

000000

EXTEST

000001

SAMPLE

000011

PRELOAD

000100

RUNBIST

000101

IDCODE

000110

USERCODE

001000

ISC_ENABLE

001001

ISC_PROGRAM

001010

ISC_NOOP

001011

ISC_DISABLE

001101

ISC_PROGRAM_USERCODE

001110

ISC_READ

010001

PLC_SCAN_RING1

010010

PLC_SCAN_RING2

010011

PLC_SCAN_RING3

010100

RAM_WRITE

010101

RAM_READ

111111

BYPASS

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Special Function Blocks

(continued)

The external test (EXTEST) instruction allows the inter-
connections between ICs in a system to be tested for
opens and stuck-at faults. If an EXTEST instruction is
performed for the system shown in Figure 25, the con-
nections between U1 and U2 (shown by nets a, b,
and c) can be tested by driving a value onto the given
nets from one device and then determining whether this
same value is seen at the other device. This is deter-
mined by shifting 2 bits of data for each pin (one for the
output value and one for the 3-state value) through the
BSR until each one aligns to the appropriate pin. Then,
based upon the value of the 3-state signal, either the
I/O pad is driven to the value given in the BSR, or the
BSR is updated with the input value from the I/O pad,
which allows it to be shifted out TDO.

The SAMPLE and PRELOAD instructions are useful for
system debugging and fault diagnosis by allowing the
data at the FPGA's I/Os to be observed during normal
operation or written during test operation. The data for
all of the I/Os is captured simultaneously into the BSR,
allowing them to be shifted-out TDO to the test host.
Since each I/O buffer in the PIOs is bidirectional, two
pieces of data are captured for each I/O pad: the value
at the I/O pad and the value of the 3-state control sig-
nal. For preload operation, data is written from the BSR
to all of the I/Os simultaneously.

There are six ORCA-defined instructions. The PLC
scan rings 1, 2, and 3 (PSR1, PSR2, PSR3) allow user-
defined internal scan paths using the PLC latches/FFs
and routing interface. The RAM_Write Enable
(RAM_W) instruction allows the user to serially config-
ure the FPGA through TDI. The RAM_Read Enable
(RAM_R) allows the user to read back RAM contents
on TDO after configuration. The IDCODE instruction
allows the user to capture a 32-bit identification code
that is unique to each device and serially output it at
TDO. The IDCODE format is shown in Table 23.

An optional IEEE 1149.3 instruction RUNBIST has
been implemented. This instruction is used to invoke
the built-in self-test (BIST) of regular structures like

RAMs, ROMs, FIFOs, etc., and the surrounding RAN-
DOM logic in the circuit.

Also implemented in Series 4 devices is the IEEE
1532/D1 standards for in-system configuration for pro-
grammable logic devices. Included are four mandatory
and two optional instructions defined in the standards.
ISC_ENABLE, ISC_PROGRAM, ISC_NOOP, and
ISC_DISABLE are the four mandatory instructions.
ISC_ENABLE initializes the devices for all subsequent
ISC instructions. The ISC_PROGRAM instruction is
similar to the RAM_WRITE instruction implemented in
all ORCA devices where the user must monitor the
PINITN pin for a high indicating the end of initialization
and a successful configuration can be started. The
ISC_PROGRAM instruction is used to program the
configuration memory through a dedicated ISC_Pdata
register. The ISC_NOOP instruction is used when pro-
gramming multiple devices in parallel. During this
mode, TDI and TDO behave like BYPASS. The data
shifted through TDI is shifted out through TDO. How-
ever, the output pins remain in control of the BSR,
unlike BYPASS where they are driven by the system
logic. The ISC_DISABLE is used upon completion of
the ISC programming. No new ISC instructions will be
operable without another ISC_ENABLE instruction.

Optional 1532/D1 instructions include
ISC_PROGRAM_USERCODE. When this instruction
is loaded, the user shifts all 32 bits of a user-defined ID
(LSB first) through TDI. This overwrites any ID previ-
ously loaded into the ID register. This ID can then be
read back through the USERCODE instruction defined
in IEEE 1149.2.

ISC_READ is similar to the ORCA RAM_Read instruc-
tion which allows the user to read back the configura-
tion RAM contents serially out on TDO. Both must
monitor the PDONE signal to determine weather or not
configuration is completed. ISC_READ used a 1-bit
register to synchronously read back data coming from
the configuration memory. The readback data is
clocked into the ISC_READ data register and then
clocked out TDO on the falling edge or TCK.

Table 23. Series 4E Boundary-Scan Vendor-ID Codes

* PLC array size of FPGA, reverse bit order.

Note: Table assumes version 0.

Device

Version (4-bit)

Part* (10-bit)

Family (6-bit)

Manufacturer (11-bit)

LSB (1-bit)

OR4E2

0000

0011100000

001000

00000011101

OR4E4

0000

0001010000

001000

00000011101

OR4E6

0000

0000110000

001000

00000011101

OR4E10

0000

0011110000

001000

00000011101

OR4E14

0000

0010001000

001000

00000011101

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Special Function Blocks

(continued)

ORCA Boundary-Scan Circuitry

The ORCA Series boundary-scan circuitry includes a
test access port controller (TAPC), instruction register
(IR), boundary-scan register (BSR), and bypass regis-
ter. It also includes circuitry to support the 18 pre-
defined instructions.

Figure 27 shows a functional diagram of the boundary-
scan circuitry that is implemented in the ORCA Series.
The input pins' (TMS, TCK, and TDI) locations vary
depending on the part, and the output pin is the dedi-
cated TDO/RD_DATA output pad. Test data in (TDI) is
the serial input data. Test mode select (TMS) controls
the boundary-scan TAPC. Test clock (TCK) is the test
clock on the board.

The BSR is a series connection of boundary-scan cells
(BSCs) around the periphery of the IC. Each I/O pad on
the FPGA, except for CCLK, DONE, and the boundary-
scan pins (TCK, TDI, TMS, and TDO), is included in
the BSR. The first BSC in the BSR (connected to TDI)
is located in the first PIO I/O pad on the left of the top
side of the FPGA (PTA PIO). The BSR proceeds clock-
wise around the top, right, bottom, and left sides of the
array. The last BSC in the BSR (connected to TDO) is
located on the top of the left side of the array (PL1D).

The bypass instruction uses a single FF, which resyn-
chronizes test data that is not part of the current scan
operation. In a bypass instruction, test data received on
TDI is shifted out of the bypass register to TDO. Since
the BSR (which requires a two FF delay for each pad)
is bypassed, test throughput is increased when devices
that are not part of a test operation are bypassed.

The boundary-scan logic is enabled before and during
configuration. After configuration, a configuration
option determines whether or not boundary-scan logic
is used.

The 32-bit boundary-scan identification register con-
tains the manufacturer's ID number, unique part num-
ber, and version (as described earlier). The
identification register is the default source for data on
TDO after RESET if the TAP controller selects the shift-
data-register (SHIFT-DR) instruction. If boundary scan
is not used, TMS, TDI, and TCK become user I/Os, and
TDO is 3-stated or used in the readback operation.

An optional USERCODE is available. The USERCODE
is a 32-bit value that the user can set during device
configuration and can be written to and read from the
FPGA via the boundary-scan logic.

Preliminary Data Sheet
December 2000

Lucent Technologies Inc.

ORCA Series 4 FPGAs

Special Function Blocks

(continued)

5-5768(F)

Figure 27. ORCA Series Boundary-Scan Circuitry Functional Diagram

TAP

CONTROLLER

TMS

TCK

BOUNDARY-SCAN REGISTER

USER CODE REGISTERS

BYPASS REGISTER

DATA

MUX

INSTRUCTION DECODER

INSTRUCTION REGISTER

M
U
X

RESET
CLOCK IR
SHIFT-IR
UPDATE-IR

PUR

TDO

SELECT

ENABLE

RESET

CLOCK DR

SHIFT-DR

UPDATE-DR

TDI

DATA REGISTERS

PSR1/PSR2/PSR3 REGISTERS (PLCs)

CONFIGURATION REGISTER

(RAM_R, RAM_W)

PRGM

I/O BUFFERS

IDCODE REGISTER

ORCA Series TAP Controller

The ORCA Series TAP controller is a 1149 compatible
TAPC. The 16 JTAG state assignments from the IEEE
1149 specification are used. The TAPC is controlled by
TCK and TMS. The TAPC states are used for loading
the IR to allow three basic functions in testing: provid-
ing test stimuli (Update-DR), providing test execution
(Run-Test/Idle), and obtaining test responses (Capture-
DR). The TAPC allows the test host to shift in and out
both instructions and test data/results. The inputs and
outputs of the TAPC are provided in the table below.
The outputs are primarily the control signals to the
instruction register and the data register.

Table 24. TAP Controller Input/Outputs

Symbol

I/O

Function

TMS

Test Mode Select

TCK

Test Clock

PUR

Powerup Reset

PRGM

BSCAN Reset

TRESET

Test Logic Reset

Select

Select IR (High); Select-DR (Low)

Enable

Test Data Out Enable

Capture-DR

Capture/Parallel Load-DR

Capture-IR

Capture/Parallel Load-IR

Shift-DR

Shift Data Register

Shift-IR

Shift Instruction Register

Update-DR

Update/Parallel Load-DR

Update-IR

Update/Parallel Load-IR

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Special Function Blocks

(continued)

The TAPC generates control signals that allow capture, shift, and update operations on the instruction and data
registers. In the capture operation, data is loaded into the register. In the shift operation, the captured data is
shifted out while new data is shifted in. In the update operation, either the instruction register is loaded for instruc-
tion decode, or the boundary-scan register is updated for control of outputs.

The test host generates a test by providing input into the ORCA Series TMS input synchronous with TCK. This
sequences the TAPC through states in order to perform the desired function on the instruction register or a data
register. Figure 28 provides a diagram of the state transitions for the TAPC. The next state is determined by the
TMS input value.

5-5370(F)

Figure 28. TAP Controller State Transition Diagram

SELECT-

DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

RUN-TEST/

IDLE

TEST-LOGIC-

RESET

SELECT-

IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

Boundary-Scan Cells

Figure 29 is a diagram of the boundary-scan cell (BSC)
in the ORCA series PIOs. There are four BSCs in each
PIO: one for each pad, except as noted above. The
BSCs are connected serially to form the BSR. The
BSC controls the functionality of the in, out, and 3-state
signals for each pad.

The BSC allows the I/O to function in either the normal
or test mode. Normal mode is defined as when an out-
put buffer receives input from the PLC array and pro-
vides output at the pad or when an input buffer
provides input from the pad to the PLC array. In the test
mode, the BSC executes a boundary-scan operation,
such as shifting in scan data from an upstream BSC in
the BSR, providing test stimuli to the pad, capturing
test data at the pad, etc.

The primary functions of the BSC are shifting scan data
serially in the BSR and observing input (p_in), output
(p_out), and 3-state (p_ts) signals at the pads. The
BSC consists of two circuits: the bidirectional data cell
is used to access the input and output data, and the
direction control cell is used to access the 3-state
value. Both cells consist of a FF used to shift scan data
which feeds a FF to control the I/O buffer. The bidirec-
tional data cell is connected serially to the direction
control cell to form a boundary-scan shift register.

The TAPC signals (capture, update, shiftn, treset, and
TCK) and the MODE signal control the operation of the
BSC. The bidirectional data cell is also controlled by
the high out/low in (HOLI) signal generated by the
direction control cell. When HOLI is low, the bidirec-
tional data cell receives input buffer data into the BSC.
When HOLI is high, the BSC is loaded with functional
data from the PLC.

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Special Function Blocks

(continued)

The MODE signal is generated from the decode of the instruction register. When the MODE signal is high
(EXTEST), the scan data is propagated to the output buffer. When the MODE signal is low (BYPASS or SAMPLE),
functional data from the FPGA's internal logic is propagated to the output buffer.

The boundary-scan description language (BSDL) is provided for each device in the ORCA Series of FPGAs on the
ORCA Foundry CD. The BSDL is generated from a device profile, pinout, and other boundary-scan information.

5-2844(F)

Figure 29. Boundary-Scan Cell

Boundary-Scan Timing

To ensure race-free operation, data changes on specific clock edges. The TMS and TDI inputs are clocked in on
the rising edge of TCK, while changes on TDO occur on the falling edge of TCK. In the execution of an EXTEST
instruction, parallel data is output from the BSR to the FPGA pads on the falling edge of TCK. The maximum fre-
quency allowed for TCK is 10 MHz.

Figure 30 shows timing waveforms for an instruction scan operation. The diagram shows the use of TMS to
sequence the TAPC through states. The test host (or BSM) changes data on the falling edge of TCK, and it is
clocked into the DUT on the rising edge.

SCAN IN

p_out

HOLI

BIDIRECTIONAL DATA CELL

I/O BUFFER

DIRECTION CONTROL CELL

MODE

UPDATE/TCK

SCAN OUT

TCK

SHIFTN/CAPTURE

p_ts

p_in

PAD_IN

PAD_TS

PAD_OUT

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Special Function Blocks

(continued)

5-5971(F)

Figure 30. Instruction Register Scan Timing Diagram

TCK

TMS

TDI

RUN-TE

/
I
DLE

RUN

-T

T/I

-
I
R

-I

-
DR-S

URE

-I

-
I
R-S

ST-

-
R

I
F

T-

-
IR

I
F

T-

-
I
R

Readback Logic

The readback logic can be enabled via a bit stream
option or by instantiation of a library readback compo-
nent.

Readback is used to read back the configuration data
and, optionally, the state of all PFU and PIO FF out-
puts. A readback operation can be done while the
FPGA is in normal system operation. The readback
operation can be daisy-chained. To use readback, the
user selects options in the bit stream generator in the
ORCA Foundry development system.

Table 25 provides readback options selected in the bit
stream generator tool. The table provides the number
of times that the configuration data can be read back.
This is intended primarily to give the user control over
the security of the FPGA's configuration program. The
user can prohibit readback (0), allow a single readback
(1), or allow unrestricted readback (U).

Table 25. Readback Options

Readback can be performed via the Series 4 MPI or by
using dedicated FPGA readback controls. If the MPI is
enabled, readback via the dedicated FPGA readback
logic is disabled. Readback using the MPI is discussed
in the MPI section.

The pins used for dedicated readback are readback
data (RD_DATA), read configuration (

RD_CFG

), and

configuration clock (CCLK). A readback operation is ini-
tiated by a high-to-low transition on

RD_CFG

. The

RD_CFG

input must remain low during the readback

operation. The readback operation can be restarted at
frame 0 by driving the

RD_CFG

pin high, applying at

least two rising edges of CCLK, and then driving

RD_CFG

low again. One bit of data is shifted out on

RD_DATA at the rising edge of CCLK. The first start bit
of the readback frame is transmitted out several cycles
after the first rising edge of CCLK after

RD_CFG

is input

low (see the readback timing characteristics table in the
timing characteristics section). To be certain of the start
of the readback frame, the data can be monitored for
the 01 frame start bit pair.

Option

Function

Prohibit Readback

Allow One Readback Only

Allow Unrestricted Number of Readbacks

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Special Function Blocks

(continued)

Readback can be initiated at an address other than
frame 0 via the new MPI control registers (see the
Microprocessor

Interface section for more information).

In all cases, readback is performed at sequential
addresses from the start address.

It should be noted that the RD_DATA output pin is also
used as the dedicated boundary-scan output pin, TDO.
If this pin is being used as TDO, the RD_DATA output
from readback can be routed internally to any other pin
desired. The

RD_CFG

input pin is also used to control

the global 3-state (TS_ALL) function. Before and during
configuration, the TS_ALL signal is always driven by
the

RD_CFG

input and readback is disabled. After con-

figuration, the selection as to whether this input drives
the readback or global 3-state function is determined
by a set of bit stream options. If used as the

RD_CFG

input for readback, the internal TS_ALL input can be
routed internally to be driven by any input pin.

The readback frame contains the configuration data
and the state of the internal logic. During readback, the
value of all registered PFU and PIO outputs can be
captured. The following options are allowed when
doing a capture of the PFU outputs:

Do not capture data (the data written to the RAMs,
usually 0, will be read back).

Capture data upon entering readback.

Capture data based upon a configurable signal inter-
nal to the FPGA. If this signal is tied to logic 0, cap-
ture RAMs are written continuously.

Capture data on either options two or three above.

The readback frame has an identical format to that of
the configuration data frame, which is discussed later in
the Configuration Data Format section. If LUT memory
is not used as RAM and there is no data capture, the
readback data (not just the format) will be identical to
the configuration data for the same frame. This eases a
bitwise comparison between the configuration and
readback data. The configuration header, including the
length count field, is not part of the readback frame.
The readback frame contains bits in locations not used
in the configuration. These locations need to be
masked out when comparing the configuration and
readback frames. The development system optionally
provides a readback bit stream to compare to readback
data from the FPGA. Also note that if any of the LUTs
are used as RAM and new data is written to them,
these bits will not have the same values as the original
configuration data frame either.

Global 3-State Control (TS_ALL)

To increase the testability of the ORCA Series FPGAs,
the global 3-state function (TS_ALL) disables the
device. The TS_ALL signal is driven from either an
external pin or an internal signal. Before and during
configuration, the TS_ALL signal is driven by the input
pad

RD_CFG

. After configuration, the TS_ALL signal

can be disabled, driven from the

RD_CFG

input pad, or

driven by a general routing signal in the upper right cor-
ner. Before configuration, TS_ALL is active-low; after
configuration, the sense of TS_ALL can be inverted.

The following occur when TS_ALL is activated:

All of the user I/O output buffers are 3-stated.

The TDO/RD_DATA output buffer is 3-stated.

The RD_CFG, RESET, and PRGM input buffers
remain active with a pull-up.

The DONE output buffer is 3-stated, and the input
buffer is pulled up.

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Microprocessor Interface (MPI)

The Series 4 FPGAs have a dedicated synchronous MPI function block. The MPI is programmable to operate with
PowerPC MPC860/MPC8260 series microprocessors. The pin listing is shown in Table 26. The MPI implements an
8-, 16-, or 32-bit interface with 4-bit parity to the host processor (PowerPC) that can be used for configuration and
readback of the FPGA as well as for user-defined data processing and general monitoring of FPGA functions. In
addition to dedicated-function registers, the MPI bridges to the AMBA embedded system bus through which the
PowerPC bus master can access the FPGA configuration logic, EBR, and other user logic. There is also capability
to interrupt the host processor either by a hard interrupt or by having the host processor poll the MPI and the
embedded system bus.

The control portion of the MPI is available following powerup of the FPGA if the mode pins specify MPI mode, even
if the FPGA is not yet configured. The width of the data port is selectable among 8-, 16-, or 32-bit and the parity bus
can be 1-, 2-, or 4- bit. In configuration mode, the data bus width and parity are related to the state of the M[0:3]
mode pins. For postconfiguration use, the MPI must be included in the configuration bit stream by using an MPI
library element in your design from the ORCA macro library, or by setting the bit of the MPI configuration control
register prior to the start of configuration. The user can also enable and disable the parity bus through the configu-
ration bit stream. These pads can be used as general I/O when they are not needed for MPI use.

The ORCA FPGA is a memory-mapped peripheral to the PowerPC processor. The MPI interfaces to the user-pro-
grammable FPGA logic using the AMBA embedded system bus. The MPI has access to a series of addressable
registers made accessible by the AMBA system bus that provide FPGA control and status, configuration and read-
back data transfer, FPGA device identification, and a dedicated user scratchpad register. All registers are 8 bits
wide. The address map for these registers and the user-logic address space utilize the same registers as the
AMBA embedded system bus. The internal AMBA bus is 32 bits wide and the proper transformation of 8-, 16-, or
32-bit data of the MPI is done when transferring data between the MPI and ESB.

Table 26. MPC 860 to ORCA MPI Interconnection

PowerPC

Signal

ORCA Pin

Name

MPI

I/O

Function

D[n:0]

D[31:0]

I/O

8-, 16-, 32-bit data bus.

DP[m:0]

DP[3:0]

I/O

Selectable parity bus width from 1-, 2-, and 4-bit.

A[14:31]

A[17:0]

32-bit MPI address bus.

MPI_STRB

Transfer start signal.

BURST

MPI_BURST

Active-low indicates burst transfer in-progress/high indicates current transfer
not a burst.

CS0

Active-low MPI select.

CS1

Active-high MPI select.

CLKOUT

MPI_CLK

PowerPC interface clock.

RD/WR

MPI_RW

Read (high)/write (low) signal.

MPI_ACK

Active-low transfer acknowledge signal.

BDIP

MPI_BDIP

Active-low burst transfer in progress signal indicates that the second beat in
front of the current one is requested by the master. Negated before the burst
transfer ends to abort the burst data phase.

Any of

IRQ[7:0]

MPI_IRQ

Active-low interrupt request signal.

TEA

MPI_TEA

Active-low indicates MPI detects a bus error on the internal system bus for
current transaction.

RETRY

MPI_RTRY

Requests the MPC860 to relinquish the bus and retry the cycle.

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Embedded System Bus (ESB)

Implemented using the open standard, on-chip bus
AMBA-AHB 2.0 specification, the Series 4 devices con-
nects all the FPGA elements together with a standard-
ized bus framework. The ESB facilitates communication
among MPI, configuration, EBRs, and user logic in all
the generic FPGA devices. AHB serves the need for
high-performance SoC as well as aligning with current
synthesis design flows. Multiple bus masters optimize
system performance by sharing resources between dif-
ferent bus masters such as the MPI and configuration
logic. The wide data bus configuration of 32 bits with
4-bit parity supports the high-bandwidth of data-inten-
sive applications of using the wide on-chip memory.
AMBA enhances a reusable design methodology by
defining a common backbone for IP modules.

The ESB is a synchronous bus that is driven by either
the MPI clock, internal oscillator, CCLK (slave configu-
ration modes), TCK (JTAG configuration modes), or by
a user clock from routing. During initial configuration
and reconfiguration, the bus clock is defaulted to the
configuration clock. The postconfiguration clock source
is set during configuration. The user has the ability to
program several slaves through the user logic interface.
Embedded block RAM also interfaces seamlessly to the
AHB bus.

A single bus arbiter controls the traffic on the bus by
ensuring that only one master has access to the bus at
any time. The arbiter monitors a number of different
requests to use the bus and decides which request is
currently the highest priority. The configuration modes
have the highest priority and overrides all normal user
modes. Priority can be programmed between MPI and
user logic at configuration in generic FPGAs. If no prior-
ity is set, a round-robin approach is used by granting
the next requesting master in a rotating fixed order.

Several interfaces exist between the ESB and other
FPGA elements. The MPI interface acts as a bridge
between the external microprocessor bus and ESB.
The MPI may have different clock domains than the
ESB if the ESB clock is not sourced from the external
microprocessor clock. Pipelined operation allows high-
speed memory interface to the EBR and peripheral
access without the requirement for additional cycles on
the bus. Burst transfers allow optimal use of the mem-
ory interface by giving advance information of the
nature of the transfers.

Table 27 is a listing of the ESB register file and brief
descriptions. Table 28 shows the system interrupt regis-
ters, and Table 29 and Table 30 show the FPGA status
and command registers, all with brief descriptions.

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Embedded System Bus (ESB)

(continued)

Table 27. Embedded System Bus/MPI Registers

Table 28. Interrupt Register Space Assignments

Register

Byte

Read/Write Initial Value

Description

03--00

32-bit device ID

07--04

R/W

Scratchpad register

0B--08

R/W

Command register

0F--0C

Status register

R/W

Interrupt enable register--MPI

R/W

Interrupt enable register--USER

R/W

Interrupt enable register--FPSC

Interrupt cause register

17--14

R/W

Readback address register (14 bits)

1B--18

Readback data register

1F--1C

R/W

Configuration data register

23--20

Reserved

27--24

Bus error address register

2B--28

Interrupt vector 1 predefined by configuration bit stream

2F--2C

Interrupt vector 2 predefined by configuration bit stream

33--30

Interrupt vector 3 predefined by configuration bit stream

37--34

Interrupt vector 4 predefined by configuration bit stream

3B--38

Interrupt vector 5 predefined by configuration bit stream

3F--3C

Interrupt vector 6 predefined by configuration bit stream

43--40

Top-left PPLL control/status

47--44

Top-left HPLL control/status

53--50

Top-right PPLL control/status

63--60

Bottom-left PPLL control/status

67--64

Bottom-left HPLL control/status

73--70

Bottom-right PPLL control/status

Byte

Bit

Read/Write

Description

7--0

R/W

Interrupt enable register--MPI

7--0

R/W

Interrupt enable register--USER

7--0

R/W

Interrupt enable register--FPSC

Interrupt cause registers

USER_IRQ_GENERAL;

USER_IRQ_SLAVE;

USER_IRQ_MASTER;

CFG_IRQ_DATA;

ERR_FLAG 1

MPI_IRQ

FPSC_IRQ_SLAVE;

FPSC_IRQ_MASTER

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Embedded System Bus (ESB)

(continued)

Table 29. Status Register Space Assignments

Table 30. Command Register Space Assignments

Byte

Bit

Read/Write

Description

7:0

Reserved

7:0

Reserved

Configuration write data acknowledge

Readback data ready

Unassigned (zero)

FPSC_BIT_ERR

RAM_BIT_ERR

Configuration write data size (1, 2, or 4 bytes)

Use with above for HSIZE[1:0] (byte, half-word, word)

Readback addresses out of range

Error response received by CFG from system bus

Error responses received by CFG from system bus

Unassigned (zero)

ERR_FLAG 1

ERR_FLAG 0

Byte

Bit

Description

Bus reset from MPI > drives HRESETn

Bus reset from USER > drives HRESETn

Bus reset from FPSC > drives HRESETn

SYS_DAISY

REPEAT_RDBK (Don't increment readback address.)

MPI_USR_ENABLE

Readback data size (1, 2, or 4 bytes)

Use with above for HSIZE[1:0]

R/W SYS_GSR (GSR Input)

SYS_RD_CFG (similar to FPGA pin RD_CFGN, but active-high)

PRGM from MPI > (similar to FPGA pin, but active-high)

PRGM from USER > (similar to FPGA pin, but active-high)

PRGM from FPSC > (similar to FPGA pin, but active-high)

LOCK from MPI

LOCK from USER

LOCK from FPSC

7:0

Reserved

7:0

Reserved

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Phase-Locked Loops

There are eight PLLs available to perform many clock
modification and clock conditioning functions on the
Series 4 FPGAs. Six of the PLLs are programmable
allowing the user the flexibility to configure the PLL to
manipulate the frequency, phase, and duty cycle of a
clock signal. Four of the programmable PLLs are capa-
ble of manipulating and conditioning clocks from
20 MHz to 200 MHz and two others are capable of
manipulating and conditioning clocks from 60 MHz to
420 MHz. Frequencies can be adjusted from 1/8x to 8x
the input clock frequency. Each programmable PLL
provides two outputs that have different multiplication
factors with the same phase relationships. Duty cycles
and phase delays can be adjusted in 12.5% of the
clock period increments. An input buffer delay compen-
sation mode is available for phase delay. Each PPLL
provides two outputs (MCLK, NCLK) that can have pro-
grammable (12.5% steps) phase differences.

The PPLLs can be utilized to eliminate skew between
the clock input pad and the internal clock inputs across
the entire device. The PPLLs can drive onto the pri-
mary, secondary, and edge clock networks inside the
FPGA. Each PPLL can take a clock input from the ded-
icated pad or differential pair of pads in its corner or
from general routing resources.

Functionality of the PPLLs is programmed during oper-
ation through a read/write interface to the internal sys-
tem bus command and status registers or via the
configuration bit stream. There is also a PLL output sig-
nal, LOCK, that indicates a stable output clock state.
Unlike Series 3, this signal does not have to be inter-
grated before use.

Table 31. PPLL Specifications

Additional highly tuned and characterized dedicated phase-locked loops (DPLLs) are included to ease system
designs. These DPLLs meet ITU-T G.811 primary clocking specifications and enable system designers to target
very tightly specified clock conditioning not available in the universal PPLLs. DPLLs are targeted to low-speed net-
working DS1 and E1 and high-speed SONET/SDH networking STS-3 and STM-1 systems.

Parameter

Min

Nom

Max

Unit

1.5

1.425

1.5

1.575

3.3

3.0

3.3

3.6

Operating Temp

125

°C

Input Clock Voltage

1.425

1.5

1.575

Output Clock Voltage

1.425

1.5

1.575

Input Clock Frequency

(no division)

PPLL

200

MHz

HPPLL

420

Output Clock Frequency

PPLL

200

MHz

HPPLL

420

Input Duty Cycle Tolerance

Output Duty Cycle

dc Power

Total On Current

8.5

Total Off Current

Cycle to Cycle Jitter (p-p)

<0.02

UIp-p

Lock Time

<50

µs

Frequency Multiplication

1x, 2x, 3x, 4x, 5x, 6x, 7x, 8x,

Frequency Division

1/8, 1/7, 1/6, 1/5, 1/4, 1/3, 1/2

Duty Cycle Adjust of Output Clock

12.5, 25, 37.5, 50, 62.5, 75, 87.5

Delay Adjust of Output Clock

0, 12.5, 25, 37.5, 50, 62.5, 75, 87.5

Phase Shift Between MCLK & NCLK

0, 45, 90, 135, 180, 225, 270, 315

degree

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

FPGA States of Operation

(continued)

Initialization

Upon powerup, the device goes through an initialization
process. First, an internal power-on-reset circuit is trig-
gered when power is applied. Dedicated power pins
called V

33 are used by the configuration logic. When

33 reaches the voltage at which portions of the

FPGA begin to operate (2.0 V), the I/Os are configured
based on the configuration mode, as determined by the
mode select inputs M[2:0]. A time-out delay is initiated
when V

33 reaches between 2.7 V to 3.0 V to allow

the power supply voltage to stabilize. The

INIT

and

DONE outputs are low. At powerup, if V

33 does not

rise from 2.0 V to V

33 in less than 25 ms, the user

should delay configuration by inputting a low into

INIT

PRGM

, or

RESET

until V

33 is greater than the recom-

mended minimum operating voltage.

At the end of initialization, the default configuration
option is that the configuration RAM is written to a low
state. This prevents shorts prior to configuration. As a
configuration option, after the first configuration (i.e., at
reconfiguration), the user can reconfigure without
clearing the internal configuration RAM first. The
active-low, open-drain initialization signal

INIT

released and must be pulled high by an external resis-
tor when initialization is complete. To synchronize the
configuration of multiple FPGAs, one or more

INIT

pins

should be wire-ANDed. If

INIT

is held low by one or

more FPGAs or an external device, the FPGA remains
in the initialization state.

INIT

can be used to signal that

the FPGAs are not yet initialized. After

INIT

goes high

for two internal clock cycles, the mode lines (M[3:0])
are sampled, and the FPGA enters the configuration
state.

The high during configuration (HDC), low during config-
uration (

LDC

), and DONE signals are active outputs in

the FPGA's initialization and configuration states. HDC,

LDC

, and DONE can be used to provide control of

external logic signals such as reset, bus enable, or
PROM enable during configuration. For parallel master
configuration modes, these signals provide PROM
enable control and allow the data pins to be shared
with user logic signals.

If configuration has begun, an assertion of

RESET

PRGM

initiates an abort, returning the FPGA to the ini-

tialization state. The

PRGM

and

RESET

pins must be

pulled back high before the FPGA will enter the config-
uration state. During the start-up and operating states,
only the assertion of

PRGM

causes a reconfiguration.

In the master configuration modes, the FPGA is the
source of configuration clock (CCLK). In this mode, the

initialization state is extended to ensure that, in daisy-
chain operation, all daisy-chained slave devices are
ready. Independent of differences in clock rates, master
mode devices remain in the initialization state an addi-
tional six internal clock cycles after

INIT

goes high.

When configuration is initiated, a counter in the FPGA
is set to 0 and begins to count configuration clock
cycles applied to the FPGA. As each configuration data
frame is supplied to the FPGA, it is internally assem-
bled into data words. Each data word is loaded into the
internal configuration memory. The configuration load-
ing process is complete when the internal length count
equals the loaded length count in the length count field,
and the required end of configuration frame is written.

During configuration, the PIO and PLC latches/FFs are
held set/reset and the internal BIDI buffers are
3-stated. The combinatorial logic begins to function as
the FPGA is configured. Figure 34 shows the general
waveform of the initialization, configuration, and start-
up states.

Configuration

The ORCA Series FPGA functionality is determined by
the state of internal configuration RAM. This configura-
tion RAM can be loaded in a number of different
modes. In these configuration modes, the FPGA can
act as a master or a slave of other devices in the sys-
tem. The decision as to which configuration mode to
use is a system design issue. Configuration is dis-
cussed in detail, including the configuration data format
and the configuration modes used to load the configu-
ration data in the FPGA, following a description of the
start-up state.

Start-Up

After configuration, the FPGA enters the start-up
phase. This phase is the transition between the config-
uration and operational states and begins when the
number of CCLKs received after

INIT

goes high is equal

to the value of the length count field in the configuration
frame and when the end of configuration frame has
been written. The system design issue in the start-up
phase is to ensure the user I/Os become active without
inadvertently activating devices in the system or caus-
ing bus contention. A second system design concern is
the timing of the release of global set/reset of the PLC
latches/FFs.

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

FPGA States of Operation

(continued)

There are configuration options that control the relative
timing of three events: DONE going high, release of the
set/reset of internal FFs, and user I/Os becoming
active. Figure 35 shows the start-up timing for ORCA
FPGAs. The system designer determines the relative
timing of the I/Os becoming active, DONE going high,
and the release of the set/reset of internal FFs. In the
ORCA Series FPGA, the three events can occur in any
arbitrary sequence. This means that they can occur
before or after each other, or they can occur simulta-
neously.

There are four main start-up modes: CCLK_NOSYNC,
CCLK_SYNC, UCLK_NOSYNC, and UCLK_SYNC.
The only difference between the modes starting with
CCLK and those starting with UCLK is that for the
UCLK modes, a user clock must be supplied to the
start-up logic. The timing of start-up events is then
based upon this user clock, rather than CCLK. The dif-
ference between the SYNC and NOSYNC modes is
that for SYNC mode, the timing of two of the start-up
events, release of the set/reset of internal FFs, and the
I/Os becoming active is triggered by the rise of the
external DONE pin followed by a variable number of ris-
ing clock edges (either CCLK or UCLK). For the
NOSYNC mode, the timing of these two events is
based only on either CCLK or UCLK.

DONE is an open-drain bidirectional pin that may
include an optional (enabled by default) pull-up resistor
to accommodate wired ANDing. The open-drain DONE
signals from multiple FPGAs can be tied together
(ANDed) with a pull-up (internal or external) and used
as an active-high ready signal, an active-low PROM
enable, or a reset to other portions of the system.
When used in SYNC mode, these ANDed DONE pins
can be used to synchronize the other two start-up
events, since they can all be synchronized to the same
external signal. This signal will not rise until all FPGAs
release their DONE pins, allowing the signal to be
pulled high.

The default for ORCA is the CCLK_SYNC synchro-
nized start-up mode where DONE is released on the
first CCLK rising edge, C1 (see Figure 35). Since this is
a synchronized start-up mode, the open-drain DONE
signal can be held low externally to stop the occurrence
of the other two start-up events. Once the DONE pin
has been released and pulled up to a high level, the
other two start-up events can be programmed individu-
ally to either happen immediately or after up to four ris-
ing edges of CCLK (Di, Di + 1, Di + 2, Di + 3, Di + 4).
The default is for both events to happen immediately
after DONE is released and pulled high.

A commonly used design technique is to release
DONE one or more clock cycles before allowing the I/O
to become active. This allows other configuration
devices, such as PROMs, to be disconnected using the
DONE signal so that there is no bus contention when
the I/Os become active. In addition to controlling the
FPGA during start-up, other start-up techniques that
avoid contention include using isolation devices
between the FPGA and other circuits in the system,
reassigning I/O locations, and maintaining I/Os as
3-stated outputs until contentions are resolved.

Each of these start-up options can be selected during
bit stream generation in ORCA Foundry, using
Advanced Options. For more information, please see
the ORCA Foundry documentation.

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

FPGA States of Operation

(continued)

Reconfiguration

To reconfigure the FPGA when the device is operating
in the system, a low pulse is input into PRGM or a pro-
gram command is sent to the system bus. The configu-
ration data in the FPGA is cleared, and the I/Os not
used for configuration are 3-stated. The FPGA then
samples the mode select inputs and begins reconfigu-
ration. When reconfiguration is complete, DONE is
released, allowing it to be pulled high.

Partial Reconfiguration

All ORCA device families have been designed to allow
a partial reconfiguration of the FPGA at any time. This
is done by setting a bit stream option in the previous
configuration sequence that tells the FPGA to not reset
all of the configuration RAM during a reconfiguration.
Then only the configuration frames that are to be modi-
fied need to be rewritten, thereby reducing the configu-
ration time.

Other bit stream options are also available that allow
one portion of the FPGA to remain in operation while a
partial reconfiguration is being done. If this is done, the
user must be careful to not cause contention between
the two configurations (the bit stream resident in the
FPGA and the partial reconfiguration bit stream) as the
second reconfiguration bit stream is being loaded.

Other Configuration Options

There are many other configuration options available to
the user that can be set during bit stream generation in
ORCA Foundry. These include options to enable
boundary scan and/or the MPI and/or the programma-
ble PLL blocks, readback options, and options to con-
trol and use the internal oscillator after configuration.

Other useful options that affect the next configuration
(not the current configuration process) include options
to disable the global set/reset during configuration, dis-
able the 3-state of I/Os during configuration, and dis-
able the reset of internal RAMs during configuration to
allow for partial configurations (see above). For more
information on how to set these and other configuration
options, please see the ORCA Foundry documenta-
tion.

5-5759(F)

Figure 36. Serial Configuration Data Format--Autoincrement Mode

5-5760(F)

Figure 37. Serial Configuration Data Format--Explicit Mode

CONFIGURATION DATA

1 0

0 1

PREAMBLE LENGTH

ID FRAME

CONFIGURATION

POSTAMBLE

CONFIGURATION HEADER

0 0

COUNT

DATA FRAME 1

DATA FRAME 2

PREAMBLE LENGTH

ID FRAME

CONFIGURATION CONFIGURATION

POSTAMBLE

CONFIGURATION HEADER

ADDRESS

0 0

COUNT

DATA FRAME 1

DATA FRAME 2

FRAME 2

FRAME 1

CONFIGURATION DATA

1 0

0 1

0 0

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

FPGA States of Operation

(continued)

Table 36A. Configuration Frame Format and Contents

Table 36B. Configuration Frame Format and Contents for Embedded Block RAM

Frame

Contents

Description

Header

11110010

Preamble for generic FPGA.

24-bit length count

Configuration bit stream length.

11111111

8-bit trailing header.

ID Frame

0101 1111 1111 1111

ID frame header.

44 reserved bits

Reserved bits set to 0.

Part ID

20-bit part ID.

Checksum

8-bit checksum.

11111111

8 stop bits (high) to separate frames.

FPGA Header

1111 0010

This is a new mandatory header for generic portion.

11111111

8 stop bits (high) to separate frames.

FPGA
Address
Frame

Address frame header.

14-bit address

14-bit address of generic FPGA.

Checksum

8-bit checksum.

11111111

Eight stop bits (high) to separate frames.

FPGA
Data Frame

Data frame header, same as generic.

Alignment bits

String of 0 bits added to frame to reach a byte boundary.

Data bits

Number of data bits depends upon device.

Checksum

8-bit checksum.

11111111

Eight stop bits (high) to separate frames.

Postamble
for Generic
FPGA

00 or 10

Postamble header, 00 = finish, 10 = more bits coming.

11111111 111111

Dummy address.

11111111 11111111

16 stop bits (high).

Frame

Contents

Description

RAM Header

11110001

A mandatory header for RAM bit stream portion.

11111111

8 stop bits (high) to separate frames.

RAM
Address
Frame

Address frame header, same as generic.

6-bit address

6-bit address of RAM blocks.

Checksum

8-bit checksum.

11111111

Eight stop bits (high) to separate frames.

RAM
Data Frame

Data frame header, same as generic.

000000

Six of 0 bits added to reach a byte boundary.

512x18 data bits

Exact number of bits in a RAM block.

Checksum

8-bit checksum.

11111111

Eight stop bits (high) to separate frames.

Postamble
for RAM

00 or 10

Postamble header. 00 = finish, 10 = more bits coming.

111111

Dummy address.

11111111 11111111

16 stop bits (high).

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

FPGA States of Operation

(continued)

Table 37. Configuration Frame Size

Devices

OR4E2

OR4E4

OR4E6

OR4E10

OR4E14

Number of Frames

1796

2436

3076

3972

4356

Data Bits/Frame

900

1284

1540

1924

2372

Maximum Configuration Data

(Number of bits/frame x Number of frames)

1,610,400

3,127,824

4,737,040

7,642,128

10,332,432

Maximum PROM Size (bits)

(add configuration header and postamble)

1,161,648

3,128,072

4,737,288

7,642,376

10,332,680

Bit Stream Error Checking

There are three different types of bit stream error
checking performed in the ORCA Series 4 FPGAs:
ID frame, frame alignment, and CRC checking.

The ID data frame is sent to a dedicated location in the
FPGA. This ID frame contains a unique code for the
device for which it was generated. This device code is
compared to the internal code of the FPGA. Any differ-
ences are flagged as an ID error. This frame is auto-
matically created by the bit stream generation program
in ORCA Foundry.

Each data and address frame in the FPGA begins with
a frame start pair of bits and ends with eight stop bits
set to 1. If any of the previous stop bits were a 0 when a
frame start pair is encountered, it is flagged as a frame
alignment error.

Error checking is also done on the FPGA for each
frame by means of a checksum byte. If an error is found
on evaluation of the checksum byte, then a checksum/
parity error is flagged. The checksum is the XOR of all
the data bytes, from the start of frame up to and includ-
ing the bytes before the checksum. It applies to the ID,
address, and data frames.

When any of the three possible errors occur, the FPGA
is forced into an idle state, forcing INIT low. The FPGA
will remain in this state until either the

RESET

PRGM

pins are asserted. Also the pin CFQ_IRQ/MPI_IRQ is
forced low to signal the error and the specific type of bit
stream error is written to one of the system bus regis-
ters by the FPGA configuration logic. The

PGRM

bit of

the system bus control register can also be used to
reset out of the error condition and restart configura-
tion.

FPGA Configuration Modes

There are twelve methods for configuring the FPGA.
Eleven of the configuration modes are selected on the
M0, M1, and M2 inputs. The twelfth configuration mode
is accessed through the boundary-scan interface. A
fourth input, M3, is used to select the frequency of the
internal oscillator, which is the source for CCLK in
some configuration modes. The nominal frequencies of
the internal oscillator are 1.25 MHz and 10 MHz. The
1.25 MHz frequency is selected when the M3 input is
unconnected or driven to a high state.

There are three basic FPGA configuration modes:
master, slave, and peripheral. The configuration data
can be transmitted to the FPGA serially or in parallel
bytes. As a master, the FPGA provides the control sig-
nals out to strobe data in. As a slave device, a clock is
generated externally and provided into the CCLK input.
In the three peripheral modes, the FPGA acts as a
microprocessor peripheral. Table 38 lists the functions
of the configuration mode pins.

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

FPGA Configuration Modes

(continued)

Table 38. Configuration Modes

Master Parallel Mode

The master parallel configuration mode is generally used to interface to industry-standard, bytewide memory. Fig-
ure 38 provides the connections for master parallel mode. The FPGA outputs an 18-bit address on A[17:0] to mem-
ory and reads 1 byte of configuration data on the rising edge of RCLK. The parallel bytes are internally serialized
starting with the least significant bit, D0. D[7:0] of the FPGA can be connected to D[7:0] of the microprocessor only
if a standard prom file format is used. If a .bit or .rbt file is used from ORCA Foundry, then the user must mirror the
bytes in the .bit or .rbt file or leave the .bit or .rbt file unchanged and connect D[7:0] of the FPGA to D[0:7] of the
microprocessor.

5-9738(F)

Figure 38. Master Parallel Configuration Schematic

CCLK

Configuration Mode

Data

Output. High-frequency. Master Serial

Serial

Output. High-frequency. Master Parallel

8-bit

Output. High-frequency. Asynchronous Peripheral

8-bit

NA.

Reserved

Output. Low-frequency. Master Serial

Serial

Input.

Slave Parallel

8-bit

Output.

MPC860 MPI

8-bit

Output.

MPC860 MPI

16-bit

Output. Low-frequency. Master Parallel

8-bit

Output. Low-frequency. Asynchronous Peripheral

8-bit

Output.

MPC860 MPI

32-bit

Input.

Slave Serial

Serial

A[21:0]

D[7:0]

EPROM

PRGM

A[21:0]

D[7:0]

DONE

ORCA

SERIES

FPGA

DOUT

CCLK

HDC

LDC

RCLK

PROGRAM

OR GND

TO DAISY-

CHAINED

DEVICES

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

FPGA Configuration Modes

(continued)

In master parallel mode, the starting memory address
is 00000 hex, and the FPGA increments the address
for each byte loaded.

One master mode FPGA can interface to the memory
and provide configuration data on DOUT to additional
FPGAs in a daisy-chain. The configuration data on
DOUT is provided synchronously with the falling edge
of CCLK. The frequency of the CCLK output is eight
times that of RCLK.

Master Serial Mode

In the master serial mode, the FPGA loads the configu-
ration data from an external serial ROM. The configura-
tion data is either loaded automatically at start-up or on
a

PRGM

command to reconfigure. Serial PROMs can

be used to configure the FPGA in the master serial
mode.

Configuration in the master serial mode can be done at
powerup and/or upon a configure command. The sys-
tem or the FPGA must activate the serial ROM's

RESET

/OE and

inputs. At powerup, the FPGA and

serial ROM each contain internal power-on reset cir-
cuitry that allows the FPGA to be configured without
the system providing an external signal. The power-on
reset circuitry causes the serial ROM's internal address
pointer to be reset. After powerup, the FPGA automati-
cally enters its initialization phase.

The serial ROM/FPGA interface used depends on such
factors as the availability of a system reset pulse, avail-
ability of an intelligent host to generate a configure
command, whether a single serial ROM is used or mul-
tiple serial ROMs are cascaded, whether the serial
ROM contains a single or multiple configuration pro-
grams, etc. Because of differing system requirements
and capabilities, a single FPGA/serial ROM interface is
generally not appropriate for all applications.

Data is read in the FPGA sequentially from the serial
ROM. The DATA output from the serial ROM is con-
nected directly into the DIN input of the FPGA. The
CCLK output from the FPGA is connected to the CLK
input of the serial ROM. During the configuration pro-
cess, CCLK clocks one data bit on each rising edge.

Since the data and clock are direct connects, the
FPGA/serial ROM design task is to use the system or
FPGA to enable the

RESET

/OE and

of the serial

ROM(s). There are several methods for enabling the

serial ROM's

RESET

/OE and

inputs. The serial

ROM's

RESET

/OE is programmable to function with

RESET active-high and

active-low or

RESET

active-

low and OE active-high.

In Figure 39, serial ROMs are cascaded to configure
multiple daisy-chained FPGAs. The host generates a
500 ns low pulse into the FPGA's

PRGM

input. The

FPGA's

INIT

input is connected to the serial ROMs'

RESET

/OE input, which has been programmed to

function with

RESET

active-low and OE active-high.

The FPGA DONE is routed to the

pin. The low on

DONE enables the serial ROMs. At the completion of
configuration, the high on the FPGA's DONE disables
the serial ROM.

Serial ROMs can also be cascaded to support the con-
figuration of multiple FPGAs or to load a single FPGA
when configuration data requirements exceed the
capacity of a single serial ROM. After the last bit from
the first serial ROM is read, the serial ROM outputs

CEO

low and 3-states the DATA output. The next serial

ROM recognizes the low on

input and outputs con-

figuration data on the DATA output. After configuration
is complete, the FPGA's DONE output into

disables

the serial ROMs.

This FPGA/serial ROM interface is not used in applica-
tions in which a serial ROM stores multiple configura-
tion programs. In these applications, the next
configuration program to be loaded is stored at the
ROM location that follows the last address for the previ-
ous configuration program. The reason the interface in
Figure 39 will not work in this application is that the low
output on the

INIT

signal would reset the serial ROM

address pointer, causing the first configuration to be
reloaded.

In some applications, there can be contention on the
FPGA's DIN pin. During configuration, DIN receives
configuration data, and after configuration, it is a user
I/O. If there is contention, an early DONE at start-up
(selected in ORCA Foundry) may correct the problem.
An alternative is to use

LDC

to drive the serial ROM's

pin. In order to reduce noise, it is generally better to

run the master serial configuration at 1.25 MHz (M3 pin
tied high), rather than 10 MHz, if possible.

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

FPGA Configuration Modes

(continued)

5-4456(F)

Figure 39. Master Serial Configuration Schematic

Asynchronous Peripheral Mode

Figure 40 shows the connections needed for the asynchronous peripheral mode. In this mode, the FPGA system
interface is similar to that of a microprocessor-peripheral interface. The microprocessor generates the control sig-
nals to write an 8-bit byte into the FPGA. The FPGA control inputs include active-low

CS0

and active-high CS1 chip

selects and

and

inputs. The chip selects can be cycled or maintained at a static level during the configura-

tion cycle. Each byte of data is written into the FPGA's D[7:0] input pins. D[7:0] of the FPGA can be connected to
D[7:0] of the microprocessor only if a standard prom file format is used. If a .bit or .rbt file is used from ORCA
Foundry, then the user must mirror the bytes in the .bit or .rbt file or leave the .bit or .rbt file unchanged and connect
D[7:0] of the FPGA to D[0:7] of the microprocessor.

The FPGA provides an RDY/

BUSY

status output to indicate that another byte can be loaded. A low on RDY/

BUSY

indicates that the double-buffered hold/shift registers are not ready to receive data, and this pin must be monitored
to go high before another byte of data can be written. The shortest time RDY/

BUSY

is low occurs when a byte is

loaded into the hold register and the shift register is empty, in which case the byte is immediately transferred to the
shift register. The longest time for RDY/

BUSY

to remain low occurs when a byte is loaded into the holding register

and the shift register has just started shifting configuration data into configuration RAM.

The RDY/

BUSY

status is also available on the D7 pin by enabling the chip selects, setting

high, and applying

low, where the

input provides an output enable for the D7 pin when

is low. The D[6:0] pins are not enabled to

drive when

is low and, therefore, only act as input pins in asynchronous peripheral mode. Optionally, the user

can ignore the RDY/

BUSY

status and simply wait until the maximum time it would take for the RDY/

BUSY

line to go

high, indicating the FPGA is ready for more data, before writing the next data byte.

DIN

M2
M1
M0

ORCA

SERIES

FPGA

CCLK

DOUT

TO DAISY-
CHAINED
DEVICES

DATA

CLK

CEO

DATA

CLK

RESET/OE

CEO

TO MORE

SERIAL ROMs

AS NEEDED

DONE

PRGM

PROGRAM

RESET/OE

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

FPGA Configuration Modes

(continued)

5-9739(F)

Figure 40. Asynchronous Peripheral Configuration

Microprocessor Interface Mode

The built-in MPI in Series 4 FPGAs is designed for use in configuring the FPGA.

Figure 41 shows the glueless

interface for FPGA configuration and readback from the PowerPC processor. When enabled by the mode pins, the
MPI

handles all configuration/readback control and handshaking with the host processor. For single FPGA configu-

ration, the host sets the configuration control register

PRGM

bit to zero then back to a one and, after reading that

the configuration write data acknowledge register is high, transfers data 8, 16, or 32 bits at a time to the FPGA's
D[#:0] input pins. If configuring multiple FPGAs through daisy-chain operation is desired, the SYS_DAISY bit must
be set in the configuration control register of the MPI.

There are two options for using the host interrupt request in configuration mode. The configuration control register
offers control bits to enable the interrupt on either a bit stream error or to notify the host processor when the FPGA
is ready for more configuration data. The MPI status register may be used in conjunction with, or in place of, the
interrupt request options. The status register contains a 2-bit field to indicate the bit stream error status. As previ-
ously mentioned, there is also a bit to indicate the MPI's readiness to receive another byte of configuration data. A
flow chart of the MPI configuration process is shown in Figure 42.

MICRO-

PRGM

ORCA

SERIES

FPGA

DOUT

CCLK

HDC

LDC

TO DAISY-

CHAINED

DEVICES

PROCESSOR

D[7:0]
RDY/BUSY
INIT
DONE

ADDRESS

DECODE LOGIC

BUS

CONTROLLER

CS0
CS1

RD
WR

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

FPGA Configuration Modes

(continued)

Slave Serial Mode

The slave serial mode is primarily used when multiple FPGAs are configured in a daisy chain (see the Daisy Chain-
ing section). It is also used on the FPGA evaluation board that interfaces to the download cable. A device in the
slave serial mode can be used as the lead device in a daisy chain. Figure 44 shows the connections for the slave
serial configuration mode.

The configuration data is provided into the FPGA's DIN input synchronous with the configuration clock CCLK input.
After the FPGA has loaded its configuration data, it retransmits the incoming configuration data on DOUT. CCLK is
routed into all slave serial mode devices in parallel.

Multiple slave FPGAs can be loaded with identical configurations simultaneously. This is done by loading the con-
figuration data into the DIN inputs in parallel.

5-4485(F)

Figure 44. Slave Serial Configuration Schematic

Slave Parallel Mode

The slave parallel mode is essentially the same as the slave serial mode except that 8 bits of data are input on pins
D[7:0] for each CCLK cycle. Due to 8 bits of data being input per CCLK cycle, the DOUT pin does not contain a
valid bit stream for slave parallel mode. As a result, the lead device cannot be used in the slave parallel mode in a
daisy-chain configuration.

Figure 45

is a schematic of the connections for the slave parallel configuration mode. WR and CS0 are active-low

chip select signals, and CS1 is an active-high chip select signal. These chip selects allow the user to configure mul-
tiple FPGAs in slave parallel mode using an 8-bit data bus common to all of the FPGAs. These chip selects can
then be used to select the FPGAs to be configured with a given bit stream. The chip selects must be active for each
valid CCLK cycle until the device has been completely programmed. They can be inactive between cycles but must
meet the setup and hold times for each valid positive CCLK. D[7:0] of the FPGA can be connected to D[7:0] of the
microprocessor only if a standard prom file format is used. If a .bit or .rbt file is used from ORCA Foundry, then the
user must mirror the bytes in the .bit or .rbt file or leave the .bit or .rbt file unchanged and connect D[7:0] of the
FPGA to D[0:7] of the microprocessor.

MICRO-

PROCESSOR

DOWNLOAD

CABLE

M2
M1
M0

HDC

SERIES

FPGA

LDC

CCLK

PRGM

DOUT

TO DAISY-
CHAINED
DEVICES

DONE

DIN

INIT

ORCA

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

FPGA Configuration Modes

(continued)

5-4487(F)

Figure 45. Slave Parallel Configuration Schematic

Daisy Chaining

Multiple FPGAs can be configured by using a daisy chain of the FPGAs. Daisy chaining uses a lead FPGA and one
or more FPGAs configured in slave serial mode. The lead FPGA can be configured in any mode except slave
parallel mode.

All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in on
positive CCLK and out on negative CCLK edges.

An upstream FPGA that has received the preamble and length count outputs a high on DOUT until it has received
the appropriate number of data frames so that downstream FPGAs do not receive frame start bit pairs. After loading
and retransmitting the preamble and length count to a daisy chain of slave devices, the lead device loads its config-
uration data frames. The loading of configuration data continues after the lead device has received its configuration
data if its internal frame bit counter has not reached the length count. When the configuration RAM is full and the
number of bits received is less than the length count field, the FPGA shifts any additional data out on DOUT.

The configuration data is read into DIN of slave devices on the positive edge of CCLK, and shifted out DOUT on the
negative edge of CCLK. Figure 46 shows the connections for loading multiple FPGAs in a daisy-chain configura-
tion.

The generation of CCLK for the daisy-chained devices that are in slave serial mode differs depending on the config-
uration mode of the lead device. A master parallel mode device uses its internal timing generator to produce an
internal CCLK at eight times its memory address rate (RCLK). The asynchronous peripheral mode device outputs
eight CCLKs for each write cycle. If the lead device is configured in slave mode, CCLK must be routed to the lead
device and to all of the daisy-chained devices.

MICRO-

PROCESSOR

SYSTEM

D[7:0]

DONE

CCLK

CS1

HDC

LDC

INIT

PRGM

CS0

SERIES

FPGA

ORCA

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

FPGA Configuration Modes

(continued)

5-4488(F

Figure 46. Daisy-Chain Configuration Schematic

EPROM

PROGRAM

D[7:0]

OE
CE

A[17:0]

D[7:0]

DONE

M2
M1
M0

DONE

HDC

LDC

RCLK

CCLK

DOUT

DIN

DOUT

DIN

CCLK

DONE

DOUT

INIT

CCLK

GND

PRGM

M2
M1
M0

PRGM

M2
M1
M0

HDC

LDC

RCLK

HDC

LDC

RCLK

ORCA

SERIES

FPGA

SLAVE 2

ORCA

SERIES

FPGA

MASTER

ORCA

SERIES

FPGA

SLAVE 1

As seen in Figure 46, the INIT pins for all of the FPGAs
are connected together. This is required to guarantee
that powerup and initialization will work correctly. In
general, the DONE pins for all of the FPGAs are also
connected together as shown to guarantee that all of
the FPGAs enter the start-up state simultaneously. This
may not be required, depending upon the start-up
sequence desired.

Daisy-Chaining with Boundary Scan

Multiple FPGAs can be configured through the JTAG
ports by using a daisy chain of the FPGAs. This daisy-
chaining operation is available upon initial configuration
after powerup, after a power-on reset, after pulling the
program pin to reset the chip, or during a reconfigura-
tion if the EN_JTAG RAM has been set.

All daisy-chained FPGAs are connected in series.
Each FPGA reads and shifts the preamble and length
count in on the positive TCK and out on the negative
TCK edges.

An upstream FPGA that has received the preamble
and length count outputs a high on TDO until it has
received the appropriate number of data frames so that
downstream FPGAs do not receive frame start bit
pairs. After loading and retransmitting the preamble
and length count to a daisy chain of downstream
devices, the lead device loads its configuration data
frames.

The loading of configuration data continues after the
lead device had received its configuration read into TDI
of downstream devices on the positive edge of TCK,
and shifted out TDO on the negative edge of TCK.

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings
can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the
device is not implied at these or any other conditions in
excess of those given in the operations sections of this
data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.

The ORCA Series FPGAs include circuitry designed to
protect the chips from damaging substrate injection
currents and to prevent accumulations of static charge.
Nevertheless, conventional precautions should be
observed during storage, handling, and use to avoid
exposure to excessive electrical stress.

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Absolute Maximum Ratings

(continued)

Table 39. Absolute Maximum Ratings

Recommended Operating Conditions

Table 40. Recommended Operating Conditions

Note: The maximum recommended junction temperature (T

) during operation is 125 °C.

Electrical Characteristics

Table 41. Electrical Characteristics

* The pull-up resistor will externally pull the pin to a level 1.0 V below V

IO.

Parameter

Symbol

Min

Max

Unit

Storage Temperature

stg

150

°C

Power Supply Voltage with Respect to Ground

4.2

Input Signal with Respect to Ground

0.3

+ 0.3

Signal Applied to High-impedance Output

0.3

+ 0.3

Maximum Package Body Temperature

220

°C

Parameter

Symbol

Min

Max

Unit

Power Supply Voltage with Respect to Ground

2.7

3.6

1.4

1.6

Input Voltages

0.3

+ 0.3

Junction Temperature

125

°C

Parameter

Symbol

Test Conditions

Min

Max

Unit

Input Leakage Current

= max, V

= V

or V

µA

Standby Current:

OR4E2
OR4E4
OR4E6
OR4E10
OR4E14

DDSB

= 25 °C, V

= 3.3 V

internal oscillator running, no output loads,

inputs V

or GND (after configuration)

--
--
--
--
--

TBD
TBD
TBD
TBD
TBD

mA
mA
mA
mA
mA

Standby Current:

OR4E2
OR4E4
OR4E6
OR4E10
OR4E14

DDSB

= 25 °C, V

= 3.3 V

internal oscillator stopped, no output loads,

inputs V

or GND (after configuration)

--
--
--
--
--

TBD
TBD
TBD
TBD
TBD

mA
mA
mA
mA
mA

Powerup Current:

OR4E2
OR4E4
OR4E6
OR4E10
OR4E14

Ipp

Power supply current at approximately 1 V, within

a recommended power supply ramp rate of

1 ms--200 ms

TBD
TBD
TBD
TBD
TBD

--
--
--
--
--

mA
mA
mA
mA
mA

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Electrical Characteristics

(continued)

Table 41. Electrical Characteristics (continued)

* The pull-up resistor will externally pull the pin to a level 1.0 V below V

IO.

Parameter

Symbol

Test Conditions

Min

Max

Unit

Data Retention Voltage

33)

= 25 °C

2.3

Input Capacitance

= 25 °C, V

= 3.3 V

Test frequency = 1 MHz

Output Capacitance

OUT

= 25 °C, V

= 3.3 V

Test frequency = 1 MHz

DONE Pull-up Resistor*

DONE

100

M[3:0] Pull-up Resistor*

100

I/O Pad Static Pull-up

Current*

IO = 3.6 V, V

= V

, T

= 0 °C

14.4

50.9

µA

I/O Pad Static

Pull-down Current

IO = 3.6 V, V

= V

, T

= 0 °C

103

µA

I/O Pad Pull-up Resistor*

IO = all, V

= V

, T

= 0 °C

100

I/O Pad Pull-down

Resistor

IO = all, V

= V

, T

= 0 °C

DONE Pull-up Resistor*

DONE

100

M[3:0] Pull-up Resistor*

100

I/O Pad Static Pull-up

Current*

= 3.6 V, V

= V

, T

= 0 °C

14.4

50.9

µA

I/O Pad Static

Pull-down Current

IO = 3.6 V, V

= V

, T

= 0 °C

103

µA

I/O Pad Pull-up

Resistor*

IO = all, V

= V

, T

= 0 °C

100

I/O Pad Pull-down

Resistor

IO = all, V

= V

, T

= 0 °C

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Pin Information

Pin Descriptions

This section describes the pins found on the Series 4 FPGAs. Any pin not described in this table is a user-program-
mable I/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled.
If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled
after configuration.

Table 42. Pin Descriptions

Symbol

I/O

Description

Dedicated Pins

-- 3 V positive power supply.

-- 1.5 V positive power supply for internal logic.

DDIO

-- Positive power supply used by I/O banks.

GND

-- Ground supply.

PLL_VF

-- Dedicated pins for PLL filtering.

PTEMP

Temperature-sensing diode pin. Dedicated input.

RESET

During configuration,

RESET

forces the restart of configuration and a pull-up is enabled.

After configuration,

RESET

can be used as a general FPGA input or as a direct input,

which causes all PLC latches/FFs to be asynchronously set/reset.

CCLK

In the master and asynchronous peripheral modes, CCLK is an output which strobes con-
figuration data in. In the slave or readback after configuration, CCLK is input synchronous
with the data on DIN or D[7:0]. CCLK is an output for daisy-chain operation when the lead
device is in master, peripheral, or system bus modes.

DONE

As an input, a low level on DONE delays FPGA start-up after configuration.*

As an active-high, open-drain output, a high level on this signal indicates that configura-
tion is complete. DONE has an optional pull-up resistor.

PRGM

is an active-low input that forces the restart of configuration and resets the bound-

ary-scan circuitry. This pin always has an active pull-up.

RD_CFG

This pin must be held high during device initialization until the

INIT

pin goes high. This pin

always has an active pull-up.

During configuration,

RD_CFG

is an active-low input that activates the TS_ALL function

and 3-states all of the I/O.

After configuration,

RD_CFG

can be selected (via a bit stream option) to activate the

TS_ALL function as described above, or, if readback is enabled via a bit stream option, a
high-to-low transition on

RD_CFG

will initiate readback of the configuration data, including

PFU output states, starting with frame address 0.

RD_DATA/TDO

RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configura-
tion data out. If used in boundary-scan, TDO is test data out.

CFG_IRQ/MPI_IRQ

During JTAG, slave, master, and asynchronous peripheral configuration assertion by the
FPGA on this

CFG_IRQ

(active-low) indicates an error or errors for block RAM or FPSC ini-

tialization.
MPI

active-low interrupt request output.

* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release

is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Pin Information

(continued)

Table 42. Pin Descriptions (continued)

Symbol

I/O

Description

Special-Purpose Pins (Can also be used as a general I/O)

M[3:0]

During powerup and initialization, M0--M3 are used to select the configuration mode with
their values latched on the rising edge of INIT. During configuration, a pull-up is enabled.

I/O After configuration, these pins are user-programmable I/O.*

PLL_CK[0:7]

I/O Dedicated PCM clock pins. These pins are a user-programmable I/O pins if not used by

PLLs.

P[TBTR]CLK[1:0][

TC]

I/O Pins dedicated for the primary clock. Input pins on the middle of each side with differential

pairing. They may be used as general I/O pins if not needed for clocking purposes.

TDI, TCK, TMS

If boundary-scan is used, these pins are test data in, test clock, and test mode select
inputs. If boundary-scan is not selected, all boundary-scan functions are inhibited once
configuration is complete. Even if boundary-scan is not used, either TCK or TMS must be
held at logic 1 during configuration. Each pin has a pull-up enabled during configuration.

I/O After configuration, these pins are user-programmable I/O.*

RDY/BUSY/RCLK

During configuration in peripheral mode, RDY/RCLK indicates another byte can be written
to the FPGA. If a read operation is done when the device is selected, the same status is
also available on D7 in asynchronous peripheral mode.

After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*

I/O During the master parallel configuration mode, RCLK is a read output signal to an external

memory. This output is not normally used.

HDC

High during configuration is output high until configuration is complete. It is used as a con-
trol output, indicating that configuration is not complete.

I/O After configuration, this pin is a user-programmable I/O pin.*

LDC

Low during configuration is output low until configuration is complete. It is used as a control
output, indicating that configuration is not complete.

I/O After configuration, this pin is a user-programmable I/O pin.*

INIT

I/O INIT is a bidirectional signal before and during configuration. During configuration, a pull-up

is enabled, but an external pull-up resistor is recommended. As an active-low, open-drain
output, INIT is held low during power stabilization and internal clearing of memory. As an
active-low input, INIT holds the FPGA in the wait-state before the start of configuration.
After configuration, this pin is a user-programmable I/O pin.*

CS0, CS1

CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor
configuration modes. The FPGA is selected when CS0 is low and CS1 is high. During con-
figuration, a pull-up is enabled.

I/O After configuration, these pins are user-programmable I/O pins.*

RD/MPI_STRB

RD is used in the asynchronous peripheral configuration mode. A low on RD changes D7
into a status output. As a status indication, a high indicates ready, and a low indicates busy.
WR and RD should not be used simultaneously. If they are, the write strobe overrides.

This pin is also used as the MPI data transfer strobe.

I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*

* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE

release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the acti-
vation of all user I/Os) is controlled by a second set of options.

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Special-Purpose Pins (continued)

A[17:0]

During MPI mode, the A[17:0] are used as the address bus driven by the PowerPC bus
master utilizing the least significant bits of the PowerPC 32-bit address.

During master parallel configuration mode, A[17:0] address the configuration EPROM. In
MPI mode, many of the A[n] pins have alternate uses as described below. See the Special
Function Blocks section for more MPI information. During configuration, if not in master par-
allel or an MPI configuration mode, these pins are 3-stated with a pull-up enabled.

MPI_BURST

A[21] is used as the MPI_BURST. It is driven low to indicate a burst transfer is in progress.
Driven high indicates that the current transfer is not a burst.

MPI_BDIP

A[22] is used as the MPI_BDIP. It is driven by the PowerPC processor. Assertion of this pin
indicates that the second beat in front of the current one is requested by the master.
Negated before the burst transfer ends to abort the burst data phase.

MPI_TSZ[1:0]

A[19:18] are used as the MPI_TSZ[1:0] signals and are driven by the bus master to indicate
the data transfer size for the transaction. Set 01 for byte, 10 for half-word, and 00 for word.

During master parallel mode A[21:0], address the configuration EPROMs up to 4M bytes.

A[21:0]

If not used for MPI, these pins are user-programmable I/O pins.*

MPI_ACK

In PowerPC mode MPI operation, this is driven low indicating the MPI received the data on
the write cycle or returned data on a read cycle.

MPI_CLK

This is the PowerPC synchronous, positive-edge bus clock used for the MPI interface. It can
be a source of the clock for the embedded system bus. If MPI is used, this can be the AMBA
bus clock.

MPI_TEA

A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on
the internal system bus for the current transaction.

MPI_RTRY

This pin requests the MPC860 to relinquish the bus and retry the cycle.

D[31:0]

I/O Selectable data bus width from 8, 16, 32 bits. Driven by the bus master in a write transac-

tion. Driven by MPI in a read transaction.

D[7:0] receive configuration data during master parallel, peripheral, and slave parallel con-
figuration modes and each pin has a pull-up enabled. During serial configuration modes, D0
is the DIN input.

D[7:3] output internal status for asynchronous peripheral mode when RD is low.

After configuration, the pins are user-programmable I/O pins.*

DP[3:0]

I/O Selectable parity bus width from 1, 2, 4-bit, DP[0] for D[7:0], DP[1] for D[15:8], DP[2] for

D[23:16], and DP[3] for D[32:24].

After configuration, this pin is a user-programmable I/O pin.*

DIN

During slave serial or master serial configuration modes, DIN accepts serial configuration
data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input.
During configuration, a pull-up is enabled.

I/O After configuration, this pin is a user-programmable I/O pin.*

DOUT

During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained
slave devices. Data out on DOUT changes on the rising edge of CCLK.

I/O After configuration, DOUT is a user-programmable I/O pin.*

Symbol

I/O

Description

* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE

Pin Information

(continued)

Table 42. Pin Descriptions (continued)

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Pin Information

(continued)

As shown in the Pair column, differential pairs and physical locations are numbered within each bank (e.g.,
L19C_A0 is the nineteenth pair in an associated bank). The C indicates complementary differential whereas a T
indicates true differential. The _A0 indicates the physical location of adjacent balls in either the horizontal or vertical
direction. Other physical indicators are as follows:

_A1 indicates one ball between pairs.

_A2 indicates two balls between pairs.

_D0 indicates balls are diagonally adjacent.

_D1 indicates diagonally adjacent separated by one physical ball.

REF

pins, shown in the Additional Function column, are associated to the bank and group (e.g., V

REF

_TL_01 is the

REF

for group one of the top left (TL) bank).

Table 44. 352-Pin PBGA Pinout

352

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

D12

PT11D

PT13D

PT18D

MPI_RTRY

L1C_D2

COMPLEMENT

B10

PT11C

PT13C

PT18C

MPI_ACK

L1T_D2

TRUE

A10

PT10D

PT12D

PT16D

L2C_A2

COMPLEMENT

D10

PT10C

PT12C

PT16C

L2T_A2

TRUE

PT10B

PT12B

PT15D

MPI_CLK

L3C_D0

COMPLEMENT

C10

PT10A

PT12A

PT15C

A21/MPI_BURST

L3T_D0

TRUE

PT9D

PT11D

PT14D

L4C_D0

COMPLEMENT

PT9C

PT11C

PT14C

L4T_D0

TRUE

PT9B

PT11B

PT13D

REF

_TL_02

L5C_D1

COMPLEMENT

PT9A

PT11A

PT13C

MPI_TEA

L5T_D1

TRUE

PT8B

PT9D

PT11D

REF

_TL_03

COMPLEMENT

PT7D

PT8D

PT10D

L6C_D2

COMPLEMENT

PT7C

PT8C

PT10C

TMS

L6T_D2

TRUE

PT7B

PT7D

PT9D

A20/MPI_BDIP

L7C_D2

COMPLEMENT

PT7A

PT7C

PT9C

A19/MPI_TSZ1

L7T_D2

TRUE

PT6D

PT8D

A18/MPI_TSZ0

L8C_D2

COMPLEMENT

PT6C

PT8C

L8T_D2

TRUE

PT5D

PT6D

L9C_A0

COMPLEMENT

PT5C

PT6C

L9T_A0

TRUE

PT4D

TDI

L10C_D2

COMPLEMENT

PT4C

TCK

L10T_D2

TRUE

PT2D

PLL_CK1C/PPLL

L11C_D2

COMPLEMENT

PT2C

PLL_CK1T/PPLL

L11T_D2

TRUE

PL2D

PLL_CK0C/

HPPLL

L12C_A1

COMPLEMENT

PL2C

PLL_CK0T/

HPPLL

L12T_A1

TRUE

PL3D

PL4D

L13C_A1

COMPLEMENT

PL3C

PL4C

L13T_A1

TRUE

PL4D

PL5D

PL6D

HDC

L14C_D1

COMPLEMENT

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

352

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

PL4C

PL5C

PL6C

LDC

L14T_D1

TRUE

PL5D

PL6D

PL8D

L15C_A1

COMPLEMENT

PL5C

PL6C

PL8C

L15T_A1

TRUE

PL5B

PL7D

PL9D

REF

_TL_09

L16C_A1

COMPLEMENT

PL5A

PL7C

PL9C

A17

L16T_A1

TRUE

PL6D

PL8D

PL10D

CS0

L17C_D1

COMPLEMENT

PL6C

PL8C

PL10C

CS1

L17T_D1

TRUE

PL7D

PL10D

PL12D

INIT

L18C_A1

COMPLEMENT

PL7C

PL10C

PL12C

DOUT

L18T_A1

TRUE

PL7B

PL11D

PL13D

REF

_TL_10

L19C_A0

COMPLEMENT

PL7A

PL11C

PL13C

A16

L19T_A0

TRUE

PRD_DATA

TDO

PRESET

PRD_CFG

PPRGRM

IO_TL

C11

IO_TL

PCFG_MPI_IRQ

CFG_IRQ/

MPI_IRQ

PCCLK

PDONE

A26

AC13

AC18

AC23

AC4

AC8

AD24

AA23

AA4

A19

PT21D

PT28D

PT35D

L1C_A1

COMPLEMENT

C19

PT21C

PT28C

PT35C

L1T_A1

TRUE

B18

PT20D

PT27D

PT34D

REF

_TC_01

L2C_A0

COMPLEMENT

A18

PT20C

PT27C

PT34C

L2T_A0

TRUE

B17

PT20B

PT27B

PT33D

L3C_D0

COMPLEMENT

C18

PT20A

PT27A

PT33C

L3T_D0

TRUE

A17

PT19D

PT26D

PT32D

L4C_A2

COMPLEMENT

D17

PT19C

PT26C

PT32C

REF

_TC_02

L4T_A2

TRUE

Pin Information

(continued)

Table 44. OR4E6 352-Pin PBGA Pinout (continued)

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

352

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

B16

PT18D

PT25D

PT30D

L5C_D0

COMPLEMENT

C17

PT18C

PT25C

PT30C

L5T_D0

TRUE

B15

PT18B

PT24D

PT29D

L6C_A0

COMPLEMENT

A15

PT18A

PT24C

PT29C

REF

_TC_03

L6T_A0

TRUE

C16

PT17D

PT23D

PT28D

L7C_D1

COMPLEMENT

B14

PT17C

PT23C

PT28C

L7T_D1

TRUE

D15

PT16D

PT21D

PT26D

L8C_D2

COMPLEMENT

A14

PT16C

PT21C

PT26C

L8T_D2

TRUE

C15

PT15D

PT19D

PT24D

L9C_D1

COMPLEMENT

B13

PT15C

PT19C

PT24C

REF

_TC_04

L9T_D1

TRUE

A13

PT14D

PT18D

PT23D

PTCK1C

L10C_D1

COMPLEMENT

C14

PT14C

PT18C

PT23C

PTCK1T

L10T_D1

TRUE

B12

PT13D

PT17D

PT22D

PTCK0C

L11C_D0

COMPLEMENT

C13

PT13C

PT17C

PT22C

PTCK0T

L11T_D0

TRUE

A12

PT13B

PT16D

PT21D

REF

_TC_05

L12C_D0

COMPLEMENT

B11

PT13A

PT16C

PT21C

L12T_D0

TRUE

C12

PT12B

PT14D

PT19D

L13C_D1

COMPLEMENT

A11

PT12A

PT14C

PT19C

REF

_TC_06

L13T_D1

TRUE

A16

IO_TC

D13

IO_TC

R15

R16

T11

T12

T13

T14

T15

T16

T23

J24

PR8C

PR11C

PR13C

L1T_D1

TRUE

G25

PR8D

PR11D

PR13D

REF

_TR_01

L1C_D1

COMPLEMENT

H23

PR7A

PR10C

PR12C

L2T_D2

TRUE

G26

PR7B

PR10D

PR12D

L2C_D2

COMPLEMENT

H24

PR7C

PR9C

PR11C

L3T_D1

TRUE

F25

PR7D

PR9D

PR11D

L3C_D1

COMPLEMENT

G23

PR6A

PR8C

PR10C

L4T_D2

TRUE

F26

PR6B

PR8D

PR10D

L4C_D2

COMPLEMENT

E25

PR6C

PR7C

PR9C

REF

_TR_02

L5T_A0

TRUE

E26

PR6D

PR7D

PR9D

L5C_A0

COMPLEMENT

F24

PR5C

PR6C

PR7C

L6T_D1

TRUE

D25

PR5D

PR6D

PR7D

REF

_TR_03

L6C_D1

COMPLEMENT

Pin Information

(continued)

Table 44. OR4E6 352-Pin PBGA Pinout (continued)

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

352

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

E23

PR4C

PR5C

L7T_D2

TRUE

D26

PR4D

PR5D

L7C_D2

COMPLEMENT

E24

PR3C

PLL_CK3T/

PLL1(1.554/

2.048 MHz)

L8T_D1

TRUE

C25

PR3D

PLL_CK3C/

PLL1(1.554/

2.048 MHz)

L8C_D1

COMPLEMENT

A24

PT27D

PT37D

PT47D

PLL_CK2C/PPLL

L9C_A0

COMPLEMENT

B23

PT27C

PT37C

PT47C

PLL_CK2T/PPLL

L9T_A0

TRUE

C23

PT26D

PT36D

PT45D

REF

_TR_05

L10C_A1

COMPLEMENT

A23

PT26C

PT36C

PT45C

L10T_A1

TRUE

B22

PT26B

PT35B

PT43D

L11C_A1

COMPLEMENT

D22

PT26A

PT35A

PT43C

L11T_A1

TRUE

C22

PT25D

PT34D

PT42D

REF

_TR_06

L12C_A1

COMPLEMENT

A22

PT25C

PT34C

PT42C

L12T_A1

TRUE

B21

PT24D

PT33D

PT40D

L13C_D1

COMPLEMENT

D20

PT24C

PT33C

PT40C

REF

_TR_07

L13T_D1

TRUE

A21

PT24B

PT32D

PT39D

L14C_D0

COMPLEMENT

B20

PT24A

PT32C

PT39C

L14T_D0

TRUE

A20

PT23D

PT31D

PT38D

L15C_A1

COMPLEMENT

C20

PT23C

PT31C

PT38C

REF

_TR_08

L15T_A1

TRUE

B19

PT22D

PT29D

PT36D

L16C_D1

COMPLEMENT

D18

PT22C

PT29C

PT36C

L16T_D1

TRUE

G24

IO_TR

D24

IO_TR

C26

A25

B24

PLL_VF

C21

IO_TR

P12

P13

P14

P15

P16

R11

R12

R13

R14

L23

V25

PR20C

PR29C

PR35C

L1T_A0

TRUE

Pin Information

(continued)

Table 44. OR4E6 352-Pin PBGA Pinout (continued)

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

352

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

V26

PR20D

PR29D

PR35D

L1C_A0

COMPLEMENT

U25

PR19C

PR28C

PR33C

REF

_CR_01

L2T_D0

TRUE

V24

PR19D

PR28D

PR33D

L2C_D0

COMPLEMENT

U23

PR18C

PR26A

PR31C

L3T_D1

TRUE

T25

PR18D

PR26B

PR31D

REF

_CR_02

L3C_D1

COMPLEMENT

U24

PR17A

PR25A

PR30C

L4T_D1

TRUE

T26

PR17B

PR25B

PR30D

L4C_D1

COMPLEMENT

R25

PR17C

PR25C

PR29C

L5T_A0

TRUE

R26

PR17D

PR25D

PR29D

REF

_CR_03

L5C_A0

COMPLEMENT

T24

PR16C

PR23C

PR27C

PRCK1T

L6T_D1

TRUE

P25

PR16D

PR23D

PR27D

PRCK1C

L6C_D1

COMPLEMENT

R23

PR15A

PR22C

PR26C

L7T_D2

TRUE

P26

PR15B

PR22D

PR26D

REF

_CR_04

L7C_D2

COMPLEMENT

N25

PR15C

PR21C

PR25C

L8T_A1

TRUE

N23

PR15D

PR21D

PR25D

L8C_A1

COMPLEMENT

N26

PR14A

PR20C

PR24C

PRCK0T

L9T_D1

TRUE

P24

PR14B

PR20D

PR24D

PRCK0C

L9C_D1

COMPLEMENT

M25

PR14C

PR19C

PR23C

REF

_CR_05

L10T_D0

TRUE

N24

PR14D

PR19D

PR23D

L10C_D0

COMPLEMENT

M26

PR13C

PR17C

PR21C

L11T_D0

TRUE

L25

PR13D

PR17D

PR21D

REF

_CR_06

L11C_D0

COMPLEMENT

M24

PR12A

PR16C

PR20C

L12T_D1

TRUE

L26

PR12B

PR16D

PR20D

L12C_D1

COMPLEMENT

K25

PR12C

PR15C

PR19C

L13T_D0

TRUE

L24

PR12D

PR15D

PR19D

L13C_D0

COMPLEMENT

K26

PR11B

PR14B

PR18D

COMPLEMENT

K23

PR11C

PR14C

PR17C

REF

_CR_07

L14T_D1

TRUE

J25

PR11D

PR14D

PR17D

L14C_D1

COMPLEMENT

K24

PR10C

PR13C

PR15C

L15T_D1

TRUE

J26

PR10D

PR13D

PR15D

L15C_D1

COMPLEMENT

H25

PR9C

PR12C

PR14C

REF

_CR_08

L16T_A0

TRUE

H26

PR9D

PR12D

PR14D

L16C_A0

COMPLEMENT

U26

IO_CR

R24

IO_CR

M23

IO_CR

M16

N11

N12

N13

N14

N15

N16

Pin Information

(continued)

Table 44. OR4E6 352-Pin PBGA Pinout (continued)

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

352

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

P11

F23

AE20

PB22A

PB30C

PB37C

L1T_D1

TRUE

AC19

PB22B

PB30D

PB37D

L1C_D1

COMPLEMENT

AF20

PB22C

PB31C

PB38C

REF

_BR_01

L2T_D1

TRUE

AD19

PB22D

PB31D

PB38D

L2C_D1

COMPLEMENT

AE21

PB23A

PB32C

PB39C

L3T_D1

TRUE

AC20

PB23B

PB32D

PB39D

L3C_D1

COMPLEMENT

AD20

PB23C

PB33C

PB40C

L4T_D1

TRUE

AE22

PB23D

PB33D

PB40D

REF

_BR_02

L4C_D1

COMPLEMENT

AF22

PB24C

PB34C

PB42C

TRUE

AD21

PB25A

PB35A

PB43A

TRUE

AE23

PB25C

PB35C

PB44C

L5T_D1

TRUE

AC22

PB25D

PB35D

PB44D

REF

_BR_03

L5C_D1

COMPLEMENT

AF23

PB26C

PB36C

PB45C

L6T_D1

TRUE

AD22

PB26D

PB36D

PB45D

L6C_D1

COMPLEMENT

AE24

PB27C

PB37C

PB47C

PLL_CK5T/PPLL

L7T_D0

TRUE

AD23

PB27D

PB37D

PB47D

PLL_CK5C/PPLL

L7C_D0

COMPLEMENT

AD26

PR26A

PR38A

PR46C

PLL_CK4T/PLL2

(155.52 MHz)

L8T_D0

TRUE

AC25

PR26B

PR38B

PR46D

PLL_CK4C/PLL2

(155.52 MHz)

L8C_D0

COMPLEMENT

AC24

PR25A

PR37C

PR44C

REF

_BR_05

L9T_A1

TRUE

AC26

PR25B

PR37D

PR44D

L9C_A1

COMPLEMENT

AB25

PR25C

PR36C

PR43C

L10T_A1

TRUE

AB23

PR25D

PR36D

PR43D

L10C_A1

COMPLEMENT

AB26

PR24C

PR35C

PR41C

REF

_BR_06

L11T_D0

TRUE

AA25

PR24D

PR35D

PR41D

L11C_D0

COMPLEMENT

Y23

PR23A

PR34C

PR40C

L12T_D0

TRUE

AA24

PR23B

PR34D

PR40D

L12C_D0

COMPLEMENT

AA26

PR23C

PR33C

PR39C

L13T_D0

TRUE

Y25

PR23D

PR33D

PR39D

REF

_BR_07

L13C_D0

COMPLEMENT

Y26

PR22A

PR32C

PR38C

L14T_A1

TRUE

Y24

PR22B

PR32D

PR38D

L14C_A1

COMPLEMENT

W25

PR22C

PR31C

PR37C

L15T_D1

TRUE

V23

PR22D

PR31D

PR37D

REF

_BR_08

L15C_D1

COMPLEMENT

W26

PR21C

PR30C

PR36C

L16T_A1

TRUE

W24

PR21D

PR30D

PR36D

L16C_A1

COMPLEMENT

AF21

IO_BR

AF24

AE26

Pin Information

(continued)

Table 44. OR4E6 352-Pin PBGA Pinout (continued)

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

352

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

AD25

IO_BR

AB24

IO_BR

L13

L14

L15

L16

M11

M12

M13

M14

M15

D21

AD11

PB13A

PB17C

PB21C

L1T_D1

TRUE

AE13

PB13B

PB17D

PB21D

L1C_D1

COMPLEMENT

AC12

PB13C

PB18C

PB22C

REF

_BC_01

L2T_D2

TRUE

AF13

PB13D

PB18D

PB22D

L2C_D2

COMPLEMENT

AD12

PB14C

PB19C

PB23C

PBCK0T

L3T_D1

TRUE

AE14

PB14D

PB19D

PB23D

PBCK0C

L3C_D1

COMPLEMENT

AF14

PB15C

PB20C

PB24C

REF

_BC_02

L4T_D1

TRUE

AD13

PB15D

PB20D

PB24D

L4C_D1

COMPLEMENT

AE15

PB16C

PB21C

PB26C

L5T_D0

TRUE

AD14

PB16D

PB21D

PB26D

REF

_BC_03

L5C_D0

COMPLEMENT

AF15

PB17A

PB22C

PB27C

L6T_D0

TRUE

AE16

PB17B

PB22D

PB27D

L6C_D0

COMPLEMENT

AD15

PB17C

PB23C

PB28C

PBCK1T

L7T_D1

TRUE

AF16

PB17D

PB23D

PB28D

PBCK1C

L7C_D1

COMPLEMENT

AC15

PB18A

PB24C

PB29C

L8T_D1

TRUE

AE17

PB18B

PB24D

PB29D

L8C_D1

COMPLEMENT

AF17

PB18C

PB25C

PB30C

L9T_A2

TRUE

AC17

PB18D

PB25D

PB30D

REF

_BC_04

L9C_A2

COMPLEMENT

AE18

PB19C

PB26C

PB32C

L10T_D0

TRUE

AD17

PB19D

PB26D

PB32D

REF

_BC_05

L10C_D0

COMPLEMENT

AF18

PB20C

PB27C

PB34C

L11T_D0

TRUE

AE19

PB20D

PB27D

PB34D

L11C_D0

COMPLEMENT

AF19

PB21A

PB28C

PB35C

L12T_D1

TRUE

AD18

PB21B

PB28D

PB35D

REF

_BC_06

L12C_D1

COMPLEMENT

AC14

IO_BC

AD16

IO_BC

J23

Pin Information

(continued)

Table 44. OR4E6 352-Pin PBGA Pinout (continued)

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

352

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

P23

W23

L11

L12

D11

D16

PL22D

PL32D

PL38D

L1C_D1

COMPLEMENT

PL22C

PL32C

PL38C

REF

_BL_01

L1T_D1

TRUE

AA2

PL22B

PL33D

PL39D

L2C_D1

COMPLEMENT

PL22A

PL33C

PL39C

D10

L2T_D1

TRUE

AA1

PL23C

PL34C

PL40C

REF

_BL_02

TRUE

AB2

PL24D

PL35B

PL42D

D11

L3C_A0

COMPLEMENT

AB1

PL24C

PL35A

PL42C

D12

L3T_A0

TRUE

AA3

PL25D

PL36B

PL44D

REF

_BL_03

L4C_D1

COMPLEMENT

AC2

PL25C

PL36A

PL44C

D13

L4T_D1

TRUE

AB4

PL27D

PL39D

PL47D

PLL_CK7C/

HPPLL

L5C_D2

COMPLEMENT

AC1

PL27C

PL39C

PL47C

PLL_CK7T/

HPPLL

L5T_D2

TRUE

AE3

PB2A

DP2

TRUE

AF3

PB2C

PLL_CK6T/PPLL

L6T_A0

TRUE

AE4

PB2D

PLL_CK6C/PPLL

L6C_A0

COMPLEMENT

AD4

PB3C

PB4A

PB4C

REF

_BL_05

L7T_A1

TRUE

AF4

PB3D

PB4B

PB4D

DP3

L7C_A1

COMPLEMENT

AE5

PB4C

PB5C

PB6C

REF

_BL_06

L8T_A1

TRUE

AC5

PB4D

PB5D

PB6D

D14

L8C_A1

COMPLEMENT

AF5

PB5C

PB6C

PB8C

D15

L9T_D0

TRUE

AE6

PB5D

PB6D

PB8D

D16

L9C_D0

COMPLEMENT

AC7

PB6A

PB7C

PB9C

D17

L10T_D0

TRUE

AD6

PB6B

PB7D

PB9D

D18

L10C_D0

COMPLEMENT

AF6

PB6C

PB8C

PB10C

REF

_BL_07

L11T_D0

TRUE

AE7

PB6D

PB8D

PB10D

D19

L11C_D0

COMPLEMENT

AF7

PB7A

PB9C

PB11C

D20

L12T_A1

TRUE

AD7

PB7B

PB9D

PB11D

D21

L12C_A1

COMPLEMENT

AE8

PB7C

PB10C

PB12C

REF

_BL_08

L13T_D1

TRUE

AC9

PB7D

PB10D

PB12D

D22

L13C_D1

COMPLEMENT

AF8

PB8C

PB11C

PB13C

D23

L14T_A1

TRUE

AD8

PB8D

PB11D

PB13D

D24

L14C_A1

COMPLEMENT

AE9

PB9C

PB12C

PB14C

REF

_BL_09

L15T_A0

TRUE

AF9

PB9D

PB12D

PB14D

D25

L15C_A0

COMPLEMENT

AE10

PB10C

PB13C

PB16C

D26

L16T_D0

TRUE

Pin Information

(continued)

Table 44. OR4E6 352-Pin PBGA Pinout (continued)

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

352

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

AD9

PB10D

PB13D

PB16D

D27

L16C_D0

COMPLEMENT

AC10

PB11C

PB14C

PB18C

REF

_BL_10

L17T_D1

TRUE

AE11

PB11D

PB14D

PB18D

D28

L17C_D1

COMPLEMENT

AD10

PB12A

PB15C

PB19C

D29

L18T_D1

TRUE

AF11

PB12B

PB15D

PB19D

D30

L18C_D1

COMPLEMENT

AE12

PB12C

PB16C

PB20C

REF

_BL_11

L19T_A0

TRUE

AF12

PB12D

PB16D

PB20D

D31

L19C_A0

COMPLEMENT

IO_BL

AB3

PTEMP

AD2

IO_BL

AC3

LVDS_R

AD1

AF2

AD5

IO_BL

AF10

IO_BL

B25

B26

C24

D14

D19

D23

AC21

AC6

PL8D

PL12D

PL14D

A15

L1C_D0

COMPLEMENT

PL8C

PL12C

PL14C

A14

L1T_D0

TRUE

PL9D

PL13D

PL16D

REF

_CL_01

L2C_A2

COMPLEMENT

PL9C

PL13C

PL16C

L2T_A2

TRUE

PL10D

PL14D

PL18D

RDY/BUSY/

RCLK

L3C_D0

COMPLEMENT

PL10C

PL14C

PL18C

REF

_CL_02

L3T_D0

TRUE

PL10B

PL15D

PL19D

A13

L4C_A0

COMPLEMENT

PL10A

PL15C

PL19C

A12

L4T_A0

TRUE

PL11B

PL17D

PL21D

A11

L5C_D1

COMPLEMENT

PL11A

PL17C

PL21C

REF

_CL_03

L5T_D1

TRUE

PL13D

PL19D

PL23D

RD/MPI_STRB

L6C_D2

COMPLEMENT

PL13C

PL19C

PL23C

REF

_CL_04

L6T_D2

TRUE

PL14D

PL20D

PL24D

PLCK0C

L7C_D1

COMPLEMENT

PL14C

PL20C

PL24C

PLCK0T

L7T_D1

TRUE

PL15D

PL21D

PL25D

A10

L8C_D1

COMPLEMENT

Pin Information

(continued)

Table 44. OR4E6 352-Pin PBGA Pinout (continued)

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

352

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

PL15C

PL21C

PL25C

L8T_D1

TRUE

PL16D

PL22D

PL26D

L9C_D0

COMPLEMENT

PL16C

PL22C

PL26C

REF

_CL_05

L9T_D0

TRUE

PL17D

PL24D

PL28D

PLCK1C

L10C_D0

COMPLEMENT

PL17C

PL24C

PL28C

PLCK1T

L10T_D0

TRUE

PL17B

PL25D

PL29D

REF

_CL_06

L11C_D1

COMPLEMENT

PL17A

PL25C

PL29C

L11T_D1

TRUE

PL18D

PL26D

PL30D

L12C_D1

COMPLEMENT

PL18C

PL26C

PL30C

L12T_D1

TRUE

PL19D

PL27D

PL32D

WR/MPI_RW

L13C_A2

COMPLEMENT

PL19C

PL27C

PL32C

REF

_CL_07

L13T_A2

TRUE

PL20D

PL28D

PL34D

L14C_D1

COMPLEMENT

PL20C

PL28C

PL34C

REF

_CL_08

L14T_D1

TRUE

PL20B

PL29D

PL35D

L15C_D0

COMPLEMENT

PL20A

PL29C

PL35C

L15T_D0

TRUE

PL21D

PL30D

PL36D

L16C_D1

COMPLEMENT

PL21C

PL30C

PL36C

L16T_D1

TRUE

PL21B

PL31D

PL37D

DP0

L17C_D1

COMPLEMENT

PL21A

PL31C

PL37C

DP1

L17T_D1

TRUE

IO_CL

AD3

AE1

AE2

AE25

AF1

AF25

AF26

AC11

AC16

Pin Information

(continued)

Table 44. OR4E6 352-Pin PBGA Pinout (continued)

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Pin Information

(continued)

_A1 indicates one ball between pairs.

_A2 indicates two balls between pairs.

_D0 indicates balls are diagonally adjacent.

_D1 indicates diagonally adjacent separated by one physical ball.

REF

pins, shown in the Additional Function column, are associated to the bank and group (e.g., V

REF

_TL_01 is the

REF

for group one of the top left (TL) bank).

Table 45. 432-Pin EBGA

432

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

B19

PT11D

PT13D

PT18D

MPI_RTRY

L1C_A0

COMPLEMENT

C19

PT11C

PT13C

PT18C

MPI_ACK

L1T_A0

TRUE

D19

PT11B

PT13B

PT17D

L2C_D0

COMPLEMENT

C20

PT11A

PT13A

PT17C

REF

_TL_01

L2T_D0

TRUE

A21

PT10D

PT12D

PT16D

L3C_A0

COMPLEMENT

B21

PT10C

PT12C

PT16C

L3T_A0

TRUE

A22

PT9D

PT11D

PT14D

L5C_A0

COMPLEMENT

B22

PT9C

PT11C

PT14C

L5T_A0

TRUE

C22

PT9B

PT11B

PT13D

REF

_TL_02

L6C_D1

COMPLEMENT

A23

PT9A

PT11A

PT13C

MPI_TEA

L6T_D1

TRUE

D20

PT10B

PT12B

PT15D

MPI_CLK

L4C_D0

COMPLEMENT

C21

PT10A

PT12A

PT15C

A21/MPI_BURST

L4T_D0

TRUE

B23

PT8B

PT9D

PT11D

REF

_TL_03

L7C_D1

COMPLEMENT

D22

PT8A

PT9C

PT11C

L7T_D1

TRUE

C23

PT7D

PT8D

PT10D

L8C_D0

COMPLEMENT

B24

PT7C

PT8C

PT10C

TMS

L8T_D0

TRUE

C24

PT7B

PT7D

PT9D

A20/MPI_BDIP

L9C_D0

COMPLEMENT

D23

PT7A

PT7C

PT9C

A19/MPI_TSZ1

L9T_D0

TRUE

A25

PT6D

PT8D

A18/MPI_TSZ0

L10C_A0

COMPLEMENT

B25

PT6C

PT8C

L10T_A0

TRUE

D24

PT5D

PT6D

L11C_D2

COMPLEMENT

A26

PT5C

PT6C

L11T_D2

TRUE

B26

PT4D

TDI

L12C_A0

COMPLEMENT

C26

PT4C

TCK

L12T_A0

TRUE

A27

PT3D

L13C_A0

COMPLEMENT

B27

PT3C

REF

_TL_06

L13T_A0

TRUE

C27

PT2D

PLL_CK1C

L14C_D0

COMPLEMENT

D26

PT2C

PLL_CK1T

L14T_D0

TRUE

F31

PL3D

PL4D

L17C_D2

COMPLEMENT

H28

PL3C

PL4C

L17T_D2

TRUE

E30

PL2D

PLL_CK0C

L15C_A0

COMPLEMENT

E31

PL2C

PLL_CK0T

L15T_A0

TRUE

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

432

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

F29

PL2B

PL3D

L16C_A0

COMPLEMENT

F30

PL2A

PL3C

REF

_TL_07

L16T_A0

TRUE

G29

PL4D

PL5D

PL6D

HDC

L18C_A0

COMPLEMENT

G30

PL4C

PL5C

PL6C

LDC

L18T_A0

TRUE

K28

PL6D

PL8D

PL10D

CS0

L21C_D1

COMPLEMENT

J30

PL6C

PL8C

PL10C

CS1

L21T_D1

TRUE

G31

PL5D

PL6D

PL8D

L19C_D2

COMPLEMENT

J28

PL5C

PL6C

PL8C

L19T_D2

TRUE

H30

PL5B

PL7D

PL9D

REF

_TL_09

L20C_D0

COMPLEMENT

J29

PL5A

PL7C

PL9C

A17

L20T_D0

TRUE

K30

PL7D

PL10D

PL12D

INIT

L23C_A0

COMPLEMENT

K31

PL7C

PL10C

PL12C

DOUT

L23T_A0

TRUE

L29

PL7B

PL11D

PL13D

REF

_TL_10

L24C_D0

COMPLEMENT

M28

PL7A

PL11C

PL13C

A16

L24T_D0

TRUE

J31

PL6B

PL9D

PL11D

L22C_D1

COMPLEMENT

K29

PL6A

PL9C

PL11C

L22T_D1

TRUE

A12

A16

A20

A24

A29

H29

IO0_TL

E29

IO0_TL

C25

IO0_TL

B20

IO0_TL

E28

D27

A31

AA28

AA4

AE28

D30

PRESET

D29

PRD_DATA

TDO

D31

PRD_CFG

F28

PPRGRM

C28

PDONE

A28

PCFG_MPI_IRQ

CFG_IRQ/MPI_IRQ

B28

PCCLK

PT21D

PT28D

PT35D

L1C_D1

COMPLEMENT

C10

PT21C

PT28C

PT35C

L1T_D1

TRUE

B10

PT20D

PT27D

PT34D

REF

_TC_01

L2C_A0

COMPLEMENT

A10

PT20C

PT27C

PT34C

L2T_A0

TRUE

Pin Information

(continued)

Table 45. OR4E6 432-Pin EBGA (continued)

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

432

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

C11

PT20B

PT27B

PT33D

L3C_D0

COMPLEMENT

D12

PT20A

PT27A

PT33C

L3T_D0

TRUE

B11

PT19D

PT26D

PT32D

L4C_A0

COMPLEMENT

A11

PT19C

PT26C

PT32C

REF

_TC_02

L4T_A0

TRUE

C12

PT19B

PT26B

PT31D

L5C_D0

COMPLEMENT

D13

PT19A

PT26A

PT31C

L5T_D0

TRUE

B12

PT18D

PT25D

PT30D

L6C_D0

COMPLEMENT

C13

PT18C

PT25C

PT30C

L6T_D0

TRUE

D14

PT18B

PT24D

PT29D

L7C_D2

COMPLEMENT

A13

PT18A

PT24C

PT29C

REF

_TC_03

L7T_D2

TRUE

C14

PT17D

PT23D

PT28D

L8C_A0

COMPLEMENT

B14

PT17C

PT23C

PT28C

L8T_A0

TRUE

A14

PT16D

PT21D

PT26D

L9C_D1

COMPLEMENT

C15

PT16C

PT21C

PT26C

L9T_D1

TRUE

B15

PT15D

PT19D

PT24D

L10C_A0

COMPLEMENT

A15

PT15C

PT19C

PT24C

REF

_TC_04

L10T_A0

TRUE

D16

PT14D

PT18D

PT23D

PTCK1C

L11C_A1

COMPLEMENT

B16

PT14C

PT18C

PT23C

PTCK1T

L11T_A1

TRUE

A17

PT13D

PT17D

PT22D

PTCK0C

L12C_A0

COMPLEMENT

B17

PT13C

PT17C

PT22C

PTCK0T

L12T_A0

TRUE

C17

PT13B

PT16D

PT21D

REF

_TC_05

L13C_D1

COMPLEMENT

A18

PT13A

PT16C

PT21C

L13T_D1

TRUE

B18

PT12D

PT15D

PT20D

L14C_A0

COMPLEMENT

C18

PT12C

PT15C

PT20C

L14T_A0

TRUE

A19

PT12B

PT14D

PT19D

L15C_D2

COMPLEMENT

D18

PT12A

PT14C

PT19C

REF

_TC_06

L15T_D2

TRUE

M31

T31

Y31

C16

IO_TC

B13

IO_TC

R28

U28

PR8D

PR11D

PR13D

REF

_TR_01

L1C_D1

COMPLEMENT

PR8C

PR11C

PR13C

L1T_D1

TRUE

PR7D

PR9D

PR11D

L3C_D0

COMPLEMENT

PR7C

PR9C

PR11C

L3T_D0

TRUE

PR7B

PR10D

PR12D

L2C_D1

COMPLEMENT

PR7A

PR10C

PR12C

L2T_D1

TRUE

PR6D

PR7D

PR9D

L5C_A0

COMPLEMENT

Pin Information

(continued)

Table 45. OR4E6 432-Pin EBGA (continued)

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

432

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

PR6C

PR7C

PR9C

REF

_TR_02

L5T_A0

TRUE

PR6B

PR8D

PR10D

L4C_D0

COMPLEMENT

PR6A

PR8C

PR10C

L4T_D0

TRUE

PR5B

PR6B

PR8D

L6C_D2

COMPLEMENT

PR5A

PR6A

PR8C

L6T_D2

TRUE

PR5D

PR6D

PR7D

REF

_TR_03

L7C_A0

COMPLEMENT

PR5C

PR6C

PR7C

L7T_A0

TRUE

PR4D

PR5D

L9C_D0

COMPLEMENT

PR4C

PR5C

L9T_D0

TRUE

PR4B

PR5D

PR6D

L8C_A0

COMPLEMENT

PR4A

PR5C

PR6C

L8T_A0

TRUE

PR3D

PLL_CK3C

L10C_A0

COMPLEMENT

PR3C

PLL_CK3T

L10T_A0

TRUE

PT27D

PT37D

PT47D

PLL_CK2C

L11C_A0

COMPLEMENT

PT27C

PT37C

PT47C

PLL_CK2T

L11T_A0

TRUE

PT26D

PT36D

PT45D

REF

_TR_05

L12C_D0

COMPLEMENT

PT26C

PT36C

PT45C

L12T_D0

TRUE

PT26B

PT35B

PT43D

L13C_A0

COMPLEMENT

PT26A

PT35A

PT43C

L13T_A0

TRUE

PT25D

PT34D

PT42D

REF

_TR_06

L14C_A0

COMPLEMENT

PT25C

PT34C

PT42C

L14T_A0

TRUE

PT25B

PT34B

PT41D

L15C_D2

COMPLEMENT

PT25A

PT34A

PT41C

L15T_D2

TRUE

PT24D

PT33D

PT40D

L16C_A0

COMPLEMENT

PT24C

PT33C

PT40C

REF

_TR_07

L16T_A0

TRUE

PT24B

PT32D

PT39D

L17C_D0

COMPLEMENT

PT24A

PT32C

PT39C

L17T_D0

TRUE

PT23D

PT31D

PT38D

L18C_D0

COMPLEMENT

PT23C

PT31C

PT38C

REF

_TR_08

L18T_D0

TRUE

D10

PT22D

PT29D

PT36D

L19C_D1

COMPLEMENT

PT22C

PT29C

PT36C

L19T_D1

TRUE

C30

C31

H31

IO_TR

Pin Information

(continued)

Table 45. OR4E6 432-Pin EBGA (continued)

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

432

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

G28

L28

PLL_VF

AB1

PR20D

PR29D

PR35D

L1C_A0

COMPLEMENT

AB2

PR20C

PR29C

PR35C

L1T_A0

TRUE

PR19D

PR28D

PR33D

L2C_D0

COMPLEMENT

AA3

PR19C

PR28C

PR33C

REF

_CR_01

L2T_D0

TRUE

PR18D

PR26B

PR31D

REF

_CR_02

L4C_D1

COMPLEMENT

PR18C

PR26A

PR31C

L4T_D1

TRUE

AA1

PR18B

PR27B

PR32D

L3C_A0

COMPLEMENT

AA2

PR18A

PR27A

PR32C

L3T_A0

TRUE

PR17B

PR25B

PR30D

L5C_A0

COMPLEMENT

PR17A

PR25A

PR30C

L5T_A0

TRUE

PR17D

PR25D

PR29D

REF

_CR_03

L6C_D2

COMPLEMENT

PR17C

PR25C

PR29C

L6T_D2

TRUE

PR16D

PR23D

PR27D

PRCK1C

L7C_A0

COMPLEMENT

PR16C

PR23C

PR27C

PRCK1T

L7T_A0

TRUE

PR15B

PR22D

PR26D

REF

_CR_04

L8C_D1

COMPLEMENT

PR15A

PR22C

PR26C

L8T_D1

TRUE

PR15D

PR21D

PR25D

L9C_D1

COMPLEMENT

PR15C

PR21C

PR25C

L9T_D1

TRUE

PR14D

PR19D

PR23D

L11C_A0

COMPLEMENT

PR14C

PR19C

PR23C

REF

_CR_05

L11T_A0

TRUE

PR14B

PR20D

PR24D

PRCK0C

L10C_A1

COMPLEMENT

PR14A

PR20C

PR24C

PRCK0T

L10T_A1

TRUE

PR13B

PR18D

PR22D

L12C_D1

COMPLEMENT

PR13A

PR18C

PR22C

L12T_D1

TRUE

PR13D

PR17D

PR21D

REF

_CR_06

L13C_A0

COMPLEMENT

PR13C

PR17C

PR21C

L13T_A0

TRUE

PR12B

PR16D

PR20D

L14C_D2

COMPLEMENT

PR12A

PR16C

PR20C

L14T_D2

TRUE

PR12D

PR15D

PR19D

L15C_D0

COMPLEMENT

PR12C

PR15C

PR19C

L15T_D0

TRUE

PR11D

PR14D

PR17D

L17C_A0

COMPLEMENT

PR11C

PR14C

PR17C

REF

_CR_07

L17T_A0

TRUE

PR11B

PR14B

PR18D

L16C_D0

COMPLEMENT

PR11A

PR14A

PR18C

L16T_D0

TRUE

PR9D

PR12D

PR14D

L19C_A0

COMPLEMENT

PR9C

PR12C

PR14C

REF

_CR_08

L19T_A0

TRUE

PR10D

PR13D

PR15D

L18C_D0

COMPLEMENT

PR10C

PR13C

PR15C

L18T_D0

TRUE

B29

Pin Information

(continued)

Table 45. OR4E6 432-Pin EBGA (continued)

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

432

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

B31

IO_CR

D15

D17

D21

D25

D28

AJ8

PB23B

PB32D

PB39D

L3C_A0

COMPLEMENT

AK8

PB23A

PB32C

PB39C

L3T_A0

TRUE

AJ9

PB22D

PB31D

PB38D

L2C_D0

COMPLEMENT

AH10

PB22C

PB31C

PB38C

REF

_BR_01

L2T_D0

TRUE

AK9

PB22B

PB30D

PB37D

L1C_A0

COMPLEMENT

AL9

PB22A

PB30C

PB37C

L1T_A0

TRUE

AL6

PB24C

PB34C

PB42C

TRUE

AH8

PB24B

PB34B

PB41D

L5C_D0

COMPLEMENT

AJ7

PB24A

PB34A

PB41C

L5T_D0

TRUE

AK7

PB23D

PB33D

PB40D

REF

_BR_02

L4C_A0

COMPLEMENT

AL7

PB23C

PB33C

PB40C

L4T_A0

TRUE

AJ5

PB26D

PB36D

PB45D

L7C_A0

COMPLEMENT

AK5

PB26C

PB36C

PB45C

L7T_A0

TRUE

AL5

PB25D

PB35D

PB44D

REF

_BR_03

L6C_D1

COMPLEMENT

AJ6

PB25C

PB35C

PB44C

L6T_D1

TRUE

AK6

PB25A

PB35A

PB43A

TRUE

AJ4

PB27D

PB37D

PB47D

PLL_CK5C

L9C_A0

COMPLEMENT

AK4

PB27C

PB37C

PB47C

PLL_CK5T

L9T_A0

TRUE

AL4

PB27B

PB37B

PB46D

REF

_BR_04

L8C_D2

COMPLEMENT

AH6

PB27A

PB37A

PB46C

L8T_D2

TRUE

AH1

PR26B

PR38B

PR46D

PLL_CK4C

L10C_A0

COMPLEMENT

AH2

PR26A

PR38A

PR46C

PLL_CK4T

L10T_A0

TRUE

AG3

PR25B

PR37D

PR44D

L11C_D0

COMPLEMENT

AF4

PR25A

PR37C

PR44C

REF

_BR_05

L11T_D0

TRUE

AG1

PR25D

PR36D

PR43D

L12C_A0

COMPLEMENT

AG2

PR25C

PR36C

PR43C

L12T_A0

TRUE

AE3

PR24D

PR35D

PR41D

L14C_D0

COMPLEMENT

AD4

PR24C

PR35C

PR41C

REF

_BR_06

L14T_D0

TRUE

AF2

PR24B

PR35B

PR42D

L13C_A0

COMPLEMENT

AF3

PR24A

PR35A

PR42C

L13T_A0

TRUE

AD3

PR23D

PR33D

PR39D

REF

_BR_07

L16C_D0

COMPLEMENT

AC4

PR23C

PR33C

PR39C

L16T_D0

TRUE

AE1

PR23B

PR34D

PR40D

L15C_A0

COMPLEMENT

AE2

PR23A

PR34C

PR40C

L15T_A0

TRUE

Pin Information

(continued)

Table 45. OR4E6 432-Pin EBGA (continued)

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

432

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

AC3

PR22B

PR32D

PR38D

L17C_D0

COMPLEMENT

AD2

PR22A

PR32C

PR38C

L17T_D0

TRUE

AC2

PR22D

PR31D

PR37D

REF

_BR_08

L18C_D1

COMPLEMENT

AB4

PR22C

PR31C

PR37C

L18T_D1

TRUE

AB3

PR21D

PR30D

PR36D

L19C_D1

COMPLEMENT

AC1

PR21C

PR30C

PR36C

L19T_D1

TRUE

AL20

AL24

AL29

AL3

AL30

AL8

AF1

IO_BR

AH3

IO_BR

AH9

IO_BR

AG4

AH5

B30

C29

D11

AK17

PB13D

PB18D

PB22D

L2C_A0

COMPLEMENT

AJ17

PB13C

PB18C

PB22C

REF

_BC_01

L2T_A0

TRUE

AL18

PB13B

PB17D

PB21D

L1C_A0

COMPLEMENT

AK18

PB13A

PB17C

PB21C

L1T_A0

TRUE

AL15

PB15D

PB20D

PB24D

L4C_D0

COMPLEMENT

AK16

PB15C

PB20C

PB24C

REF

_BC_02

L4T_D0

TRUE

AJ16

PB14D

PB19D

PB23D

PBCK0C

L3C_D1

COMPLEMENT

AL17

PB14C

PB19C

PB23C

PBCK0T

L3T_D1

TRUE

AL13

PB17D

PB23D

PB28D

PBCK1C

L7C_D1

COMPLEMENT

AJ14

PB17C

PB23C

PB28C

PBCK1T

L7T_D1

TRUE

AK14

PB17B

PB22D

PB27D

L6C_A0

COMPLEMENT

AL14

PB17A

PB22C

PB27C

L6T_A0

TRUE

AJ15

PB16D

PB21D

PB26D

REF

_BC_03

L5C_A0

COMPLEMENT

AK15

PB16C

PB21C

PB26C

L5T_A0

TRUE

AL11

PB19B

PB26B

PB31D

L10C_D1

COMPLEMENT

AJ12

PB19A

PB26A

PB31C

L10T_D1

TRUE

AH13

PB18D

PB25D

PB30D

REF

_BC_04

L9C_D1

COMPLEMENT

AK12

PB18C

PB25C

PB30C

L9T_D1

TRUE

AK13

PB18B

PB24D

PB29D

L8C_A0

COMPLEMENT

AH14

PB18A

PB24C

PB29C

L8T_A0

TRUE

AL10

PB20D

PB27D

PB34D

L12C_D1

COMPLEMENT

AJ11

PB20C

PB27C

PB34C

L12T_D1

TRUE

AH12

PB19D

PB26D

PB32D

REF

_BC_05

L11C_D1

COMPLEMENT

Pin Information

(continued)

Table 45. OR4E6 432-Pin EBGA (continued)

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

432

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

AK11

PB19C

PB26C

PB32C

L11T_D1

TRUE

AJ10

PB21B

PB28D

PB35D

REF

_BC_06

L13C_A0

COMPLEMENT

AK10

PB21A

PB28C

PB35C

L13T_A0

TRUE

AK3

AK31

AL12

AL16

AL2

AJ13

IO_BC

AH16

IO_BC

AJ3

AK2

AK30

AL1

AL31

AC29

PL22D

PL32D

PL38D

L1C_D0

COMPLEMENT

AD30

PL22C

PL32C

PL38C

REF

_BL_01

L1T_D0

TRUE

AD29

PL22B

PL33D

PL39D

L2C_D0

COMPLEMENT

AC28

PL22A

PL33C

PL39C

D10

L2T_D0

TRUE

AE31

PL23D

PL34D

PL40D

L3C_A0

COMPLEMENT

AE30

PL23C

PL34C

PL40C

REF

_BL_02

L3T_A0

TRUE

AF30

PL25D

PL36B

PL44D

REF

_BL_03

L5C_A0

COMPLEMENT

AF29

PL25C

PL36A

PL44C

D13

L5T_A0

TRUE

AD28

PL24D

PL35B

PL42D

D11

L4C_D2

COMPLEMENT

AF31

PL24C

PL35A

PL42C

D12

L4T_D2

TRUE

AG29

PL27D

PL39D

PL47D

PLL_CK7C

L7C_D1

COMPLEMENT

AF28

PL27C

PL39C

PL47C

PLL_CK7T

L7T_D1

TRUE

AG31

PL26D

PL37B

PL45D

L6C_A0

COMPLEMENT

AG30

PL26C

PL37A

PL45C

REF

_BL_04

L6T_A0

TRUE

AJ27

PB3D

PB4B

PB4D

DP3

L9C_D0

COMPLEMENT

AH26

PB3C

PB4A

PB4C

REF

_BL_05

L9T_D0

TRUE

AL28

PB2D

PLL_CK6C

L8C_A0

COMPLEMENT

AK28

PB2C

PLL_CK6T

L8T_A0

TRUE

AJ28

PB2A

DP2

TRUE

AH24

PB5B

PB6B

PB7D

L12C_D2

COMPLEMENT

AL26

PB5A

PB6A

PB7C

L12T_D2

TRUE

AK26

PB4D

PB5D

PB6D

D14

L11C_A0

COMPLEMENT

AJ26

PB4C

PB5C

PB6C

REF

_BL_06

L11T_A0

TRUE

AL27

PB4B

PB4D

PB5D

L10C_A0

COMPLEMENT

AK27

PB4A

PB4C

PB5C

L10T_A0

TRUE

AJ23

PB6D

PB8D

PB10D

D19

L15C_D0

COMPLEMENT

AK24

PB6C

PB8C

PB10C

REF

_BL_07

L15T_D0

TRUE

AJ24

PB6B

PB7D

PB9D

D18

L14C_D0

COMPLEMENT

AH23

PB6A

PB7C

PB9C

D17

L14T_D0

TRUE

AL25

PB5D

PB6D

PB8D

D16

L13C_A0

COMPLEMENT

Pin Information

(continued)

Table 45. OR4E6 432-Pin EBGA (continued)

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

432

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

AK25

PB5C

PB6C

PB8C

D15

L13T_A0

TRUE

AJ22

PB7D

PB10D

PB12D

D22

L17C_D1

COMPLEMENT

AL23

PB7C

PB10C

PB12C

REF

_BL_08

L17T_D1

TRUE

AK23

PB7B

PB9D

PB11D

D21

L16C_D1

COMPLEMENT

AH22

PB7A

PB9C

PB11C

D20

L16T_D1

TRUE

AH20

PB9D

PB12D

PB14D

D25

L19C_D0

COMPLEMENT

AJ21

PB9C

PB12C

PB14C

REF

_BL_09

L19T_D0

TRUE

AL22

PB8D

PB11D

PB13D

D24

L18C_A0

COMPLEMENT

AK22

PB8C

PB11C

PB13C

D23

L18T_A0

TRUE

AJ19

PB11D

PB14D

PB18D

D28

L21C_D0

COMPLEMENT

AK20

PB11C

PB14C

PB18C

REF

_BL_10

L21T_D0

TRUE

AJ20

PB11B

PB14B

PB17D

COMPLEMENT

AL21

PB10D

PB13D

PB16D

D27

L20C_A0

COMPLEMENT

AK21

PB10C

PB13C

PB16C

D26

L20T_A0

TRUE

AJ18

PB12D

PB16D

PB20D

D31

L23C_D1

COMPLEMENT

AL19

PB12C

PB16C

PB20C

REF

_BL_11

L23T_D1

TRUE

AH18

PB12B

PB15D

PB19D

D30

L22C_D1

COMPLEMENT

AK19

PB12A

PB15C

PB19C

D29

L22T_D1

TRUE

AJ1

AJ2

AJ30

AJ31

AK1

AK29

AH19

IO_BL

AJ25

IO_BL

AH30

IO_BL

AE29

IO_BL

AH27

AG28

AH25

AH28

AH4

AH7

AJ29

AH31

PTEMP

AH29

LVDS_R

M29

PL9D

PL13D

PL16D

REF

_7_01

L2C_D0

COMPLEMENT

N28

PL9C

PL13C

PL16C

L2T_D0

TRUE

L30

PL8D

PL12D

PL14D

A15

L1C_A0

COMPLEMENT

L31

PL8C

PL12C

PL14C

A14

L1T_A0

TRUE

M30

PL9B

PL13B

PL17D

COMPLEMENT

N29

PL10D

PL14D

PL18D

RDY/BUSY/RCLK

L3C_A0

COMPLEMENT

N30

PL10C

PL14C

PL18C

REF

_7_02

L3T_A0

TRUE

Pin Information

(continued)

Table 45.OR4E6 432-Pin EBGA (continued)

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

432

BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E2

OR4E4

OR4E6

N31

PL10B

PL15D

PL19D

A13

L4C_D1

COMPLEMENT

P29

PL10A

PL15C

PL19C

A12

L4T_D1

TRUE

P30

PL11D

PL16D

PL20D

L5C_A0

COMPLEMENT

P31

PL11C

PL16C

PL20C

L5T_A0

TRUE

R29

PL11B

PL17D

PL21D

A11

L6C_A0

COMPLEMENT

R30

PL11A

PL17C

PL21C

REF

_7_03

L6T_A0

TRUE

T28

PL14D

PL20D

PL24D

PLCK0C

L8C_A1

COMPLEMENT

T30

PL14C

PL20C

PL24C

PLCK0T

L8T_A1

TRUE

R31

PL13D

PL19D

PL23D

RD/MPI_STRB

L7C_D1

COMPLEMENT

T29

PL13C

PL19C

PL23C

REF

_7_04

L7T_D1

TRUE

V31

PL16D

PL22D

PL26D

L10C_A0

COMPLEMENT

V30

PL16C

PL22C

PL26C

REF

_7_05

L10T_A0

TRUE

U30

PL15D

PL21D

PL25D

A10

L9C_A0

COMPLEMENT

U29

PL15C

PL21C

PL25C

L9T_A0

TRUE

W29

PL18D

PL26D

PL30D

L13C_D0

COMPLEMENT

Y30

PL18C

PL26C

PL30C

L13T_D0

TRUE

V29

PL17D

PL24D

PL28D

PLCK1C

L11C_D1

COMPLEMENT

W31

PL17C

PL24C

PL28C

PLCK1T

L11T_D1

TRUE

V28

PL17B

PL25D

PL29D

REF

_7_06

L12C_D1

COMPLEMENT

W30

PL17A

PL25C

PL29C

L12T_D1

TRUE

AA31

PL19D

PL27D

PL32D

WR/MPI_RW

L14C_A0

COMPLEMENT

AA30

PL19C

PL27C

PL32C

REF

_7_07

L14T_A0

TRUE

Y29

PL18B

PL26B

PL31D

COMPLEMENT

AB29

PL21D

PL30D

PL36D

L17C_D1

COMPLEMENT

AC31

PL21C

PL30C

PL36C

L17T_D1

TRUE

AC30

PL21B

PL31D

PL37D

DP0

L18C_D1

COMPLEMENT

AB28

PL21A

PL31C

PL37C

DP1

L18T_D1

TRUE

Y28

PL20D

PL28D

PL34D

L15C_D0

COMPLEMENT

AA29

PL20C

PL28C

PL34C

REF

_7_08

L15T_D0

TRUE

AB31

PL20B

PL29D

PL35D

L16C_A0

COMPLEMENT

AB30

PL20A

PL29C

PL35C

L16T_A0

TRUE

A30

AD1

AD31

W28

IO_CL

U31

IO_CL

P28

IO_CL

AE4

AH11

AH15

AH17

AH21

Pin Information

(continued)

Table 45. OR4E6 432-Pin EBGA (continued)

Lucent Technologies Inc.

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Pin Information

(continued)

_A1 indicates one ball between pairs.

_A2 indicates two balls between pairs.

_D0 indicates balls are diagonally adjacent.

_D1 indicates diagonally adjacent separated by one physical ball.

REF

pins, shown in the Additional Function column, are associated to the bank and group (e.g., V

REF

_TL_01 is the

REF

for group one of the top left (TL) bank).

Table 46. 680-Pin PBGAM Pinout

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

E16

PT13D

PT18D

MPI_RTRY

L1C_D1

COMPLEMENT

D14

PT13C

PT18C

MPI_ACK

L1T_D1

TRUE

C14

PT13B

PT17D

L2C_D0

COMPLEMENT

D13

PT13A

PT17C

REF

_TL_01

L2T_D0

TRUE

A12

PT12D

PT16D

L3C_A0

COMPLEMENT

B12

PT12C

PT16C

L3T_A0

TRUE

E15

PT12B

PT15D

MPI_CLK

L4C_D3

COMPLEMENT

B11

PT12A

PT15C

A21/

MPI_BURST

L4T_D3

TRUE

C11

PT11D

PT14D

L5C_D2

COMPLEMENT

E14

PT11C

PT14C

L5T_D2

TRUE

D12

PT11B

PT13D

REF

_TL_02

L6C_A0

COMPLEMENT

D11

PT11A

PT13C

MPI_TEA

L6T_A0

TRUE

A10

PT10D

PT12D

L7C_A0

COMPLEMENT

B10

PT10C

PT12C

L7T_A0

TRUE

C10

PT10A

PT12A

TRUE

PT9D

PT11D

REF

_TL_03

L8C_D0

COMPLEMENT

D10

PT9C

PT11C

L8T_D0

TRUE

E13

PT9A

PT11A

TRUE

PT8D

PT10D

L9C_A0

COMPLEMENT

PT8C

PT10C

TMS

L9T_A0

TRUE

PT7D

PT9D

A20/MPI_BDIP L10C_D2 COMPLEMENT

PT7C

PT9C

A19/MPI_TSZ1 L10T_D2

TRUE

PT6D

PT8D

A18/MPI_TSZ0 L11C_D3 COMPLEMENT

E12

PT6C

PT8C

L11T_D3

TRUE

PT6B

PT7D

REF

_TL_04

L12C_A0 COMPLEMENT

PT6A

PT7C

L12T_A0

TRUE

E11

PT5D

PT6D

L13C_D3 COMPLEMENT

100

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

PT5C

PT6C

L13T_D3

TRUE

PT5B

PT5D

L14C_D0 COMPLEMENT

PT5A

PT5C

REF

_TL_05

L14T_D0

TRUE

PT4D

TDI

L15C_A0 COMPLEMENT

PT4C

TCK

L15T_A0

TRUE

E10

PT4B

L16C_D4 COMPLEMENT

PT4A

L16T_D4

TRUE

PT3D

L17C_D2 COMPLEMENT

PT3C

REF

_TL_06

L17T_D2

TRUE

PT3B

L18C_D0 COMPLEMENT

PT3A

L18T_D0

TRUE

PT2D

PLL_CK1C/

PPLL

L19C_A0 COMPLEMENT

PT2C

PLL_CK1T/

PPLL

L19T_A0

TRUE

PT2B

L20C_D1 COMPLEMENT

PT2A

L20T_D1

TRUE

PL2D

PLL_CK0C/

HPPLL

L21C_D2 COMPLEMENT

PL2C

PLL_CK0T/

HPPLL

L21T_D2

TRUE

PL3D

L22C_D0 COMPLEMENT

PL3C

REF

_TL_07

L22T_D0

TRUE

PL4D

L23C_D2 COMPLEMENT

PL4C

L23T_D2

TRUE

PL4B

PL5D

L24C_D0 COMPLEMENT

PL4A

PL5C

REF

_TL_08

L24T_D0

TRUE

PL5D

PL6D

HDC

L25C_D3 COMPLEMENT

PL5C

PL6C

LDC

L25T_D3

TRUE

PL5B

PL7D

L26C_D0 COMPLEMENT

PL5A

PL7C

L26T_D0

TRUE

PL6D

PL8D

L27C_D0 COMPLEMENT

PL6C

PL8C

L27T_D0

TRUE

PL7D

PL9D

REF

_TL_09

L28C_D3 COMPLEMENT

PL7C

PL9C

A17

L28T_D3

TRUE

PL8D

PL10D

CS0

L29C_D1 COMPLEMENT

PL8C

PL10C

CS1

L29T_D1

TRUE

PL9D

PL11D

L30C_D0 COMPLEMENT

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

Lucent Technologies Inc.

101

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

PL9C

PL11C

L30T_D0

TRUE

PL9A

PL11A

TRUE

PL10D

PL12D

INIT

L31C_D0 COMPLEMENT

PL10C

PL12C

DOUT

L31T_D0

TRUE

PL11D

PL13D

REF

_TL_10

L32C_D1 COMPLEMENT

PL11C

PL13C

A16

L32T_D1

TRUE

PL11A

PL13A

TRUE

PRD_DATA

PRESET

PRD_CFG

PPRGRM

PCFG_MPI_IRQ

CFG_IRQ/

MPI_IRQ

PCCLK

PDONE

A18

A33

A34

B33

B34

C13

N16

N17

N18

N19

P16

P17

IO_TL

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

102

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

IO_TL

C25

PT28D

PT35D

L1C_D1

COMPLEMENT

E24

PT28C

PT35C

L1T_D1

TRUE

D24

PT28A

PT35A

L2T_D2

TRUE

A25

PT28B

PT35B

L2C_D2

COMPLEMENT

D23

PT27D

PT34D

REF

_TC_01

L3C_D1

COMPLEMENT

B25

PT27C

PT34C

L3T_D1

TRUE

C24

PT27B

PT33D

L4C_D1

COMPLEMENT

E23

PT27A

PT33C

L4T_D1

TRUE

B24

PT26D

PT32D

L5C_D1

COMPLEMENT

D22

PT26C

PT32C

REF

_TC_02

L5T_D1

TRUE

E22

PT26B

PT31D

L6C_D0

COMPLEMENT

D21

PT26A

PT31C

L6T_D0

TRUE

B23

PT25D

PT30D

L7C_A0

COMPLEMENT

B22

PT25C

PT30C

L7T_A0

TRUE

A23

PT24D

PT29D

L8C_D1

COMPLEMENT

C21

PT24C

PT29C

REF

_TC_03

L8T_D1

TRUE

E21

PT24A

PT29A

TRUE

D20

PT23D

PT28D

L9C_D2

COMPLEMENT

A22

PT23C

PT28C

L9T_D2

TRUE

E20

PT23A

PT28A

TRUE

A21

PT22D

PT27D

L10C_A0 COMPLEMENT

B21

PT22C

PT27C

L10T_A0

TRUE

D19

PT22A

PT27A

TRUE

B20

PT21D

PT26D

L11C_A0 COMPLEMENT

A20

PT21C

PT26C

L11T_A0

TRUE

B19

PT20D

PT25D

L12C_A0 COMPLEMENT

C19

PT20C

PT25C

L12T_A0

TRUE

E19

PT19D

PT24D

L13C_D0 COMPLEMENT

D18

PT19C

PT24C

REF

_TC_04

L13T_D0

TRUE

B18

PT19A

PT24A

L14T_A0

TRUE

C18

PT19B

PT24B

L14C_A0 COMPLEMENT

B17

PT18D

PT23D

PTCK1C

L15C_D0 COMPLEMENT

C17

PT18C

PT23C

PTCK1T

L15T_D0

TRUE

D17

PT18A

PT23A

L16T_D2

TRUE

A16

PT18B

PT23B

L16C_D2 COMPLEMENT

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

Lucent Technologies Inc.

103

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

B16

PT17D

PT22D

PTCK0C

L17C_A0 COMPLEMENT

C16

PT17C

PT22C

PTCK0T

L17T_A0

TRUE

D16

PT17A

PT22A

TRUE

E18

PT16D

PT21D

REF

_TC_05

L18C_D3 COMPLEMENT

A15

PT16C

PT21C

L18T_D3

TRUE

B15

PT16A

PT21A

TRUE

D15

PT15D

PT20D

L19C_D2 COMPLEMENT

A14

PT15C

PT20C

L19T_D2

TRUE

B14

PT15A

PT20A

TRUE

E17

PT14D

PT19D

L20C_D3 COMPLEMENT

A13

PT14C

PT19C

REF

_TC_06

L20T_D3

TRUE

B13

PT14A

PT19A

TRUE

C22

VSS

C32

D31

N13

N14

N15

N20

N21

N22

P18

P19

R16

R17

R18

R19

A11

IO_TC

A17

IO_TC

A19

IO_TC

A24

IO_TC

C12

IO_TC

C15

IO_TC

C20

IO_TC

C23

IO_TC

J34

PR11B

PR13B

L1C_A0

COMPLEMENT

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

104

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

H34

PR11A

PR13A

L1T_A0

TRUE

J33

PR11C

PR13C

L2T_A1

TRUE

J31

PR11D

PR13D

REF

_TR_01

L2C_A1

COMPLEMENT

J32

PR10C

PR12C

L3T_D1

TRUE

G34

PR10D

PR12D

L3C_D1

COMPLEMENT

M30

PR9A

PR11A

TRUE

H33

PR9C

PR11C

L4T_A0

TRUE

H32

PR9D

PR11D

L4C_A0

COMPLEMENT

L30

PR8A

PR10A

TRUE

H31

PR8C

PR10C

L5T_D1

TRUE

G33

PR8D

PR10D

L5C_D1

COMPLEMENT

F34

PR7A

PR9A

TRUE

F33

PR7C

PR9C

REF

_TR_02

L6T_D0

TRUE

G32

PR7D

PR9D

L6C_D0

COMPLEMENT

K30

PR6A

PR8C

L7T_D2

TRUE

G31

PR6B

PR8D

L7C_D2

COMPLEMENT

E34

PR6C

PR7C

L8T_D2

TRUE

J30

PR6D

PR7D

REF

_TR_03

L8C_D2

COMPLEMENT

D34

PR5A

PR6A

TRUE

F32

PR5C

PR6C

L9T_A0

TRUE

F31

PR5D

PR6D

L9C_A0

COMPLEMENT

E33

PR4C

PR5C

L10T_A0

TRUE

D33

PR4D

PR5D

L10C_A0 COMPLEMENT

H30

PR3A

PR4C

L11T_D2

TRUE

E32

PR3B

PR4D

REF

_TR_04

L11C_D2 COMPLEMENT

E31

PR3C

PLL_CK3T/

PLL1(1.554/

2.048 MHz)

L12T_A0

TRUE

G30

PR3D

PLL_CK3C/

PLL1(1.554/

2.048 MHz)

L12C_A0 COMPLEMENT

C30

PT37D

PT47D

PLL_CK2C/

PPLL

L13C_D0 COMPLEMENT

B31

PT37C

PT47C

PLL_CK2T/

PPLL

L13T_D0

TRUE

E28

PT37B

PT46D

L14C_D2 COMPLEMENT

B30

PT37A

PT46C

L14T_D2

TRUE

D29

PT36D

PT45D

REF

_TR_05

L15C_D2 COMPLEMENT

A31

PT36C

PT45C

L15T_D2

TRUE

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

Lucent Technologies Inc.

105

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

D28

PT35D

PT44D

L16C_D1 COMPLEMENT

B29

PT35C

PT44C

L16T_D1

TRUE

E27

PT35B

PT43D

L17C_D1 COMPLEMENT

C29

PT35A

PT43C

L17T_D1

TRUE

A30

PT34D

PT42D

REF

_TR_06

L18C_D3 COMPLEMENT

E26

PT34C

PT42C

L18T_D3

TRUE

A29

PT34B

PT41D

L19C_D2 COMPLEMENT

D27

PT34A

PT41C

L19T_D2

TRUE

C28

PT33D

PT40D

L20C_A0 COMPLEMENT

C27

PT33C

PT40C

REF

_TR_07

L20T_A0

TRUE

B28

PT32D

PT39D

L21C_D2 COMPLEMENT

E25

PT32C

PT39C

L21T_D2

TRUE

A28

PT31D

PT38D

L22C_D2 COMPLEMENT

D26

PT31C

PT38C

REF

_TR_08

L22T_D2

TRUE

C26

PT30D

PT37D

COMPLEMENT

B27

PT30A

PT37A

TRUE

D25

PT29D

PT36D

L23C_D2 COMPLEMENT

A27

PT29C

PT36C

L23T_D2

TRUE

A26

PT29A

PT36A

L24T_A0

TRUE

B26

PT29B

PT36B

L24C_A0 COMPLEMENT

F30

E29

D30

PLL_VF

N32

P13

P14

P15

P20

P21

P22

R13

R14

R15

R20

T13

T14

T15

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

106

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

T20

T21

T22

A32

IO_TR

B32

IO_TR

C31

IO_TR

C33

IO_TR

C34

IO_TR

D32

IO_TR

E30

IO_TR

AE32

PR29A

PR35C

L1T_D1

TRUE

AC30

PR29B

PR35D

L1C_D1

COMPLEMENT

AD31

PR28A

PR34A

TRUE

AE33

PR29C

PR34C

L2T_D1

TRUE

AC31

PR29D

PR34D

L2C_D1

COMPLEMENT

AE34

PR28B

PR33B

COMPLEMENT

AD32

PR28C

PR33C

REF

_CR_01

L3T_D1

TRUE

AB30

PR28D

PR33D

L3C_D1

COMPLEMENT

AD33

PR27D

PR32B

COMPLEMENT

AB31

PR27A

PR32C

L4T_D0

TRUE

AA30

PR27B

PR32D

L4C_D0

COMPLEMENT

AA31

PR27C

PR31A

TRUE

AC33

PR26A

PR31C

L5T_A0

TRUE

AB33

PR26B

PR31D

REF

_CR_02

L5C_A0

COMPLEMENT

AC34

PR26C

PR30A

TRUE

AA32

PR25A

PR30C

L6T_D1

TRUE

Y30

PR25B

PR30D

L6C_D1

COMPLEMENT

Y31

PR24B

PR29B

COMPLEMENT

AB34

PR25C

PR29C

L7T_D3

TRUE

W30

PR25D

PR29D

REF

_CR_03

L7C_D3

COMPLEMENT

AA34

PR24A

PR28A

TRUE

AA33

PR24C

PR28C

L8T_D1

TRUE

W31

PR24D

PR28D

L8C_D1

COMPLEMENT

Y33

PR23A

PR27A

TRUE

Y34

PR23C

PR27C

PRCK1T

L9T_D0

TRUE

W33

PR23D

PR27D

PRCK1C

L9C_D0

COMPLEMENT

W32

PR22A

PR26A

TRUE

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

Lucent Technologies Inc.

107

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

V30

PR22C

PR26C

L10T_A0

TRUE

V31

PR22D

PR26D

REF

_CR_04

L10C_A0 COMPLEMENT

V33

PR21C

PR25C

L11T_A0

TRUE

V32

PR21D

PR25D

L11C_A0 COMPLEMENT

U33

PR20A

PR24A

L12T_A0

TRUE

U32

PR20B

PR24B

L12C_A0 COMPLEMENT

T34

PR20C

PR24C

PRCK0T

L13T_D2

TRUE

U31

PR20D

PR24D

PRCK0C

L13C_D2 COMPLEMENT

T33

PR19A

PR23A

TRUE

T32

PR19C

PR23C

REF

_CR_05

L14T_A0

TRUE

T31

PR19D

PR23D

L14C_A0 COMPLEMENT

U30

PR18A

PR22A

TRUE

R31

PR18C

PR22C

L15T_D1

TRUE

R34

PR18D

PR22D

L15C_D1 COMPLEMENT

R33

PR17A

PR21A

TRUE

P34

PR17C

PR21C

L16T_A1

TRUE

P32

PR17D

PR21D

REF

_CR_06

L16C_A1 COMPLEMENT

T30

PR16A

PR20A

TRUE

P31

PR16C

PR20C

L17T_A1

TRUE

P33

PR16D

PR20D

L17C_A1 COMPLEMENT

R30

PR16B

PR19B

COMPLEMENT

N33

PR15C

PR19C

L18T_A1

TRUE

N31

PR15D

PR19D

L18C_A1 COMPLEMENT

N34

PR15B

PR18B

COMPLEMENT

M31

PR14A

PR18C

L19T_A1

TRUE

M33

PR14B

PR18D

L19C_A1 COMPLEMENT

P30

PR15A

PR17A

TRUE

M34

PR14C

PR17C

REF

_CR_07

L20T_D1

TRUE

L32

PR14D

PR17D

L20C_D1 COMPLEMENT

L31

PR13B

PR16D

COMPLEMENT

L33

PR13A

PR15A

TRUE

K34

PR13C

PR15C

L21T_A0

TRUE

K33

PR13D

PR15D

L21C_A0 COMPLEMENT

K32

PR12A

PR14A

TRUE

N30

PR12C

PR14C

REF

_CR_08

L22T_D2

TRUE

K31

PR12D

PR14D

L22C_D2 COMPLEMENT

R21

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

108

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

R22

T16

T17

T18

T19

U16

U17

U18

U19

U13

U14

U15

U20

U21

U22

L34

IO_CR

M32

IO_CR

R32

IO_CR

U34

IO_CR

W34

IO_CR

Y32

IO_CR

AC32

IO_CR

AD34

IO_CR

AM26

PB30A

PB37A

TRUE

AP27

PB30C

PB37C

L1T_A0

TRUE

AN27

PB30D

PB37D

L1C_A0

COMPLEMENT

AK25

PB31C

PB38C

REF

_BR_01

L2T_D0

TRUE

AL26

PB31D

PB38D

L2C_D0

COMPLEMENT

AM27

PB32C

PB39C

L3T_D1

TRUE

AK26

PB32D

PB39D

L3C_D1

COMPLEMENT

AP28

PB33C

PB40C

L4T_A0

TRUE

AN28

PB33D

PB40D

REF

_BR_02

L4C_A0

COMPLEMENT

AL27

PB34A

PB41C

L5T_A0

TRUE

AL28

PB34B

PB41D

L5C_A0

COMPLEMENT

AK27

PB34C

PB42C

TRUE

AM28

PB35A

PB43A

TRUE

AN29

PB35B

PB43D

COMPLEMENT

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

Lucent Technologies Inc.

109

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

AK28

PB35C

PB44C

L6T_D1

TRUE

AM29

PB35D

PB44D

REF

_BR_03

L6C_D1

COMPLEMENT

AP29

PB36B

PB45B

L7C_A2

COMPLEMENT

AL29

PB36A

PB45A

L7T_A2

TRUE

AP30

PB36C

PB45C

L8T_A0

TRUE

AN30

PB36D

PB45D

L8C_A0

COMPLEMENT

AK29

PB37A

PB46C

L9T_D1

TRUE

AM30

PB37B

PB46D

REF

_BR_04

L9C_D1

COMPLEMENT

AL30

PB37C

PB47C

PLL_CK5T/

PPLL

L10T_D2

TRUE

AP31

PB37D

PB47D

PLL_CK5C/

PPLL

L10C_D2 COMPLEMENT

AJ30

PR38A

PR46C

PLL_CK4T/PLL2

(155.52 MHz)

L11T_D1

TRUE

AK32

PR38B

PR46D

PLL_CK4C/PLL2

(155.52 MHz)

L11C_D1 COMPLEMENT

AL33

PR38C

PR45C

L12T_D2

TRUE

AH30

PR38D

PR45D

L12C_D2 COMPLEMENT

AL34

PR37C

PR44C

REF

_BR_05

L13T_D2

TRUE

AJ31

PR37D

PR44D

L13C_D2 COMPLEMENT

AJ32

PR36C

PR43C

L14T_D0

TRUE

AH31

PR36D

PR43D

L14C_D0 COMPLEMENT

AK33

PR35A

PR42C

L15T_D2

TRUE

AG30

PR35B

PR42D

L15C_D2 COMPLEMENT

AK34

PR35C

PR41C

REF

_BR_06

L16T_D0

TRUE

AJ33

PR35D

PR41D

L16C_D0 COMPLEMENT

AF30

PR34A

PR40A

TRUE

AJ34

PR34C

PR40C

L17T_D2

TRUE

AG31

PR34D

PR40D

L17C_D2 COMPLEMENT

AH32

PR33A

PR39A

TRUE

AG32

PR33C

PR39C

L18T_D0

TRUE

AH33

PR33D

PR39D

REF

_BR_07

L18C_D0 COMPLEMENT

AE30

PR32A

PR38A

TRUE

AH34

PR32C

PR38C

L19T_D2

TRUE

AF31

PR32D

PR38D

L19C_D2 COMPLEMENT

AF32

PR31A

PR37A

TRUE

AG33

PR31C

PR37C

L20T_D1

TRUE

AE31

PR31D

PR37D

REF

_BR_08

L20C_D1 COMPLEMENT

AG34

PR30A

PR36A

TRUE

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

110

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

AF33

PR30B

PR36B

COMPLEMENT

AD30

PR30C

PR36C

L21T_D3

TRUE

AF34

PR30D

PR36D

L21C_D3 COMPLEMENT

AN31

AK31

V16

V17

V18

V19

V34

W16

W17

W18

W19

Y13

Y14

V13

V14

V15

V20

V21

V22

AK30

IO_BR

AL32

IO_BR

AM31

IO_BR

AM33

IO_BR

AM34

IO_BR

AN32

IO_BR

AP32

IO_BR

AN15

PB17A

PB21A

TRUE

AN16

PB17C

PB21C

L1T_D2

TRUE

AK17

PB17D

PB21D

L1C_D2

COMPLEMENT

AL16

PB18A

PB22A

TRUE

AM16

PB18C

PB22C

REF

_BC_01

L2T_A1

TRUE

AP16

PB18D

PB22D

L2C_A1

COMPLEMENT

AN17

PB19A

PB23A

L3T_A1

TRUE

AL17

PB19B

PB23B

L3C_A1

COMPLEMENT

AM17

PB19C

PB23C

PBCK0T

L4T_A0

TRUE

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

Lucent Technologies Inc.

111

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

AM18

PB19D

PB23D

PBCK0C

L4C_A0

COMPLEMENT

AN18

PB20B

PB24B

L5C_A1

COMPLEMENT

AL18

PB20A

PB24A

L5T_A1

TRUE

AL19

PB20C

PB24C

REF

_BC_02

L6T_D0

TRUE

AK18

PB20D

PB24D

L6C_D0

COMPLEMENT

AM19

PB21A

PB25C

L7T_A0

TRUE

AN19

PB21B

PB25D

L7C_A0

COMPLEMENT

AP20

PB21C

PB26C

L8T_A0

TRUE

AN20

PB21D

PB26D

REF

_BC_03

L8C_A0

COMPLEMENT

AL20

PB22A

PB27A

TRUE

AP21

PB22C

PB27C

L9T_A0

TRUE

AN21

PB22D

PB27D

L9C_A0

COMPLEMENT

AK19

PB23A

PB28A

TRUE

AM21

PB23C

PB28C

PBCK1T

L10T_A0

TRUE

AL21

PB23D

PB28D

PBCK1C

L10C_A0 COMPLEMENT

AK20

PB24A

PB29A

TRUE

AP22

PB24C

PB29C

L11T_A0

TRUE

AN22

PB24D

PB29D

L11C_A0 COMPLEMENT

AK21

PB25A

PB30A

TRUE

AL22

PB25C

PB30C

L12T_A0

TRUE

AL23

PB25D

PB30D

REF

_BC_04

L12C_A0 COMPLEMENT

AK22

PB26A

PB31C

L13T_D2

TRUE

AN23

PB26B

PB31D

L13C_D2 COMPLEMENT

AP23

PB26C

PB32C

L14T_A3

TRUE

AK23

PB26D

PB32D

REF

_BC_05

L14C_A3 COMPLEMENT

AN24

PB27A

PB33C

L15T_A0

TRUE

AM24

PB27B

PB33D

L15C_A0 COMPLEMENT

AL24

PB27C

PB34C

L16T_D2

TRUE

AP25

PB27D

PB34D

L16T_D2 COMPLEMENT

AN25

PB28A

PB35A

TRUE

AK24

PB28C

PB35C

L17T_D3

TRUE

AP26

PB28D

PB35D

REF

_BC_06

L17C_D3 COMPLEMENT

AN26

PB29A

PB36A

TRUE

AL25

PB29C

PB36C

L18T_A0

TRUE

AM25

PB29D

PB36D

L18C_A0 COMPLEMENT

Y15

Y20

Y21

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

112

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

Y22

AA13

AA14

AA15

AA20

AA21

AA22

AB3

W13

W14

W15

W20

W21

W22

AM12

IO_BC

AM15

IO_BC

AM20

IO_BC

AM23

IO_BC

AP11

IO_BC

AP17

IO_BC

AP19

IO_BC

AP24

IO_BC

AF1

PL32D

PL38D

L1C_A0

COMPLEMENT

AF2

PL32C

PL38C

REF

_BL_01

L1T_A0

TRUE

AE4

PL32A

PL38A

TRUE

AF3

PL33D

PL39D

L2C_A0

COMPLEMENT

AF4

PL33C

PL39C

D10

L2T_A0

TRUE

AE5

PL34D

PL40D

L3C_D3

COMPLEMENT

AG1

PL34C

PL40C

REF

_BL_02

L3T_D3

TRUE

AG2

PL34B

PL41D

L4C_D2

COMPLEMENT

AF5

PL34A

PL41C

L4T_D2

TRUE

AG3

PL35B

PL42D

D11

L5C_A0

COMPLEMENT

AG4

PL35A

PL42C

D12

L5T_A0

TRUE

AH1

PL36D

PL43D

L6C_A1

COMPLEMENT

AH3

PL36C

PL43C

L6T_A1

TRUE

AH4

PL36B

PL44D

REF

_BL_03

L7C_D0

COMPLEMENT

AG5

PL36A

PL44C

D13

L7T_D0

TRUE

AH2

PL37D

PL44B

COMPLEMENT

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

Lucent Technologies Inc.

113

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

AJ2

PL37B

PL45D

L8C_D2

COMPLEMENT

AH5

PL37A

PL45C

REF

_BL_04

L8T_D2

TRUE

AJ3

PL38C

PL45A

TRUE

AJ4

PL38B

PL46D

COMPLEMENT

AJ1

PL38A

PL46A

TRUE

AK1

PL39D

PL47D

PLL_CK7C/

HPPLL

L9C_A0

COMPLEMENT

AK2

PL39C

PL47C

PLL_CK7T/

HPPLL

L9T_A0

TRUE

AJ5

PL39B

PL47B

L10C_D1 COMPLEMENT

AK3

PL39A

PL47A

L10T_D1

TRUE

AL5

PB2A

DP2

L11T_A0

TRUE

AM5

PB2B

L11C_A0 COMPLEMENT

AN4

PB2C

PLL_CK6T/

PPLL

L12T_D2

TRUE

AK7

PB2D

PLL_CK6C/

PPLL

L12C_D2 COMPLEMENT

AP4

PB3A

TRUE

AL6

PB3C

L13T_A0

TRUE

AM6

PB3D

L13C_A0 COMPLEMENT

AL7

PB4A

PB4C

REF

_BL_05

L14T_D1

TRUE

AN5

PB4B

PB4D

DP3

L14C_D1 COMPLEMENT

AK8

PB4C

PB5C

L15T_D3

TRUE

AP5

PB4D

PB5D

L15C_D3 COMPLEMENT

AN6

PB5C

PB6C

REF

_BL_06

L16T_D2

TRUE

AK9

PB5D

PB6D

D14

L16C_D2 COMPLEMENT

AP6

PB6A

PB7C

L17T_D2

TRUE

AL8

PB6B

PB7D

L17C_D2 COMPLEMENT

AM7

PB6C

PB8C

D15

L18T_A0

TRUE

AM8

PB6D

PB8D

D16

L18C_A0 COMPLEMENT

AN7

PB7A

PB9A

TRUE

AK10

PB7C

PB9C

D17

L19T_D3

TRUE

AP7

PB7D

PB9D

D18

L19C_D3 COMPLEMENT

AL9

PB8A

PB10A

TRUE

AK11

PB8C

PB10C

REF

_BL_07

L20T_D1

TRUE

AM9

PB8D

PB10D

D19

L20C_D1 COMPLEMENT

AN8

PB9A

PB11A

TRUE

AL10

PB9C

PB11C

D20

L21T_D2

TRUE

AP8

PB9D

PB11D

D21

L21C_D2 COMPLEMENT

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

114

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

AN9

PB10A

PB12A

TRUE

AP9

PB10C

PB12C

REF

_BL_08

L22T_D1

TRUE

AM10

PB10D

PB12D

D22

L22C_D1 COMPLEMENT

AK12

PB11A

PB13A

L23T_D0

TRUE

AL11

PB11B

PB13B

L23C_D0 COMPLEMENT

AN10

PB11C

PB13C

D23

L24T_A0

TRUE

AP10

PB11D

PB13D

D24

L24C_A0 COMPLEMENT

AN11

PB12A

PB14A

L25T_A0

TRUE

AM11

PB12B

PB14B

L25C_A0 COMPLEMENT

AK13

PB12C

PB14C

REF

_BL_09

L26T_D0

TRUE

AL12

PB12D

PB14D

D25

L26C_D0 COMPLEMENT

AN12

PB13A

PB15C

L27T_D2

TRUE

AK14

PB13B

PB15D

L27C_D2 COMPLEMENT

AP12

PB13C

PB16C

D26

L28T_A0

TRUE

AP13

PB13D

PB16D

D27

L28C_A0 COMPLEMENT

AL13

PB14A

PB17C

L29T_A1

TRUE

AN13

PB14B

PB17D

L29C_A1 COMPLEMENT

AP14

PB14C

PB18C

REF

_BL_10

L30T_D3

TRUE

AK15

PB14D

PB18D

D28

L30C_D3 COMPLEMENT

AN14

PB15A

PB19A

TRUE

AM14

PB15C

PB19C

D29

L31T_D1

TRUE

AK16

PB15D

PB19D

D30

L31C_D1 COMPLEMENT

AL14

PB16A

PB20A

TRUE

AP15

PB16C

PB20C

REF

_BL_11

L32T_A2

TRUE

AL15

PB16D

PB20D

D31

L32C_A2 COMPLEMENT

AK4

PTEMP

AL1

LVDS_R

AL2

AK6

AB13

AB14

AB15

AB20

AB21

AB22

AB32

AL4

AL31

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

Lucent Technologies Inc.

115

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

AM3

AM13

Y16

Y17

Y18

Y19

AA16

AA17

AK5

IO_BL

AL3

IO_BL

AM1

IO_BL

AM2

IO_BL

AM4

IO_BL

AN3

IO_BL

AP3

IO_BL

PL12D

PL14D

A15

L1C_D1

COMPLEMENT

PL12C

PL14C

A14

L1T_D1

TRUE

PL12B

PL15D

L2C_D0

COMPLEMENT

PL12A

PL15C

L2T_D0

TRUE

PL13D

PL16D

REF

_CL_01

L3C_D1

COMPLEMENT

PL13C

PL16C

L3T_D1

TRUE

PL13B

PL17D

L4C_A1

COMPLEMENT

PL13A

PL17C

L4T_A1

TRUE

PL14D

PL18D

RDY/BUSY/

RCLK

L5C_D3

COMPLEMENT

PL14C

PL18C

REF

_CL_02

L5T_D3

TRUE

PL15D

PL19D

A13

L6C_A2

COMPLEMENT

PL15C

PL19C

A12

L6T_A2

TRUE

PL16D

PL20D

L7C_D0

COMPLEMENT

PL16C

PL20C

L7T_D0

TRUE

PL16A

PL20A

TRUE

PL17D

PL21D

A11

L8C_A0

COMPLEMENT

PL17C

PL21C

REF

_CL_03

L8T_A0

TRUE

PL17A

PL21A

TRUE

PL18D

PL22D

L9C_D2

COMPLEMENT

PL18C

PL22C

L9T_D2

TRUE

PL18A

PL22A

L10T_A1

TRUE

PL18B

PL22B

L10C_A1 COMPLEMENT

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

116

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

PL19D

PL23D

RD/MPI_STRB

L11C_D0 COMPLEMENT

PL19C

PL23C

REF

_CL_04

L11T_D0

TRUE

PL19A

PL23A

L12T_D3

TRUE

PL19B

PL23B

L12C_D3 COMPLEMENT

PL20D

PL24D

PLCK0C

L13C_A0 COMPLEMENT

PL20C

PL24C

PLCK0T

L13T_A0

TRUE

PL20B

PL24B

L14C_A0 COMPLEMENT

PL20A

PL24A

L14T_A0

TRUE

PL21D

PL25D

A10

L15C_A0 COMPLEMENT

PL21C

PL25C

L15T_A0

TRUE

PL21B

PL25B

L16C_A0 COMPLEMENT

PL21A

PL25A

L16T_A0

TRUE

PL22D

PL26D

L17C_A2 COMPLEMENT

PL22C

PL26C

REF

_CL_05

L17T_A2

TRUE

PL23D

PL27D

L18C_D1 COMPLEMENT

PL23C

PL27C

L18T_D1

TRUE

PL23A

PL27A

TRUE

PL24D

PL28D

PLCK1C

L19C_D2 COMPLEMENT

AA1

PL24C

PL28C

PLCK1T

L19T_D2

TRUE

AA2

PL24A

PL28A

TRUE

PL25D

PL29D

REF

_CL_06

L20C_A0 COMPLEMENT

PL25C

PL29C

L20T_A0

TRUE

AA3

PL25A

PL29A

TRUE

AA5

PL26D

PL30D

L21C_D3 COMPLEMENT

AB1

PL26C

PL30C

L21T_D3

TRUE

AB2

PL26B

PL31D

COMPLEMENT

AA4

PL27D

PL32D

WR/MPI_RW

L22C_A0 COMPLEMENT

AB4

PL27C

PL32C

REF

_CL_07

L22T_A0

TRUE

AB5

PL27B

PL33D

L23C_D3 COMPLEMENT

AC1

PL27A

PL33C

L23T_D3

TRUE

AC2

PL28D

PL34D

L23C_A2 COMPLEMENT

AC5

PL28C

PL34C

REF

_CL_08

L23T_A2

TRUE

AD2

PL29D

PL35D

L23C_A0 COMPLEMENT

AD3

PL29C

PL35C

L23T_A0

TRUE

AC4

PL29A

PL35A

TRUE

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

Lucent Technologies Inc.

117

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

680 BGA

Ball

Bank

REF

Group

General-Purpose User I/O

Additional

Function

Pair

Differential

OR4E4

OR4E6

AE1

PL30D

PL36D

L24C_A0 COMPLEMENT

AE2

PL30C

PL36C

L24T_A0

TRUE

AD4

PL31D

PL37D

DP0

L25C_D0 COMPLEMENT

AE3

PL31C

PL37C

DP1

L25T_D0

TRUE

AD5

PL31A

PL37A

TRUE

AM22

AM32

AN1

AN2

AN33

AN34

AP1

AP2

AP18

AP33

AP34

AA18

AA19

AB16

AB17

AB18

AB19

IO_CL

AC3

IO_CL

AD1

IO_CL

Pin Information

(continued)

Table 46. OR4E6 680-Pin PBGAM Pinout (continued)

118

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Package Thermal Characteristics
Summary

There are three thermal parameters that are in com-
mon use:

JC, and

. It should be noted that all

the parameters are affected, to varying degrees, by
package design (including paddle size) and choice of
materials, the amount of copper in the test board or
system board, and system airflow.

This is the thermal resistance from junction to ambient
(theta-JA, R-theta, etc.).

where T

is the junction temperature, T

is the ambient

air temperature, and Q is the chip power.

Experimentally,

is determined when a special ther-

mal test die is assembled into the package of interest,
and the part is mounted on the thermal test board. The
diodes on the test chip are separately calibrated in an
oven. The package/board is placed either in a JEDEC
natural convection box or in the wind tunnel, the latter
for forced convection measurements. A controlled
amount of power (Q) is dissipated in the test chip's
heater resistor, the chip's temperature (T

) is deter-

mined by the forward drop on the diodes, and the ambi-
ent temperature (T

) is noted. Note that

expressed in units of °C/W.

This JEDEC designated parameter correlates the junc-
tion temperature to the case temperature. It is generally
used to infer the junction temperature while the device
is operating in the system. It is not considered a true
thermal resistance, and it is defined by:

where T

is the case temperature at top dead center,

is the junction temperature, and Q is the chip power.

During the

measurements described above,

besides the other parameters measured, an additional
temperature reading, T

, is made with a thermocouple

attached at top-dead-center of the case.

is also

expressed in units of °C/W.

This is the thermal resistance from junction to case. It
is most often used when attaching a heat sink to the
top of the package. It is defined by:

The parameters in this equation have been defined
above. However, the measurements are performed with
the case of the part pressed against a water-cooled
heat sink to draw most of the heat generated by the
chip out the top of the package. It is this difference in
the measurement process that differentiates

from

JC.

is a true thermal resistance and is expressed

in units of °C/W.

This is the thermal resistance from junction to board
(

). It is defined by:

where T

is the temperature of the board adjacent to a

lead measured with a thermocouple. The other param-
eters on the right-hand side have been defined above.
This is considered a true thermal resistance, and the
measurement is made with a water-cooled heat sink
pressed against the board to draw most of the heat out
of the leads. Note that

is expressed in units of

°C/W, and that this parameter and the way it is mea-
sured are still in JEDEC committee.

--------------------

Lucent Technologies Inc.

119

Preliminary Data Sheet
December 2000

ORCA Series 4 FPGAs

Package Thermal Characteristics

Table 47. ORCA Series 4 FPGAs Plastic Package Thermal Guidelines

Package Coplanarity

The coplanarity limits of the Lucent packages are as follows:

PBGA: 8.0 mils

EBGA: 8.0 mils

PBGAM: 8.0 mils

Package Parasitics

The electrical performance of an IC package, such as signal quality and noise sensitivity, is directly affected by the
package parasitics. Table 48 lists eight parasitics associated with the ORCA packages. These parasitics represent
the contributions of all components of a package, which include the bond wires, all internal package routing, and
the external leads.

Four inductances in nH are listed: L

and L

SL,

the self-inductance of the lead; and L

and L

, the mutual induc-

tance to the nearest neighbor lead. These parameters are important in determining ground bounce noise and
inductive crosstalk noise. Three capacitances in pF are listed: C

, the mutual capacitance of the lead to the nearest

neighbor lead; and C

and C

, the total capacitance of the lead to all other leads (all other leads are assumed to be

grounded). These parameters are important in determining capacitive crosstalk and the capacitive loading effect of
the lead. Resistance values are in m

The parasitic values in

Table 48 are for the circuit model of bond wire and package lead parasitics. If the mutual

capacitance value is not used in the designer's model, then the value listed as mutual capacitance should be added
to each of the C

and C

capacitors.

Table 48. ORCA Series 4 FPGAs Package Parasitics

Package

(°C/W)

T = 70 °C Max, T

= 125 °C Max

0 fpm (W)

0 fpm

200 fpm

500 fpm

352-Pin PBGA

19.0

16.0

15.0

2.9

432-Pin EBGA

11.0

8.5

7.5

5.0

680-Pin PBGAM

14.5

TBD

3.8

Package Type

352-Pin PBGA

220

1.5

7--12

3--6

432-Pin EBGA

4.0

1.5

500

1.0

0.3

3.0--5.5

0.5--1

680-Pin PBGAM

3.8

1.3

250

1.0

0.3

2.8--5

0.5--1

Preliminary Data Sheet

ORCA Series 4 FPGAs

December 2000

Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information. ORCA is a registered trademark of Lucent Technologies Inc. Foundry is a trademark of Xilinx, Inc.

December 2000
DS01-024NCIP (Replaces DS00-221FPGA)

For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET:

http://www.lucent.com/micro, or for FPGA information, http://www.lucent.com/orca

E-MAIL:

docmaster@micro.lucent.com

N. AMERICA:

Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256

Tel. (65) 778 8833, FAX (65) 777 7495

CHINA:

Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai
200233 P. R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652

JAPAN:

Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700

EUROPE:

Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),

FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)

Ordering Information

5-6435 (F)

Table 49. Series 4 Package Matrix (Speed Grades)

Table 50. Package Options

Packages

352-Pin PBGA

1.27 mm

432-Pin EBGA

1.27 mm

680-Pin PBGAM

1 mm

OR4E2

-1/-2

OR4E4

-1/-2

OR4E6

-1/-2

OR4E10

-1/-2

Symbol

Description

Plastic Ball Grid Array (PBGA)

Enhanced Ball Grid Array (EBGA)

Plastic Multilayer Ball Grid Array (PBGAM)

DEVICE TYPE

PACKAGE TYPE

OR4Exx -1 BM

NUMBER OF PINS

680

SPEED GRADE

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: OR4E10

Document Outline

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Document Outline

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