May 3, 2004; 6251-633-1AI

Micronas

Contents

Page

Section

Title

PVP 9390A

ADVANCE INFORMATION

General Description

1.1.

Features

1.2.

Block Diagram

Functional Description

2.1.

Analog Front-end

2.1.1.

Input Selection

2.1.2.

AD-Conversion

2.1.3.

Automatic Gain Control

2.1.4.

Signal Magnitudes

2.2.

Inset Synchronization

2.3.

Chroma Decoding And Standard Identification

2.4.

Comb Filtering

2.5.

Luminance Processing

2.6.

Decimation

2.6.1.

Single PIP Mode

2.6.2.

Continuos Zoom

2.6.3.

Horizontal And Vertical Fine Positioning

2.6.4.

Multi Display Mode

2.6.5.

Split Screen

2.6.6.

Multi-PIP Mode

2.7.

Display Control

2.7.1.

100 Hz Frame Mode

2.7.2.

Mixed Standard Applications and (S)VGA Support

2.7.3.

Display Standard

2.7.4.

Picture Positioning

2.7.5.

Wipe In/Wipe Out

2.8.

Output Signal Processing

2.8.1.

Luminance Peaking

2.8.2.

RGB Matrix

2.8.3.

Frame Generation And Colored Background

2.8.4.

16:9 Inset Picture Support

2.8.5.

Parent Clock Generation

2.8.6.

Select Signal

2.8.7.

Automatic Brightness Reduction

2.9.

On Screen Display (OSD)

2.9.1.

Display Format

2.9.2.

Character Programming

2.9.3.

Character and Character Background Color

2.10.

DA-Conversion And RGB/YUV Switch

2.10.1.

Pedestal Level Adjustment

2.10.2.

Contrast, Brightness and Peak Level Adjustment

2.11.

Data Slicer

2.11.1.

Closed Caption

2.11.2.

Wide-screen Signalling (WSS)

2.11.3.

Indication of New Data

2.11.4.

Violence Protection

PVP 9390A

ADVANCE INFORMATION

May 3, 2004; 6251-633-1AI

Micronas

PVP 9390A
Picture-in-Picture IC

1. General Description

The PVP 9390A is a Picture-in-Picture (PIP) processor
that combines high-quality digital PIP signal process-
ing, digital multistandard color decoding and A/D-D/A-
conversion on a single chip. The device is equipped
with CVBS, Y/C, and YUV input interfaces to display
standard and high-quality video signals e.g. from a
DVD source. The PVP 9390A replaces the Micronas
PIPIV Picture-in-Picture processor and provides
future-proof characteristics.

The integrated digital color decoder is able to decode
all analog TV standards (PAL, NTSC, and SECAM)
and detects the standard automatically. Therefore, the
IC is suited for world-wide use.

A picture reduction from 1/4 to 1/81 of original size,
selectable in fine steps, is possible. The transfer func-
tions of the decimation filters are optimally matched to
the selected picture size reduction and can further-
more be adjusted to the viewer's requirements by a
selectable peaking. A maximum of 324 luminance and
2x81 chrominance pixels per line are stored in the
memory. The PIP supports split-screen applications as
well as multi-PIP display.

1.1. Features

� Single-chip solution

� A/D-conversion for CVBS or Y/C or YUV, multi-

standard color decoding, PLL for synchronization
of inset channel, decimation filtering, embedded
memory, RGB-matrix, D/A-conversion, RGB/YUV
switch, data-slicer and clock generation inte-
grated on chip

� Analog inputs

� 4x CVBS, 2x Y/C, 2x YUV (some inputs shared)

� Clamping of each input

� All ADCs with 8-bit amplitude resolution

� Automatic Gain Control (AGC) for Y and CVBS

� Inset synchronization

� Multiple time constants for reliable synchroniza-

tion

� Automatic recognition of 625 lines/525 lines stan-

dard

� Color decoder

� PAL-B/G, PAL-M, PAL-N(Argentina), PAL60,

NTSC-M, NTSC4.4, and SECAM

� Adjustable color saturation

� Hue control for NTSC

� Automatic chroma control (

24 dB ... +6 dB)

� Automatic recognition of chroma standards:

different search strategies selectable

� Single crystal for all standards

� IF-characteristic compensation filter

� Decimation

� PIP sizes between 1/81 and 1/4 adjustable in

steps of 2 lines and 4 pixel

� Resolution up to 324 luminance and 2x81 chromi-

nance pixels per inset line

� Horizontal and vertical filtering dependent on pic-

ture size

� Automatic zoom in/out possible in three speeds

� Display features

� 7 bits per pixel stored in memory

� Field and joint-line free frame mode display (even

at 100/120 Hz AABB with picture sizes

1/9)

� Two "split-screen" modes with horizontal decima-

tion of 2 and vertical of 1.5 or 1.0 (1.0 with single-
scan 50/60 Hz display only)

� POP display

� Up to 12 pictures of 1/36th size (11 still and 1

moving)

� Up to 6 pictures of 1/16th size (5 still and 1 mov-

ing)

� Up to 3 pictures of 1/9th size (2 still and 1 mov-

ing)

� Display on VGA and SVGA screen (f

limited to

40 kHz)

� 8 different read frequencies for 16:9 compatibility

� Line-doubling mode for progressive scan applica-

tions

� Freeze picture

� Coarse positioning at 4 corners of the parent pic-

ture

� Fine positioning at steps of 4 pixels and 2 lines

� Wipe in/out programmable with 3 time periods

� Output signal processing

� 7-bit DAC

� RGB or YUV switch: Insertion of an external

source without PIP processing

� Digital interpolation for anti-imaging

� Adjustable transient improvement for luma (peak-

ing)

� Contrast, brightness, and pedestal level adjust-

able

� Analog outputs: Y, +(B

Y), +(R

Y), or

Y),

Y) or RGB

� Three RGB matrices available: NTSC(Japan),

NTSC(USA), or EBU

� 64 different background colors and 4096 different

frame colors

� Plain or 3D-frame with variable width and height

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Micronas

1.2. Block Diagram

Fig. 1�1: Block Diagram

RGB

Matr

eaking

er-

sampling

Inser

tion

RAM

768kbit

OSD &

r
ame

Gener

ation

Displa

Controller

arent

Sync

Processing

Cloc

Synthesiz

Memor

Controller

wcomp

H/V Scaler

Decimation

Color

Decoder

AL/SECAM/

NTSC

Y/C &

Sync

Separ

ation

Inset

Sync

Processing

Input

Select

Clamp

Gain

DEMUX

Data Slicer

Acquisition

Controller

MUX

3x ADC

8bit

r
iple

3x7bit

IN1

IN3

FSW

OUT1

OUT2

OUT3

SEL

ast

RGB/YUV

Switch

IN2

VDD33D

VSS33D

VDD18

VSS18

CVBS1

CVBS2

CVBS3

VSS33ADC

VDD18ADC

XIN

I2C1

SCL

HSP

VSP

20.25 MHz

INTR

CVBS4

CLK

OUT

GP0..2

I2C2

VDD33P

VSS33P

VSS18ADC

VDD33ADC

RESET

PVP 9390A

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PVP 9390A

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May 3, 2004; 6251-633-1AI

2. Functional Description

2.1. Analog Front-end

2.1.1. Input Selection

An analog inset CVBS signal can be applied to the
inputs CVBS1-3 of PVP 9390A. Each of these sources
is selectable via I

C bus (CVBSEL). Additionally

CVBS4 can be enabled with INSEL. CVBS1/CVBS2
and CVBS2/CVBS3 can be used as separate Y/C
inputs. YUV sources can be connected to CVBS1,
CVBS2 and CVBS3 or to Y, U, V. The YUV source is
enabled by YUVSEL or INSEL. The PVP 9390A can
operate in applications with both YUV and CVBS sig-
nals without an external switch. See Fig. 2�1.

2.1.2. AD-Conversion

All signal are clamped and AD-converted with an
amplitude resolution of 8 bit. CVBS and Y signals are
clamped to the sync bottom or backporch, selectable
by CLMSTGY. U/V and C signals are always clamped
to their mid-level during blanking.

The clamping pulse can be shifted in position (CLMP-
IST) and length (CLMPID) to adjust to the specific
application. The ADCs are driven by a 20.25 MHz free
running crystal clock which is not related to the incom-
ing CVBS signal.

To avoid aliasing by sub-sampling the CVBS signal
and the Y/C signals should be band-limited to 10 MHz.
In the same manner the U/V signal frequency spec-
trum should not exceed 5 MHz. Analog anti-alias filter
can be enabled for each channel. The digital filtering
suppresses all frequencies above the usable spec-
trum.

2.1.3. Automatic Gain Control

To accommodate to different CVBS input voltages an
automatic gain control has been implemented. The
chip works correctly for input voltages in the range
from 0.5 to 1.5 V

. For best signal-to-noise ratio, the

maximum CVBS amplitude is recommended if avail-
able. The AGC behavior can be chosen out of four
possibilities (AGCMDE).

The sync height serves as reference for the gain con-
trol in the typical application. When using overflow
detection only, the gain is set to maximum and is
reduced whenever an overflow occurs. This procedure
will be executed again when a channel change is
detected or the gain control is manually reset by
AGCRES.

Fig. 2�1: Clamping Timing

Fig. 2�2: AGC Characteristic

I ns et
V id eo

CLAMPI

C LMPID

CLMPIST

0.5

1.5

Automatic Gain Control Characteristic

AGCVAL

I
nput V

o
lta

[

]

PVP 9390A

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May 3, 2004; 6251-633-1AI

Micronas

2.1.4. Signal Magnitudes

The nominal CVBS signal with 75 % color has a mag-
nitude of 1 V

. The upper headroom is left to permit

signals with 100 % color resulting in 1.23 V

. The Y-

signal must always contain the sync part. Its levels cor-

respond to the CVBS levels except for the missing
color and burst. After A/D conversion the video part is
clamped to its black value and is amplified to 224 digi-
tal steps. The nominal signal levels ensure correct
brightness and saturation. The YUV signal levels con-
form to the ITU 601 recommendation.

Fig. 2�3: CVBS/Y and Chroma ADC Input Signal Range

Fig. 2�4: UV Input Signal Range

Table 2�1: Input selection

INSEL

CVBSEL

YUVSEL

Input

CVBS1

CVBS2

CVBS3

CVBS4

CVBS

U (P

)

V (P

)

CVBS

U (P

)

V (P

)

lower headroom

Y =

1
V

p
p

CRY

= 1.

2 V

p
p

% chr

o
m

h
r
o
m

r
s
t

white

black

r
s
t

128

224

255

217

255

CRY

= 1.

2 V

p
p

upper headroom

lower headroom

CRUV

8 Vp

p
p

128

240

255

75% U

212

CRUV

0.8 V

p
p

0.7

Vpp

128

240

255

212

lower headroom

upper headroom

lower headroom

75% V

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PVP 9390A

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May 3, 2004; 6251-633-1AI

2.2. Inset Synchronization

Horizontal and vertical sync pulses are separated after
elimination of the high frequency components of the
CVBS signal by a low pass filter. Horizontal sync
pulses are generated by a digital phase-locked-loop
(DPLL). Its time constant is adjustable between fast
and slow behavior in four steps (PLLITC) to consider
different input sources (e.g. VCR). Noisy input signals
become more stable when a noise-reduction is
enabled (NSRED). Additionally weak input signals
from a satellite dish ('fishes') become more stable
when SATNR is enabled. Both should be enabled to
have best available performance. A vertical flywheel
mode improves vertical sync separation for weak sig-
nals (VFLYWHL, VFLYWHLMD). Additionally, v-syncs
may be gated by VTHRL50/60 and VTHRH50/60 to
reject invalid v-syncs. Dependent on detected line
standard, the VTHRx50 or VTHRx60 setting is used.
50 Hz or 60 Hz operation for sync separation may be
forced separately or selected to work automatically
(FLNSTRD).When NOSIGB is enabled, a colored
background is shown instead of the picture when PIP
is out of (horizontal) synchronization. The detected line
standard is indicated by SYNCSTAT.

2.3. Chroma Decoding And Standard Identification

The system is able to decode NTSC and PAL signals
with a subcarrier of 3.58 MHz and 4.43 MHz (PAL B/M/
N/60, NTSC M/4.4) as well as SECAM signals with
4.05/4.2 MHz subcarrier. The system may be forced to
a certain standard, or an automatic standard detection
can be used (CSTAND). For automatic standard
detection, some standards which are not likely to be
received can be ignored to improve the detection pro-
cess (CSTDEX).

Depending on the detected line standard (525 or
625 lines) the color standard detection circuit searches
for 60 Hz signals (NTSC-M/PAL-M/PAL 60/NTSC44) or
50 Hz signals (PAL-B/SECAM/PAL-N) respectively.
Within each line standard, the standard is detected by

consequently switching from one to another. This stan-
dard detection process can be set to slow or fast
behavior (LOCKSP). In slow behavior, 25 fields are
used to detect the standard, whereas 15 fields are
used in fast behavior. If unsuccessful within this time
period the system tries to detect another standard. For
SECAM detection, a choice between different recogni-
tion levels is possible (SCMIDL, SECACCL, SECDIV)
and the evaluated burst position is selectable
(BGPOS).

For getting the chrominance information the digitized
video signal is multiplied with the regenerated color
subcarrier once in-phase and once phase-shifted by
90 �. After lowpass filtering digital UV is available for
PAL and NTSC. The subcarrier is regenerated by a
digital PLL. At SECAM operation the PLL runs free and
generates the line-wise alternating subcarriers. A
CORDIC structure demodulates the frequency-modu-
lated UV signals. The following SECAM de-emphasis
filter characteristic is adjustable (DEEMP).
The chroma signal can be filtered before demodulation
by means of a selectable IF-prefilter (IFCOMP).

Table 2�2: ADC conversion range and required input signal voltage

AGCVAL

Conversion
Range
CRYC

Signal
Range
SRY

Signal
Range
SRC

Conversion
Range
CRUV

Signal
Range
SRUV

0.5 Vpp

0.42 Vpp

...

1.2 Vpp

1.0 Vpp

0.89 Vpp

0.8 Vpp

0.7 Vpp

...

1.5 Vpp

1.25 Vpp

Table 2�3: Considered color standards for automatic
standard detection

CSTDEX

NTSC-M

-
N

-
M

-
B

SEC

NTSC 44

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The Hue control (HUE) influences the phase of the
demodulation subcarrier between

44.8 � and 43.4 � in

steps of 1.4 �. This is provided for NTSC only and
adjustment is ineffective for PAL and SECAM signals.

The reference for the subcarrier generation is a crystal
stable clock of 20.25000 MHz. In order to avoid color
standard detection problems, the maximum deviation
of this frequency should not exceed 100 ppm. For a
good PLL locking behavior a maximum deviation of
40 ppm is recommended. A small frequency adjust-
ment (

150 ... +310 ppm) is possible for using a crystal

with small frequency deviations (SCADJ). For test pur-
poses, CPLL allows to open the loop of the chroma
PLL.

For deviations in the chroma signal up to 30 dB, a sta-
ble output amplitude after chroma decoding is
achieved due to the ACC (Automatic Chroma Control).
If the chroma signal (color burst) is below a selectable
threshold (CKILL), the color will be switched off. Alter-
natively the color-killer can be bypassed and the color
can be switched on or off under all conditions
(COLON). By setting ACCFIX, the automatic chroma
control is disabled and set to a default value.

The bandwidth of the chroma filter is adjustable via
CHRBW. The bandwidth depends on whether the
decoder is in SECAM operation or not. A change in
CHRBW does not result in a chrominance position
shift on the screen.

CKSTAT can be read out and gives information
whether the color is switched on or off. STDET indi-
cates the detected color standard. Additionally PALID
and PALDET signal whether a PAL signal is applied.

2.4. Comb Filtering

Depending on the selected picture size and color stan-
dard, a comb filtering is performed for luminance and
chrominance. A comb filter uses the spectral interleav-
ing of the encoded luminance and chrominance to
separate both without cross artifacts. Thus cross-color
and cross-luminance are suppressed effectively. For
NTSC sources, a comb filtering is performed for all pic-
ture sizes. Due to reduced bandwidth in horizontal and
vertical direction a strong reduction of cross artifacts
can be achieved for PAL signals. The same applies for
the luminance signal of SECAM signals.

2.5. Luminance Processing

The A/D-converted CVBS (or Y) signal is digitally
clamped to back porch. Depending on the transmitted
standard and operational area, an offset between
black- and blanking level can be found in the incoming
signal (`7.5 IRE'). As for some applications a black off-
set is not desired, controlling may be done using
LMOFST. The positive or negative offset is added to
the Y signal before scaling.

The color carrier is removed out of a CVBS signal by
means of a notch filter. It is set to the corresponding
color carrier (3.58 or 4.4 MHz) only if the standard is
detected permanently. This prevents the luminance
sharpness of being changed within the standard
search process. For Y signals the notch is disabled. A
special peaking can be applied to the notch-filter
(NADJ) to make it steeper. For a fine adjustment of
delay compensation between luminance and chromi-
nance, YCDEL allows a luminance shifting in 16 steps
of 50 ns.

Fig. 2�5: Black Level Correction of Luminance Signal

Table 2�4: Color killer adjustment

CKILL

COLON

Color Killed at Clamping
of

30 dB

18 dB

24 dB

Color always off

Color always on

Received Signal

BLACK value

BLANK value

LMOFST='00' (no additional offset)

Processed Signal

BLACK value

BLANK value

LMOFST='10' (reduction of 16 LSB)

BLACK value

BLANK value

BLACK value

LMOFST='00' (no additional offset)

LMOFST='01' (addition of 16 LSB)

M Standard Signals

B/G/H/I/N Standard Signals

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2.6. Decimation

2.6.1. Single PIP Mode

Luminance and chrominance signals are filtered in
horizontal and vertical direction. The coarse horizontal
and vertical picture size (1/2, 1/3, 1/4, 1/6) is indepen-
dently programmable with SIZEHOR and SIZEVER. A
fine adjustment in steps of 4 pixel and 2 lines is possi-
ble by HSHRINK and VSHRINK, which allows correct
aspect ratio for multistandard applications (50/60 Hz
mixed mode, (S)VGA).

For main decimation factors, the stored number of
pixel and lines are listed in the following tables.

2.6.2. Continuos Zoom

The continuos zoom feature changes the picture size
rapidly in an animated manner. It is available in single-
PIP mode for picture sizes smaller or equal 1/4 of the
undecimated picture.

There are three possibilities of using the zoom feature:

� The PIP is zoomed via HSHRINK and VSHRINK

manually. This requires an I�C protocol each time
the picture size should change. CZMEN should be
used to synchronize the update of HSHRNK/
VSHRNK with SIZEHOR/SIZEVER.

� A different way is to make usage of the automatic

zooming. The zoom speed can be controlled by
CZMSP. When switching PIP on or off by using
PIPON, the PIP zooms automatically to the selected
picture size or disappears at size of 1/81.

� A zooming between two picture sizes can be per-

formed by changing the HSHRINK, VSHRINK,
SIZEHOR, SIZEVER values, when CZMEN is
enabled. The new picture size is obtained by zoom-
ing and not taken immediately.

Automatic zooming is only possible in frame mode.
Being in field mode, the picture size remains stable
until frame mode occurs or until the internal counter
reaches the desired picture size. Then, the size
changes immediately. Equal to the wipe process, the
zooming direction depends on the coarse position
(CPOS).

Table 2�5: Number of stored pixel per line dependent
on SIZEHOR

SIZEHOR

Horizontal
Scaling

PIP Pixel per Line

(B-Y)

(R-Y)

2:1

324

3:1

216

4:1

160

6:1

108

Table 2�6: Number of stored lines per field

SIZEVER

Vertical
Scaling

PIP Lines

625 Lines
Source

525 Lines
Source

2:1

132

108

3:1

4:1

6:1

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Fig. 2�6: Number of Stored Pixel per Line Dependent on HSHRNK

2,00

324

3,00

216

6,00

108

2,02

320

3,04

212

6,23

104

2,05

316

3,11

208

6,48

100

2,08

312

3,17

204

6,75

2,10

308

3,23

200

7,04

2,13

304

3,29

196

7,35

2,16

300

3,37

192

7,70

2,19

296

3,44

188

8,10

2,22

292

3,51

184

8,52

2,25

288

3,60

180

8,99

2,28

284

3,67

176

9,51

2,31

280

3,76

172

10,12

2,35

276

3,84

168

10,64

2,38

272

3,94

164

2,41

268

4,05

160

2,45

264

4,16

156

2,49

260

4,27

152

2,53

256

4,38

148

2,57

252

4,50

144

2,61

248

4,63

140

2,66

244

4,77

136

2,70

240

4,91

132

2,74

236

5,06

128

2,80

232

5,22

124

2,84

228

5,41

120

2,89

224

5,59

116

2,95

220

5,78

112

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Fig. 2�7: Number of Stored Lines per Field Dependent on VSHRNK

2.6.3. Horizontal And Vertical Fine Positioning

All picture sizes are pre-centered inside the frame. In
addition, if necessary the vertical and horizontal acqui-
sition area can be shifted by VFP for vertical and HFP
for horizontal direction.

2.6.4. Multi Display Mode

The PVP 9390A offers the feature to display a sub-pic-
ture more than once. The picture size and arrange-
ment depends on the display mode (DISPMOD) and
not on SIZEHOR or SIZEVER. Hence variable scaling
is not possible in these modes.

The display modes are shown in the appendix. The
sizes of the partial pictures are listed in Table 2.7. on
page 15

2 132

2 108

4,01

2,03 130

2,03 106

4,13

4,15

2,06 128

2,08 104

4,25

4,31

2,09 126

2,13 102

4,41

4,5

2,13 124

2,16 100

4,56

4,69

2,16 122

2,2

4,72

4,9

2,2 120

2,25

4,88

5,13

2,23 118

2,3

5,06

5,39

2,28 116

2,34

5,28

5,7

2,31 114

2,41

5,5

2,36 112

2,45

5,75

2,41 110

2,52

2,44 108

2,58

6,28

6,38

2,48 106

2,64

6,61

6,75

2,53 104

2,7

6,94

7,22

2,59 102

2,77

7,31

7,73

2,64 100

2,84

7,78

8,3

2,69

2,92

8,25

2,75

8,81

9,8

2,81

9,42

28 10,78

2,88

3 10,17

2,94

3 11,02

3,07

3,09

3,14

3,19

3,21

3,28

3,3

3,38

3,49

3,47

3,61

3,56

3,73

3,66

3,87

3,77

3,89

625 lines

525 lines

625 lines

525 lines

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2.6.5. Split Screen

For split screen applications two selectable "double
window" modes in which one half of the picture is gen-
erated by the PVP 9390A can be used. The split
screen mode can be selected by two possible combi-
nations of DISPMOD.

Fig. 2�8: Double Window Mode 1.5 (left picture) and
Mode 1 (right picture)

The D1.5 mode is suited for displaying split screen on
16:9 tubes keeping the aspect ratio. The DW1 format
covers the full height of the screen. The DW1 format is
only suited for 50/60 Hz single-scan applications and
is not suited for 100 Hz or "progressive" displays.

2.6.6. Multi-PIP Mode

There is a great variety of multi-PIP modes available.
Up to 11 different still pictures and one moving picture
can be shown. This is useful to give an overview over
broadcasted programmes (e.g. tuner-scan) or for
supervising purposes. For multi-PIP modes only three
fixed picture sizes are available (1/9, 1/16 or 1/36). The
picture size and arrangement depends on the display
mode (DISPMOD) and not on SIZEHOR or SIZEVER.
Variable scaling is thus not possible in these modes.
Because of limited memory capacity, the number of
frozen multi-pictures is limited dependent on picture
size to the number shown in the table below:

The partial picture that is written is addressed via
WRPOS. With INFRM, a frame for separation of every
PIP can be selected. This is adjustable to single or
dual PIP mode (INFRMOD). The current updated pic-
ture can be highlighted with PIPHLT. To avoid garbage
pictures after switching from one mode to another the
selected picture can be blanked with PIPBLK.
MPIPBG defines wether the picture will be blanked
with black or with the adjusted background color.

For compatibility reasons to other devices, the DISP-
MOD register is split into two segments. If a display
mode is chosen that is not implemented, the PIP inser-
tion is switched off automatically (PIPON = `0'). The
sizes of the partial pictures correspond to the sizes of
the inset pictures of the single PIP modes.

Table 2�7: Multi-display modes

Display
Mode

DISPMOD

Size

Picture Configuration

Pixel

Lines

625

525

SIZEHOR/SIZEVER

HSRHNK/VSHRNK

Single PIP mode

324

132

108

3 X1/9

One upon another (same content)

216

264

216

4 X 1/16

One upon another (same content)

156

264

216

Table 2�8: Maximum number of pictures in multi-PIP
mode

Picture
Sizes

Maximum Number of Pictures
(Including One Live Picture)

1/9

1/16

1/36

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2.7. Display Control

The on-chip memory capacity is 768 kbits. Provided
that the same standard (50 or 60 Hz)

video sources

are applied to inset and parent channel, joint-line free
frame mode display is possible. This means that every
incoming field is processed and displayed by the
PVP 9390A processors. The result is a high vertical
and time resolution. For this purpose the standard is
analyzed internally and the frame mode display is
blocked automatically, if the described restrictions are
not fulfilled. Then, only every second incoming field is
shown (field mode). Field mode normally shows joint-
lines. This is caused by an update of the memory dur-
ing read out. The result is that one part of the picture
contains new picture information and the other part

contains one earlier written field. The switching from or
to frame mode is free of artifacts.

Activation of frame-mode display is blocked automati-
cally when at least one of the following conditions is
not fulfilled:

� Inset and parent channel have the same field repeti-

tion frequency. This means that frame mode is pos-
sible only for 50 Hz inset and parent sources or
60 Hz inset and parent sources.

� Interlace signal is detected for inset and parent

channel. Therefore, for progressive scan or (S)VGA
display, only field mode is possible. For some VCRs
in trick mode, often no interlace is detected.

Table 2�9: Display Modes

Display
Mode

DISPMOD

Size

Picture Configuration

Pixel

Lines

625

525

2 x 1/9,

One upon another

216

176

144

2 x 1/9,

Side by side

432

3 x 1/9,

Side by side

648

3 x 1/9

Pne upon another

216

264

216

4 x 1/16

Side by side

624

6 x 1/16

Inverted U shaped

624

132

108

6 x 1/16

U shaped

624

132

108

4 x 1/16

2 rows of 2 pictures

312

132

108

4 x 1/16

One upon another

156

264

216

12 x 1/36

6 rows of 2 pictures

216

264

216

12 x 1/36

2 rows of 6 pictures

648

9 x 1/36

3 rows of 3 pictures

324

132

108

12 x 1/36

3 rows of 4 pictures

432

132

108

11 x 1/36

Angular of 11 pictures

648

264

216

9 x 1/36

Angular of 9 pictures

540

220

180

1 x 1/3

Double Window (V=1.5)

324

176

144

1 x 1/2

Double Window (V=1)

324

264

216

OSD only

Others

Reserved

Single-scan display only

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� The number of lines is within a predefined range for

inset (FMACTI) or parent (FMACTP) channel
(assuming standard signals according to ITU)

The system may be forced to field mode by means of
FIESEL. Either first or second field is selectable. "One
of both" takes every second field independent of the
field number. This is meant for sources generating only
one field (e.g. video-games).

For progressive scan conversion systems and HDTV/
(S)VGA displays a line doubling mode is available
(PROGEN). Every line of the inset picture is read
twice.

Memory writing is stopped by FREEZE bit. The field
stored in the memory is then continuously read. As the
picture decimation takes place before storing, the pic-
ture size of a frozen picture can not be changed.

Synchronization of memory reading with the parent
channel is achieved by processing the parent horizon-
tal and vertical synchronization signals connected to
the pin HSP for horizontal synchronization and pin
VSP for vertical synchronization. HSPINV or VSPINV
respectively allow an inversion of the expected signal
polarity.

Fig. 2�9: Field Detection and Phase Adjustment of Vertical Pulse (VSP)

Depending on the phase between inset and parent sig-
nals a correction of the display raster for the read out
data is performed. As the external VSP and HSP sig-
nals may come from different devices with different
delay paths, the phase between V-sync and H-sync is
adjustable (VSPDEL). An incorrect setting of VSPDEL
may result in wrong or unreliable field detection of par-
ent channel.

Normally a noise reduction of the incoming parent ver-
tical pulse is performed. With this function missing ver-

tical pulses are compensated. The circuit works for 50/
60 Hz applications as well as progressive and 100/
120 Hz application. (S)VGA signals are supposed to
be very stable and therefore not supported by the
noise suppression. By means of VSPNSRQ, vertical
noise suppression is switched off.

A great variety of combinations of inset and parent fre-
quencies are possible. Table 2�11 on page 17 shows
some constellations.

Table 2�10: Required number of lines for frame mode display

FMACTP

Parent
Standard

Number of Lines
per Field

FMACTI

Inset
Standard

Number of Lines
per Field

50 Hz

310...315

50 Hz

310...315

50 Hz

290...325

50 Hz

290...325

60 Hz

260...265

60 Hz

260...265

60 Hz

250...275

60 Hz

250...275

VSPDEL

max

=151 (75)

�s

values in brackets () apply for 100Hz systems

field 0 window

field 1 window

tH = 64 (32)

�s

tH/2 = 32 (16)

�s

HSP

VSP

VSPD

(internal)

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2.7.1. 100 Hz Frame Mode

If the picture size is smaller or equal than 1/9 PIP a
true frame mode display for 100 Hz parent standard
with a double field repetition rate is possible (display
raster

only). The picture size is indicated by the

horizontal and vertical decimation factors that must be
equal or below 1/3 of undecimated picture size in both
directions. This guarantees enough memory for a joint-
line free picture with full vertical resolution. For bigger

pictures only field mode is supported. The 100 Hz
frame mode is activated if READD='1' for the above
mentioned picture sizes. For an acceptable quality
without line flicker or motion artifacts only the mode

is supported for HSP and VSP. If the sequence

is detected, the field mode will be activated

again. Continuos switching between these modes is
possible, resulting in continuos switching between
field- and frame mode.

Table 2�11: Available features with varying inset and parent standards

Inset
Frequency

Parent
Frequency

(HSP/VSP)

Frame
Mode

Correct Aspect Ratio
(Single PIP)

Correct Aspect Ratio
(Multi Display)

Vertical Noise
Suppression
Selectable

50i

60i

50i

60i

50p

60p

50p

60p

100i

120i

100i

120i

(S)VGA

60 (S)VGA

1) Standard signals supposed
2) AABB only and picture size smaller than 1/9
3) Valid for some parent frequencies. Please refer to Chapter 2.7.2.

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2.7.2. Mixed Standard Applications and (S)VGA Support

The PVP 9390A allows multiple scan rates for the use
in desktop video applications, VGA compatible or
100 Hz TV sets. All features are provided in "normal"
operating modes at auto detected 50 Hz and 60 Hz
parent and inset standards. 2f

modes (100/120 Hz

and progressive) are supported by line frequency- and
pixel clock doubling and are not detected automati-
cally. Even on a 16:9 picture tube correct aspect ratio
can be displayed by selecting the suitable parent clock.
The video synthesizer generates also a special pixel
clock for VGA display (see chapter 5.5.9 for details).
As (S)VGA consists of a variety of scan rates the cor-
rect aspect ratio is not adjustable for all modes with the
parent clock (HZOOM) because of the limited count of
frequencies. For single PIP only, correct aspect ratio is
maintained by the vertical and horizontal scaler
(HSHRINK and VSHRINK).

It is possible to display (S)VGA sources for parent dis-
play, as long as the horizontal frequency is lower than
40 kHz and the signal does not contain more than
1023 lines. For progressive scan mode, PROGEN
must be set. Additionally field-mode should be forced

to prevent not allowed frame-mode displaying (FIE-
SEL). As the (S)VGA normally does not fit to the dis-
play raster generated in the vertical noise suppression,
VSPNSRQ should be disabled. (S)VGA signals for
inset channel are not supported.

Table 2�12: Examples of supported parent signals

Remark
(N

apel

x N

aline

)

(kHz)

(

�

Hact

(

�

Lines/
Active

dot

(MHz)

Scan

Correct
Aspect Ratio

720 x 576@50 Hz (TV)

15.6

64.0

52.0

625/576

13.5

Interlace

702 x 488@60 Hz (TV)

15.7

63.6

52.7

525/488

13.5

Interlace

720 x 576@100 Hz (TV 100 Hz)

31.2

32.0

26.0

625/576

Interlace

702 x 488@120 Hz (TV 120 Hz)

31.2

31.8

26.4

525/488

Interlace

720 x 576@50 Hz
(TV progressive)

31.2

32.0

26.0

625/576

Progressive

702 x 488@60 Hz
(TV progressive)

31.2

31.8

26.4

525/488

Progressive

640 x 480@60 Hz (VGA)

31.5

31.8

25.4

525/480

25.2

Progressive

640 x 480@72 Hz (VGA)

37.9

26.4

20.3

520/480

31.5

Progressive

640 x 480@75 Hz (VGA)

37.5

26.7

20.3

500/480

31.5

Progressive

800 x 600@56 Hz (SVGA)

35.2

28.4

22.2

625/600

36.0

Progressive

800 x 600@60 Hz (SVGA)

37.9

26.4

20.0

625/600

40.0

Progressive

800 x 600@72 Hz (SVGA)

48.1

20.8

16.0

666/600

50.0

Progressive

800 x 600@75 Hz (SVGA)

46.9

21.3

16.2

625/600

49.5

Progressive

800 x 600@85 Hz (SVGA)

53.7

18.6

14.2

631/600

56.3

Progressive

1024 x 768@43 Hz (SVGA)

35.5

28.2

22.8

817/768

44.9

Interlace

Table 2�13: Selection of display field repetition

READD

PROGEN

Expected Input Signal

50 or 60 Hz
Signal Interlace

100 or 120 Hz
Signals Interlace

(Reserved)

50 or 60 Hz or (S)VGA
Signal Progressive

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2.7.3. Display Standard

For a single-PIP, the number of displayed lines
depends on the selected picture size and on the signal
standard. For multi picture display, the number of dis-
played lines depends on the selected picture size and
on the signal standard of the parent signal. Addition-
ally, a standard can be forced by DISPSTD. See
table 2�14.

When a 625 lines picture is shown with a 525 lines par-
ent signal, some lines are missing on top and bottom
of picture. When a 525 lines picture is shown with a
625 lines display standard, missing lines at top and
bottom are filled with background color or black
depending on MPIPBG.See Fig. 2�10.

Fig. 2�10: 50 and 60 Hz Multi PIP Display on 50 Hz
and 60 Hz Display

2.7.4. Picture Positioning

The display position of the inset picture is programma-
ble to the 4 corners of the parent picture (CPOS). From
there PIP can be moved to the middle of the TV Pic-
ture with POSHOR and POSVER. The corner posi-
tions can be centered coarsely on the screen with
POSOFH and POSOFV. Depending on coarse posi-
tion, one PIP corner remains stable when changing the
picture size.

Fig. 2�11: Coarse Positioning

There are 256 horizontal locations (4 pixel increments)
and 256 vertical locations (2 line increments). The
pixel width on the screen depends on the selected
HZOOM factor. Even POP-positions (Picture Outside
Picture) in 16:9 applications are possible.

Table 2�14: Display standard selection

DISPSTD

DISP
MOD

Display Standard

PIP depends on detected
inset standard (single PIP)

PIP depends on detected
parent standard (multi dis-
play)

PIP display is always in 625
lines mode

PIP display is always in 525
lines mode

Freeze last detected display
standard and size

625 lines / 50 Hz

525 lines / 60 Hz

POSHOR

POSVER

POSHOR

POSVER

CPOS='01'

CPOS='10'

CPOS='11'

CPOS='00'

Table 2�15: Coarse Positioning

CPOS

Coarse
Position

Reference Corner of
PIP

Increasing
POSVER

Increasing
POSHOR

Upper left

Down

Right

Upper right

Down

Left

Lower left

Right

Lower right

Left

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2.7.5. Wipe In/Wipe Out

With the wipe in/wipe out function it is possible to let
appear or disappear the complete inset picture starting
or ending at the corner of the inset picture position
defined by CPOS. Thereby the size of the visible pic-
ture-part is continuously increased and decreased
respectively. During this procedure the frame is shown
with its chosen widths. 3 different wipe in/out time peri-
ods or "no wipe" are programmable via WIPESP. The
wipe algorithm always works in horizontal and vertical
direction.

If WIPESP is set accordingly, PIPON controls the wipe
operation. When PIPON changes the wipe operation
starts. During this period, the readable PIPSTAT indi-
cates the ongoing wipe-process. A transition of PIPON
from `0' to `1' triggers the wipe-in. The wipe-in process
stops when the picture reaches its programmed size.
When PIPON changes from `1' to `0' the wipe-out
starts. The wipe-out is finished when the PIP picture
vanishes. Even for multi-picture display wipe operation
is possible. A change of PIPON or WIPESP during
wipe operation has only an effect after the wipe opera-
tion has been finished.

Fig. 2�12: Wipe Display

CPOS='01'

CPOS='10'

CPOS='11'

CPOS='00'

CPOS='01'

CPOS='10'

CPOS='11'

CPOS='00'

CPOS='01'

CPOS='10'

CPOS='11'

CPOS='00'

wipe in

wipe out

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2.8. Output Signal Processing

2.8.1. Luminance Peaking

To improve picture sharpness, a peaking filter which
amplifies higher frequencies of the input signal is
implemented. The amount of peaking can be varied in
seven steps by YPEAK. The setting `000' switches off
the peaking. The value `011' is recommended as this
value provides a good compromise between sharp-
ness impression and annoying aliasing. The character-
istic for all possible settings is shown in Fig. 2�13. The
emphasized frequency depends on the adjusted deci-
mation. The gain maximum is always located before
the band-limit ensuring optimal picture impression.
Peaking can be additionally increased by PKBOOST.

Coring should be switched on by YCOR to reduce
noise, which is also amplified when peaking is
enabled. As the coring stage is in front of the peaking
filter, 1 LSB noise will not be peaked.

2.8.2. RGB Matrix

The chip contains three different matrices, one suited
for EBU standards, one suited for NTSC-Japan and
one suited for NTSC-USA, which are selected via
MAT. The signal OUTFOR switches between YUV out-
put or RGB output. The signal UVPOLAR inverts the U
and V channels and results in Y-U-V output. The stan-
dard magnitudes and angles of the color-difference
signals in the UV-plane are defined as shown in
Table 2�16.

The color saturation can be adjusted with SATADJ
register in 16 steps between 0 and 1.875. Values
above 1.0 may clip the chrominance signals.

Fig. 2�13: Characteristics of Selectable Peaking Factors (0.5 = band limit)

0.1

0.2

0.3

0.4

0.5

normed frequency

gain [dB]

YPEAK = `000'

YPEAK = `001'

YPEAK = `010'

YPEAK = `011'

YPEAK = `100'

YPEAK = `101'

YPEAK = `110'

YPEAK = `111'

Table 2�16: RGB matrices characteristics

MAT

Magnitudes

Angles

Standard

(B-Y)

(R-Y)

(G-Y)

(B-Y)

(R-Y)

(G-Y)

2.028

1.14

0.7

236

EBU

2.028

1.582

0.608

240

NTSC (Japan)

2.028

0.608

105

250

NTSC (USA)

(Reserved)

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2.8.3. Frame Generation And Colored Background

With FRWIDH and FRWIDV different to `0', a colored
frame is shown. With FRSEL a shaded frame is dis-
played

Note: If FRSEL is on, a shaded frame is shown, even if

FRWIDH and FRWIDV is `0'. Therefore, if no
frame is required, FRSEL as well as FRWIDH
and FRWIDV must be set to `0'.

The chip can display two different types of frames, one
simple monochrome frame and a more sophisticated
frame giving a three dimensional impression.

Fig. 2�14: Normal Frame and 3D Frame

The frame elements are always placed outside the
inset picture, except for the inner shade of three
dimensional frame or inner frame in multi-PIP mode.
There is no shift of the inset picture position if the inset
frame width is modified.

Fig. 2�15: Selectable Picture Configurations

A total of 4096 frame colors are programmable by FRY,
FRU, and FRV, 4 bits for each component. Horizontal
and vertical width of the frame are programmable inde-
pendently by FRWIDH and FRWIDV. If desired, frame
color is displayed over the whole PIP size or whole pic-
ture size of the main channel when PIPBG is set
accordingly. 64 background colors are programmable
by BGY, BGU, BGV, 2 bits for each component. Alter-
natively BGFRC sets the background to frame color.

2.8.4. 16:9 Inset Picture Support

To remove dark stripes at 16:9 inset pictures the verti-
cal display area is shrinkable with VPSRED. The num-
ber of omitted lines depends on the vertical decimation
factor.

Fig. 2�16: 16:9 Inset Picture without and with
Reduction of Vertical Picture Size

frame

frame color

background

background color

frame color

shades

dark/light

PiP Picture

background

picture

character

character

luminance

frame color

character background

transparent

char. background luminance

semi-transparent

Table 2�17: Number of lines with and without
reduction of vertical picture size

Vertical
Decimation
Factor

Displayed Lines

50 Hz

60 Hz

With

Without
Reduction

With

Without
Reduction

214

264

175

216

...

35 44

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2.8.5. Parent Clock Generation

The phase of the output signals is locked to the rising
edge of the horizontal sync pulse. The frequency can
be varied in a certain range to ensure correct aspect
ratio for 16:9 applications depending on HZOOM. The
horizontal and vertical scaling can be used for all dis-
play frequencies.

2.8.6. Select Signal

For controlling an external RGB or YUV switch a select
signal is supplied. The delay of this signal is program-
mable for adaptation to different external output signal
processing devices (SELDEL).

Fig. 2�17: Select Timing

2.8.7. Automatic Brightness Reduction

Displaying a bright PIP picture, the beam current limi-
tation of the parent system may become active. This
may cause the parent picture to be influenced by the
inset picture. Therefore a detection circuit reduces the
brightness of the inset picture when the average
brightness is above a selectable threshold. After bright
picture content has disappeared, the initial brightness
reappears. The threshold is adjustable via ABRTHD
and the speed via ABRSPD. Both settings have to be
selected for parent system accordingly.

2.9. On Screen Display (OSD)

2.9.1. Display Format

The on screen display allows to insert a block of 5
characters into each of the PIP pictures. The charac-
ters are placed in a box (background) whose width is
64 pixels and height is 12 lines. This box is placed in
the upper left corner of the PIP picture. 64 different
characters are stored in a character ROM. Each char-
acter is defined by a pixel matrix consisting of 10 lines
and 12 pixels per line. A doubling of the character's
height and width is achieved by CHRDHW. The OSD
starting position is not influenced.

OSD display is also possible if PIP is switched off
(DISPMOD ='10010'). Now 3 lines of 20 characters
each are displayed at the PIP position.

Fig. 2�18: Example of OSD-only Mode

Fig. 2�19: Example of Transparent Mode (Normal and
Double Size OSD)

Table 2�18: Format conversion using HZOOM

Display
Format

set

t
ure

Format

red

I
P

Format

quire

d P

rent

Freq

uen

Value of HZOOM

4:3

16:9

20.25

16:9

4:3

16:9

SELDEL

PIP signal

OUTx

SEL

frame

picture

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2.9.2. Character Programming

The characters are programmed via I�C bus using a
7 bit code which is identical with the ASCII code
except for some of the special characters. The codes
are stored in a character RAM consisting of 60 cells.
The character codes can be transmitted in two ways:
each character position can be addressed separately
by its 7 bit address or the characters can be written
consecutively starting at an arbitrarily chosen position.
In this case the address is increased automatically.
The 7 bit address consists of two parts: the 4 MSBs
are used to chose one of the partial pictures and the
3 LSBs to select one of the 5 characters per block.

2.9.3. Character and Character Background Color

The character's color is either same as frame color
(CHRFRC) or the character appears with a grey value
programmable with CHRY.

The character's background box is influenced by CHR-
BGON and CHRBGY. It can be made transparent so
that behind the characters the inset picture becomes
visible. Alternatively the semi-transparent mode can be
chosen. At this mode the background box contains the
original picture content with reduced luminance value.
This mode offers a good trade-off between reduction of
visible display area and character readability.

2.10. DA-Conversion And RGB/YUV Switch

The PVP 9390A includes three 7 bit DA-converters.
Brightness BRTADJ, Contrast CONADJ and overall
amplitude PKLR, PKLG, PKLB of the output signal
are adjustable. External RGB or YUV signals can be
connected to the inputs IN1...3. By forcing the FSW
input to high-level these signals are switched to the
outputs OUT1...3 while the internal signals are
switched off. The switch of YUV signals with sync on Y
is possible, if YSYNCOFS is set. The FSW input signal
is passed through to the SEL output. The setting of
RGBINS determines wether an RGB insertion is possi-
ble and which source, the external picture or the PIP,
gets priority. See Fig. 2�20.

The external RGB or YUV signals are each clamped to
the reference levels of the DACs to force uniform black
levels in each channel. The clamping needs careful
adjustment especially for VGA applications. The posi-
tion and the length of the blanking pulse as well as the
clamping pulse are adjustable (CLPPOS, CLPLEN). If
READD is set to `1' (100 Hz mode), all pulses are
shortened by one half. HZOOM influences the adjust-
ment range of the clamping and blanking pulse
because of the modified clock frequency, but the pulse
length is kept nearly constant.

Fig. 2�20: Visualization of RGB/YUV Insertion

OSD

RGB/VYU

R/V
G/Y

B/U

FSW

SEL

OSD

RGBINS='10'
PIPON='1'

RGBINS='00'
PIPON='1'

OSD

RGBIN='1X'
PIPON='0'

OSD

RGBINS='11'
PIPON='1'

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Fig. 2�21: PIP Horizontal Blanking Timing

2.10.1. Pedestal Level Adjustment

The pedestal level adjustment controlled by I�C signals
BLKLR, BLKLG, BLKLB enables the correction of
small offset errors, possibly appearing at the succes-
sive blanking stage of RGB processor. This adjustment
has an effect on the setup level during the active line
interval of each channel like the brightness adjustment
but has an enhanced resolution of 0.5 LSB. The maxi-
mum possible offset amounts to 7.5 LSBs. In YUV
mode (OUTFOR = `1') the action depends on the set-
ting of BLKINVR and BLKINVB. If BLKINVR (BLK-
INVB) is active the offset applies to the blank level of
the RV (BU) channel during the clamping interval for
shifting the setup level to the negative direction. In
RGB mode (OUTFOR = `0') BLKINVR and BLKINVB
have no effect.

2.10.2. Contrast, Brightness and Peak Level

Adjustment

The peak level adjustment modifies the magnitude of
each channel separately. It should be used to adapt
once the signal levels to the following stage. The con-
trast adjustment influences all three channels and
allows a further increase of 30 % of the peak level
magnitude. The effect of the brightness adjustment
depends on the selected output mode (RGB/YUV). In
YUV mode it changes the offset of the OUT2 (Y) signal
only while in RGB mode it changes the offset of all
three channels at the same time. The brightness
increase is up to 20 %.

BLANKP

HSP

CLAMPP

Parent

Video

allowed

HSP range

256 T

Table 2�19: PIP horizontal blanking timing examples

READD

CLPDEL

CLPLEN

a (

�

Blanking
Start

b (

�

Blanking
Duration

c (

�

Clamping
Start

d (

�

Clamping
Duration

-1.5

10.5

-11

10.5

-6.4

-1.5

7.9

2.2

3.8

-11.0

7.9

-7.3

3.8

-0.8

5.3

1.5

2.5

-5.5

5.3

-3.2

2.5

-0.8

1.1

1.9

-5.5

-3.6

1.9

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

2.11. Data Slicer

Depending on SERVICE, Closed Caption data ("Line
21") or WSS (Wide-screen signalling) is sliced by the
digital data slicer and can be read out from I�C inter-
face. The line number of the sliced data is selectable
with SELLNR. Therefore WSS and CC can be pro-
cessed in different regions (e.g. CC with PAL M). The
Closed Caption data is assumed to conform with the
ITU standards EIA-608 and EIA-744-A. WSS data is
assumed to conform with ETS 300 294 (2nd edition,
May 1996).

2.11.1. Closed Caption

The closed caption data stream contains different data
services. In field 1 (line 21) the captions CC1 and CC2
and the text pages T1 and T2 are transmitted whereas
in field 2 (line 284) caption CC3, CC4, text T3, T4 and
the XDS data are transmitted. For more information
please refer to the above mentioned standards.

Raw CC as well as pre-filtered data is provided alter-
natively. With the built-in programmable XDS-Filter
(XDSCLS), the program rating information ("V-chip")
as well as others can be filtered out. The XDS filter
reduce traffic on the I�C bus and save calculation
power of the main controller. If no class filter is
selected, all incoming data (both fields) is sliced and
provided by the I�C interface. When one or more class
filters are chosen, only data in field 2 is sliced. Any
combination of class filters is allowed. Each "CLASS"
is divided into "TYPES" which can be sorted out by the
XDS-secondary filter (XDSTPE). Any combination of
type filter is allowed. Some type filter require an appro-
priate class filter.

2.11.2. Wide-screen Signalling (WSS)

In WSS mode (SERVICE='1') no filtering is possible.
All sliced data is passed to the output registers. In this
case XDSTPE selects the field number of the data to
be sliced. In Europe WSS carries for instance informa-
tion about aspect ratio and movie mode.

2.11.3. Indication of New Data

The sliced and possibly filtered data is available in
DATAA and DATAB. The corresponding status bits are
DATAV and SLFIELD. When new data were received,
DATAV becomes `1' and the controller must read
DATAA, DATAB and the status information. After both
data bytes were read DATAV becomes `0' until new
data arrives. It must be ensured that the data polling is
activated once per field (16.7 or 20 ms) or every sec-
ond field (33.3 or 40 ms), depending on the slicer con-
figuration and inset field frequency. The field number of
the data in DATAA and DATAB can be found in
SLFIELD. If one or more XDS-class filter are activated,
SLFIELD contains always `1'.

Additionally pin 10 (INT) may flag that new data is
received. Default this pin is in tri-state mode to be com-
patible with the Micronas SDA 9388X/9389X PIP
devices. It can also be configured by IRQCON to out-
put a single short pulse when new data is available or
behave equal to DATAV. In the last case the output
remains active until the two data registers DATAA/
DATAB are read. Both modes are useful to avoid con-
tinuos polling of the I�C bus. The microcontroller ini-
tiates I�C transfers only when required.

Fig. 2�23: Example in Pseudo-code for Reading the Data

while (1){

i2c_read pip_adr, status_reg_adr, status

if (status & data_valid_mask) {

i2c_read_inc pip_adr, dataa_reg_adr, dataa, datab, status

process_data dataa, datab, status

}

PVP 9390A

ADVANCE INFORMATION

May 3, 2004; 6251-633-1AI

Micronas

2.11.4. Violence Protection

The rating information is sent in the program rating
packet of the current (sometimes future) class in the
XDS data stream. If only this information is desired the
corresponding XDS filter (class 01h, type 05h) should
be used to suppress other data. The class/packet
bytes (0105h) precede the 2 Bytes rating information.
Each sequence is closed by the end-of-packet Byte
(0fh) and a checksum. This checksum complements
the Byte truncated sum of all Bytes to 00h. Except
comparison of the received rating with the adjusted

user rating threshold the microcontroller should check
the parity of each Byte and validate the checksum to
avoid misinterpretation of wrong received data.

The PVP 9390A offer some alternatives to blocking the
PIP channel completely by switching it off (see Fig. 2�
24).

The Mosaic mode (MOSAIC) hides details of the pic-
ture by reduced sharpness and increased aliasing.
The picture looks scrambled and is less perceptible.

Fig. 2�24: Possibilities of PIP Blocking

"Blue Screen"

"Mosaic"

"Warning Message"

THIS PROGRAM
CONTAINS VIOLENT
SCENES

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

2.13. OSD Character Set

Fig. 2�39: OSD Character Set

1011010=5A

1011110=5E

1011111=5F

0001010=0A

0100000=20

0100001=21

0100100=24

0100101=25

0001011=0B

0101010=2A

0101011=2B

0101101=2D

0110000=30

0110001=31

0110010=32

0110011=33

0110100=34

0110101=35

0101111=2F

0110110=36

0111000=38

0111001=39

0111100=3C

0111101=3D

0110111=37

0111110=3E

1000001=41

1000010=42

1000011=43

1000100=44

1000101=45

1000110=46

0111111=3F

1000111=47

1001001=49

1001010=4A

1001011=4B

1001100=4C

1001101=4D

1001110=4E

1001000=48

1001111=4F

1010001=51

1010010=52

1010100=54

1010101=55

1010110=56

1010000=50

1010111=57

1011001=59

1011101=5D

1011000=58

1011011=5B

1010011=53

0100011=23

0000001=01

0000010=02

0000011=03

0000100=04

0000101=05

0000110=06

0001000=08

0001001=09

0000111=07

PVP 9390A

ADVANCE INFORMATION

May 3, 2004; 6251-633-1AI

Micronas

3. I

C Bus

3.1. I

C Bus Address

3.2. I

C Bus Format

Write operation is possible at registers 00h-21h and
2Eh-3Eh only, read operation is possible at registers
28h, 2Ah-2Ch, 3Fh only. An automatic address incre-
ment function is implemented.

Table 3�1: First address (I2C1= `0', I2C2= `0')

Write Address1 1

(D6h)

Read Address1 1

(D7h)

Table 3�2: Third address (I2C1= `0', I2C2= `1')

Write Address1 1

(D4h)

Read Address1 1

(D5h)

Table 3�3: Second address (I2C1= `1', I2C2= `0')

Write Address2 1

(DEh)

Read Address2 1

(DFh)

Table 3�4: Fourth address (I2C1= `1', I2C1= `1')

Write Address1 1

(DCh)

Read Address1 1

(DDh)

Table 3�5: I

C-bus format

WRITE

1101x110

Subaddress

Data Byte

****

READ

1101x110

Subaddress

1101x111

Data Byte n

S: Start condition / Sr Repeated start condition / A: Acknowledge / P: Stop condition / NA: No Acknowledge

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

3.3. I

C Bus Command TableI

Table 3�6: I

C bus command table

Subadd
(Hex)

Data Byte

00h

PIPON

CPOS1

CPOS0

YUVSEL

READD

PROGEN

FIESEL1

FIESEL0

01h

POSHOR7

POSHOR6

POSHOR5

POSHOR4

POSHOR3

POSHOR2

POSHOR1

POSHOR0

02h

POSVER7

POSVER6

POSVER5

POSVER4

POSVER3

POSVER2

POSVER1

POSVER0

03h

VFP3

VFP2

VFP1

VFP0

HFP3

HFP2

HFP1

HFP0

04h

DISPSTD1

DISPSTD0

FREEZE

MOSAIC

SIZEHOR1

SIZEHOR0

SIZEVER1

SIZEVER0

05h

FPSTD1

FPSTD0

PIPBG1

PIPBG0

FMACTP

HZOOM2

HZOOM1

HZOOM0

06h

HSPINV

VSPINV

VSPNSRQ

VSPDEL4

VSPDEL3

VSPDEL2

VSPDEL1

VSPDEL0

07h

FRSEL

INFRM

VPSRED

FRWIDH2

FRWIDH1

FRWIDH0

FRWIDV1

FRWIDV0

08h

RGBINS1

RGBINS0

VERBLK

SELDOWN

SELDEL3

SELDEL2

SELDEL1

SELDEL0

09h

Set to 0

DISPMOD1

DISPMOD0

CLPDEL4

CLPDEL3

CLPDEL2

CLPDEL1

CLPDEL0

0Ah

AGCRES

AGCMD1

AGCMD0

AGCVAL3

AGCVAL2

AGCVAL1

AGCVAL0

NOSIGB

0Bh

CVBSEL1

CVBSEL0

CLMPID1

CLMPID0

BLKVCHYS

BLKVCVAL

LMOFST1

LMOFST0

0Ch

PLLITC1

PLLITC0

BLKVCFIL

(reserved)

YCDEL3

YCDEL2

YCDEL1

YCDEL0

0Dh

CSTAND2

CSTAND1

CSTAND0

CSTDEX1

CSTDEX0

(reserved)

CKILL1

CKILL0

0Eh

BGPOS

(reserved)

DEEMP1

DEEMP0

COLON

ACCFIX

CHRBW1

CHRBW0

0Fh

IFCOMP1

IFCOMP0

HUE5

HUE4

HUE3

HUE2

HUE1

HUE0

10h

SATNR

FMACTI

CPLLOF

SCADJ4

SCADJ3

SCADJ2

SCADJ1

SCADJ0

11h

CONADJ3

CONADJ2

CONADJ1

CONADJ0

BLKLR3

BLKLR2

BLKLR1

BLKLR0

12h

BRTADJ3

BRTADJ2

BRTADJ1

BRTADJ0

BLKLG3

BLKLG2

BLKLG1

BLKLG0

13h

TRIOUT

REFINT

BLKINVR

BLKINVB

BLKLB3

BLKLB2

BLKLB1

BLKLB0

14h

PKLR7

PKLR6

PKLR5

PKLR4

PKLR3

PKLR2

PKLR1

PKLR0

15h

PKLG7

PKLG6

PKLG5

PKLG4

PKLG3

PKLG2

PKLG1

PKLG0

16h

PKLB7

PKLB6

PKLB5

PKLB4

PKLB3

PKLB2

PKLB1

PKLB0

17h

MAT1

MAT0

BGY1

BGY0

FRY3

FRY2

FRY1

FRY0

18h

OUTFOR

UVPOLAR

BGU1

BGU0

FRU3

FRU2

FRU1

FRU0

19h

(reserved)

BGFRC

BGV1

BGV0

FRV3

FRV2

FRV1

FRV0

1Ah

SATADJ3

SATADJ2

SATADJ1

SATADJ0

YPEAK2

YPEAK1

YPEAK0

YCOR

1Bh

XDSCLS4

XDSCLS3

XDSCLS2

XDSCLS1

XDSCLS0

XDSTPE2

XDSTPE1

XDSTPE0

1Ch

UVSEQ

MPIPBG

SERVICE

SELLNR1

SELLNR0

IRQCON2

IRQCON1

IRQCON0

1Dh

(reserved)

PALIDL2

PALIDL1_1

PALIDL1_0

PIPBLK

(reserved)

PALIDL0

1Eh

POSOFV2

POSOFV1

POSOFV0

POSOFH4

POSOFH3

POSOFH2

POSOFH1

POSOFH0

1Fh

(reserved)

VSHRNK4

VSHRNK3

VSHRNK2

VSHRNK1

VSHRNK0

PVP 9390A

ADVANCE INFORMATION

May 3, 2004; 6251-633-1AI

Micronas

20h

(reserved)

HSHRNK4

HSHRNK3

HSHRNK2

HSHRNK1

HSHRNK0

21h

(reserved)

DWCOR

PKBOOST

CLPLEN1

CLPLEN0

22h

PIPHLT

ABRTHD3

ABRTHD2

ABRTHD1

ABRTHD0

ABRSPD2

ABRSPD1

ABRSPD0

23h

INFRMOD

DISPMOD6

DISPMOD5

DISPMOD4

DISPMOD3

DISPMOD2

WIPESP1

WIPESP0

24h

CZMEN

CZMSP1

CZMSP0

(reserved)

WRPOS3

WRPOS2

WRPOS1

WRPOS0

25h

CHRFRC

CHRDHW

CHRY1

CHRY0

CHRBGY1

CHRBGY0

CHRBGON1

CHRBGON0

26h

OSDON

CHRADR6

CHRADR5

CHRADR4

CHRADR3

CHRADR2

CHRADR1

CHRADR0

27h

CHRCLR

CHRCOD6

CHRCOD5

CHRCOD4

CHRCOD3

CHRCOD2

CHRCOD1

CHRCOD0

28h

FRMMD

PIPSTAT

SYSNCST1

SYSNCST0

CKSTAT

STDET2

STDET1

STDET0

29h

(reserved)

2Ah

DATAA7

DATAA6

DATAA5

DATAA4

DATAA3

DATAA2

DATAA1

DATAA0

2Bh

DATAB7

DATAB6

DATAB5

DATAB4

DATAB3

DATAB2

DATAB1

DATAB0

2Ch

PALDET

(reserved)

DEVICE1

DEVICE0

PRNSTD

PALID

DATAV

SLFIELD

2Dh

(reserved)

2Eh

SCMREL1

SCMREL0

SCMIDL2

SCMIDL1

SCMIDL0

SCCDIV

(reserved)

BELLIIR

2Fh

PALINC1

PALINC2

LOCKSP1

LOCKSP0

SECACCL2

SECACCL1

SECACCL0

SECACC

30h

ADLCK

ADLCKSEL

ADLCKCC

CLRANGE1

CLRANGE0

NADJ2

NADJ1

NADJ0

31h

NSRED2

NSRED1

NSRED0

SLLTHD1

SLLTHD0

ISHFT1

ISHFT0

ENLIM

32h

DETECT5060

VTHRL50_6

VTHRL50_5

VTHRL50_4

VTHRL50_3

VTHRL50_2

VTHRL50_1

VTHRL50_0

33h

BCOROFF

VTHRL60_6

VTHRL60_5

VTHRL60_4

VTHRL60_3

VTHRL60_2

VTHRL60_1

VTHRL60_0

34h

VTHRH50_3

VTHRH50_2

VTHRH50_1

VTHRH50_0

VTHRH60_3

VTHRH60_2

VTHRH60_1

VTHRH60_0

35h

CLMPSTGY

SLLTHDVP

SLLTHDV2

SLLTHDV1

SLLTHDV0

VFLYWHLMD1 VFLYWHLMD0 VFLYWHL

36h

FLNSTRD1

FLNSTRD0

CLMPCHARY1 CLMPCHARY0 VDETIFS

VDETITC

VLP1

VLP0

37h

LATENCY1

LATENCY0

FILTBRST

CLMPIST4

CLMPIST3

CLMPIST2

CLMPIST1

CLMPIST0

38h

(reserved)

CLKP_INV

INCRSEL

FINECLMP

INSEL_1

INSEL_0

39h

DTOINCR_7

DTOINCR_6

DTOINCR_5

DTOINCR_4

DTOINCR_3

DTOINCR_2

DTOINCR_1

DTOINCR_0

3Ah

(reserved)

GPO_2

GPO_1

GPO_0

GPOEN

CLKOUTEN

3Bh

(reserved)

YSYNCOFS

3Ch

(reserved)

AFIL_OFF

STBY_REF

STBY_OTA

STBY_ADC1

STBY_ADC2

STBY_ADC3

3Dh

STBY_BUFFE
R

STBY_CLAMP STBY_DAC1

STBY_DAC2

STBY_DAC3

STBY_GAIN

STBY_OFFSE
T

STBY_REF

3Eh

TRIM_BGP_7

TRIM_BGP_6

TRIM_BGP_5

TRIM_BGP_4

TRIM_BGP_3

TRIM_BGP_2

TRIM_BGP_1

TRIM_BGP_0

3Fh

(reserved)

PVPREV_1

PVPREV_0

Grey shading = After power on, the grey marked data bits are set to '1', all other to `0`

Table 3�6: I

C bus command table, continued

Subadd
(Hex)

Data Byte

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

3.4. I

C Bus Command Description

Subaddress 00h

Table 3�7: PIPON

PIPON

PIP On:
Switches the PIP insertion on

PIP insertion off

PIP insertion on

Table 3�8: CPOS

CPOS

Coarse Position:
Coarse position of the picture

Upper left position

Upper right position

Lower left position

Lower right position

Table 3�9: YUVSEL

YUVSEL

YUV Select:
Selects YUV mode

CVBS or Y/C source

YUV source

Table 3�10: READD

READD

Read Double Mode:
Double read frequency for compatibility with systems that use 2fH (e.g.100 Hz, progressive)

PIP display with single read frequency and 2x oversampling

PIP display with double read frequency

PVP 9390A

ADVANCE INFORMATION

May 3, 2004; 6251-633-1AI

Micronas

Subaddress 01h

Subaddress 02h

Table 3�11: PROGEN

PROGEN

Progressive Scan Enable:
For compatibility with progressive scan systems

Each line of PIP is read once (normal operation)

Each line of PIP is read twice (line doubling operation)

Table 3�12: FIESEL

FIESEL

Field Select:
Set field or frame display mode

Frame mode (if possible)

Field mode (first field only)

Field mode (second field only)

Field mode (one of both)

Table 3�13: POSHOR

POSHOR

Horizontal Picture Position:
Horizontal position adjustment of the PIP in steps of 4 pixel shift direction depends on the
coarse positioning of the picture

D7-D0

Table 3�14: POSVER

POSVER

Vertical Picture Position:
Vertical position adjustment of the PIP in steps of 1 lines shift direction depends on the coarse
positioning of the picture

D7-D0

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

Subaddress 03h

Subaddress 04h

Table 3�15: HFP

HFP

Horizontal Fine Positioning:
Changes the position of the horizontal acquisition window
by steps of 2 pixel

Note

-16 pixel (-0.8

�

s), most right position of the image

Values refer to the
undecimated picture

...

0 pixel, nominal center position

...

+14 pixel (0.7

�

s), most left position

Table 3�16: VFP

VFP

Vertical Fine Positioning:
Changes the position of the vertical acquisition window
by steps of 1 line

Note

8 lines, most upper position of the image

Values refer to the
undecimated picture

...

0 lines, nominal center position

...

+7 lines, most lower position

Table 3�17: DISPSTD

DISPSTD

Display Standard:
Selects the line standard of PIP display

PIP depends on detected parent standard (multi PIP) or inset standard (single PIP)

PIP display is always in 625 line mode

PIP display is always in 525 line mode

Freeze last detected display standard and size

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

Subaddress 05h

Table 3�22: FPSTD

FPSTD

Force Parent Standard:
Forces the parent standard to one of the following modes

Auto-detect parent standard

50 Hz/625 lines parent standard forced

60 Hz/525 lines parent standard forced

Freeze last detected standard

Table 3�23: PIPBG

PIPBG

PIP Background Display:
Selects the background display

PIP visible, no background display

PIP invisible, background display in PIP

PIP visible, full screen background display

PIP invisible, background display in PIP and full screen background

Table 3�24: FMACTP

FMACTP

Frame Mode Activation Parent:
Selects the parent condition for the activation of the frame mode

Frame mode active for standard parent video sources only

Frame mode active for some nonstandard sources also

Table 3�25: HZOOM

HZOOM

Horizontal Zoom:
Selects the parent (display) clock frequency

27.34 MHz

20.25 MHz

35.27 MHz

PVP 9390A

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May 3, 2004; 6251-633-1AI

Micronas

Subaddress 06h

25.43 MHz

26.67 MHz

20.63 MHz

34.17 MHz

28.04 MHz

Table 3�25: HZOOM, continued

HZOOM

Horizontal Zoom:
Selects the parent (display) clock frequency

Table 3�26: HSPINV

HSPINV

Horizontal Sync Pulse Inversion:
Inverts the polarity of HSP

No inversion, raising edge is sync reference

HSP inverted, falling edge is sync reference

Table 3�27: VSPINV

VSPINV

Vertical Sync Pulse Inversion:
Inverts the polarity of VSP

No inversion, raising edge is sync reference

VSP inverted, falling edge is sync reference

Table 3�28: VSPNSRQ

VSPNSRQ

Vertical Sync Pulse Noise Reduction:
Activates automatic V insertion that generates vertical sync pulses in case of missing external
VSP

Off

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

Subaddress 07h

Table 3�29: VSPDEL

VSPDEL

Vertical Sync Pulse Delay:
Delay of the vertical sync pulse in steps of
128 parent clocks

Note

No delay (0)

Delay depends on
HZOOM

...

Maximum delay, 4096 clocks of parent fre-
quency

Table 3�30: FRSEL

FRSEL

Frame Select:
Selects between the normal frame and the shaded frame

Normal frame

Shaded frame with 3D impression

Table 3�31: INFRM

INFRM

Inner Frame Activation:
Actives inner frame (4 pixel width, 2 lines height) for multi-PIP display)

Inner frame off

Inner frame on

Table 3�32: VPSRED

VPSRED

Vertical Picture Size Reduction:
Reduces vertical picture size to suppress black bars in 16:9 programs

No reduction

Reduction on

PVP 9390A

ADVANCE INFORMATION

May 3, 2004; 6251-633-1AI

Micronas

Subaddress 08h

Table 3�33: FRWIDH

FRWIDH

Frame Width Horizontal:
Adjusts the horizontal width of the PIP frame in steps of one pixel

No horizontal frame

...

7 pixel

Table 3�34: FRWIDV

FRWIDV

Frame Width Vertical:
Adjusts the vertical width of the PIP frame in steps of one line

No vertical frame

...

3 lines

Table 3�35: RGBINS

RGBINS

RGB Insertion:
Controls the insertion of external RGB/YUV sources

No external insertion possible, FSW input inactive

External insertion forced (FSW = 1)

External insertion with FSW possible (priority of FSW input)

External insertion with FSW possible (priority of PIP)

Table 3�36: VERBLK

VERBLK

Vertical Blanking:
Switches the vertical blanking mode

Blanking level at DAC outputs only during line-blanking intervals

Blanking level at DAC outputs during line-blanking intervals and field-blanking intervals, 16
lines following the parent vertical synchronization pulse are blanked

PVP 9390A

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May 3, 2004; 6251-633-1AI

Micronas

Subaddress 0Dh

Table 3�53: CSTAND

CSTAND

Color Standard:
Forces the desired color standard

Automatic standard identification

NTSC-M

PAL-N (Argentina)

PAL-M

NTSC44

PAL-B/G/H/I/D

SECAM

PAL60

Table 3�54: CSTDEX

CSTDEX

Color Standard Exclusion:
Excludes standards from automatic standard identification

Ignore PAL-M / PAL-N

Ignore SECAM, PAL B/G, PAL60, NTSC4.4

Ignore PAL-M /PAL-N / NTSC-M

Ignore PAL-M / PAL-N / NTSC4.4 / PAL60

Table 3�55: CKILL

CKILL

Color Killer Threshold:
Damping of color carrier to switch color off

Note

30 dB

Only valid if color killer active
(COLON='0'),
Values are approximative

18 dB

24 dB

Color always off

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

Subaddress 10h

Table 3�63: SATNR

SATNR

Satellite Noise Reduction:
Stabilizes the horizontal PLL for bad satellite signals ("fishes")

Disabled

Enabled

Table 3�64: FMACTI

FMACTI

Frame Mode Activation Inset:
Sets the inset condition for the activation of the frame mode

Frame mode only active for standard inset video sources

Enhanced frame mode activation range

Table 3�65: CPLLOF

CPLLOF

Chroma PLL Off:
Opens loop of chroma PLL (only for test and servicing)

Chroma PLL active

Chroma PLL opened (free running oscillator)

Table 3�66: SCADJ

SCADJ

Color Subcarrier Adjustment:
Color subcarrier frequency fine adjustment

Max. negative deviation (

150 ppm)

...

Default (for nominal crystal frequency

...

Max. positive deviation (+310 ppm)

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May 3, 2004; 6251-633-1AI

Micronas

Subaddress 11h

Subaddress 12h

Table 3�67: CONADJ

CONADJ

Contrast Adjustment:
Adjusts the contrast of the picture, acts on OUT1-OUT3

Nominal contrast

...

+30 % contrast increase

Table 3�68: BLKLR

BLKLR

Blanking Level Red:
Adjusts the pedestal level of the OUT1 channel in steps of 0.5 LSB

No pedestal

...

+7.5 LSB offset

Table 3�69: BRTADJ

BRTADJ

Brightness Adjustment:
Adjusts the brightness of the picture, acts on OUT1-OUT3 in RGB mode
(YUVFOR = `0') and on OUT1 in YUV mode (YUVFOR = `1')

Nominal brightness

...

+20 % brightness increase

Table 3�70: BLKLG

BLKLG

Blanking Level Green:
Adjusts the pedestal level of the OUT2 channel in steps of 0.5 LSB

No pedestal

...

+7.5 LSB offset

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PVP 9390A

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Subaddress 13h

Table 3�71: TRIOUT

TRIOUT

Tri-state Output:
Sets OUT1-OUT3 to tristate mode (high resistance)

Normal operation, outputs are active

Pins OUT1-3 are in tri-state mode

Table 3�72: REFINT

REFINT

Refresh Intervall:
Changes the refresh rate of eDRAM

Note

Normal refresh

Keep it at `0'

Fast refresh

Table 3�73: BLKINVR

BLKINVR

Blanking Inversion Red:
Inverts the sign of the OUT1 channel offset (BLKLR)

Offset added during the active picture

Offset added during blanking

Table 3�74: BLKINVB

BLKINVB

Blanking Inversion Blue:
Inverts the sign of the OUT3 channel offset (BLKLB)

Offset added during the active picture

Offset added during blanking

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PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

Subaddress 15h

Subaddress 16h

Subaddress 17h

Table 3�77: PKLG

PKLG

Peak Level Green:
Peak to peak output
voltage of the OUT2
channel

Note

0.3 V

Values refer to con-
trast (CONADJ) and
brightness (BRT-
ADJ) at minimum

...

1 V

...

1.2 V

Table 3�78: PKLB

PKLB

Peak Level Blue:
Peak to peak output
voltage of the OUT2
channel

Note

0.3 V

Values refer to
contrast (CON-
ADJ) and bright-
ness (BRTADJ)
at minimum

...

1 V

...

1.2 V

Table 3�79: MAT

MAT

RGB Matrix Select:
Selects the RGB matrix coefficients for YUV to RGB conversion

EBU- Matrix

NTSC-Japan Matrix

NTSC-USA Matrix

(Reserved)

PVP 9390A

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Subaddress 18h

Table 3�80: BGY

BGY

Background Color Y:
Adjusts the Y background color component the values gives the two MSBs of the Y
background signal

D5-D4

Table 3�81: FRY

FRY

Frame Color Y:
Adjusts the Y frame color component the value gives the 4 MSBs of the Y frame signal

D3-D0

Table 3�82: OUTFOR

OUTFOR

Output Format:
Switches between RGB output and YUV output

RGB output signals, matrix active

YUV output signals

Table 3�83: UVPOLAR

UVPOLAR

UV Polarity:
Switches between UV or inverted UV output, has no influence in RGB mode

+U / +V output

U /

V output

Table 3�84: BGU

BGU

Background Color U:
Adjusts the U background color component the values gives the two MSBs of the U
background signal

D5-D4

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

Subaddress 1Bh

Table 3�92: XDSCLS

XDSCLS

XDS Class Select:
Closed Caption XDS-Primary Filter (Class)

Transparent, no filtering

`Current' class selected

`Future' class selected

`Channel' class selected

`Miscellaneous' class selected

`Public Services' class selected

Table 3�93: XDSTPE

XDSTPE

XDS Type Select/WSS Field Select

XDS-Secondary Filter Type

Meaning

WSS
field

Note

All No

filtering

Behavior of
these bits
depends on
selected data-
service

05h

Program rating

01h, 04h

Time information only

0/1

40h

Out of band only

0/1

01h, 02h, 03h, 04h, 0Dh, 40h

VCR information

0/1

01h, 04h, 05h

Time information and program rating

0/1

05h, 40h

Out of band and program rating

0/1

01h, 02h, 03h, 04h, 05h, 0Dh,
40h

VCR information and program rating

0/1

PVP 9390A

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May 3, 2004; 6251-633-1AI

Micronas

Subaddress 1Ch

Table 3�94: UVSEQ

UVSEQ

UV Sequence:
Changes the UV multiplex sequence

Note

U and V are correct

Valid only if YUVSEL= `1'

U and V are exchanged

Table 3�95: MPIPBG

MPIPBG

Multi-PIP Background:
Selects the background color for multi-PIP mode

Black

Same as background color

Table 3�96: SERVICE

SERVICE

Data Service Select:
Selects data service for slicing

Closed Caption

Widescreen Signalling (WSS)

Table 3�97: SELLNR

SELLNR

Select Line Number:
Line number of data service field 0 (field1)

Note

[NTSC] 20 (283), [PAL M] 17 (280)

WSS

[NTSC] 21 (284), [PAL M] 18 (281)

Closed Caption

[PAL B/G] 22 (329)

Closed Caption

[PAL B/G] 23 (330)

WSS

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

Subaddress 1Dh

Table 3�98: IRQCON

IRQCON

Interrupt Request Pin Configuration:
Output of INT pin is:

Note

Tri-state (high-Z)

Interrupt, when new data received
(neg. polarity)

Pulse length is approximately
2

�

Interrupt, when new data received
(pos. polarity)

Equivalent to DATAV for both registers (neg. polarity)

Equivalent to DATAV for both registers (pos. polarity)

Inset V-pulse (neg. polarity)

Pulse length is 50 ns

Inset field

High = first field, low = second
field,

Inset clamping pulse (neg. polarity)

Only for test purpuse

Table 3�99: PALIDL2

PALIDL2

PAL/NTSC identifikation level 2 :
Sensitivity of identification of PAL/NTSC signals

1/2 or 1/4

1/8 or 1/16

Table 3�100: PALIDL1

PALIDL1

PAL/NTSC identifikation level 1:
Sensitivity of identification of PAL/NTSC signals

+32

+64

+128

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

Subaddress 1Fh

Subaddress 20h

Table 3�104: POSOFH

POSOFH

Position Offset Horizontal:
Horizontal position offset in steps of 16 pixel

256 pixel

...

0 pixel

...

+240 pixel

Table 3�105: VSHRNK

VSHRNK

Vertical Shrink:
Changes the vertical size in steps of 2 lines

Note

No shrink, picture size according to SIZEVER

Max. usable value
depends on
SIZEVER

...

Max. possible shrink

Table 3�106: HSHRNK

HSHRNK

Horizontal Shrink:
Changes the horzontal size in steps of 4 pixel

Note

No shrink, picture size according to SIZEHOR

Max. usable value
depends on
SIZEVER

...

Max. possible shrink

PVP 9390A

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Micronas

Subaddress 21h

Subaddress 22h

Table 3�107: DWCOR

DWCOR

Test only

(Reserved)

Normal operation

Table 3�108: PKBOOST

PKBOOST

Peaking Boost:
Influences peaking of YPEAK (A2h)

Use normal peaking values

Double peaking values

Table 3�109: CLPLEN

CLPLEN

Clamping Pulse Length

Blanking Duration

Note

�

10.5

�

The clamping pulse length and the
blanking is also influenced by the
setting of READD and HZOOM

3.75

�

7.9

�

2.5

�

5.2

�

1.25

�

2.6

�

Table 3�110: PIPHLT

PIPHLT

PIP Highlighting:
Highlights the current selected (WRPOS) PIPr

No highlighting

Highlighting the PIP

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

Subaddress 23h

Table 3�111: ABRTHD

ABRTHD

Automatic Brightness Reduction Threshold:
Threshold adjustment for reduction of luminance magnitude

ABR off

ABR threshold at luminance value of 240

...

ABR threshold at luminance value of 180

Table 3�112: ABRSPD

ABRSPD

Automatic Brightness Reduction Speed:
Speed adjustment for reduction of luminance magnitude

2 fields

...

16 fields

Table 3�113: INFRMOD

INFRMOD

Inner Frame Modification:
Modifies the look of the frame for dual-PIP applications

Inner frame suited for usage of single PIP applications

Inner frame suited for usage of dual PIP applications

Table 3�114: DISPMOD

DISPMOD

Display Mode:
Selects the single PIP modes, multi-PIP modes or
double-window mode

Note

Single PIP mode

See Table 2�9 on
page 15 for
description of
modes

...

OSD only mode

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

Subaddress 25h

Table 3�118: WRPOS

WRPOS

Write Position:
Position of the current written picture

Note

First writing position = first picture

Number of last valid writing posi-
tion depends on display mode
(DISPMOD)

Second writing position

...

Maximum writing position

Table 3�119: CHRFRC

CHRFRC

Character Frame Color:
Modifies the character color

Character luminance table used

Frame color table used

Table 3�120: CHRDHW

CHRDHW

Character Double Height and Width:
Doubles the characters' height and width

Normal height and width

Double height and width

Table 3�121: CHRY

CHRY

Character Luminance:
Character luminance level (IRE)

Note

Valid only if CHRFRC = `0', charac-
ter chrominance is 0 IRE

PVP 9390A

ADVANCE INFORMATION

May 3, 2004; 6251-633-1AI

Micronas

Subaddress 2Ch

Table 3�135: PALDET

PALDET

PAL identification:
PAL identification (algorithm B)

Not PAL

PAL

Table 3�136: DEVICE

DEVICE

Device Identification:
Micronas PIP IC

SDA 9488X (PIP IV Basic)

SDA 9489X (PIP IV Advanced)

SDA 9588X (OCTOPUS)

SDA 9589X (SOPHISTICUS) / PVP 9390A (see Table 3�202 on page 89).

Table 3�137: PRNSTD

PRNSTD

Parent Standard Detection:
Status of parent (display) standard detection

60 Hz field frequency detected

50 Hz field frequency detected

Table 3�138: PALID

PALID

PAL Identification:
Identification of PAL signal (algorithm A)

Note

NTSC signal

Not valid if STDET= `000'

PAL signal

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

Subaddress 33h

Subaddress 34h

Table 3�160: VTHRL50

VTHRL50

Vertical Window Noise Suppression Opening
50 Hz

Note

D6-D0

0000000

Opening in first line

Opening=4*VTHRL50

...

1111111

Opening in line 508

Table 3�161: BCOROFF

BCOROFF

Blanklevel Coring Off:
Blanklevel generation coring (for sync-tip clamping only)

Coring on

Coring off

Table 3�162: VTHRL60

VTHRL60

Vertical Window Noise Suppression Opening
60 Hz

Note

D6-D0

0000000

Opening in first line

Opening=4*VTHRL60

...

1111111

Opening in line 508

Table 3�163: VTHRH60

VTHRH60

Vertical Window Noise Suppression Closing
60 Hz

Note

D3-D0

0000

Closing in line 262

Closing=262+4*VTHRH60

...

1111

Closing in line 262+60

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

4.2. Pin Connections and Short Descriptions

NC = not connected, leave vacant
LV = if not used, leave vacant
STG = short to GND
OBL = obligatory; connect as described in circuit diagram

Pin
No.

Pin Name

Type

Connection

(If not used)

Short Description

XOUT

OBL

Crystal oscillator (output)

XIN

OBL

Crystal oscillator (input) or external clock input

VSS18

Supply

OBL

1.8 V digital core ground

VDD18

Supply

OBL

1.8 V digital core supply

GPO0

I/O

General purpose output

SEL

OBL

Fast blanking output for PIP

OUT3

O/Analog

OBL

Analogue output: chrominance signal +(B-Y) or -(B-
Y) or B

OUT2

O/Analog

OBL

Analogue output: luminance signal Y or G

OUT1

O/Analog

OBL

Analogue output: chrominance signal +(R-Y) or
-(R-Y) or R

VSS33DAC

Supply

OBL

3.3 V DAC analog ground

VDD33DAC

Supply

OBL

3.3 V DAC analog supply

FSW

Fast switch input for YUV/RGB switch

IN3

I/Analog

U/B input for external YUV/RGB source

IN2

I/Analog

Y/G input for external YUV/RGB source

IN1

I/Analog

V/R input for external YUV/RGB source

VDD18ADC

Supply

OBL

1.8 V ADC analog supply

VSS18ADC

Supply

OBL

1.8 V ADC analog ground

CVBS1

I/Analog

CVBS1 or Y (from YUV) input

TEST

I/O

STG

Reserved (tie to VSS)

CVBS2

I/Analog

CVBS2 or U or Y (from Y/C) input

STG

Test mode (tie to VSS)

CVBS3

I/Analog

CVBS3 or V or C Input

CVBS4

I/Analog

CVBS4

VSS33ADC

Supply

OBL

3.3 V ADC analog ground

VDD33ADC

Supply

OBL

3.3 V ADC analog supply

YIN

I/Analog

Y input

UIN

I/Analog

U input

PVP 9390A

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VIN

I/Analog

V input

RESET

OBL

Asynchronous reset input

VDD18

Supply

OBL

1.8 V digital core supply

VSS18

Supply

OBL

1.8 V digital core ground

POR

Reserved (open)

GPO2

I/O

General purpose output

I2C1

OBL

I�C

Address 1

I2C2

OBL

I�C

Address 2

SDA

I/O

OBL

I�C

-bus data

SCL

OBL

I�C

-bus clock

INTR

Interrupt output

VDD33PAD

Supply

OBL

3.3 V digital pad supply

VSS33PAD

Supply

OBL

3.3 V digital pad ground

VSP

OBL

Vertical sync for parent channel

HSP

OBL

Horizontal sync for parent channel

GPO1

I/O

General purpose output

CLKOUT

Clock output

Pin
No.

Pin Name

Type

Connection

(If not used)

Short Description

PVP 9390A

ADVANCE INFORMATION

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Micronas

4.4. Electrical Characteristics

Abbreviations:

tbd = to be defined
vacant = not applicable
positive current values mean current flowing into the chip

4.4.1. Absolute Maximum Ratings

Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute
maximum rating conditions for extended periods will affect device reliability.

This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric
fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than abso-
lute maximum-rated voltages to this high-impedance circuit.

All voltages listed are referenced to ground (VSS18, VSS33PAD, VSS33DAC, VSS18ADC, VSS33ADC) except
where noted.

All GND pins must be connected to a low-resistive ground plane close to the IC.

Table 4�1: Absolute Maximum Ratings

Symbol

Parameter

Pin Name

Limit Values

Unit

Min.

Max.

Ambient Operating Temperature
PMQFP44-1

�

Case Operating Temperature
PMQFP44-1

-10

115

�C

Storage Temperature

125

�

max

Maximum Power Dissipation
Package PMQFP44-1

750

SUP1

Supply Voltage 1

VDD33DAC,
VDD33ADC,
VDD33PAD

0.3

3.63

SUP2

Supply Voltage 2

VDD18,
VDD18ADC

0.3

1.98

SUP

Voltage Differences within Sup-
ply Domains

0.25

Input Voltage

All except power
supply

0.3

SUP1

+0.3 V

Output Voltage

All except power
supply

0.3

SUP1

+0.3 V

Measured on Micronas typical 2-layer (1s1p) board based on JESD - 51.2 Standard with maximum power con-

sumption allowed for this package.

A power-optimized board layout is recommended. The Case Operating Temperature mentioned in the Absolute

Maximum Ratings must not be exceeded at worst case conditions of the application

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

4.4.2. Recommended Operating Conditions

Functional operation of the device beyond those indicated in the "Recommended Operating Conditions/Characteris-
tics" is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device.

All voltages listed are referenced to ground (VSS18, VSS33PAD, VSS33DAC, VSS18ADC, VSS33ADC) except
where noted.

All GND pins must be connected to a low-resistive ground plane close to the IC.

Do not insert the device into a live socket. Instead, apply power by switching on the external power supply.

Symbol

Parameter

Pin Name

Limit Values

Unit

Min.

Typ.

Max.

Ambient Operating Temperature
Package PMQFP44-1

�

Case Operating Temperature
Package PMQFP44-1

�

max

Maximum Power Dissipation
Package PMQFP44-1

400

SUP1

Supply Voltage 1

VDD33DAC,
VDD33ADC,
VDD33PAD

3.13

3.3

3.46

SUP2

Supply Voltage 2

VDD18,
VDD18ADC

1.71

1.8

1.89

SUP

Voltage Differences within Supply
Domains

0.25

Input Voltage Low

0.8

Input Voltage High

2.0

A power-optimized board layout is recommended. The Case Operating Temperatures mentioned in the "Rec-
ommended Operating Conditions" must not be exceeded at worst case conditions of the application.

By T

Amin

and 300 mW

By T

=25�C and 350 mW

By T

Amax

and 400 mW

ADVANCE INFORMATION

PVP 9390A

Micronas

May 3, 2004; 6251-633-1AI

5. Application

5.1. Application Circuit

Fig. 5�1: Application Circuit

100

SCL

47n

CVBS4

I2C

Address

+3.3V

*) depends on cr

ystal specification

XOUT

12345

7891

XIN

VSS18

VDD18

GPO0

SEL

OUT3

OUT2

OUT1

VSS33DA

VDD33DA

CVBS4

VSS33ADC

VDD33ADC

YIN

UIN

VIN

RESET

VDD18

VSS18

POR

GPO2

PVP 9390A

FSW

CVBS3

I2C1

CLK

OUT

IN3

IN2

IN1

VDD18ADC

VSS18ADC

CVBS1

TEST

CVBS2

I2C2

SCL

INTR

VDD33P

VSS33P

VSP

HSP

GPO1

20.25 MHz

C24 *

18p

C23 *

18p

+3.3V

47n

CVBS2

CVBS1

CVBS3

C16

47n

C17

47n

C18

47n

BIN

GIN

RIN

FSW

BOUT

GOUT

OUT

SEL

INT

RESET

C15

10n

C14

+3.3V

C19

10n

C20

+3.3V

47n

R11

R10

R12

C12

10n

C13

+1.8V

C10

10n

C11

+3.3V

10n

+1.8V

All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples deliv-
ered. By this publication, Micronas GmbH does not assume responsibil-
ity for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication
and to make changes to its content, at any time, without obligation to
notify any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.

PVP 9390A

ADVANCE INFORMATION

May 3, 2004; 6251-633-1AI

Micronas

Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: docservice@micronas.com
Internet: www.micronas.com

Printed in Germany
Order No. 6251-633-1AI

6. Data Sheet History

1. Advance Information: "PVP 9390A Picture-in-Pic-

ture IC", May 3, 2004, 6251-633-1AI. First release of
the advance information.

Электронный компонент: PVP9390A

Document Outline