Document Outline

Features
Description
Functional Description
Pin Information
Absolute Maximum Ratings
Handling Precautions
Electrical Characteristics
- dc Characteristics
Transmission Characteristics
- ac Transmission Characteristics
  - Overload Compression
Timing Characteristics
Applications
Outline Diagram
- 28-Pin PLCC
- 44-Pin MQFP
Ordering Information
List of Figures
- Figure 1. Block Diagram For 28-Pin DIP and 28-Pin PLCC
- Figure 2. Typical Analog Input Section
- Figure 3. 28-Pin PLCC Pin Diagram
- Figure 4. 44-Pin MQFP Pin Diagram
- Figure 5. Overload Compression
- Figure 6. T7504 Transmit and Receive Timing, FSEP = 1 MCLK
- Figure 7. T7504 Receive Timing, FSEP > 1 MCLK
- Figure 8. T5504 Transmit and Receive Timing, FSEP = 1 MCLK
- Figure 9. T5504 Receive Timing, FSEP > 1 MCLK
- Figure 10. Typical Frame Sync Timing (2 MHz Operation)
- Figure 11. Typical T7504 and T5504/SLIC Interconnection
List of Tables
- Table 1. Pin Descriptions
- Table 2. Digital Interface
- Table 3. Power Dissipation
- Table 4. Analog Interface
- Table 5. Absolute Gain
- Table 6. Gain Tracking
- Table 7. Distortion
- Table 8. Envelope Delay Distortion
- Table 9. Noise
- Table 10. Receive Gain Relative to Gain at 1.02 kHz
- Table 11. Transmit Gain Relative to Gain at 1.02 kHz
- Table 12. Interchannel Crosstalk (Between Channels) ...
- Table 13. Intrachannel Crosstalk (Within Channels) ...
- Table 14. Clock Section
- Table 15. T7504 Transmit Section
- Table 16. T5504 Transmit Section
- Table 17. T7504 and T5504 Receive Section
Contact Us

T7504 and T5504 Quad PCM Codecs with Filters

Data Sheet
March 1999

Features

5 V only

Low-power, latch-up-free CMOS technology
-- 37 mW/channel typical operating power

dissipation

-- 1 mW/channel typical powerdown dissipation

Automatic master clock frequency selection
-- 2.048 MHz or 4.096 MHz

On-chip sample and hold, autozero, and precision
voltage reference

Differential architecture for high noise immunity
and power supply rejection

Flexible time-slotted PCM interface
-- 2.048 MHz or 4.096 MHz data rate

Meets or exceeds ITU-T G.711--G.714 require-
ments and VF characteristics of D3/D4 (as per
Lucent Technologies PUB43801)

Operating temperature range: 40

C to +85

-law/A-law companding selectable

Description

The T7504 and T5504 devices are single-chip, four-
channel

-law/A-law PCM codecs with filters. These

integrated circuits provide analog-to-digital and
digital-to-analog conversion. They provide the
transmit and receive filtering necessary to interface a
voice telephone circuit to a time-division multiplexed
system. These devices are available in 28-pin
PLCCs. The T7504 is also available in a 44-pin
MQFP.

The T5504 differs from the T7504 in its timing mode.
The T5504 operates in the nondelay timing mode
(digital data valid when frame sync goes high), and
the T7504 operates in the delayed timing mode
(digital data is valid one clock cycle after frame sync
goes high) (see Figures 6--9).

5-3579.d(C)

Figure 1. Block Diagram For 28-Pin DIP and 28-Pin PLCC

IN0

INF1

IN2

IN3

FILTER

NETWORK

ENCODER

CHANNEL 0

+2.4 V

DECODER

PCM

INTERFACE

POWERDOWN

CONTROL

INTERNAL TIMING

& CONTROL

BIAS

CIRCUITRY

REFERENCE

CHANNEL 1

CHANNEL 2

CHANNEL 3

FILTER

NETWORK

FSEP
GNDD

MCLK

ASEL

(2)

GNDA (4) (PLCC ONLY)

(2) (MQFP ONLY)

GNDA (5) (MQFP ONLY)

Lucent Technologies Inc.

Data Sheet

March 1999

T7504 and T5504 Quad PCM Codecs with Filters

Functional Description

Four channels of PCM data input and output are
passed through only two ports, D

and D

, so some

type of time-slot assignment is necessary. The scheme
used here is to utilize timing modes of 32 or 64 time
slots corresponding to master clock frequencies of
either 2.048 MHz or 4.096 MHz, respectively. Each
device has four transmit frame sync (FS

) inputs, one

for each channel. During a single 125

s frame, each

transmit frame sync input is supplied a single pulse.
The timing of the pulse indicates the beginning of the
time slot during which the data for that channel is
clocked out of the device. During a frame, transmit
frame sync pulses must be separated from each other
by one or more time slots. A channel is placed in a
standby (low-power) mode if its FS

input has been low

for 500

There is a single frame sync separation input (FSEP).
The number of negative clock edges minus one that
occurs while FSEP is high is the delay (in clock
periods) that is placed between the rising edge of a
transmit frame sign bit and the falling edge used by the
receiver to sample the sign bit. There must always be a
pulse on the FSEP input since this input provides the
8 kHz signal required to maintain internal timing. If the
FSEP pulse is one clock period or less, the device
makes the transmit edges and receive sampling edges
one half clock period apart. The entire device is placed
in a powerdown mode if FSEP remains low for 500

Time slot zero is defined as starting on the first rising
MCLK edge after FSEP = 1 is detected by a negative
MCLK edge. In the T7504, MCLK negative-going
edges that detect the start of FSEP and FS

N must be

integer multiples of eight MCLK periods apart (zero
multiples are allowed). Since FSEP is assumed to
define time slot 0, the number of multiples separating
FS

N and FSEP is the time-slot number. In the T5504,

N for time slot 0 nominally starts on the MCLK

positive edge following the negative edge which
detects FSEP.

The frequency of the master clock must be either
2.048 MHz or 4.096 MHz. Internal circuitry determines
the master clock frequency during the powerup reset
interval.

Powerdown is not guaranteed if MCLK is lost unless
the device is already in the powerdown mode due to
FSEP low for at least 500

The analog input section in Figure 2 includes an on-
chip op amp that is used in conjunction with external,
user-supplied resistors to vary encoder passband gain.
The feedback resistance (R

) should range from 10 k

to 200 k

and capacitance from GSx to ground should

be kept to less than 50 pF. The input signal at VF

should be ac coupled. For best performance, the maxi-
mum gain of this op amp should be limited to 20 dB or
less.

5-3786

Figure 2. Typical Analog Input Section

TO
CODEC
FILTERS

2.4 V

GAIN =

Lucent Technologies Inc.

Data Sheet
March 1999

T7504 and T5504 Quad PCM Codecs with Filters

Pin Information

5-3580.b

Figure 3. 28-Pin PLCC Pin Diagram

5-4770

Figure 4. 44-Pin MQFP Pin Diagram

GNDA3

GNDD

FSEP

MCLK

ASEL

IN2

GNDA2

GNDA0

IN0

GNDA1

IN1

IN3

T - 7504 - - - ML

T - 5504 - - - ML

MCLK

ASEL

DDA

IN2

GNDA2

DDA

IN0

GNDA1

GNDA0

GNDD

FSEP

GNDA3

GNDA4

T7504---JL

IN3

IN1

Lucent Technologies Inc.

Data Sheet

March 1999

T7504 and T5504 Quad PCM Codecs with Filters

Pin Information

(continued)

* I

Indicates a pull-down device is included on this lead.

Table 1. Pin Descriptions

Symbol

Pin

Type

Name/Function

PLCC

MQFP

IN3

IN2

IN1

IN0

16
22

19
26

Voice Frequency Transmitter Input.

Analog inverting input to the uncommitted

operational amplifier at the transmit filter input. Connect the signal to be digitized
to this pin through a resistor R

(see

Figure 2

17
21

20
25

Gain Set for Transmitter.

Output of the transmit uncommitted operational

amplifier. The pin is the input to the transmit differential filters. Connect the pin to
its corresponding VF

IN through a resistor R

(see

Figure 2

12
10
18
20

13
10
21
24

Voice Frequency Receiver Output.

This pin can drive 2000

(or greater) loads.

[1:0]

DDA

[1:0]

7, 24

3, 31
4, 30

5 V Digital and Analog Power Supplies

. All pins must be connected on the circuit

board. Each pin should be bypassed to ground with at least 0.1

F of capacitance

as close to the device as possible. For the DIP and PLCC packages, V

serves

both analog and digital internal circuits.

GNDA4
GNDA3
GNDA2
GNDA1
GNDA0

15
11
19
23

18
16
11
23
27

Analog Grounds

. All ground pins must be connected on the circuit board.

Receive PCM Data Input

. The data on this pin is shifted into the device on the fall-

ing edges of MCLK. Data is only entered for valid time slots as defined by the re-
lationship of the pulses on the FS

inputs and the pulse on the FSEP input.

Transmit PCM Data Output

. This pin remains in the high-impedance state except

during active transmit time slots. An active transmit time slot is defined as one in
which a pulse is present on one of the FSx inputs. Data is shifted out on the rising
edge of MCLK.

MCLK

Master Clock Input

. The frequency must be 2.048 MHz or 4.096 MHz. This clock

serves as the bit clock for all PCM data transfer. A 40% to 60% duty cycle is re-
quired.

GNDD

Digital Ground

. Ground connection for the digital circuitry. All ground pins must be

connected on the circuit board.

28
27
26
25

36
35
34
33

Transmit Frame Sync

. This signal is an edge trigger and must be high for a min-

imum of one MCLK cycle. This signal must be derived from MCLK. The division ra-
tio is 1:256 or 1:512 (FS

:MCLK). Each FS

input must have a pulse present at the

start of the desired active output time slot. Pulses on the various FS

inputs must

be separated by one or more integer multiples of time slots. An internal pull-down
device is included on each FS

ASEL

A-Law/

-Law Select

. A logic low selects

-law coding. A logic high selects A-law

coding. A pull-down device is included.

FSEP

Frame Sync Separation

. The pulse width of this 8 kHz signal defines the timing

offset between the transmit and receive frames. Internally generated receive frame
sync pulses are delayed from the corresponding transmit frame sync pulse rising
edge by one less than the FSEP pulse width in negative MCLK edges. If the pulse
width is one MCLK period or less, the transmit and receive frame syncs are made
coincident. Loss of FSEP causes the device to powerdown. If the master clock fre-
quency is 2.048 MHz or 4.096 MHz, delays of 255 or 511 clock pulses are not al-
lowed, respectively. Timing relationships between FSEP, FS

N, and time slot 0 are

given in Figures

Lucent Technologies Inc.

Data Sheet
March 1999

T7504 and T5504 Quad PCM Codecs with Filters

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.

Handling Precautions

Although protection circuitry has been designed into this device, proper precautions should be taken to avoid
exposure to electrostatic discharge (ESD) during handling and mounting. Lucent Technologies Microelectronics
Group employs a human-body model (HBM) and a charged-device model (CDM) for ESD susceptibility testing and
protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the
model. No industry-wide standard has been adopted for CDM. However, a standard HBM (resistance = 1500

capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD
threshold presented here was obtained by using these circuit parameters:

Electrical Characteristics

Specifications apply for T

= 40

C to +85

C, V

= 5 V

5%, MCLK = either 2.048 MHz or 4.096 MHz, and

GND = 0 V, unless otherwise noted.

dc Characteristics

Table 2. Digital Interface

Parameter

Symbol

Min

Max

Unit

Storage Temperature Range

stg

150

Power Supply Voltage

6.5

Voltage on Any Pin with Respect to Ground

0.5

0.5 + V

Maximum Power Dissipation (package limit)

600

HBM ESD Threshold Voltage

Device

Rating

T7504

>2000 V

T5504

>2000 V

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Input Low Voltage

All digital inputs

0.8

Input High Voltage

All digital inputs

2.0

Output Low Voltage

, I

= 3.2 mA

0.4

Output High Voltage

, I

= 3.2 mA

2.4

, I

= 320

3.5

Input Current, Pins without Pull-down

Any digital input GND < V

Input Current, Pins with Pull-down

Any digital input GND < V

150

Output Current in High-impedance State

Input Capacitance

Lucent Technologies Inc.

Data Sheet

March 1999

T7504 and T5504 Quad PCM Codecs with Filters

Electrical Characteristics

(continued)

Table 3. Power Dissipation

Power measurements are made at MCLK = 4.096 MHz, outputs unloaded.

Transmission Characteristics

Table 4. Analog Interface

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Powerdown Current

DD0

MCLK present, FS

[3:0] = 0.4 V, FSEP = 0.4 V

0.2

Powerup Current

DD1

MCLK, FS

[3:0], FSEP present

Standby Current

DDS

MCLK, FSEP present; FS

[3:0] = 0.4 V

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Input Resistance, VF

VFXI

0.25 V < VFxI < 4.75 V

1.0

Input Leakage Current, VF

BVFXI

0.25 V < VFxI < 4.75 V

2.4

dc Open-loop Voltage Gain, GS

VOL

5000

Open-loop Unity Gain Bandwidth, GS

MHz

Load Capacitance, GS

Load Resistance, GS

Input Voltage, VF

Relative to ground

2.25 2.35

2.5

Load Resistance, VF

2000

Load Capacitance, VF

100

Output Resistance, VF

0 dBm0, 1020 Hz PCM code

applied to D

Partial powerdown FS

= 0 for

channel under test

3000

10000

Output Voltage, VF

Alternating

zero

-law PCM

code applied to D

2.25 2.35

2.5

Output Voltage, VF

O, Standby

RPD

[3:0] = 0.4 V, FSEP = active,

no load

2.15

2.4

2.65

Output Leakage Current, VF

O, Pow-

erdown

FSEP = 0.4 V

Output Voltage Swing, VF

SWR

RL = 2000

3.2

Vp-p

Lucent Technologies Inc.

Data Sheet
March 1999

T7504 and T5504 Quad PCM Codecs with Filters

Transmission Characteristics

(continued)

ac Transmission Characteristics

Unless otherwise noted, the analog input is a 0 dBm0, 1020 Hz sine wave; the input amplifier is set for unity gain.
The digital input is a PCM bit stream equivalent to that obtained by passing a 0 dBm0, 1020 Hz sine wave through
an ideal encoder. The output level is sin(x)/x-corrected.

Table 5. Absolute Gain

Table 6. Gain Tracking

Table 7. Distortion

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Encoder Milliwatt

Response (transmit gain toler-
ance)

EmW

Signal input of 0.775 Vrms,

-law or

A-law

0.25

dBm0

Decoder Milliwatt

Response (receive gain toler-
ance)

DmW

Measured relative to 0.775 Vrms

-law

or A-law,

PCM input of 0 dBm0 1020 Hz

RL = 10 k

0.25

dBm0

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Transmit Gain Tracking Error

Sinusoidal Input

-Law/A-Law

+3 dBm0 to 37 dBm0

37 dBm0 to 50 dBm0

0.25
0.50

--
--

0.25
0.50

dB
dB

Receive Gain Tracking Error

Sinusoidal Input

-Law/A-Law

+3 dBm0 to 37 dBm0

37 dBm0 to 50 dBm0

0.25
0.50

--
--

0.25
0.50

dB
dB

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Transmit Signal to Distortion

-law 3 dBm0

30 dBm0

A-law 3 dBm0

30 dBm0

36
35

--
--

dB
dB

-law 30 dBm0

40 dBm0

A-law 30 dBm0

40 dBm0

30
29

--
--

dB
dB

-law 40 dBm0

VFxI

45 dBm0

A-law 40 dBm0

VFxI

45 dBm0

25
25

--
--

dB
dB

Receive Signal to Distortion

-law 3 dBm0

30 dBm0

A-law 3 dBm0

30 dBm0

36
35

--
--

dB
dB

-law 30 dBm0

40 dBm0

A-law 30 dBm0

40 dBm0

30
29

--
--

dB
dB

-law 40 dBm0

45 dBm0

A-law 40 dBm0

45 dBm0

25
25

--
--

dB
dB

Single Frequency Distortion,

Transmit

SFD

200 Hz--3400 Hz, 0 dBm0 input,

output any other single

frequency

3400 Hz

dBm0

Single Frequency Distortion,

Receive

SFD

200 Hz--3400 Hz, 0 dBm0 input,

output any other single

frequency

3400 Hz

dBm0

Intermodulation Distortion

IMD

Transmit or receive, two frequencies

in the range (300 Hz--3400 Hz)

at 6 dBm0

dBm0

Lucent Technologies Inc.

Data Sheet

March 1999

T7504 and T5504 Quad PCM Codecs with Filters

Transmission Characteristics

(continued)

Table 8. Envelope Delay Distortion

* Varies as a function of time slots chosen.

Overload Compression

Figure 5 shows the region of operation for encoder signal levels above the reference input power (0 dBm0).

5-3586

Figure 5. Overload Compression

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Delay, Absolute*

f = 1600 Hz

175 to 425

Delay, Relative to 1600 Hz

f = 500 Hz--600 Hz
f = 600 Hz--800 Hz

f = 800 Hz--1000 Hz

f = 1000 Hz--1600 Hz
f = 1600 Hz--2600 Hz
f = 2600 Hz--2800 Hz
f = 2800 Hz--3000 Hz

--
--
--
--
--
--
--

220
145

75
40
75

105
155

Delay, Absolute*

f = 1600 Hz

150 to 405

Delay, Relative to 1600 Hz

f = 500 Hz--1000 Hz

f = 1000 Hz--1600 Hz
f = 1600 Hz--2600 Hz
f = 2600 Hz--2800 Hz
f = 2800 Hz--3000 Hz

40
30

--
--
--

--
--
--
--
--

--
--

125
175

Round Trip Delay, Absolute*

RTA

Any time slot/channel to

any time slot/channel

f = 1600 Hz

325 to 650

ACCEPTABLE
REGION

FUNDAMENTAL INPUT POWER (dBm)

FUNDAMENTAL OUTPUT POWER (dBm)

Lucent Technologies Inc.

Data Sheet
March 1999

T7504 and T5504 Quad PCM Codecs with Filters

Transmission Characteristics

(continued)

Table 9. Noise

Table 10. Receive Gain Relative to Gain at 1.02 kHz

Table 11. Transmit Gain Relative to Gain at 1.02 kHz

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Transmit Noise

-Law

dBrnC0

Input amplifier gain = 20 dB

dBrnC0

Transmit Noise

A-Law

dBm0p

Receive Noise

-Law

PCM code is alternating positive

and negative zero

dBrnC0

Receive Noise

A-Law

PCM code is A-law positive one

dBm0p

Noise, Single Frequency

f = 0 kHz--100 kHz

IN = 0 Vrms, measurement at

O, D

= D

dBm0

Power Supply Rejection Transmit

PSR

= 5.0 Vdc + 100 mVrms:

f = 0 kHz--4 kHz

f = 4 kHz--50 kHz

36
30

--
--

dB
dB

Power Supply Rejection Receive

PSR

PCM code is positive one LSB

= 5.0 Vdc + 100 mVrms:

f = 0 kHz--4 kHz

f = 4 kHz--25 kHz

f = 25 kHz--50 kHz

36
40
30

--
--
--

dB
dB
dB

Spurious Out-of-Band Signals at

O Relative to Input

SOS

0 dBm0, 300 Hz--3400 Hz input

PCM code applied:
4600 Hz--7600 Hz
7600 Hz--8400 Hz

8400 Hz--50 kHz

--
--
--

30
40
30

dB
dB
dB

Frequency (Hz)

Min

Typ

Max

Unit

Below 3000

0.150

0.04

0.150

3140 0.570

0.04

0.150

3380 0.885

0.58

0.010

3860 --

10.7

9.4

4600 and above

Frequency (Hz)

Min

Typ

Max

Unit

16.67

200

1.8

0.5

300 to 3000

0.150

0.04

0.150

3140

0.570

0.04

0.150

3380

0.885

0.58

0.010

3860

10.7

9.4

4600 and above

Lucent Technologies Inc.

Data Sheet

March 1999

T7504 and T5504 Quad PCM Codecs with Filters

Transmission Characteristics

(continued)

Table 12. Interchannel Crosstalk (Between Channels) R

200 k

(See note below.)

Table 13. Intrachannel Crosstalk (Within Channels) R

200 k

(See Note below.)

Note: For Tables 11 and 12, crosstalk into the transmit channels (VF

IN) can be significantly affected by parasitic

capacitive feeds from GS

and VF

O outputs. PWB layouts should be arranged to keep these parasitics

low. The resistor value of R

(from GS

to VF

IN) should also be kept as low as possible (while maintaining

the load on GS

above 10 k

per Table 4) to minimize crosstalk.

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Transmit to Receive

Crosstalk 0 dBm0
Transmit Levels

XX-RY

f = 300 Hz--3400 Hz

idle PCM code for channel under test;

0 dBm0 into any other single channel VF

Receive to Transmit

Crosstalk 0 dBm0
Receive Levels

RX-XY

f = 300 Hz--3400 Hz

IN = 0 Vrms for channel under test;

0 dBm0 code level on any other single channel D

Transmit to Trans-

mit Crosstalk
0 dBm0 Transmit
Levels

XX-XY

f = 300 Hz--3400 Hz

0 dBm0 applied to any single channel

IN except channel under test,

which has VF

IN = 0 Vrms

Receive to Receive

Crosstalk 0 dBm0
Receive Levels

RX-RY

f = 300 Hz--3400 Hz

0 dBm0 code level on any single channel D

except

channel under test, which has idle code applied

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Transmit to Receive

Crosstalk 0 dBm0
Transmit Levels

XX-RX

f = 300 Hz--3400 Hz

idle PCM code for channel under test;

0 dBm0 into VF

Receive to Transmit

Crosstalk 0 dBm0
Receive Levels

RX-XX

f = 300 Hz--3400 Hz

IN = 0 Vrms for channel under test;

0 dBm0 code level on D

Lucent Technologies Inc.

Data Sheet
March 1999

T7504 and T5504 Quad PCM Codecs with Filters

Timing Characteristics

Table 14. Clock Section (See Figures 6, 7, 8, and 9.)

Table 15. T7504 Transmit Section (See Figure 6.)

* Timing parameter tMCLDZ is referenced to a high-impedance state.

Table 16. T5504 Transmit Section (See Figure 8.)

* Timing parameter tMCHDZ is referenced to a high-impedance state.

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

tMCHMCL1

Clock Pulse Width

tCDC

Duty Cycle, MC

tMCH1MCH2

tMCL2MCL1

Clock Rise and

Fall Time

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

tMCHDV

Data Enabled on TS Entry

0 < C

LOAD

< 100 pF

tMCHDV1

Data Delay from MC

0 < C

LOAD

< 100 pF

tMCLDZ*

Data Float on TS Exit

LOAD

= 0

100

tFSHMCL

Frame-sync Hold Time

tMCLFSH

Frame-sync High Setup

tFSLMCL

Frame-sync Low Setup

tFSHFSL

Frame-sync Pulse Width

0.1

125 tMCHMCH

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

tFSHDV

Data Enabled on TS Entry

0 < C

LOAD

< 100 pF

tMCHDV1

Data Delay from FS

0 < C

LOAD

< 100 pF

tMCHDZ*

Data Float on TS Exit

LOAD

= 0

tFSHMCL

Frame-sync Hold Time

tMCLFSH

Frame-sync High Setup

tFSLMCL

Frame-sync Low Setup

tFSHFSL

Frame-sync Pulse Width

0.1

125 tMCHMCH

Lucent Technologies Inc.

Data Sheet

March 1999

T7504 and T5504 Quad PCM Codecs with Filters

Timing Characteristics

(continued)

Table 17. T7504 and T5504 Receive Section (See Figures 6, 7, 8, and 9.)

5-3581

Figure 6. T7504 Transmit and Receive Timing, FSEP = 1 MCLK

5-3582

Figure 7. T7504 Receive Timing, FSEP > 1 MCLK

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

tDVMCL

Receive Data Setup

tMCLDV

Receive Data Hold

tSPHMCL

Frame Separation Hold Time

tMCLSPH

Frame Separation High Setup

tSPLMCL

Frame Separation Low Setup

MCLK

FSx

FSEP

TIME SLOT

tFSLMCL

tMCH1MCH2

tFSLMCL

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

tMCHDV

tMCLDZ

tDVMCL

BIT

tMCLDV

STABLE

tMCHMCL1

tMCHDV1

tMCL2MCL1

FSHFSL

tMCLSPH

tFSHMCL

tMCLFSH

MCLK

FSEP

tDVMCL

BIT

tMCLDV

STABLE

TIME SLOT

tFSLMCL

tMCHMCL1

tSPLMCL

tSPHMCL

tFSHMCL

Lucent Technologies Inc.

Data Sheet
March 1999

T7504 and T5504 Quad PCM Codecs with Filters

Timing Characteristics

(continued)

5-3581.a

Figure 8. T5504 Transmit and Receive Timing, FSEP = 1 MCLK

5-3582.a

Figure 9. T5504 Receive Timing, FSEP > 1 MCLK

MCLK

FSx

FSEP

tFSHMCL

TIME SLOT

tFSLMCL

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

tFSHDV

tMCHDZ

tDVMCL

BIT

tMCLDV

STABLE

tMCHMCL1

tMCHDV1

tMCL2MCL1

tMCH1MCH2

tFSLMCL

FSHFSL

tMCLFSH

tMCLSPH

MCLK

FSEP

tDVMCL

tMCLDV

STABLE

TIME SLOT

tFSLMCL

tMCHMCL1

tSPLMCL

tSPHMCL

tFSHMCL

BIT

Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.

March 1999
DS99-201ALC (Replaces DS99-184ALC)

For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET: http://www.lucent.com/micro
E-MAIL: docmaster@micro.lucent.com
N. AMERICA:

Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256

Tel. (65) 778 8833, FAX (65) 777 7495

CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai

200233 P. R. China

Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652

JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan

Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700

EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148

Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),

FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: T7504

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: T7504