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Preliminary Data Sheet

October 2000

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

Features

The T7630 Dual T1/E1 Terminator consists of two
independent, highly integrated, software-config-
urable, full-featured short-haul transceiver/framers.
The T7630 provides glueless interconnection from a
T1/E1 line to a digital PCM system. Minimal external
clocks are needed. Only a system clock/frame sync
and a phase-locked line rate clock are required. Sys-
tem diagnostic and performance monitoring capabil-
ity with integrated programmable test pattern
generator/detector and loopback modes is provided.

Power Requirements and Package

Single 5 V ± 5% supply.

Low power: 375 mW per channel maximum.

144-pin TQFP package.

Operating temperature range: 40 °C to +85 °C.

T1/E1 Line Interface Features

Full T1/E1 pulse template compliance.

Receiver provides equalization for up to 11 dB of
loss.

Digital clock and data recovery.

Line coding: B8ZS, HDB3, ZCS, and AMI.

Line interface coupling and matching networks for
T1 and E1 (120

and 75

T1/E1 Framer Features

Supports T1 framing modes ESF, D4,

SLC

-96,

T1DM DDS.

Supports G.704 basic and CRC-4 multiframe for-
mat E1 framing and procedures consistent with
G.706.

Supports unframed transmission format.

T1 signaling modes: transparent; ESF 2-state,
4-state, and 16-state; D4 2-state and 4-state;

SLC

-96 2-state, 4-state, 9-state and 16-state. E1

signaling modes: transparent and CAS.

Alarm reporting and performance monitoring per
AT&T,

ANSI

*, and ITU-T standards.

Programmable, independent transmit and receive
system interfaces at a 2.048 MHz, 4.096 MHz, or
8.192 MHz data rate.

System interface master mode for generation of
system frame sync from the line source.

Internal phase-locked loop (with external VCXO)
for generation of system clock from the line source.

Facility Data Link Features

HDLC or transparent modes.

Automatic transmission and detection of

ANSI

T1.403 FDL performance report message and bit-
oriented codes.

64-byte FIFO in both transmit and receive direc-
tions.

Microprocessor Interface

33 MHz, 8-bit data interface, no wait-states.

Intel

Motorola

interface modes with multi-

plexed or demultiplexed buses.

Directly addressable control registers.

Applications

Customer Premises Equipment--CSU/DSU,
routers, digital PBX, channel banks (CB), base
transceiver stations (BTS-picocell), small switches,
and digital subscriber loop access multiplexers
(DSLAM).

Loop/Access--DLC/IDLC, DCS, BTS (microcell/
macrocell), DSLAMs, and multiplexers (terminal,
synchronous/asynchronous, add drop).

Central Office--Digital switches, DCS, CB,
access concentrators, remote switch modules
(RSM), and DSLAMs.

Test Equipment--Transmission/BERT tester.

ANSI

is a registered trademark of American National Standards

Institute, Inc.

Intel

is a registered trademark of Intel Corporation.

Motorola

is a registered trademark of Motorola, Inc.

Table of Contents

Contents

Page

Preliminary Data Sheet

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

October 2000

Lucent Technologies Inc.

Features ................................................................................................................................................................... 1

T1/E1 Line Interface Features............................................................................................................................... 1
Power Requirements and Package....................................................................................................................... 1
T1/E1 Framer Features ......................................................................................................................................... 1
Facility Data Link Features.................................................................................................................................... 1
Microprocessor Interface....................................................................................................................................... 1
Applications ........................................................................................................................................................... 1

Feature Descriptions .............................................................................................................................................. 12

Functional Description ............................................................................................................................................ 14
Pin Information ....................................................................................................................................................... 18
Line Interface Unit: Block Diagram ......................................................................................................................... 25
Line Interface Unit: Receive ................................................................................................................................... 25

Data Recovery..................................................................................................................................................... 25
Jitter Accommodation and Jitter Transfer Without the Jitter Attenuator .............................................................. 26
Receive Line Interface Configuration Modes ...................................................................................................... 26

Line Interface Unit: Transmit .................................................................................................................................. 32

Output Pulse Generation..................................................................................................................................... 32
LIU Transmitter Configuration Modes ................................................................................................................. 33
LIU Transmitter Alarms ....................................................................................................................................... 33
DSX-1 Transmitter Pulse Template and Specifications ...................................................................................... 34
CEPT Transmitter Pulse Template and Specifications ....................................................................................... 36

Line Interface Unit: Jitter Attenuator ....................................................................................................................... 37

Generated (Intrinsic) Jitter................................................................................................................................... 37
Jitter Transfer Function ....................................................................................................................................... 37
Jitter Accommodation.......................................................................................................................................... 38
Jitter Attenuator Enable (Transmit or Receive Path)........................................................................................... 38

Line Interface Unit: Loopbacks ............................................................................................................................... 41

Full Local Loopback (FLLOOP)........................................................................................................................... 41
Remote Loopback (RLOOP) ............................................................................................................................... 41
Digital Local Loopback (DLLOOP) ...................................................................................................................... 41

Line Interface Unit: Other Features ........................................................................................................................ 41

LIU Powerdown (PWRDN) .................................................................................................................................. 41
Loss of Framer Receive Line Clock (LOFRMRLCK Pin)..................................................................................... 41
In-Circuit Testing and Driver High-Impedance State (3-STATE)......................................................................... 41
LIU Delay Values................................................................................................................................................. 42

SYSCK Reference Clock........................................................................................................................................ 42
Line Interface Unit: Line Interface Networks........................................................................................................... 43
LIU-Framer Interface .............................................................................................................................................. 46

LIU-Framer Physical Interface............................................................................................................................. 46
Interface Mode and Line Encoding...................................................................................................................... 47
DS1: Alternate Mark Inversion (AMI)................................................................................................................... 48
DS1: Zero Code Suppression (ZCS)................................................................................................................... 48
CEPT: High-Density Bipolar of Order 3 (HDB3).................................................................................................. 49

Frame Formats ....................................................................................................................................................... 49

T1 Framing Structures......................................................................................................................................... 49

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

Table of Contents

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Contents

Page

T1 Loss of Frame Alignment (LFA)......................................................................................................................57
T1 Frame Recovery Alignment Algorithms ..........................................................................................................58
T1 Robbed-Bit Signaling ..................................................................................................................................... 59
CEPT 2.048 Basic Frame, CRC-4 Time Slot 0, and Signaling Time Slot 16 Multiframe Structures ....................61
CEPT 2.048 Basic Frame Structure.....................................................................................................................62
CEPT Loss of Basic Frame Alignment (LFA).......................................................................................................63
CEPT Loss of Frame Alignment Recovery Algorithm ..........................................................................................63
CEPT Time Slot 0 CRC-4 Multiframe Structure ...................................................................................................64
CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA) ....................................................................................65
CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms ......................................................................66
CEPT Time Slot 16 Multiframe Structure.............................................................................................................70
CEPT Loss of Time Slot 16 Multiframe Alignment (LTS16MFA) .........................................................................71
CEPT Loss of Time Slot 16 Multiframe Alignment Recovery Algorithm ..............................................................71

CEPT Time Slot 0 FAS/NOT FAS Control Bits ......................................................................................................71

FAS/NOT FAS Si- and E-Bit Source....................................................................................................................71
NOT FAS A-Bit (CEPT Remote Frame Alarm) Sources ......................................................................................72
NOT FAS Sa-Bit Sources ....................................................................................................................................72
Sa Facility Data Link Access................................................................................................................................73
NOT FAS Sa Stack Source and Destination........................................................................................................74
CEPT Time Slot 16 X0--X2 Control Bits .............................................................................................................76

Signaling Access.....................................................................................................................................................76

Transparent Signaling..........................................................................................................................................76
DS1: Robbed-Bit Signaling ..................................................................................................................................76

CEPT: Time Slot 16 Signaling.................................................................................................................................77
Auxiliary Framer I/O Timing ....................................................................................................................................78
Alarms and Performance Monitoring.......................................................................................................................81

Interrupt Generation.............................................................................................................................................81
Alarm Definition....................................................................................................................................................81
Event Counters Definition ....................................................................................................................................86
Loopback and Transmission Modes ....................................................................................................................88
Line Test Patterns................................................................................................................................................91
Automatic and On-Demand Commands ..............................................................................................................95
Receive Facility Data Link Interface.....................................................................................................................97
Transmit Facility Data Link Interface..................................................................................................................103
HDLC Operation ................................................................................................................................................104
Transparent Mode..............................................................................................................................................107
Diagnostic Modes ..............................................................................................................................................108

Phase-Lock Loop Circuit .......................................................................................................................................110
Framer-System (CHI) Interface .............................................................................................................................112

DS1 Modes ........................................................................................................................................................112
CEPT Modes......................................................................................................................................................112
Receive Elastic Store .........................................................................................................................................112
Transmit Elastic Store ........................................................................................................................................112

Concentration Highway Interface ..........................................................................................................................112

CHI Parameters .................................................................................................................................................113
CHI Frame Timing..............................................................................................................................................115
CHI Offset Programming....................................................................................................................................118

JTAG Boundary-Scan Specification ......................................................................................................................120

Principle of the Boundary Scan..........................................................................................................................120

Contents

Page

Preliminary Data Sheet

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

October 2000

Lucent Technologies Inc.

Table of Contents

(continued)

Test Access Port Controller............................................................................................................................... 121
Instruction Register ........................................................................................................................................... 123
Boundary-Scan Register ................................................................................................................................... 124
BYPASS Register.............................................................................................................................................. 124
IDCODE Register .............................................................................................................................................. 124
3-State Procedures ........................................................................................................................................... 124

Microprocessor Interface ...................................................................................................................................... 125

Overview ........................................................................................................................................................... 125
Microprocessor Configuration Modes................................................................................................................ 125
Microprocessor Interface Pinout Definitions...................................................................................................... 126
Microprocessor Clock (MPCLK) Specifications................................................................................................. 127
Microprocessor Interface Register Address Map .............................................................................................. 127
I/O Timing.......................................................................................................................................................... 127

Reset .................................................................................................................................................................... 134

Hardware Reset (Pin 43/139)............................................................................................................................ 134
Software Reset/Software Restart ...................................................................................................................... 134

Register Architecture ............................................................................................................................................ 135
Global Register Architecture................................................................................................................................. 139
Global Register Structure ..................................................................................................................................... 140

Primary Block Interrupt Status Register (GREG0) ............................................................................................ 140
Primary Block Interrupt Enable Register (GREG1) ........................................................................................... 140
Global Loopback Control Register (GREG2) .................................................................................................... 141
Global Loopback Control Register (GREG3) .................................................................................................... 141
Global Control Register (GREG4) ..................................................................................................................... 142
Device ID and Version Registers (GREG5--GREG7) ...................................................................................... 142

Line Interface Unit (LIU) Register Architecture..................................................................................................... 143
Line Interface Alarm Register ............................................................................................................................... 144

Alarm Status Register (LIU_REG0)................................................................................................................... 144

Line Interface Alarm Interrupt Enable Register .................................................................................................... 144

Alarm Interrupt Enable Register (LIU_REG1) ................................................................................................... 144

Line Interface Control Registers ........................................................................................................................... 145

LIU Control Register (LIU_REG2) ..................................................................................................................... 145
LIU Control Register (LIU_REG3) ..................................................................................................................... 145
LIU Control Register (LIU_REG4) ..................................................................................................................... 146
LIU Configuration Register (LIU_REG5) ........................................................................................................... 147
LIU Configuration Register (LIU_REG6) ........................................................................................................... 147

Framer Register Architecture ............................................................................................................................... 148

Framer Status/Counter Registers...................................................................................................................... 149

FDL Register Architecture .................................................................................................................................... 190
FDL Parameter/Control Registers (800--80E; E00--E0E) .................................................................................. 191
Register Maps ...................................................................................................................................................... 198

Global Registers................................................................................................................................................ 198
Line Interface Unit Parameter/Control and Status Registers ............................................................................ 198
Framer Parameter/Control Registers (Read-Write)........................................................................................... 199
Receive Framer Signaling Registers (Read-Only) ............................................................................................ 201
Framer Unit Parameter Register Map .............................................................................................................. 202
Transmit Signaling Registers (Read/Write) ....................................................................................................... 205
Facility Data Link Parameter/Control and Status Registers (Read-Write)........................................................ 206

Absolute Maximum Ratings................................................................................................................................. 207

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

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Page

Operating Conditions ........................................................................................................................................... 207
Handling Precautions ............................................................................................................................................207
Electrical Characteristics .......................................................................................................................................208

Logic Interface Characteristics...........................................................................................................................208

Power Supply Bypassing ......................................................................................................................................208
Outline Diagram ....................................................................................................................................................209

144-Pin TQFP ....................................................................................................................................................209

Ordering Information .............................................................................................................................................210

Figures

Page

Figure 1. T7630 Block Diagram (One of Two Channels) .........................................................................................14
Figure 2. T7630 Block Diagram: Receive Section (One of Two Channels) .............................................................16
Figure 3. T7630 Block Diagram: Transmit Section (One of Two Channels).............................................................17
Figure 4. Pin Assignment ........................................................................................................................................18
Figure 5. Block Diagram of Line Interface Unit: Single Channel .............................................................................25
Figure 6. T1/DS1 Receiver Jitter Accommodation Without Jitter Attenuator...........................................................30
Figure 7. T1/DS1 Receiver Jitter Transfer Without Jitter Attenuator........................................................................30
Figure 8. CEPT/E1 Receiver Jitter Accommodation Without Jitter Attenuator ........................................................31
Figure 9. CEPT/E1 Receiver Jitter Transfer Without Jitter Attenuator .....................................................................31
Figure 10. DSX-1 Isolated Pulse Template .............................................................................................................34
Figure 11. ITU-T G.703 Pulse Template..................................................................................................................36
Figure 12. T1/DS1 Receiver Jitter Accommodation with Jitter Attenuator ..............................................................39
Figure 13. T1/DS1 Jitter Transfer of the Jitter Attenuator ........................................................................................39
Figure 14. CEPT/E1 Receiver Jitter Accommodation with Jitter Attenuator............................................................40
Figure 15. CEPT/E1 Jitter Transfer of the Jitter Attenuator .....................................................................................40
Figure 16. Line Termination Circuitry ......................................................................................................................43
Figure 17. T7630 Line Interface Unit Approximate Equivalent Analog I/O Circuits .................................................45
Figure 18. Block Diagram of Framer Line Interface.................................................................................................46
Figure 19. Transmit Framer TLCK to TND, TPD and Receive Framer RND, RPD to RLCK Timing ........................47
Figure 20. T1 Frame Structure ................................................................................................................................50
Figure 21. T1 Transparent Frame Structure ............................................................................................................51
Figure 22. T7630 Facility Data Link Access Timing of the Transmit and Receive Framer Sections ........................53
Figure 23. Fs Pattern

SLC

-96 Superframe Format .................................................................................................53

Figure 24. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated Signaling Multiframe

Structures .............................................................................................................................................................61

Figure 25. CEPT Transparent Frame Structure.......................................................................................................62
Figure 26. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer ...................................67
Figure 27. Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4

Equipment Interworking as Defined by ITU (From ITU Rec. G.706, Annex B.2.2 - 1991) ....................................69

Figure 28. Facility Data Link Access Timing of the Transmit and Receive Framer Sections in the CEPT Mode.....73
Figure 29. Transmit and Receive Sa Stack Accessing Protocol..............................................................................75
Figure 30. Timing Specification for RFRMCK, RFRMDATA, and RFS in DS1 Mode...............................................78
Figure 31. Timing Specification for TFS, TLCK, and TPD in DS1 Mode .................................................................78
Figure 32. Timing Specification for RFRMCK, RFRMDATA, and RFS in CEPT Mode ............................................79
Figure 33. Timing Specification for RFRMCK, RFRMDATA, RFS, and RSSFS in CEPT Mode ..............................79
Figure 34. Timing Specification for RCRCMFS in CEPT Mode ..............................................................................80
Figure 35. Timing Specification for TFS, TLCK, and TPD in CEPT Mode ..............................................................80
Figure 36. Timing Specification for TFS, TLCK, TPD, and TSSFS in CEPT Mode .................................................80
Figure 37. Timing Specification for TFS, TLCK, TPD, and TCRCMFS in CEPT Mode ...........................................81

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Figures

Page

Preliminary Data Sheet

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

October 2000

Lucent Technologies Inc.

Figure 38. Relation Between RLCK1 and Interrupt (Pin 99)................................................................................... 81
Figure 39. Timing for Generation of LOPLLCK (Pin 39/143) .................................................................................. 83
Figure 40. The T and V Reference Points for a Typical CEPT E1 Application........................................................ 85
Figure 41. Loopback and Test Transmission Modes............................................................................................... 90
Figure 42. 20-Stage Shift Register Used to Generate the Quasi-Random Signal.................................................. 91
Figure 43. 15-Stage Shift Register Used to Generate the Pseudorandom Signal ................................................. 92
Figure 44. T7630 Facility Data Link Access Timing of the Transmit and Receive Framer Sections ....................... 97
Figure 45. Block Diagram for the Receive Facility Data Link Interface ................................................................... 98
Figure 46. Block Diagram for the Transmit Facility Data Link Interface................................................................. 103
Figure 47. Local Loopback Mode ......................................................................................................................... 109
Figure 48. Remote Loopback Mode ..................................................................................................................... 109
Figure 49. T7630 Phase Detector Circuitry .......................................................................................................... 111
Figure 50. Nominal Concentration Highway Interface Timing (for FRM_PR43 bit 0--bit 2 = 100 (Binary)) ......... 115
Figure 51. CHIDTS Mode Concentration Highway Interface Timing .................................................................... 116
Figure 52. Associated Signaling Mode Concentration Highway Interface Timing ................................................ 117
Figure 53. CHI Timing with ASM and CHIDTS Enabled....................................................................................... 117
Figure 54. TCHIDATA and RCHIDATA to CHICK Relationship with CMS = 0

(CEX = 3 and CER = 4, Respectively) ............................................................................................................... 118

Figure 55. Receive CHI (RCHIDATA) Timing ........................................................................................................ 119
Figure 56. Transmit CHI (TCHIDATA) Timing........................................................................................................ 119
Figure 57. Block Diagram of the T7630's Boundary-Scan Test Logic .................................................................. 120
Figure 58. BS TAP Controller State Diagram........................................................................................................ 121
Figure 59. Mode 1--Read Cycle Timing (MPMODE = 0, MPMUX = 0) ............................................................... 130
Figure 60. Mode 1--Write Cycle Timing (MPMODE = 0, MPMUX = 0) ............................................................... 130
Figure 61. Mode 2--Read Cycle Timing (MPMODE = 0, MPMUX = 1) ............................................................... 131
Figure 62. Mode 2--Write Cycle Timing (MPMODE = 0, MPMUX = 1) ............................................................... 131
Figure 63. Mode 3--Read Cycle Timing (MPMODE = 1, MPMUX = 0) ............................................................... 132
Figure 64. Mode 3--Write Cycle Timing (MPMODE = 1, MPMUX = 0) ............................................................... 132
Figure 65. Mode 4--Read Cycle Timing (MPMODE = 1, MPMUX = 1) ............................................................... 133
Figure 66. Mode 4--Write Cycle Timing (MPMODE = 1, MPMUX = 1) ............................................................... 133

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

Table of Contents

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Table

Page

Table 1. Pin Descriptions-Channel 1 and Channel 2..............................................................................................19
Table 2. Pin Descriptions-Global ............................................................................................................................23
Table 3. Digital Loss of Signal Standard Select......................................................................................................27
Table 4. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes) ..................................27
Table 5. T1/DS1 LIU Receiver Specifications.........................................................................................................28
Table 6. CEPT LIU Receiver Specifications ...........................................................................................................29
Table 7. Transmit Line Interface Short-Haul Equalizer/Rate Control ......................................................................32
Table 8. DSX-1 Pulse Template Corner Points (from CB119, T1.102) ...................................................................35
Table 9. DS1 Transmitter Specifications .................................................................................................................35
Table 10. CEPT Transmitter Specifications ............................................................................................................37
Table 11. Loopback Control....................................................................................................................................41
Table 12. SYSCK (16x, CKSEL = 1) Timing Specifications....................................................................................42
Table 13. SYSCK (1x, CKSEL = 0) Timing Specifications......................................................................................42
Table 14. Termination Components by Application.................................................................................................44
Table 15. AMI Encoding .........................................................................................................................................48
Table 16. DS1 ZCS Encoding.................................................................................................................................48
Table 17. DS1 B8ZS Encoding ...............................................................................................................................49
Table 18. ITU HDB3 Coding ...................................................................................................................................49
Table 19. T-Carrier Hierarchy..................................................................................................................................49
Table 20. D4 Superframe Format ...........................................................................................................................52
Table 21. DDS Channel-24 Format ........................................................................................................................52
Table 22.

SLC

-96 Data Link Block Format .............................................................................................................54

Table 23.

SLC

-96 Line Switch Message Codes .....................................................................................................55

Table 24. Transmit and Receive

SLC

-96 Stack Structure.......................................................................................55

Table 25. Extended Superframe (ESF) Structure ...................................................................................................56
Table 26. T1 Loss of Frame Alignment Criteria ......................................................................................................57
Table 27. T1 Frame Alignment Procedures ............................................................................................................58
Table 28. Robbed-Bit Signaling Options.................................................................................................................59
Table 29.

SLC

-96 9-State Signaling Format ...........................................................................................................59

Table 30. 16-State Signaling Format ......................................................................................................................60
Table 31. Allocation of Bits 1 to 8 of the FAS Frame and the NOT FAS Frame ......................................................62
Table 32. ITU CRC-4 Multiframe Structure.............................................................................................................64
Table 33. ITU CEPT Time Slot 16 Channel Associated Signaling Multiframe Structure ........................................70
Table 34. Transmit and Receive Sa Stack Structure...............................................................................................74
Table 35. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames ...........................................77
Table 36. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels....................................77
Table 37. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT .....................................................77
Table 38. Red Alarm or Loss of Frame Alignment Conditions................................................................................82
Table 39. Remote Frame Alarm Conditions............................................................................................................82
Table 40. Alarm Indication Signal Conditions .........................................................................................................82
Table 41. Sa6 Bit Coding Recognized by the Receive Framer-Asynchronous Bit Stream .....................................84
Table 42. Sa6 Bit Coding Recognized by the Receive Framer-Synchronous Bit Stream .......................................85
Table 43. AUXP Synchronization and Clear Sychronization Process ....................................................................85
Table 44. Event Counters Definition .......................................................................................................................86
Table 45. Summary of the Deactivation of SSTSSLB and SSTSLLB Modes as a Function

of Activating the Primary Loopback Modes ..........................................................................................................89

Table 46. Register FRM_PR69 Test Patterns.........................................................................................................92
Table 47. Register FRM_PR70 Test Patterns.........................................................................................................93
Table 48. Automatic Enable Commands ................................................................................................................95
Table 49. On-Demand Commands .........................................................................................................................96

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Table

Page

Preliminary Data Sheet

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

October 2000

Lucent Technologies Inc.

Table 50. Receive

ANSI

Code ............................................................................................................................... 99

Table 51. Performance Report Message Structure................................................................................................ 99
Table 52. FDL Performance Report Message Field Definition............................................................................. 100
Table 53. Octet Contents and Definition .............................................................................................................. 100
Table 54. Receive Status of Frame Byte.............................................................................................................. 101
Table 55. HDLC Frame Format ............................................................................................................................ 104
Table 56. Receiver Operation in Transparent Mode............................................................................................. 108
Table 57. Summary of the T7630's Concentration Highway Interface Parameters .............................................. 113
Table 58. Programming Values for TOFF[2:0] and ROFF[2:0] when CMS = 0 .................................................... 118
Table 59. TAP Controller States in the Data Register Branch.............................................................................. 122
Table 60. TAP Controller States in the Instruction Register Branch..................................................................... 122
Table 61. T7630's Boundary-Scan Instructions ................................................................................................... 123
Table 62. IDCODE Register................................................................................................................................. 124
Table 63. Microprocessor Configuration Modes .................................................................................................. 125
Table 64. Mode [1--4] Microprocessor Pin Definitions ........................................................................................ 126
Table 65. Microprocessor Input Clock Specifications .......................................................................................... 127
Table 66. T7630 Register Address Map .............................................................................................................. 127
Table 67. Microprocessor Interface I/O Timing Specifications ............................................................................. 128
Table 68. Register Summary ............................................................................................................................... 135
Table 69. Global Register Set (0x000--0x008) ................................................................................................... 139
Table 70. Primary Block Interrupt Status Register (GREG0) (000) ..................................................................... 140
Table 71. Primary Block Interrupt Enable Register (GREG1) (001) .................................................................... 140
Table 72. Global Loopback Control Register (GREG2) (002) .............................................................................. 141
Table 73. Global Loopback Control Register (GREG3) (003) .............................................................................. 141
Table 74. Global Control Register (GREG4) (004) .............................................................................................. 142
Table 75. Device ID and Version Registers (GREG5--GREG7) (005--007) ...................................................... 142
Table 76. Line Interface Units Register Set* ((400--40F); (A00--A0F)).............................................................. 143
Table 77. LIU Alarm Status Register (LIU_REG0) (400, A00) ............................................................................. 144
Table 78. LIU Alarm Interrupt Enable Register (LIU_REG1) (401, A01) ............................................................. 144
Table 79. LIU Control Register (LIU_REG2) (402, A02) ...................................................................................... 145
Table 80. LIU Control Register (LIU_REG3) (403, A03) ...................................................................................... 145
Table 81. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes) (from Table 3) ...... 146
Table 82. LIU Register (LIU_REG4) (404, A04)................................................................................................... 146
Table 83. LIU Configuration Register (LIU_REG5) (405, A05) ............................................................................ 147
Table 84. Loopback Control ................................................................................................................................. 147
Table 85. LIU Configuration Register (LIU_REG6) (406, A06) ............................................................................ 147
Table 86. Transmit Line Interface Short-Haul Equalizer/Rate Control (from Table 6)........................................... 148
Table 87. Framer Status and Control Blocks Address Range (Hexadecimal)...................................................... 148
Table 88. Interrupt Status Register (FRM_SR0) (600; C00) ................................................................................ 149
Table 89. Facility Alarm Condition Register (FRM_SR1) (601; C01) ................................................................... 150
Table 90. Remote End Alarm Register (FRM_SR2) (602; C02) .......................................................................... 151
Table 91. Facility Errored Event Register-1 (FRM_SR3) (603; C03) ................................................................... 152
Table 92. Facility Event Register-2 (FRM_SR4) (604; C04) ................................................................................ 153
Table 93. Exchange Termination and Exchange Termination Remote

End Interface Status Register (FRM_SR5) (605; C05) ...................................................................................... 154

Table 94. Network Termination and Network Termination Remote

End Interface Status Register (FRM_SR6) (606; C06) ...................................................................................... 155

Table 95. Facility Event Register (FRM_SR7) (607; C07) ................................................................................... 156
Table 96. Bipolar Violation Counter Registers (FRM_SR8--FRM_SR9) ((608--609); (C08--C09)) .................. 156
Table 97. Framing Bit Error Counter Registers (FRM_SR10--FRM_SR11) ((60A--60B); (C0A--C0B)) ........... 156

Lucent Technologies Inc.

Preliminary Data Sheet
October 2000

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

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Table

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Table 98. CRC Error Counter Registers (FRM_SR12--FRM_SR13) ((60C--60D); (C0C--C0D))......................157
Table 99. E-Bit Counter Registers (FRM_SR14--FRM_SR15) ((60E--60F); (C0E--C0F))................................157
Table 100. CRC-4 Errors at NT1 from NT2 Counter Registers (FRM_SR16--FRM_SR17) ((610--611);

(C10--C11)) .......................................................................................................................................................157

Table 101. E Bit at NT1 from NT2 Counter (FRM_SR18--FRM_SR19) ((612--613); (C12--C13)) ...................157
Table 102. ET Errored Seconds Counter (FRM_SR20--FRM_SR21) ((614--615); (C14--C15)) ......................158
Table 103. ET Bursty Errored Seconds Counter (FRM_SR22--FRM_SR23) ((616--617); (C16--C17)) ...........158
Table 104. ET Severely Errored Seconds Counter (FRM_SR24--FRM_SR25) ((618--619); (C18--C19))........158
Table 105. ET Unavailable Seconds Counter (FRM_SR26--FRM_SR27) ((61A--61B); (C1A--C1B)) ..............158
Table 106. ET-RE Errored Seconds Counter (FRM_SR28--FRM_SR29) ((61C--61D); (C1C--C1D)) ..............158
Table 107. ET-RE Bursty Errored Seconds Counter (FRM_SR30--FRM_SR31) ((61E--61F); (C1E--C1F)) ....158
Table 108. ET-RE Severely Errored Seconds Counter (FRM_SR32--FRM_SR33) ((620--621); (C20--C21)) ..158
Table 109. ET-RE Unavailable Seconds Counter (FRM_SR34--FRM_SR35) ((622--623); (C22--C23)) ..........159
Table 110. NT1 Errored Seconds Counter (FRM_SR36--FRM_SR37) ((624--625); (C24--C25)) ....................159
Table 111. NT1 Bursty Errored Seconds Counter (FRM_SR38--FRM_SR39) ((626--627); (C26--C27)) .........159
Table 112. NT1 Severely Errored Seconds Counter (FRM_SR40--FRM_SR41) ((628--629); (C28--C29)) .....159
Table 113. NT1 Unavailable Seconds Counter (FRM_SR42--FRM_SR43) ((62A--62B); (C2A--C2B)) ............159
Table 114. NT1-RE Errored Seconds Counter (FRM_SR44--FRM_SR45) ((62C--62D); (C2C--C2D))............159
Table 115. NT1-RE Bursty Errored Seconds Counter (FRM_SR46--FRM_SR47) ((62E--62F); (C2E--C2F))..159
Table 116. NT1-RE Severely Errored Seconds Counter (FRM_SR48--FRM_SR49 ((630--631);

(C30--C31)) .......................................................................................................................................................160

Table 117. NT1-RE Unavailable Seconds Counter (FRM_SR50--FRM_SR51) ((632--633); (C32--C33)) .......160
Table 118. Receive NOT-FAS TS0 Register (FRM_SR52) (634; C34) .................................................................160
Table 119. Receive Sa Register (FRM_SR53) (635; C35) ...................................................................................160
Table 120.

SLC

-96 FDL Receive Stack (FRM_SR54--FRM_SR63) ((636--63F); (C36--C3F)) ........................161

Table 121. CEPT Sa Receive Stack (FRM_SR54--FRM_SR63) ((636--63F); (C36--C3F)) .............................161
Table 122. Transmit Framer

ANSI

Performance Report Message Status Register Structure ..............................162

Table 123. Received Signaling Registers: DS1 Format (FRM_RSR0--FRM_RSR23) ((640--658);

(C40--C58)) .......................................................................................................................................................162

Table 124. Receive Signaling Registers: CEPT Format (FRM_RSR0--FRM_RSR31) ((640--65F);

(C40--C5F)) .......................................................................................................................................................162

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: T7630

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: T7630