Preliminary Data Sheet

July 2001

T8533/34 Quad Programmable Line Card
Signal Processor

Features

Includes codec, termination impedance, and echo
canceller in one device for line card applications

Programmable

-law, linear, or A-law PCM input

and output (ITU-T G.712 compliant)

Per-channel programmable gains

Per-channel programmable internal termination
impedance

Per-channel 64-tap echo canceller (ITU-T G.168
compliant)

Fully programmable time-slot assignment

Analog and digital loopback test modes

Serial microprocessor interface

Sigma-delta converters with dither to reduce noise

Six per-channel, bidirectional control pins for SLIC
and line card function control (68-pin package)

Quad design to minimize package count on dense
line card applications

Built-in level correction (transmit equalization) to
accommodate current-sensing SLICs

Single 5 V operation

Available in 68-pin, 64-pin, and 44-pin packages

General Description

The quad programmable line card signal processor
consists of four independent channels of codec and
digital signal processing functions on one chip. In
addition to the classic A-to-D and D-to-A conversion,
the device includes termination impedance synthesis
and a 64-tap echo canceller, functionally, on a per-
channel basis. The device is capable of meeting all
international standards for terminating impedance
and digital encoding format. The processing circuitry
for the adjustment of the transmit level (equalization)
to accommodate current-sensing SLICs is also
included.

The device is controlled by a serial microprocessor
interface, and a set of bidirectional I/O pins are pro-
vided, on a per-channel basis, so that this control
mechanism can be utilized to operate the battery
feed device, ringing voltage switches, etc. Common
data and clock paths can be shared over any number
of devices. All the filter coefficients, signal process-
ing, SLIC, and test features are accessible through
this interface. This serial interface can be operated at
speeds up to 4.096 Mbits/s.

The PCM bus is also programmable, with any chan-
nel capable of being assigned to any time slot.
The PCM bus can be operated at speeds up to
16.384 Mbits/s, allowing for a maximum of 256 time
slots. Separate transmit and receive interfaces are
available for 4-wire bus designs, or they can be
strapped together for a 2-wire PCM bus.

The device is available in 68-pin, 64-pin, and 44-pin
surface-mount packages for economic use of board
space.

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Table of Contents

Contents

Page

Features ......................................................................1
General Description.....................................................1
Functional Description .................................................3
Pin Information ............................................................5
Functional Description ...............................................11

Clocking Considerations .........................................11
The Control Interface ..............................................11

Modes ..................................................................11
Protocol ................................................................12
Write Command ...................................................14
Read Command ...................................................16
Fast Scan Mode ...................................................20
Write All Channels................................................23

Reset Functionality .................................................23

Memory Control Mapping .....................................24

Standby Mode .........................................................24
Test Capabilities .....................................................24
Echo Canceller Functionality ..................................25
SLIC Control Capabilities ........................................25
Suggested Initialization Procedures........................25
Signal Processing ...................................................26

Absolute Maximum Ratings.......................................26
Operating Ranges ....................................................27
Handling Precautions ................................................27
Electrical Characteristics ...........................................27

dc Characteristics ...................................................27
Analog Interface ......................................................28
Transmission Characteristics ..................................29
Noise Characteristics ..............................................31
Distortion and Group Delay.....................................32
Crosstalk .................................................................33

Timing Characteristics ...............................................34
Bus Timing Diagrams ................................................36

Normal Mode ..........................................................36
Byte-by-Byte Mode .................................................36
PCM Interface .........................................................37

Applications ...............................................................44
Outline Diagrams.......................................................45

68-Pin PLCC ...........................................................45
64-Pin TQFP ...........................................................46
44-Pin PLCC ...........................................................47

Ordering Information..................................................48

Figures

Page

Figure 1. Functional Block Diagram, Each Section ....3
Figure 2. 44-Pin PLCC Pin Diagram........................... 5
Figure 3. 68-Pin PLCC Pin Diagram ...........................7
Figure 4. 64-Pin TQFP Pin Diagram ...........................9
Figure 5. Command Frame Format, Master to Slave,

Read or Write Commands .........................13

Figure 6. Command Frame Format, Slave to Master,

Read Commands ......................................13

Figure 7. Write Operation, Normal Mode

(Continuous DCLK) ...................................14

Figure 8. Write Operation, Normal Mode

(Gapped DCLK) .........................................14

Figure 9. Write Operation, Byte-by-Byte Mode

(Continuous DCLK) .................................. 15

Figure 10. Write Operation, Byte-by-Byte Mode

(Gapped DCLK) ...................................... 15

Figure 11. Read Operation, Normal Mode

(Continuous DCLK) ................................ 16

Figure 12. Read Operation, Normal Mode

(Gapped Clock) ...................................... 17

Figure 13. Read Operation, Byte-by-Byte Mode

(Continuous DCLK) ................................ 18

Figure 14. Read Operation, Byte-by-Byte Mode

(Gapped DCLK) ...................................... 19

Figure 15. Fast Scan, Normal Mode

(Continuous DCLK) ................................ 20

Figure 16. Fast Scan, Normal Mode

(Gapped DCLK) ...................................... 21

Figure 17. Fast Scan, Byte-by-Byte Mode

(Continuous DCLK) ................................ 22

Figure 18. Fast Scan, Byte-by-Byte Mode

(Gapped DCLK) ...................................... 22

Figure 19. Hardware Reset Procedure .................... 23
Figure 20. Internal Signal Processing ...................... 26
Figure 21. Serial Interface Timing, Normal Mode

(One Byte Transfer Shown) .................... 36

Figure 22. Serial Interface Timing, Byte-by-Byte

Mode (One Byte Transfer and Gapped
DCLK Shown) ......................................... 36

Figure 23. PCM Bus Timing (Diagram Shown has Bit

Offset of Zero and Minimum Width of
FS) .......................................................... 37

Figure 24. POTS Interface ....................................... 44

Tables

Page

Table 1. Pin Assignments, 44-Pin PLCC,

Per-Channel Functions ................................ 5

Table 2. Pin Assignments, 44-Pin PLCC,

Common Functions .................................... 6

Table 3. Pin Assignments, 68-Pin PLCC,

Per-Channel Functions ................................ 7

Table 4. Pin Assignments, 68-Pin PLCC,

Common Functions .................................... 8

Table 5. Pin Assignments, 64-Pin TQFP,

Per-Channel Functions ................................ 9

Table 6. Pin Assignments, 64-Pin TQFP,

Common Functions .................................. 10

Table 7. Bit Assignments for Fast Scan Mode ....... 20
Table 8. dc Characteristics ..................................... 27
Table 9. Analog Interface ....................................... 28
Table 10. Power Requirements .............................. 29
Table 11. Transmission Characteristics ................. 29
Table 12. Per-Channel Noise Characteristics ........ 31
Table 13. Distortion and Group Delay ..................... 32
Table 14. Crosstalk .................................................. 33
Table 15. Timing Characteristics ............................. 34
Table 16. Echo Canceller Characteristics ............... 35
Table 17. Memory Mapping ..................................... 38
Table 18. Control Bit Definition ................................ 39

Preliminary Data Sheet
July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Functional Description

Refer to Figure 1 for the following discussion. (It should be noted that much of the processing is performed in a dig-
ital processor; thus, the actual data flow may be different than this functional, analog analogy based diagram
shows.)

5-7172.ar5(F)

Figure 1. Functional Block Diagram, Each Section

RST

MCLK

SLIC

TO/FROM

ANALOG

GAIN

A/D

CONVERTER

ANALOG

BUFFER

D/A

CONVERTER

ANAL

PBA

GIT

PBA

GIT

PBA

TERMINATION

IMPEDANCE

ECHO

CancellER

DIGITAL GAIN

(GAIN TRANSFER)

-LAW

PER

CHANNEL

COMMON

GIT

PBA

GIT

PBA

PCM BUS

INTERFACE

TO/FROM
PCM BUS

POWER AND
GROUND

BCLK

SLIC

CONTROL LATCHES

MICROPROCESSOR CONTROL

CONTROL AND DATA SIGNALS

SERIAL

CONTROL

INTERFACE

PER

CHANNEL

COMMON

0 TO 6

FREQUENCY

SYNTHESIZER

FACTORY TEST

CONVERSION

A-LAW

DIGITAL GAIN

(GAIN TRANSFER)

INn

OPn

ONn

This device performs virtually all the signal processing
functions associated with a central office line termina-
tion. Functionality includes line termination impedance
synthesis, adaptive or fixed hybrid balance (echo can-
celler), and level conversion both in the analog sense
(transmit equalization), to accommodate various sub-
scriber line interface circuits (SLICs), and in the digital
sense, for adjustment of the levels on the PCM bus
(gain transfer). In general, the termination impedance
synthesis generates the equivalent of a circuit with the
parallel combination of a capacitor and a resistor in
series with a resistor or the parallel combination of a
resistor and the series combination of a resistor and
capacitor. These general forms of impedance charac-
teristic will satisfy most of the requirements specified

throughout the world. Programmable selection of either

-law or A-law encoding further aids worldwide deploy-

ment. In addition to the programmable features for
impedance and coding, the device also contains an
echo canceller that meets international requirements
for network echo cancellers. This includes the ability to
automatically disable the adaptation in the presence of
2100 Hz modem tones. All coefficients used in the fil-
tering algorithms can be computed off-line in advance
and downloaded to the device at the time of powerup.
All signal processing is contained within the device,
and there are only three interfaces of consequence to
the system designer: the SLIC interface, the PCM inter-
face, and the control interface.

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Functional Description

(continued)

The SLIC interface is designed to be flexible and con-
venient to use with a variety of SLIC circuits. With an
appropriate choice of SLIC, no external components
are required in the interface, with the exception of a dc
blocking capacitor in the transmit direction. In some
cases, dc blocking capacitors in the receive direction
may be necessary as well, since the device operates
from a single 5 V supply.

The PCM bus interface is flexible in that it allows, inde-
pendently, the transmit and receive data for any chan-
nel to be placed in any time slot. The bus can be
operated at a maximum of a 16.384 Mbits/s rate to
accommodate a maximum of 256 time slots. Separate
pins are provided for each direction of transmission to
allow 4-wire bus operation. The frame strobe signal is
an 8 kHz signal that defines the beginning of the frame
structure. The interface will count 8 bits per time slot
and insert or read the data for each channel as pro-
grammed. Lower speeds of the PCM bus are allowed.
The PCM clock must be synchronous with the master
clock for the device (if present) and with the frame
strobe signal.

The microprocessor control interface is a serial inter-
face that uses the classic chip select type of operation.
The interface controls the device by writing or reading
various internal addresses. The command set com-
prises simple read and write operations, with the
address determining the effect. All the memory loca-
tions, including the per-chip functions, are organized by
channel, allowing a straightforward migration path to
architectures other than quad.

There are several test modes included to facilitate
confirmation of correct operation. In the signal path,
both an analog and four digital loopback tests are avail-
able, while in the microprocessor interface, there is a
write/read test mode that tests the operation of the
memory. Use of external test access switches allows a
complete test of the signal path through the line card so
that correct operation of various operational modes can
be verified.

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Pin Information

(continued)

Table 2. Pin Assignments, 44-Pin PLCC, Common Functions

Pin

Name

Type

Name/Description

Serial Data Output. This is a 3-state output.

Serial Data Input.

DCLK

Serial Data Clock Input.

Chip Select Input. This pin determines the interval that the serial interface is
active.

INTS

Serial Interface Select. Leaving this pin open places the serial interface in
the normal mode; grounding it places the interface into the byte-by-byte
mode. This pin has an internal pull-up.

FILTV

PWR

Frequency Synthesizer Power (5 V). This pin must be tied to V

PVCOIN

Internal Test Point. Do not connect to this pin.

PVCO

Internal Test Point. Do not connect to this pin.

PLLT

Internal Test Point. Do not connect to this pin.

SGND

GND

Synthesizer Ground. Connect to DGND. A common AGND, DGND, SGND
plane is highly recommended.

16, 29, 38, 44

DGND

GND

Digital Ground. Logic ground and return for logic power supply. A common
AGND, DGND, SGND plane is highly recommended.

17, 28, 35, 42

PWR

Digital Power Supply (5 V).

PCM Frame Strobe Input. This 8 kHz clock must be derived from the same
source as BCLK. See the Clocking Considerations section.

BCLK

PCM Clock Input. This pin is used to develop internal clocks for certain clock
rates. See the Clocking Considerations section.

PCM Bus Output Pin. This is a 3-state output.

PCM Bus Input Pin.

RST

Power-On Reset. A low causes a reset of the entire chip. This pin may be
connected to DGND with a 0.1

F capacitor for a power-on reset function, or

it may be driven by external logic. This pin has an internal pull-up.

MCLK

1.024 MHz Master Clock Input. Internal timing is derived from this clock
input for certain PCM bus rates. See Clocking Considerations. When unused,
this pin may be left open. This pin has an internal pull-up.

Preliminary Data Sheet
July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Pin Information

(continued)

5-8194(F)

Figure 3. 68-Pin PLCC Pin Diagram

Table 3. Pin Assignments, 68-Pin PLCC, Per-Channel Functions

Ckt

Name

Type

Name/Description

21 34 35 48

AGND

GND Analog Ground. A common AGND, DGND, SGND plane is highly recom-

mended.

20 33 36 49

PWR 5 V Analog Power Supply.

19 32 37 50

Transmit Analog Input. For complex terminations, this node requires a 10 M

or 20 M

resistance to AGND.

18 31 38 51 VF

Receive Analog Output, Positive Polarity.

17 30 39 52 VF

Receive Analog Output, Negative Polarity.

16 29 41 53

SLIC0

I/O

SLIC Control Pin 0.

15 27 42 54

SLIC1

I/O

SLIC Control Pin 1.

26 43 61

SLIC2

I/O

SLIC Control Pin 2.

25 44 63

SLIC3

I/O

SLIC Control Pin 3.

23 46 64

SLIC4

I/O

SLIC Control Pin 4.

22 47 62

SLIC5

I/O

SLIC Control Pin 5.

4 3 2 1 68 67 66 6564

MCL

DCL

63 6261

SLI

NDc

41 42 43

SLI

NDb

SLIC0a

FILTV

SGND

SLIC5b

DGND

SLIC2b

OPa

24
25
26

SLIC1a

PVCOIN

PLLT

AGNDa

SLIC4b

SLIC3b

ONa

SLIC1d

DGND

AGNDd

SLIC4c

SLIC3c

ONd

46
45
44

OPd

BCLK

SLIC5c

DGND

SLIC0d

T8534

PVCO

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Pin Information

(continued)

Table 4. Pin Assignments, 68-Pin PLCC, Common Functions

Pin

Name

Type

Name/Description

Serial Data Output. This is a 3-state output.

Serial Data Input.

DCLK

Serial Data Clock Input.

Chip Select Input. This pin determines the interval that the serial interface is
active.

INTS

Serial Interface Select. Leaving this pin open places the serial interface in
the normal mode; grounding it places the interface into the byte-by-byte
mode. This pin has an internal pull-up.

FILTV

PWR

Frequency Synthesizer Power (5 V). This pin must be tied to V

PVCOIN

Internal Test Point. Do not connect to this pin.

PVCO

Internal Test Point. Do not connect to this pin.

PLLT

Internal Test Point. Do not connect to this pin.

SGND

GND

Synthesizer Ground. Connect to DGND. A common AGND, DGND, SGND
plane is highly recommended.

24, 45, 58, 68

DGND

GND

Digital Ground. Logic ground and return for logic power supply. A common
AGND, DGND, SGND plane is highly recommended.

28, 40, 55, 66

PWR

Digital Power Supply (5 V).

PCM Frame Strobe Input. This 8 kHz clock must be derived from the same
source as BCLK. See the Clocking Considerations section.

BCLK

PCM Clock Input. This pin is used to develop internal clocks for certain clock
rates. See the Clocking Considerations section.

59 DX

PCM Bus Output Pin. This is a 3-state output.

PCM Bus Input Pin.

RST

Power-On Reset. A low causes a reset of the entire chip. This pin may be
connected to DGND with a 0.1

F capacitor for a power-on reset function, or

it may be driven by external logic. This pin has an internal pull-up.

MCLK

1.024 MHz Master Clock Input. Internal timing is derived from this clock
input for certain PCM bus rates. See the Clocking Considerations section.
When unused, this pin may be left open. This pin has an internal pull-up.

Preliminary Data Sheet
July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Pin Information

(continued)

5-8196(F)

Figure 4. 64-Pin TQFP Pin Diagram

Table 5. Pin Assignments, 64-Pin TQFP, Per-Channel Functions

Ckt

Name

Type

Name/Description

12 24 25 37

AGND

GND Analog Ground. A common AGND, DGND, SGND plane is highly recom-

mended.

11 23 26 38

PWR 5 V Analog Power Supply.

10 22 27 39

Transmit Analog Input. For complex terminations, this node requires a 10 M

or 20 M

resistance to AGND.

21 28 40 VF

Receive Analog Output, Positive Polarity.

20 29 41 VF

Receive Analog Output, Negative Polarity.

19 31 42

SLIC0

I/O

SLIC Control Pin 0.

17 32 43

SLIC1

I/O

SLIC Control Pin 1.

64 16 33 50

SLIC2

I/O

SLIC Control Pin 2.

63 15 34 51

SLIC3

I/O

SLIC Control Pin 3.

62 13 36 52

SLIC4

I/O

SLIC Control Pin 4.

60 59 58 57 56 55 54 53 52

MCL

DCL

51 50 49

SLI

NDc

31 32

NDb

SLIC0a

FILTV

PVCO

SGND

DGND

SLIC2b

OPa

SLIC1a

PVCOIN

PLLT

AGNDa

SLIC4b

SLIC3b

ONa

SLIC1d

DGND

AGNDd

DGND

SLIC2c

ONd

OPd

BCLK

SLIC4c

SLIC3c

SLIC0d

T8534

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Pin Information

(continued)

Table 6. Pin Assignments, 64-Pin TQFP, Common Functions

Pin

Name

Type

Name/Description

FILTV

PWR

Frequency Synthesizer Power (5 V). This pin must be tied to V

PVCOIN

Internal Test Point. Do not connect to this pin.

PVCO

Internal Test Point. Do not connect to this pin.

PLLT

Internal Test Point. Do not connect to this pin.

SGND

GND

Synthesizer Ground. Connect to DGND. A common AGND, DGND, SGND
plane is highly recommended.

14, 35, 47, 56

DGND

GND

Digital Ground. Logic ground and return for logic power supply. A common
AGND, DGND, SGND plane is highly recommended.

18, 30, 44, 54

PWR

Digital Power Supply (5 V).

PCM Frame Strobe Input. This 8 kHz clock must be derived from the same
source as BCLK. See the Clocking Considerations section.

BCLK

PCM Clock Input. This pin is used to develop internal clocks for certain clock
rates. See the Clocking Considerations section.

PCM Bus Output Pin. This is a 3-state output.

PCM Bus Input Pin.

RST

Power-On Reset. A low causes a reset of the entire chip. This pin may be
connected to DGND with a 0.1

F capacitor for a power-on reset function, or

it may be driven by external logic. This pin has an internal pull-up.

MCLK

Serial Data Output. This is a 3-state output.

Serial Data Input.

DCLK

Serial Data Clock Input.

Chip Select Input. This pin determines the interval that the serial interface is
active.

INTS

Serial Interface Select. Leaving this pin open places the serial interface in
the normal mode; grounding it places the interface into the byte-by-byte
mode. This pin has an internal pull-up.

Agere Systems Inc.

Preliminary Data Sheet
July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Functional Description

Clocking Considerations

This device has several clock inputs for the various
interfaces. The PCM bus uses BCLK as the bit clock
and the one-going edge of FS to determine the location
of the beginning of a frame. These two clocks must be
derived from the same source. Internally, the device
develops all the internal clocks with a phase-locked
loop that uses BCLK as the timing source when BCLK
is 16.384, 8.192, 4.096, 2.048, or 1.024 MHz. In these
instances, MCLK is not used and may be left open
since any signal driving MCLK is ignored. For BCLK
rates of 256 kHz and 512 kHz, MCLK is used as a
source for the PLL and must be 1.024 MHz. In this lat-
ter case, BCLK, MCLK, and FS must be derived from
the same source and the rising edge of BCLK must be
within 10 ns of the rising edge of MCLK. BCLK, FS,
and MCLK (if required) must be continuously present
and without gaps in order for the device to operate cor-
rectly. Note that the nominal values in Table 15 are the
valid frequencies for BCLK.

DCLK is used to clock the internal serial interface and
may be asynchronous to the other clocks. There is no
need to derive this clock from the same source as the
other clocks. The serial bus may be operated at any
speed up to 4.096 Mbits/s. DCLK can be gapped, how-
ever additional clock cycles are required in and around
the command frame to process data, and during and
after a hardware or a software reset to ensure com-
plete clearing of internal logic. There is no limit on the
number of devices on the same serial bus.

The Control Interface

The device is controlled via a series of memory loca-
tions accessed by a serial data connection to the exter-
nal master controller. This interface operates using the
chip select lead to enable transmission of information.
All chip functions are enabled or disabled by setting or
clearing bits in the control memory. Filter coefficients
and gain adjustments are also stored in this memory.

The codec has both a serial input lead and a serial out-
put lead. These may be used individually for a 4-wire
serial interface, or tied together for a 2-wire interface.
The line driver circuitry is capable of driving relatively
high currents so that in the event that the line is long
enough to show significant transmission line effects, it
can be terminated in the characteristic impedance at
each end with resistors to V

and ground.

All data transfers on the serial bus are byte oriented
with the least significant bit (shown in this data sheet as
bit 0) transmitted first, followed by the more significant
bits. For data fields, the least significant byte of the first
data byte is transmitted first, followed by the more sig-
nificant bytes, each byte transmitted LSB first. This for-
mat is compatible with the serial port on most
microcontrollers.

Modes

There are two different modes of operation for the
serial interface, the normal mode and the byte-by-byte
mode. These two modes differ in the manner in which
CS is used to control the transfer. Note that the CS
lead is used to control the transfer of serial data from
master controller to slave codec and in the reverse
direction.

In normal mode, (INTS pin open) the CS lead must go
low for the duration of the transfer. The only error check
performed by the codec is to verify that CS is low for an
integral number of bytes. Detection of an active (active-
low) chip select for other than an integral multiple of 8
bits results in the operation being terminated. The next
active excursion of chip select will be interpreted as a
new command; hence, the serial I/O interface can
always be initialized by asserting CS for a number of
clock periods that is not an integral multiple of 8. CS is
captured using DCLK, so DCLK must be transitioned to
perform this initialization. Undefined command codes
are reserved for future use and may cause unwanted
operation of the device.

The byte-by-byte mode (INTS pin tied to ground) uses
CS to control each byte of the transfer. In this mode,
CS goes low for exactly 8 bits at a time, corresponding
to a 1-byte transfer either to or from the codec chip.
Repeated transitions of CS are used to control subse-
quent bytes of data to/from the codec. For a write com-
mand in this mode, CS must go low for each byte of the
transfer until the transfer is complete. For a read com-
mand, CS will go low for each of the 3 bytes of the read
command transferred to the device, then low again for
each byte to be read. Notice that the total number of
bytes transferred (and excursions on CS) is N + 3,
where N is the number of bytes to be read in the com-
mand. This mode of operation is useful in cases where
the master is a microprocessor with a built-in UART
that transfers 1 byte at a time. Error detection is limited
to detection of an active CS for other than an integral
multiple of 8 bits. Recovery is the same as normal
mode. Note that the clock phase is shifted in this mode.

Flow control can be accomplished by suspending the
transitions on DCLK by holding either state. During the
data transfer, CS must remain low while clock transi-
tions are suspended with DCLK in either state.

Agere Systems Inc.

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Functional Description

(continued)

The Control Interface

(continued)

Protocol

The format of the command protocol is shown in Fig-
ures 5 and 6.

The control interface operates with one external master
controller and multiple slave codec devices. Each
transfer is initiated by the master, and the slave
responds for either read operations or the fast scan
mode. The slave does not check the bus for activity
prior to transmitting; it only checks for an active CS.
The master should allow for a wait between the end of
a read command until CS becomes active for the read
data. The master must refrain from sending additional
commands to the slave chip until the response is
received. On a 4-wire bus, commands to other devices
may be initiated before the response is received, but
care in generating the CS function is needed to ensure
that the multiple responses do not interfere. It should
be noted that multiple memory locations can be
accessed in the same command by setting the data
field length field to the desired number of bytes to be
transferred. If flow control is desired, it must be per-
formed by using separate commands, each transfer-
ring smaller blocks of information, or by controlling the
serial clock (gapping the serial clock), or with CS in the
case of byte-by-byte mode.

There is no response from the slave to the master for a
write operation. The response to a read operation sim-
ply includes the data to be read in the data field. This
data is sent least significant bit first, with the bytes sent
in ascending sequence. Commands from the master
controller include data for write operations, but not for
read operations. Since the coefficients and gains are
stored in volatile memory, all the coefficients and gains
must be loaded after powerup. There is, however, no
need to reload them when switching from active to
standby modes, or vice versa. Great care should be
exercised in loading memory when the codec channel
is not in standby mode. Sudden changes in the termi-
nation or balance impedances can result in undesirable
system operation.

All data is transmitted in a byte-oriented fashion with
the least significant bit of each byte transferred first.
Multibyte fields are transferred least significant byte
first in both directions. The data field will contain the
first addressed data location first, with subsequent data
locations transmitted in ascending order.

Preliminary Data Sheet
July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Functional Description

(continued)

The Control Interface

(continued)

Protocol (continued)

* Location of memory bank selection. All user controls are in memory bank 0; other memory banks contain internal state information for the

device.

Note: Data field length is in bytes for all operations. All data is transmitted in bytes with the LSB for each byte transmitted first. For 16-bit mem-

ory operations, the least significant byte of the first memory location is transmitted first, followed by the most significant byte; each byte is
transmitted LSB first. Additional memory locations are loaded in ascending sequence.

Figure 5. Command Frame Format, Master to Slave, Read or Write Commands

Note: All data is transmitted in bytes with the LSB for each byte transmitted first. For memory operations, the least significant byte of the first

memory location is transmitted first, followed by the most significant byte, each byte transmitted LSB first. Additional memory locations
are loaded in ascending sequence.

Figure 6. Command Frame Format, Slave to Master, Read Commands

LSB

MSB LSB

COMMAND (8 bits)

START ADDRESS (8 bits)

DATA FIELD LENGTH (8 bits)

DATA FIELD (VARIABLE LENGTH) WRITE OPERATIONS ONLY

TIME

MSB

LSB

START ADDRESS:

MSB

LSB

DATA FIELD LENGTH:

MSB

LSB

COMMAND:

CKT

SELECT

COMMAND

CKT SELECT:

CKT a:
CKT b:
CKT c:
CKT d:

00
01
10
11

COMMANDS: FAST SCAN MODE:

WRITE MEMORY:
WRITE ALL CHANNELS:
READ MEMORY:

10
01
11
00

LSB

DATA FIELD (VARIABLE LENGTH) READ OPERATIONS ONLY

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Functional Description

(continued)

The Control Interface

(continued)

Read Command

The normal flow of information to the master controller is always in response to a read command. All control mem-
ory locations are accessed in 8-bit bytes. All read commands from the master controller require a response from
the addressed codec. It is the responsibility of the master controller to ensure that only one device is transmitting
on the serial interface line at any one time. The master controller also must ensure that the CS lead goes high after
transferring the 3-byte sequence used to initiate the read, and then it goes low again for the response. In this case,
it should be noted that the device expects the second time CS goes low that data is to be sent to the master; thus,
it does not interpret the DI lead as containing a valid instruction during that CS excursion and a write during this
time is not recommended. Note also that the CS lead must allow the number of bytes sent in a read command to
be transferred before a subsequent command can be received by the codec. Figures 11--14 illustrate normal or
byte-by-byte operation with continuous or gapped DCLKs. Like a write command, transitions, not frequency, are
critical with regard to gapped DCLK operation.

0079

* Provide sufficient wait time to access read data. Provide sufficient DCLK cycles to effectively wait

1.5

s after the second full DCLK cycle

and before the second to last full DCLK cycle. DCLK operation of 4.096 MHz would require 10 cycles of DCLK between LENGTH and DATA.
The first two DCLK cycles, when CS goes high, processes the command. A wait is then required to access the read data. Two final DCLK
cycles are required to process the read data.

Two or more DCLK cycles are required before the start of a new command frame.

Note: Data field length of 1 shown.

Figure 11. Read Operation, Normal Mode (Continuous DCLK)

COMMAND FRAME

DCLK

COMMAND

START ADDRESS

DATA

LENGTH

WAIT

1.5

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Functional Description

(continued)

The Control Interface

(continued)

Fast Scan Mode

The fast scan mode allows a single byte command to read two SLIC control leads for all four channels with a
1-byte reply. This mode significantly speeds up the normal scanning for off-hook, ring trip, and ring ground detec-
tion. This special command sequence allows the controlling microprocessor to fast scan 2 bits in the SLIC control
byte of each of the four channels. The command code is (00000010)

, there are no start address or length fields.

The command returns only a single byte of data, formatted as shown in Table 9.

Table 7. Bit Assignments for Fast Scan Mode

The circuit select in the command structure (Figure 5) is not used for this special single-byte command. The rules
for toggling chip select apply as for the read command. Figures 15--18 illustrate normal or byte-by-byte operation
with continuous or gapped DCLKs.

0125

* Provide sufficient wait time to access read data. Provide sufficient DCLK cycles to effectively wait

1.5

s after the second full DCLK cycle

and before the second to last full DCLK cycle. DCLK operation of 4.096 MHz would require 10 cycles of DCLK between COMMAND and
DATA. The first two DCLK cycles, when CS goes high, processes the command. A wait is then required to access the read data. Two final
DCLK cycles are required to process the read data.

Two or more DCLK cycles are required before the start of a new command frame.

Figure 15. Fast Scan, Normal Mode (Continuous DCLK)

Bit

Reported Status

0 (LSB)

Channel 0, bit 0 (ckt a, address 160, bit 0)

Channel 0, bit 1 (ckt a, address 160, bit 1)

Channel 1, bit 0 (ckt b, address 160, bit 0)

Channel 1, bit 1 (ckt b, address 160, bit 1)

Channel 2, bit 0 (ckt c, address 160, bit 0)

Channel 2, bit 1 (ckt c, address 160, bit 1)

Channel 3, bit 0 (ckt d, address 160, bit 0)

7 (MSB)

Channel 3, bit 1 (ckt d, address 160, bit 1)

DCLK

COMMAND

DATA

WAIT

1.5

Preliminary Data Sheet
July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Functional Description

(continued)

The Control Interface

(continued)

Write All Channels

The write all channels command causes all four channels to be loaded with the same coefficients with a single data
transfer from the master controller. This allows for a faster initialization of the device after a powerup. This com-
mand should be used with caution since it affects all four channels. The normal memory write and read commands
affect only one channel.

Reset Functionality

0071

Figure 19. Hardware Reset Procedure

The reset function allows the internal logic of the device to be set to a known initial condition, either externally by
activating the reset lead, or on a per-channel basis through the microprocessor interface by setting and then
clearing bits, if required, in address RESCTRL (address 128). These two reset functions have different effects, and
each of the software reset functions is a subset of the hardware reset functionality. The primary difference is in
the treatment of the internal memory. The hardware reset is assumed to be a result of a catastrophic hardware
event, such as a loss of power or an initial powerup. Accordingly, the assumption is made that the internal memory
does not contain valid data, and default values for all memory locations are loaded. A software reset, however, can
only be initiated if the device is operational (at least the microprocessor interface), so the contents of the memory
may indeed be valid; thus, the resets may be more specific. Additionally, software resets only affect the selected
channel.

BCLK

RST

DCLK

(GAPPED)

DCLK

(CONTINUOUS)

8 PULSES REQUIRED

DURING RESET

12 PULSES REQUIRED

AFTER RESET

NO GAP IS REQUIRED HERE.

8 PULSES REQUIRED

DURING RESET

12 PULSES REQUIRED

AFTER RESET

DEVICE

CAN NOW BE PROGRAMMED

WAIT

5 ms

RUNS CONTINUOUSLY

Agere Systems Inc.

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Functional Description

(continued)

Reset Functionality

(continued)

A 0.1

F capacitor between the RST lead and ground

will effectively hold the lead low long enough to reset
the device on powerup, allowing for a cost-effective
power-on reset function. Notice that the memory must
be reloaded through the serial interface after a hard-
ware reset function. For proper operation, it is neces-
sary for FS and BCLK to be present and stable during
a reset. DCLK transitions (frequency is not critical as
long as the maximum rate is not exceeded) are also
required in order for all internal logic to be properly
cleared as is a wait period for the internal PLL to stabi-
lize. See the timing diagram shown in Figure 19 for the
proper hardware or power-on reset procedure.

For a software reset, the control memory should not be
accessed for a minimum of 256

s following the reset.

Memory Control Mapping

Several memory locations are used to control the
device. The Software Interface tables (Table 17, Mem-
ory Mapping and Table 18, Control Bit Definition) show
the memory assignments that are useful in call pro-
cessing and system testing. It should be noted that
other memory locations are used by the device to hold
intermediate results and other device state information.
Writing to these other locations can cause serious dis-
ruptions in the operation of the device and should be
avoided.

Standby Mode

The device enters a low-power standby mode with
powerup or software reset, or by programming the
CHACTIVE register 129, bit 0. In standby mode, the
control interface is active, capable of writing or reading
registers. SLIC read and write data latches are also
active. Analog signals at VF

I and PCM signals at D

are ignored in this mode. BCLK must be present for
proper standby mode operation.

Test Capabilities

The device has several built-in test capabilities that can
be used to verify correct operation of the signal pro-
cessing of the line card. These test functions are
accessed in several different control addresses. Five
loopback modes are employed (the first four in the list
below are digital loopbacks):

Digital 1.

Allows the digital signal from the PCM bus
to be looped back to the PCM bus. This
loopback facility can be used to verify cor-
rect operation of the PCM bus interface
logic, as well as operation of the PCM
bus.

Digital 2.

Allows complete testing of the digital pro-
cessing capability of the codec by looping
the data back at the analog/digital conver-
sion interface.

Digital 3.

This loopback function is at the digital side
of the sigma-delta mode converters and
loops analog transmit data back to the
analog receive path.

Digital 4.

This loopback is at the PCM bus interface
and loops the transmit data from the line
back to the receive path.

Analog 5.

The analog loopback facility can be used
to check the operation of all the signal
processing performed in the device,
including the conversions to/from analog.

Three of these loopback functions (digital 1 and 2, and
the analog loopback) can be used with tone generation
and reception via the PCM bus.

By assigning the transmit and receive time slots identi-
cally, a loopback arrangement at the PCM bus can be
effectively programmed for signals generated on the
line side of the codec. This mode is useful for testing
from the line side through the entire device.

An optional 16-bit encoding mode is included on a per-
channel basis for use in various test scenarios, or for
use by an external digital signal processor. This mode
of operation differs from the companded modes in both
the bit order and the use of multiple time slots on the
PCM bus.

Agere Systems Inc.

Preliminary Data Sheet
July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Functional Description

(continued)

Echo Canceller Functionality

The echo canceller has three sets of coefficient mem-
ory storage locations. One, called HPRE, contains the
default balance coefficients and can be accessed as
memory addresses 0--127. This serves as the coeffi-
cients for a fixed balance network (adaptation dis-
abled), or as a starting point for echo cancelllation. The
contents of these memory locations do not change with
adaptation. The adaptation coefficients, which are
added to the corresponding coefficients in HPRE, are
stored in the HHAT area. Normally, the user has no
need to access these coefficients; thus, these
addresses are not described in this data sheet. The
HHAT coefficients cover either the first 8, 16, 32, or the
entire 64-tap length of the balance filter, depending on
the settings in the LMSGAIN address. Note that all
echo canceller length options in this control location
may not be implemented, but are reserved for future
use.

A third set of coefficients is contained in HDTA, which
are used for special data call functions.

SLIC Control Capabilities

Memory locations 158, 159, and 160 are used to con-
trol six bidirectional latches that are intended to allow
the serial interface to control other line card devices,
such as ringing/test switches, telecom electromechani-
cal relays, and SLIC devices. When the TTL latches
are configured as outputs, external devices should be
set up to sink current from the latch. Location 158 sets
the operational mode of these latches as either inputs
or outputs. Location 159 specifies what is to be written
on the latch leads driven by the device. Location 160
reports the actual state of these leads. It should be
noted that a channel control reset forces all of these
external leads, except those corresponding to bits 2
and 3, to the high-impedance state, so any inputs con-
nected to bits 0, 1, 4, and 5 should have appropriate
pull-up or pull-down resistors (off-chip, if required) to
force the external device into a known state at power-
up or in the event of a reset. Bits 2 and 3 will reset to
outputs with a value of zero.

The fast scan mode allows for a minimal data transfer
on the serial bus to monitor bits 0 and 1 of the SLIC
data memory location (159). If these 2 bits are wired as
inputs to the off-hook and/or ring ground detection cir-
cuits, a convenient method of rapidly scanning for
these two functions is obtained. Bits 2 and 3 default to
outputs; thus, they are convenient to provide control of
the SLIC state. In any event, all six leads are program-
mable for maximum flexibility.

Suggested Initialization Procedures

It is suggested that upon powerup, a hardware reset be
used to set the device into a known state. The serial
interface should then be used to load the memory
addresses that differ from the default values (the write
all channels command is convenient for this function).
If other devices are controlled by the SLIC data mem-
ory location, then it also should be loaded with a known
configuration. After the completion of this sequence,
the device is ready to be activated. Depending on the
application, the next step may either be normal opera-
tion or a set of test sequences. After the initialization of
the memory, the device and associated line card
devices can be controlled by using memory locations
130, 131, 145, 155, 156, 157, 158, 159, and 129; that
is, by supplying the PCM bus time-slot addresses,
switching the SLIC into the proper mode, and activating
the codec. Within memory location 129, the codec
would normally be placed into active mode, with both
directions of the PCM bus enabled at the start of a call.
At the completion of a call, the codec should be placed
into standby mode and the PCM bus disabled. Great
caution should be used when changing the memory
while the codec is in active mode, since termination
impedances, balance impedances, and gains may
change. These changes are likely to yield undesirable
system effects. It is safe to refresh coefficients that are
known to be unchanging in the application. It is always
possible to read the memory to verify its contents with-
out deleterious effects on codec operation. Normal
operation would load the memory and perform all gain
adjustments while the codec is in standby mode. Under
no circumstances should memory above address 162
be written, since this section of memory is used for
state data and intermediate results. Also, all reserved
addresses should not be written. Changing this infor-
mation may have deleterious effects on system opera-
tion.

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Functional Description

(continued)

Signal Processing

Figure 20 details the signal processing functional blocks of one channel of the codec.

0496 F

* Programmable blocks.

Figure 20. Internal Signal Processing

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational section of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.

Parameter

Symbol

Min Max

Unit

Storage Temperature Range

stg

150

°C

Power Supply Voltage (all pins designated power)

DDX

Negative Voltage on Any Pin with Respect to Ground

0.25

Thermal Resistance, Junction to Case (68-pin PLCC)

°C/W

Package Power Dissipation (68-pin PLCC)

930

Thermal Resistance, Junction to Case (64-pin MQFP)

°C/W

Package Power Dissipation (64-pin MQFP)

1.14

Thermal Resistance, Junction to Case (44-pin PLCC)

°C/W

Package Power Dissipation (44-pin PLCC)

815

SPEED

FROM

PCM

BUS

GRX1

GAIN

8 kHz

COMP

TO LIN.

TRANSFER

XLPF

GAIN

TWEAKING

GRX2

SINC

D/A

1-bit

D/A

RCF

SMF

0 dB

ECHO

32 kHz

4096 kHz

LPF

DIGITAL

SLIC

PCM

BUS

GAIN

GTX2

LIN.TO

COMP

YLPF

GAIN

TWEAKING

GTX1

SINC

FROM

0 dB TO 24 dB

SLIC

TRANSFER

TEQ

A/D

LPF

RTZ

8 STEPS

IN 5 STEPS

XAG

ANALOG

CTZ

CANCELLER

Preliminary Data Sheet
July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Operating Ranges

Handling Precautions

Although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo-
sure to electrostatic discharge (ESD) during handling and mounting. Agere Systems Inc. employs a human-body
model (HBM) and a charged-device model (CDM) for ESD susceptibility testing and protection design evaluation.
ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide stan-
dard has been adopted for the CDM. A standard HBM (resistance = 1500

, capacitance = 100 pF) is widely

accepted and can be used for comparison. The HBM ESD threshold of >1000 V was obtained by using these cir-
cuit parameters:

Electrical Characteristics

For all specifications: T

40 °C to +85 °C, V

= 5 V ± 5%, unless otherwise noted. Typical values are for

= 25 °C and V

= 5 V. Input signal frequency is 1004 Hz, unless otherwise noted.

dc Characteristics

Table 8. dc Characteristics

Parameter

Symbol

Min Max

Unit

Ambient Operating Temperature

°C

Operating Junction Temperature

125

°C

HBM ESD Threshold Voltage

Device

Voltage

T8533/T8534

>2000

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Input Voltage Low

All inputs

0.8

Input Voltage High

All inputs

2.0

Input Current

Digital, without pull-up, inputs,

GND < V

< V

With internal pull-up, V

= GND

(INTS, MCLK, and RST pins)

With internal pull-up, V

= V

(INTS, MCLK, and RST pins)

240

Output Voltage Low

= 3.2 mA

0.4

Output Voltage High

320

3.5

Output Current in High-impedance

State

GND < V

OUT

< V

Line Driver (DX and DO pins) Output

Voltage High

10 mA

0.5

Line Driver (DX and DO pins) Output

Voltage Low

= 10 mA

0.5

Preliminary Data Sheet
July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Electrical Characteristics

(continued)

Analog Interface

(continued)

Table 10. Power Requirements

Transmission Characteristics

Table 11. Transmission Characteristics

Parameter

Min

Typ

Max

Unit

Operating Voltage:

DDX

4.75
4.75

--
--

5.25
5.25

V
V

Power Supply Current, V

+ V

DDX

All Channels in Standby Mode
All Channels Active

--
--

110

mA
mA

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Absolute Levels

GAL

Maximum 0 dBm0 levels (1004 Hz):

I (encoder milliwatt), all program-

mable transmit gains set to 0 dB

2.80

Vp-p

RCV (decoder milliwatt), termination

impedance off, all programmable

receive gains set to 0 dB

5.29

Vp-p

Minimum 0 dBm0 levels (1004 Hz):

I (encoder milliwatt)

XAG = 24 dB

GTX1 = 6 dB
GTX2 = 0 dB

87.5

mVp-p

RCV (decoder milliwatt), termination

impedance off

GRX1 = 0 dB

GRX2 =

6 dB

2.63

Vp-p

Absolute Maximum Volt-

age Swings

GAL

OP to VF

ON (differential)

--
--

3.2

5.28

Vp-p
Vp-p

Transmit Gain Absolute

Accuracy

GXA

Transmit gain programmed for maxi-

mum 0 dBm0 test level, measured
deviation of digital code from ideal

0 dBm0 level at DX digital outputs,

with transmit gain set to 0 dB:

20 °C to 70 °C

0 °C to 85 °C

40 °C to +85 °C

0.25

0.35

±0.15

--
--

0.25
0.35

dB
dB
dB

Transmit Gain Variation

with Programmed Gain

GXAG

Measured transmit gain over the

range from maximum to minimum,

calculated deviation from the pro-

grammed gain relative to GXA at

0 dB, V

= 5 V

0.1

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Electrical Characteristics

(continued)

Transmission Characteristics

(continued)

Table 11. Transmission Characteristics (continued)

* Applied to all four channels.

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Transmit Gain Varia-

tion with Fre-
quency, 600

Resistive Source
Impedance and
Synthesized Termi-
nation Impedance

GXAF

Relative to 1004 Hz, minimum

gain < GX < maximum gain, VF

I = 0 dBm0

signal, path gain set to 0 dB:

f = 16.67 Hz

f = 40 Hz
f = 50 Hz
f = 60 Hz

f = 200 Hz

f = 300 Hz to 3000 Hz

f = 3140 Hz
f = 3380 Hz
f = 3860 Hz

f = 4600 Hz and above

--
--
--
--
--

0.125

0.57

0.735

--
--

3.5

±0.04

0.01

0.03

9.0

30
0

0.135
0.125
0.015

8.98

dB
dB
dB
dB
dB
dB
dB
dB
dB
dB

Transmit Gain Varia-

tion with Signal
Level

GXAL

Sinusoidal test method*,

reference level = 0 dBm0:

I =

40 dBm0 to +3 dBm0

I =

50 dBm0 to

40 dBm0

I =

55 dBm0 to

50 dBm0

0.25

0.50

1.40

--
--
--

0.25
0.50
1.40

dB
dB
dB

Receive Gain Abso-

lute Accuracy

GRA

Receive gain programmed to

6 dB, apply

0 dBm0 signal to DR, measure V

RCV

= 100 k

differential:

20 °C to 70 °C

0 °C to 85 °C

40 °C to +85 °C

0.25

0.30

±0.15

--
--

0.25
0.30

dB
dB
dB

Relative Gain,

OP to VF

Digital input 0 dBm0 signal,

f = 300 Hz to 3400 Hz

0.01

Relative Phase,

OP to VF

Digital input 0 dBm0 signal,

f = 300 Hz to 3400 Hz

0.25

Degrees

Receive Gain Varia-

tion with Pro-
grammed Gain

GRAG

Measure receive gain over the range from

maximum to minimum setting, calculated

deviation from the programmed gain rela-

tive to GRA at 0 dB, V

= 5 V

0.1

Receive Gain Varia-

tion with Fre-
quency, 600

Resistive Termina-
tion

GRAF

Relative to 1004 Hz, digital input =

0 dBm0 code, minimum gain < GR < maxi-

mum gain, 0 dB path gain:

f = below 3000 Hz

f = 3140 Hz
f = 3380 Hz
f = 3860 Hz

f = 4600 Hz and above

0.125

0.57

0.735

--
--

±0.04
±0.04

0.550

10.7

0.125
0.125
0.015

8.98

dB
dB
dB
dB
dB

Receive Gain Varia-

tion with Signal
Level

GRAL

Sinusoidal test method*,

reference level = 0 dBm0:

IPCM digital level =

40 dBm0 to +3 dBm0

IPCM digital level =

50 dBm0 to

40 dBm0

IPCM digital level =

55 dBm0 to

50 dBm0

0.25

0.50

1.40

--
--
--

0.25
0.50
1.40

dB
dB
dB

Preliminary Data Sheet
July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Electrical Characteristics

(continued)

Noise Characteristics

Table 12. Per-Channel Noise Characteristics

* RTZ and CTZ paths open. All channels active.

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Transmit Noise,

C-Message Weighted

0 dB transmit gain*

dBrnC0

Transmit Noise,

P-Message Weighted

0 dB transmit gain*

dBm0p

Receive Noise,

C-Message Weighted

0 dB receive gain, digital pattern

corresponding to idle PCM code,

-law

dBrnC0

Receive Noise,

P-Message Weighted

0 dB receive gain, digital pattern

corresponding to idle PCM code, A-law

dBm0p

Noise, Single Frequency

f = 0 kHz to 100 kHz, loop around

measurement, V

VFxI

= 0 Vrms

dBm0

Power Supply Rejection,

Transmit

PSR

= 5.0 V

+ 100 mVrms

f = 0 kHz to 4 kHz

f = 4 kHz to 50 kHz

C-message weighted

36
30

--
--

dBC
dBC

Power Supply Rejection,

Receive

PSR

Measured on VF

OP,

= 5.0 V

+ 100 mVrms:

f = 0 kHz to 4 kHz

f = 4 kHz to 25 kHz

f = 25 kHz to 50 kHz

36
40
36

--
--
--

dBC
dBC
dBC

Spurious Out-of-Band Sig-

nals at the Channel Out-
puts

SOS

0 dBm0, 300 Hz to 3400 Hz signal applied

to V

VFxI

, transmit gain set to 0 dB:

4600 Hz to 7600 Hz
7600 Hz to 8400 Hz

8.4 kHz to 50 kHz

--
--
--

dB
dB
dB

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Timing Characteristics

Table 15. Timing Characteristics

* PCM clock (BCLK) must be synchronous with both FS and MCLK, if used. If MCLK is used, then the rising edge of MCLK must coincide with

the rising edge of BCLK within 10 ns.

The t

SXBDLY

delay is from either DCLK or CS, whichever transition is later, for the first bit of the byte.

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

DCLK

Serial Bus Clock Frequency

4096

kHz

BCLK

Allowable PCM Bus Clock Fre-

quencies* (512 kHz minimum
if linear encoding is selected.)

--
--
--
--
--
--
--

256
512

1024
2048
4096
8192

16384

--
--
--
--
--
--
--

kHz
kHz
kHz
kHz
kHz
kHz
kHz

Jitter of BCLK

100 ns in

100 ms = 1 ppm

Serial Bus Clock Duty Cycle

PCM Bus Clock Duty Cycle

CSSETUP

Chip Select Setup Time, Normal

Mode

Serial clock frequency

= 4.096 MHz

CSHOLD

Chip Select Hold Time, Normal

Mode

Serial clock frequency

= 4.096 MHz

SXDLY

Serial Bus Output Data Delay,

Normal Mode

Serial clock frequency

= 4.096 MHz

SDHOLD

Serial Bus Input Data Hold

Time, Normal Mode

Serial clock frequency

= 4.096 MHz

SDSETUP

Serial Bus Input Data Setup

Time, Normal Mode

Serial clock frequency

= 4.096 MHz

FSSETUP

Frame Strobe Setup Time

PCM clock frequency

= 16.384 MHz

FSHOLD

Frame Strobe Hold Time

PCM clock frequency

= 16.384 MHz

FSWIDTH

Frame Strobe Width

FS synchronous with

BCLK

125

BCLK

XDLY

PCM Bus Output Data Delay

PCM clock frequency

= 16.384 MHz

Preliminary Data Sheet
July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Timing Characteristics

(continued)

Table 15. Timing Characteristics (continued)

* PCM clock (BCLK) must be synchronous with both FS and MCLK, if used. If MCLK is used, then the rising edge of MCLK must coincide with

the rising edge of BCLK within 10 ns.

The t

SXBDLY

delay is from either DCLK or CS, whichever transition is later, for the first bit of the byte.

Table 16. Echo Canceller Characteristics

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

IDHOLD

PCM Bus Input Data Hold Time

PCM clock frequency

= 16.384 MHz

IDSETUP

PCM Bus Input Data Setup

Time

PCM clock frequency

= 16.384 MHz

RISE

Clock Edge Rise Time

Serial clock frequency

= 4.096 MHz, PCM

clock frequency =

16.384 MHz

FALL

Clock Edge Fall Time

Serial clock frequency

= 4.096 MHz, PCM

clock frequency =

16.384 MHz

RISE

FALL

Line Driver Rise/Fall Time (DO

and DX outputs)

= 15 mA,

LOAD

= 100 pF

30 ns

CSBHOLD

Chip Select Hold Time, Byte-by-

Byte Mode

Serial clock frequency

= 4.096 MHz

SXBDLY

Serial Bus Output Data Delay,

Byte-by-Byte Mode

Serial clock frequency

= 4.096 MHz

CSBSETUP

Chip Select Setup Time, Byte-

by-Byte Mode

Serial clock frequency

= 4.096 MHz

SDBHOLD

Serial Bus Data Hold Time,

Byte-by-Byte Mode

Serial clock frequency

= 4.096 MHz

SDBSETUP

Serial Bus Data Setup Time,

Byte-by-Byte Mode

Serial clock frequency

= 4.096 MHz

CSBHOLD

Chip Select Hold Time, Byte-by-

Byte Mode

Serial clock frequency

= 4.096 MHz

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Echo Return Loss

Convergence Time

100+

dB/s

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Software Interface

Table 17. Memory Mapping

With the exceptions noted, all of these memory locations may be read to determine the state of the controls con-
tained therein. In the following table, bit 0 is the LSB (transmitted first on the serial interface) and bit 7 is the most
significant bit of the byte. Unused bits in an address or multibyte address should be loaded as zero. All of the mem-
ory locations can be programmed on a per-channel basis.

Note that the entire coefficient set for a channel (or all four channels) may be loaded with one command.

* The coefficients to be entered can be obtained from the Aquarium coefficient software.

Control Name

Address

(decimal)

Number

of Bits

Used

Default

Value

Name/Description

HBALTAPS*

0--127

1024

See Table

Balance impedance tap coefficients.

RESCTRL

128

0x00

Reset address. Writing a 1 in the used positions causes a
reset as defined by the bit definition. This reset remains in
force until the bit is written as a 0.

CHACTIVE

129

0x00

Standby/active control.

RXBITOFF

130

0x00

Bit offset for receive direction.

RXOFF

131

(16*

channel #)

Time-slot offset for receive direction.

GRX1*

132--133

0x0400

Control of gain affecting receive direction gain transfer.

GRX2*

134--135

0x01ac

Control of gain sensitive to impedance and SLIC parameter
choices, receive direction.

NORMCTRL*

136

0x25

Peak and far-end speech detector control.

NESCTRL*

137

0x06

Near-end speech detector control.

LMSGAIN*

138

0xee

Adaptation control address.

TDETCTRL*

139

0x00

Data call control address.

CTZCTRL*

140--143

0x07ed0000 CTZ bleed coefficients.

LMSCTRL*

144

0x01

Adaptation leak values.

RECCTRL*

145

0x00

Residual echo control.

SDCTRL*

146

0x19

RTZ, transmit analog gain (XAG), and analog loopback
controls.

SDTSI

147

(17*

channel #)

Internal time-slot interchanger. Default sets external pins to
state referenced in this data sheet.

GTX2*

148--149

0x0400

Control of gain affecting transmit direction gain transfer.

ZEQCTRL*

150--152

0x000000

Coefficients for the equalization stage that accommodates
current-sensing SLICs.

GTX1*

153--154

0x051a

Control of gain sensitive to impedance and SLIC parameter
choices, transmit direction.

TXBITOFF

155

0x00

Bit offset for transmit direction.

TXOFF

156

(16*

channel #)

Time-slot offset for transmit direction.

PCMCTRL

157

0x00

PCM control address.

SLICTS

158

0x0c

SLIC 3-state control address. A 1 enables the correspond-
ing SLIC pin to operate as an output pin.

Preliminary Data Sheet
July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Software Interface

(continued)

Table 17. Memory Mapping (continued)

Table 18. Control Bit Definition

The following table shows the control bit assignments in the memory control addresses. In all control bit cases, the
bit being set places the function into the active mode as defined in the function column.

Control Name

Address

(decimal)

Number

of Bits

Used

Default

Value

Name/Description

SLICWR

159

0x00

Data to be written to the SLIC latches if the corresponding
bit is set in the SLICTS control word.

SLICRD

160

Current actual state of the SLIC pins. This will be the same
as SLICWR for those pins configured as outputs. All other
positions will reflect the actual state of the external pin. A
write operation to this word will be ignored, and within one
PCM frame (125

s), the data will be overwritten.

VERIFY

162

Test address for serial interface verification.

DATACALL

167

Read-only indicator of a data call in progress. Do not write
this register.

254--255

Factory test only, do not access.

Control Name

(Address, Decimal)

[Address, Hex]

Bit

Assignment(s)

Function

HBALTAPS

(0--127)

[0x00--0x7f]

0--1023

Balance impedance coefficients. Default value is 0x00 for all bytes except
for addresses 3 and 5, which are 0x80, and address 69, which is 0x88.

RESCTRL

(128)

[0x80]

4--7

Not used, load as 0s.

A one resets the state associated with special data call processing.

A one resets the echo canceller coefficients to 0 when channel is active.

A one resets all other internal states. Does not affect programmed regis-
ters.

Reset all control addresses to default values. Note that setting this bit will
result in it and all others of this word becoming cleared on the next PCM
frame as a normal part of this control reset functionality. Also, the state
reset bits (1--3) are cleared before they are acted upon if this bit is
raised; hence, it is not possible to reset both state and control by writing
0x0F to RESCTRL. If such an action is desired, it is necessary to first
reset control by writing 0x01 and then, in a subsequent frame, write first
0x0E and then 0x00. Alternatively, hardware reset can be used to reset all
control and state.

It is necessary to wait at least 256

s after asserting this bit before initiat-

ing any other serial I/O transactions.

CHACTIVE

(129)

[0x81]

1--7

Load as 0s.

Active/Standby mode. A 0 causes the channel to enter standby (low
power) mode and disables the PCM interface for this channel. A 1 acti-
vates the channel and the corresponding PCM bus interface. Default is 0.

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Software Interface

(continued)

Table 18. Control Bit Definitions (continued)

Control Name

(Address, Decimal)

[Address, Hex]

Bit

Assignments

Function

RXBITOFF

(130)

[0x82]

5--7

Receive direction bit offset for the FS signal. Defaults to 0. These 3 bits
can be thought of as the least significant bits (RXOFF contains the more
significant bits) of a bit counter that determines the location of the first bit
of the PCM data from FS.

0--4

Load as 0.

RXOFF

(131)

[0x83]

0--7

Receive time-slot assignment. Defaults to (16 * channel number). Each
time slot represents 8 bits, allow for two time slots when using linear
mode.

GRX1

(132--133)

[0x84--0x85]

0--10

Gain adjustment for gain transfer stage in receive direction. Defaults to
0x0400 (0 dB). This is an 11-bit multiply operation with a maximum gain of
2 (6 dB). 0 dB is the maximum recommended setting.

GRX2

(134--135)

[0x86--0x87]

0--10

Gain adjustment for tweak gain stage in receive direction. Defaults to
0x01ac (

7.58 dB). This is an 11-bit multiply operation with a maximum

gain of 2 (6 dB). 0 dB is the maximum recommended setting.

NORMCTRL

(136)

[0x88]

6--7

Load as 0s.

3--5

Peak detector tweaking control. Use default
of 4.

Bit Number

Function

(dB)

0.0

3.01

6.02

9.03

12.04

15.05

18.06

21.07

0--2

Far-end speech detector threshold. Use
default of 5.

Bit Number

Function

(dBm0)

Preliminary Data Sheet
July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Software Interface

(continued)

Table 18. Control Bit Definitions (continued)

Control Name

(Address, Decimal)

[Address, Hex]

Bit

Assignments

Function

NESCTRL

(137)

[0x89]

3--7

Load as 0s.

Enable near-end speech detector. Defaults to 1 (active).

0--1

Threshold for the near-end speech detec-
tor. Default is 2 (

6 dB).

Bit

Number

Function (dB)

(Threshold =)

0.0

3.5

6.0

9.5

LMSGAIN

(138)

[0x8a]

6--7

Length of echo canceller (8, 16, 32, 64
taps). Defaults to 3 (64 taps).

Bit

Number

Function

8 taps

16 taps

32 taps

64 taps

3--5

Relative adaptive gain of the two IIR taps in the echo canceller. Defaults
to 5. A setting of 0 provides no adaptive loop gain.

0--2

Loop gain for adaptation algorithm.
Default is 6.

Bit Number

Function

(Gain =)

0.0078

0.0156

0.0313

0.0625

0.1250

0.2500

0.5000

1.000

TDETCTRL

(139)

[0x8b]

6--7

Load as 0.

This bit being set allows the echo canceller coefficients developed off-
line during a data call to be captured and saved for potential use during
the next data call. Default is 0 (do not capture).

This bit enables the echo canceller to continue to adapt during a data
call. Default is 0 (do not adapt during a data call).

This bit, when set, enables the use of the internal logic to determine the
proper time for the off-line adaptation during a data call. Default is 0.

Selects the internal set of hybrid balance network coefficients to use on
a data call. Default is 0.

This bit, when set to a 1, clears the H register at the start of a data call.
Default is 0.

This bit being set freezes the echo canceller. Default is 0.

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Software Interface

(continued)

Table 18. Control Bit Definitions (continued)

Control Name

(Address, Decimal)

[Address, Hex]

Bit

Assignments

Function

CTZCTRL

(140--143)

[0x8c

--0x8f]

0--30

Coefficients for the CTZ termination bleed. Defaults to 0x07ed0000.

LMSCTRL

(144)

[0x90]

3--7

Load as 0s.

0--2

Leak coefficient for LMS adaptation algorithm. Defaults to 1.

RECCTRL

(145)

[0x91]

5--7

Load as 0s.

Noise match enable (comfort noise). Defaults to 0 (disabled).

Enable residual echo control. Defaults to 0 (disabled).

0--2

Residual echo control sensitivity factor.
Defaults to 0.

Bit Number

Function

(dB)

(Threshold =)

0.0

3.5

6.0

9.5

12.0

15.5

18.0

21.6

SDCTRL

(146)

[0x92]

Load as 0.

Enable analog loopback. Defaults to 0 (no loopback).

3--5

RTZ gain. Defaults to 3 (equal level point value of 3 * 0.075 = 0.225).

0--2

Transmit analog gain (XAG). Defaults to 1
(6 dB) gain.

Bit Number

Function

(dB)

0.0

6.02

12.04

18.06

24.08

SDTSI

(147)

[0x93]

Load as 0.

Digital loopback, loopback from receive to transmit at the sigma-delta
converters (digital loopback 2). Defaults to 0 (no loopback).

4--5

Digital channel feeding this analog receive channel. Defaults to channel
number.

Send idle channel code (alternating bits) to this analog receive path.
Defaults to 0 (do not send idle channel code).

Loopback from transmit to receive at the sigma-delta converters (digital
loopback 3). Defaults to 0 (no loopback).

0--1

Analog channel feeding this digital channel in the transmit direction.
Defaults to channel number.

GTX2

(148--149)

[0x94

--0x95]

0--11

Gain control for gain transfer stage in transmit direction. Defaults to
0x0400 (0 dB). This is a 12-bit multiply operation with a maximum gain of
4 (12 dB).

Preliminary Data Sheet
July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Software Interface

(continued)

Table 18. Control Bit Definitions (continued)

Control Name

(Address, Decimal)

[Address, Hex]

Bit

Assignments

Function

ZEQCTRL

(150--152)

[0x96--0x98]

0--20

Coefficients for the equalization stage that accommodates current-sens-
ing SLICs. Defaults to 0x000000.

GTX1

(153--154)

[0x99--0x9a]

0--11

Gain control for tweak gain stage in transmit direction. Defaults to 0x051a
(2.11 dB). This is a 12-bit multiply operation with a maximum gain of 4
(12 dB).

TXBITOFF

(155)

[0x9b]

5--7

Transmit direction bit offset for the FS signal. Defaults to 0. These 3 bits
can be thought of as the least significant bits (TXOFF contains the more
significant bits) of a bit counter that determines the location of the first bit
of the PCM data from FS.

0--4

Load as 0.

TXOFF

(156)

[0x9c]

0--7

Transmit time-slot assignment. Defaults to (16 * channel number). Each
time slot represents 8 bits, allow for two time slots when using linear
mode.

PCMCTRL

(157)

[0x9d]

3-state transmit PCM interface. Defaults to 0. A 1 forces the PCM inter-
face into a high-impedance state during its assigned time slot on the PCM
bus. Placing the channel in standby mode also forces a high-impedance
condition on the transmit interface.

Transmit zeroes instead of data. Defaults to 0 (off).

Load as 0.

Place idle channel code on receive path. Defaults to 0 (off).

Loopback receive to transmit at PCM conversion interface (digital loop-
back 1). Defaults to 0 (no loopback).

Loopback transmit to receive at PCM conversion interface (digital loop-
back 4). Defaults to 0 (no loopback).

Linear/companded. A 1 sets 16-bit linear mode with two adjacent time
slots used, LSB transmitted first. Linear data is in two's complement form.
A 0 sets companded mode with only one time slot used, and MSB trans-
mitted first. Defaults to 0.

-law or A-law. A 0 sets

-law mode, and a 1 sets A-law mode. This bit

has no effect if bit 1 of this address is set to 1. Defaults to 0 (

-law).

SLICTS

(158)

[0x9e]

6--7

Load as 0.

0--5

Controls the drivers for the corresponding SLIC latches. A 1 enables the
pin as an output. Defaults to 0x0c (bits 2 and 3 set, the rest cleared).

SLICWR

(159)

[0x9f]

6--7

Load as 0.

0--5

SLIC data latches. If the corresponding bit in the SLICTS address is set
for an output, the device will drive the corresponding bit according to the
contents of this address. Writes are performed within 125

s. Wait

125

s before a subsequent write to the same channel or between write

all channel commands. Default is 0.

SLICRD

(160)

[0xa0]

6--7

Not used, ignore on a codec read command addressing this location.

0--5

Reports the actual state of the SLIC pins. Anything written to this address
is ignored. Updates within 125

VERIFY

(162)

[0xa2]

0--7

Test location for serial interface. This location has no internal use, but
merely latches write data for the purpose of testing the serial interface.
This register does not clear with reset.

DATACALL

(167)

[0xa7]

This bit is set to a 1 if a data call is in progress. Do not attempt to write this
register.

0--4, 6, 7

Internal state control bits; do not write and ignore on read.

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc.

Applications

The following reference circuit shows a complete schematic for interfacing to the Agere L9215G SLIC. All ac
parameters are programmed by the T8534. Note that this implementation differentiates itself in that no external
components are required in the ac interface to provide a dc termination impedance or for stability. For illustration
purposes, 0.5 Vrms PPM injection was assumed in this example and no meter pulse rejection is used. Also, this
example illustrates the device using programmable overhead and current limit.

12-3534.z (F)

VFxI

is required for complex terminations. Optional for resistive terminations.

Figure 24. POTS Interface

BAT1

BGND

BAT2

AGND

ICM

TRGDET

ground key

not used

BAT1

0.1

BAT2

0.1

RTFLT

DCOUT

OVH

PROG

REF

0.1

383

AGERE

L7591

BAT1

FUSIBLE OR PTC

CF1

CF2

rate of battery

reversal not

ramped

FB1 FB2 NSTAT BR

B2 B1 B0

0.22

0.1

PPM
0.5 Vrms

PPM

10 nF

RING

PPM

VITR

RCVP

RCVN

ITR

VTX

TXI

4750

BAT1

BAT2

0.1

RING

0.47

FROM

PROGRAMMABLE

D/A VOLTAGE

SOURCE

PCM

HIGHWAY

DX0

DR0

DX1

DR1

BCLK

DGND

SYNC

AND

VFXI

VFROP

VFRON

SLIC4a

SLIC3a

SLIC2a

SLIC1a

SLIC0a

CLOCK

L9215G

FROM/TO

CONTROL

NSTAT

0.1

FUSIBLE OR PTC

T8534

VFxI

20 M

Preliminary Data Sheet

July 2001

Signal Processor

T8533/34 Quad Programmable Line Card

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

July 2001
DS01-250ALC (Replaces DS01-058ALC)

For additional information, contact your Agere Systems Account Manager or the following:
INTERNET: http://www.agere.com
E-MAIL: docmaster@micro.lucent.com
N. AMERICA:

Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256

Tel. (65) 778 8833, FAX (65) 777 7495

CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC

Tel. (86) 21 50471212, FAX (86) 21 50472266

JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan

Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700

EUROPE: Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148

Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),

FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)

Ordering Information

Device Code Package Comcode

T-8533 - - - ML - D 44-Pin PLCC, Dry-bagged 108269408

T-8534 - - - TL - DB 64-Pin TQFP, Dry pack tray 108420217

T-8534 - - - ML - D 68-Pin PLCC, Dry-bagged 108269424

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