Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Features

5 V operation

Per-channel programmable gains, equalization,
termination impedance, and hybrid balance

Programmable

-law, linear, or A-law modes:

-- Up to 256 time slots per frame
-- Supports PCM data rates of 512 kbits/s to

16.384 Mbits/s

-- Double-clock mode timing compatible with

ISDN standard interfaces

Fully programmable time-slot assignment with bit
offset

Analog and digital loopback test modes

Serial microprocessor interface:
-- Normal and byte-by-byte control modes
-- Fast scan mode

Six bidirectional control leads per channel, for
SLIC and line card function control

Differential analog output:
-- Mates directly to SLICs, eliminating external

components

Sigma-delta converters with dither noise reduction

Quad design to minimize package count on dense
line card applications

Meets or exceeds ITU-T G.711--G.712 and rele-
vant

Telcordia Technologies

requirements

Description

The device consists of four independent channels of
codec and digital signal processing functions on one
chip. In addition to the classic A-to-D and D-to-A con-
version, each channel provides termination imped-
ance synthesis and a hybrid balance network.

The device is controlled by a serial microprocessor
interface, and a series of bidirectional I/O leads are
provided so that this control mechanism can be uti-
lized to operate the battery feed device, ringing volt-
age switches, etc. Common data and clock paths can
be shared over any number of devices. All the filter
coefficients, signal processing, SLIC, and test fea-
tures are accessible through this interface. This
serial interface can be operated at speeds up to
4.096 Mbits/s.

The choice of a PCM bus is also programmable, with
any channel capable of being assigned to any time
slot. The PCM bus can be operated at speeds up to
16.384 Mbits/s, allowing for a maximum of 256 time
slots. Separate transmit and receive interfaces are
available for 4-wire bus designs, or they can be
strapped together for a 2-wire PCM bus.

The device is available in four packages:

The T8536B 64-pin TQFP features five data latches
per channel and the 100-pin TQFP features six-data
latches per channel. Both devices have two PCM
ports and are pin-compatible with the T8538B 3.3 V
Quad Programmable Codec.

The T8536B 68-pin PLCC features six data latches
per channel and has one PCM port. This device is
pin-compatible with the T8534 Quad Programmable
Echo Canceller Codec.

The T8535B 44-pin PLCC has no data latches and
has one PCM port. This device is pin-compatible with
the T8533 Quad Programmable Echo Canceller
Codec.

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Table of Contents

Contents

Page

Features .................................................................................................................................................................... 1
Description................................................................................................................................................................. 1
General Description................................................................................................................................................... 4
Pin Information .......................................................................................................................................................... 5
Functional Description ............................................................................................................................................. 13

Clocking Considerations ....................................................................................................................................... 13
The Control Interface ............................................................................................................................................ 13

Modes ................................................................................................................................................................ 13
Protocol .............................................................................................................................................................. 14
Write Command ................................................................................................................................................. 16
Read Command ................................................................................................................................................. 18
Fast Scan Mode ................................................................................................................................................. 20
Write All Channels.............................................................................................................................................. 23

Reset Functionality ............................................................................................................................................... 23

Memory Control Mapping ................................................................................................................................... 24

Standby Mode ....................................................................................................................................................... 24
Test Capabilities ................................................................................................................................................... 24
SLIC Control Capabilities ...................................................................................................................................... 24
Suggested Initialization Procedures...................................................................................................................... 25
Signal Processing ................................................................................................................................................. 25

Absolute Maximum Ratings.....................................................................................................................................26
Operating Ranges ................................................................................................................................................... 26
Handling Precautions .............................................................................................................................................. 26
Electrical Characteristics ......................................................................................................................................... 27

dc Characteristics ................................................................................................................................................. 27
Analog Interface .................................................................................................................................................... 28
Gain and Dynamic Range .....................................................................................................................................29
Noise Characteristics ............................................................................................................................................ 31
Distortion and Group Delay................................................................................................................................... 32
Crosstalk ...............................................................................................................................................................33

Timing Characteristics ............................................................................................................................................. 34

Control Interface Timing........................................................................................................................................ 34

Serial Control Port Timing .................................................................................................................................. 34
Normal Mode...................................................................................................................................................... 35
Byte-by-Byte Mode............................................................................................................................................. 35

PCM Interface Timing ...........................................................................................................................................36

Single-Clocking Mode ........................................................................................................................................ 36
Double-Clocking Mode ....................................................................................................................................... 38

Software Interface ................................................................................................................................................... 40
Applications ............................................................................................................................................................. 44
Outline Diagrams..................................................................................................................................................... 45

100-Pin TQFP ....................................................................................................................................................... 45
68-Pin PLCC ......................................................................................................................................................... 46
64-Pin TQFP ......................................................................................................................................................... 47
44-Pin PLCC ......................................................................................................................................................... 48

Ordering Information................................................................................................................................................ 49

Agere Systems Inc.

Preliminary Data Sheet
September 2001

T8535B/T8536B Quad Programmable Codec

Table of Contents

(continued)

Figures

Page

Figure 1. Functional Block Diagram, Each Section ................................................................................................... 4
Figure 2. 44-Pin PLCC Pin Diagram ......................................................................................................................... 5
Figure 3. 68-Pin PLCC Pin Diagram ......................................................................................................................... 7
Figure 4. 100-Pin TQFP Pin Diagram ....................................................................................................................... 9
Figure 5. 64-Pin TQFP Pin Diagram .......................................................................................................................11
Figure 6. Command Frame Format, Master to Slave, Read or Write Commands ..................................................15
Figure 7. Command Frame Format, Slave to Master, Read Commands................................................................15
Figure 8. Write Operation, Normal Mode (Continuous DCLK) ................................................................................16
Figure 9. Write Operation, Normal Mode (Gapped DCLK) .....................................................................................16
Figure 10. Write Operation, Byte-by-Byte Mode (Gapped DCLK)...........................................................................17
Figure 11. Write Operation, Byte-by-Byte Mode (Continuous DCLK) .....................................................................17
Figure 12. Read Operation, Normal Mode (Continuous DCLK) ..............................................................................18
Figure 13. Read Operation, Normal Mode (Gapped DCLK) ...................................................................................19
Figure 14. Read Operation, Byte-by-Byte Mode (Gapped DCLK) ..........................................................................19
Figure 15. Read Operation, Byte-by-Byte Mode (Continuous DCLK) .....................................................................20
Figure 16. Fast Scan, Normal Mode (Continuous DCLK) .......................................................................................21
Figure 17. Fast Scan, Normal Mode (Gapped DCLK) ............................................................................................21
Figure 18. Fast Scan, Byte-by-Byte Mode (Gapped DCLK) ...................................................................................22
Figure 19. Fast Scan, Byte-by-Byte Mode (Continuous DCLK) ..............................................................................22
Figure 20. Hardware Reset Procedure ...................................................................................................................23
Figure 21. Internal Signal Processing .....................................................................................................................25
Figure 22. Serial Interface Timing, Normal Mode (One Byte Transfer and Continuous DCLK Shown) ..................35
Figure 23. Serial Interface Timing, Byte-by-Byte Mode (One Byte Transfer and Gapped DCLK Shown)...............35
Figure 24. Single-Clocking Mode (TXBITOFF = 0, RXBITOFF = 0, PCMCTRL2 = 0x00) ......................................37
Figure 25. Single-Clocking Mode (TXBITOFF = 1, RXBITOFF = 2, PCMCTRL2 = 0x01) ......................................37
Figure 26. Double-Clocking Mode (RXBITOFF = 0x20, PCMCTRL2 = 0x00) ........................................................39
Figure 27. POTS Interface ......................................................................................................................................44

Tables

Page

Table 1. Pin Assignments, 44-Pin PLCC, Per-Channel Functions............................................................................5
Table 2. Pin Assignments, 44-Pin PLCC, Common Functions .................................................................................6
Table 3. Pin Assignments, 68-Pin PLCC, Per-Channel Functions............................................................................7
Table 4. Pin Assignments, 68-Pin PLCC, Common Functions .................................................................................8
Table 5. Pin Assignments, 100-Pin TQFP, Per-Channel Functions..........................................................................9
Table 6. Pin Assignments, 100-Pin TQFP, Common Functions .............................................................................10
Table 7. Pin Assignments, 64-Pin TQFP, Per-Channel Functions..........................................................................11
Table 8. Pin Assignments, 64-Pin TQFP, Common Functions ...............................................................................12
Table 9. Bit Assignments for Fast Scan Mode ........................................................................................................20
Table 10. dc Characteristics....................................................................................................................................27
Table 11. Analog Interface ......................................................................................................................................28
Table 12. Power Dissipation ...................................................................................................................................28
Table 13. Gain and Dynamic Range .......................................................................................................................29
Table 14. Per-Channel Noise Characteristics .........................................................................................................31
Table 15. Distortion and Group Delay .....................................................................................................................32
Table 16. Crosstalk .................................................................................................................................................33
Table 17. Serial Control Port Timing .......................................................................................................................34
Table 18. PCM Interface Timing: Single-Clocking Mode ........................................................................................36
Table 19. PCM Interface Timing: Double-Clocking Mode .......................................................................................38
Table 20. Memory Mapping ....................................................................................................................................40
Table 21. Control Bit Definition ...............................................................................................................................41

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

General Description

Refer to Figure 1 for the following discussion.

5-8125aF

* Second PCM port not available in all package types.

Figure 1. Functional Block Diagram, Each Section

RST

SLIC

TO/FROM

ANALOG

GAIN

A/D

CONVERTER

ANALOG

BUFFER

D/A

CONVERTER

I
T

OPBACK 3

ANA

LOOPBA

CK 1

GIT

LOOPBA

CK 2

TERMINATION

IMPEDANCE

HYBRID

BALANCE

NETWORK

DIGITAL GAIN

(GAIN TRANSFER)

-LAW

PER

CHANNEL

COMMON

ANA

LOOPB

ACK 2

DIGI

TAL

LOOPB

ACK 1

PCM BUS

INTERFACE

DX0

DR1*

TO/FROM
PCM BUS

POWER AND
GROUND

BCLK

SLIC

CONTROL LATCHES

MICROPROCESSOR CONTROL

CONTROL AND DATA SIGNALS

SERIAL CONTROL INTERFACE

PER

CHANNEL

COMMON

0 TO 6

FREQUENCY

SYNTHESIZER

0 TO 3

FILTER

CONVERSION

A-LAW

DIGITAL GAIN

(GAIN TRANSFER)

DX1*
TSX0*
TSX1*

DR0

OPn

ONn

This device performs virtually all the signal processing
functions associated with a central office line termina-
tion. Functionality includes line termination impedance
synthesis, fixed hybrid balance impedance synthesis,
and level conversion both in the analog sense to
accommodate various subscriber line interface circuits
(SLICs) and in the digital sense for adjustment of the
levels on the PCM bus. In general, the termination
impedance synthesis generates the equivalent of a cir-
cuit with the parallel combination of a capacitor and a
resistor in series with a resistor, or the parallel combi-
nation of a resistor and the series combination of a
resistor and capacitor. These general forms of imped-
ance characteristics will satisfy most of the require-
ments specified throughout the world. Programmable
selection of either

-law or A-law encoding further aids

worldwide deployment. All coefficients used in the filter-
ing algorithms can be computed off-line in advance and
downloaded to the device at the time of powerup. All
signal processing is contained within the device, and
there are only three interfaces of consequence to the
system designer: the SLIC interface, the PCM inter-
face, and the control interface.

The SLIC interface is designed to be flexible and con-
venient to use with a variety of SLIC circuits. With an
appropriate choice of SLIC, no external components
are required in the interface, with the exception of a dc
blocking capacitor in the transmit direction. In some
cases, dc blocking capacitors in the receive direction
may be necessary as well, since the device operates
from a single low-voltage supply.

The PCM bus interface is flexible in that it allows, inde-
pendently, the transmit and receive data for any chan-
nel to be placed in any time slot. The bus can be
operated at a maximum 16.384 Mbits/s rate to accom-
modate a maximum 256 time slots. Separate pins
are provided for each direction of transmission to
allow 4-wire bus operation. The frame strobe signal is
an 8 kHz signal that defines the beginning of the frame
structure for all four channels. The interface will count
8 bits per time slot and insert or read the data for each
channel as programmed. Lower speeds of the PCM
bus are allowed. The PCM clock must be synchronous
with the frame strobe signal.

The microprocessor control interface is a serial inter-
face that uses the classical chip select type of opera-
tion. The interface controls the device by writing or
reading various internal addresses. The command set
consists of simple read and write operations, with the
address determining the effect. All the memory loca-
tions, including the per-chip functions, are organized by
channel.

There are several test modes included to facilitate con-
firmation of correct operation. In the signal path, two
analog and three digital loopback tests are available,
while in the microprocessor interface, there is a write/
read test mode that tests the operation of the memory.
Use of external test access switches allows a complete
test of the signal path through the line card so that cor-
rect operation of various operational modes can be ver-
ified.

Agere Systems Inc.

Preliminary Data Sheet
September 2001

T8535B/T8536B Quad Programmable Codec

Pin Information

5-7187.b(F)

Figure 2. 44-Pin PLCC Pin Diagram

Table 1. Pin Assignments, 44-Pin PLCC, Per-Channel Functions

Ckt

Name

Type

Name/Description

AGND

GND

Analog Ground. A common AGND, DGND, SGND plane is
highly recommended.

PWR

Analog Power Supply.

Voice Frequency Transmit Input. This node requires a 10 M

or 20 M

resistance to AGND. The value is dependent upon the

gain of the XAG amplifier (register 146). 20 M

can be used for

any gain setting, 10 M

can only be used for XAG gain settings

of 0 dB and +6.02 dB.

Voice Frequency Receive Output, Positive Polarity. This pin
can drive 2000

(or greater) loads.

Voice Frequency Receive Output, Negative Polarity. This pin
can drive 2000

(or greater) loads.

NDc

NDb

PVCOIN

PVCO

SGND

DGND

OPa

PLLT

AGNDa

ONa

DGND

AGNDd

DGND

ONd

OPd

BCLK

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Pin Information

(continued)

Table 2. Pin Assignments, 44-Pin PLCC, Common Functions

Pin

Name

Type

Name/Description

Serial Data Output. This is a 3-state output.

Serial Data Input.

DCLK

Serial Data Clock Input.

Chip Select Input. This lead determines the interval that the serial interface is
active.

INTS

Serial Interface Select. Leaving this lead open places the serial interface in the nor-
mal mode; grounding it places the interface into the byte-by-byte mode. This lead
has an internal pull-up.

FILTV

PWR

Frequency Synthesizer Power (5 V). This pin must be tied to V

PVCOIN

Internal Test Point. Do not connect to this lead.

PVCO

Internal Test Point. Do not connect to this lead.

PLLT

Synthesizer Test Point. Do not connect to this lead.

SGND

GND

Synthesizer Ground. Connect to digital ground. A common AGND, DGND, SGND
plane is highly recommended.

16, 29,

38, 44

DGND

GND

Digital Ground. Logic ground and return for logic power supply. A common AGND,
DGND, SGND plane is highly recommended.

17, 28,

35, 42

PWR

Digital Power Supply (5 V).

PCM Frame Strobe Input. This 8 kHz clock must be derived from the same source
as BCLK.

BCLK

PCM Bit Clock Input. This lead is used to develop internal clocks for certain clock
rates.

39 DX

PCM Transmit Data Output. This is a 3-state output.

PCM Receive Data Input.

RST

Power-On Reset. A low causes a reset of the entire chip. This pin may be con-
nected to DGND with a 0.1

F capacitor for a power-on reset function, or it may be

driven by external logic. This lead has an internal pull-up.

No Connect. This pin may be used as a tie point.

Agere Systems Inc.

Preliminary Data Sheet
September 2001

T8535B/T8536B Quad Programmable Codec

Pin Information

(continued)

5-8126 (F)

Figure 3. 68-Pin PLCC Pin Diagram

Table 3. Pin Assignments, 68-Pin PLCC, Per-Channel Functions

Ckt

Name

Type

Name/Description

AGND

GND

Analog Ground. A common AGND, DGND, SGND plane is
highly recommended.

PWR

Analog Power Supply.

Voice Frequency Transmit Input. This node requires a 10 M

or 20 M

resistance to AGND. The value is dependent upon the

gain of the XAG amplifier (register 146). 20 M

can be used for

any gain setting, 10 M

can only be used for XAG gain settings

of 0 dB and +6.02 dB.

Voice Frequency Receive Output, Positive Polarity. This pin
can drive 2000

(or greater) loads.

Voice Frequency Receive Output, Negative Polarity. This pin
can drive 2000

(or greater) loads.

SLIC0

I/O

SLIC Control 0.

SLIC1

I/O

SLIC Control 1.

SLIC2

I/O

SLIC Control 2.

SLIC3

I/O

SLIC Control 3.

SLIC4

I/O

SLIC Control 4.

SLIC5

I/O

SLIC Control 5.

1 68 67 66 65 64

DCL

I
C

INT

I
C

63 62 61

I
C

DGND

VDDb

I
C

RONc

I
C

AGNDc

41 42 43

VDDc

VDD

RONb

VDD

I
C

AGNDb

SLIC0a

VDDa

FILTV

PVCO

SGND

SLIC5b

DGND

SLIC2b

VFROPa

SLIC1a

VFXIa

PVCOIN

PLLT

AGNDa

SLIC4b

SLIC3b

VFRONa

SLIC1d

VFXId

DGND

AGNDd

SLIC4c

SLIC3c

VFRONd

VDD

VFROPd

BCLK

VDDd

SLIC5c

DGND

SLIC0d

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Pin Information

(continued)

Table 4. Pin Assignments, 68-Pin PLCC, Common Functions

Pin

Name

Type

Name/Description

Serial Data Output. This is a 3-state output.

Serial Data Input.

DCLK

Serial Data Clock Input.

Chip Select Input. This lead determines the interval that the serial interface is
active.

INTS

Serial Interface Select. Leaving this lead open places the serial interface in the nor-
mal mode; grounding it places the interface into the byte-by-byte mode. This lead
has an internal pull-up.

FILTV

PWR

Frequency Synthesizer Power (5 V). This pin must be tied to V

PVCOIN

Internal Test Point. Do not connect to this lead.

PVCO

Internal Test Point. Do not connect to this lead.

PLLT

Synthesizer Test Point. Do not connect to this lead.

SGND

GND

Synthesizer Ground. Connect to digital ground. A common AGND, DGND, SGND
plane is highly recommended.

24, 45,

58, 68

DGND

GND

Digital Ground. Logic ground and return for logic power supply. A common AGND,
DGND, SGND plane is highly recommended.

28, 40,

55, 66

PWR

Digital Power Supply (5 V).

PCM Frame Strobe Input. This 8 kHz clock must be derived from the same source
as BCLK.

BCLK

PCM Bit Clock Input. This lead is used to develop internal clocks for certain clock
rates.

59 DX

PCM Transmit Data Output. This is a 3-state output.

PCM Receive Data Input.

RST

Power-On Reset. A low causes a reset of the entire chip. This pin may be con-
nected to DGND with a 0.1

F capacitor for a power-on reset function, or it may be

driven by external logic. This lead has an internal pull-up.

No Connect. This pin may be used as a tie point.

Agere Systems Inc.

Preliminary Data Sheet
September 2001

T8535B/T8536B Quad Programmable Codec

Pin Information

(continued)

5-8885 (F)

Figure 4. 100-Pin TQFP Pin Diagram

Table 5. Pin Assignments, 100-Pin TQFP, Per-Channel Functions

Ckt

Name

Type

Name/Description

AGND

GND

Analog Ground. A common AGND, DGND, SGND plane is highly rec-
ommended.

PWR

Analog Power Supply.

Voice Frequency Transmit Input. This node requires a 10 M

20 M

resistance to AGND. The value is dependent upon the gain of

the XAG amplifier (register 146). 20 M

can be used for any gain

setting, 10 M

can only be used for XAG gain settings of 0 dB and

+6.02 dB.

Voice Frequency Receive Output, Positive Polarity. This pin can
drive 2000

(or greater) loads.

Voice Frequency Receive Output, Negative Polarity. This pin can
drive 2000

(or greater) loads.

SLIC0

I/O

SLIC Control 0.

SLIC1

I/O

SLIC Control 1.

100

SLIC2

I/O

SLIC Control 2.

SLIC3

I/O

SLIC Control 3.

SLIC4

I/O

SLIC Control 4.

SLIC5

I/O

SLIC Control 5.

FILTV

DX1

DCL

INT

I
C

NC
NC

SGND

SLIC1a
SLIC0a

NC
NC
NC
NC

ONa

OPa

AGNDa

SLIC5b
SLIC4b

DGND

SLIC3b

SLIC2b
SLIC1b

I
C

ONb

VDDb

AGNDb

AGNDc

ONc

I
C

TSX0
DR0
DX0
DGND
NC
BCLK
FS
V

SLIC1d
SLIC0d
NC
NC
NC
NC
NC
NC
VF

ONd

OPd

AGNDd
SLIC5c

DGND

RST

I
C

TSX

DR1

52
51

SLIC4c

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Pin Information

(continued)

Table 6. Pin Assignments, 100-Pin TQFP, Common Functions

Pin

Name

Type

Name/Description

FILTV

PWR

Frequency Synthesizer Power (5 V). This pin must be tied to V

2, 3, 7--10,

12, 15, 22, 32,

33, 35,

37--40,

44, 50,

59--64, 70,

85, 91--96

No Connect. This pin may be used as a tie point.

SGND

GND

Synthesizer Ground. Connect to digital ground. A common AGND, DGND,
SGND plane is highly recommended.

20, 51, 71, 84

DGND

GND

Digital Ground. Logic ground and return for logic power supply. A common
AGND, DGND, SGND plane is highly recommended.

25, 45, 67, 83

PWR

Digital Power Supply (5 V).

PCM Frame Strobe Input. This 8 kHz clock must be derived from the same
source as BCLK.

BCLK

PCM Bit Clock Input. This lead is used to develop internal clocks for certain
clock rates.

72 DX0

PCM Transmit Data Output 0. This is a 3-state output.

DR0

PCM Receive Data Input 0.

TSX0

Backplane Line Driver Enable 0 (Active-Low). Normally, these open-drain
outputs are floating in a high-impedance state. When a time slot is active on
DX0, this output pulls low to enable a backplane line driver.

DX1

PCM Transmit Data Output 1. This is a 3-state output.

DR1

PCM Receive Data Input 1.

TSX1

Backplane Line Driver Enable 1 (Active-Low). Normally, these open-drain
outputs are floating in a high-impedance state. When a time slot is active on
DX1, this output pulls low to enable a backplane line driver.

RST

Power-On Reset. A low causes a reset of the entire chip. This pin may be
connected to DGND with a 0.1

F capacitor for a power-on reset function, or it

may be driven by external logic. This lead has an internal pull-up.

Serial Data Output. This is a 3-state output.

Serial Data Input.

DCLK

Serial Data Clock Input.

Chip Select Input. This lead determines the interval that the serial interface is
active.

INTS

Serial Interface Select. Leaving this lead open places the serial interface in
the normal mode; grounding it places the interface into the byte-by-byte mode.
This lead has an internal pull-up.

Agere Systems Inc.

Preliminary Data Sheet
September 2001

T8535B/T8536B Quad Programmable Codec

Pin Information

(continued)

5-7187dF

Figure 5. 64-Pin TQFP Pin Diagram

Table 7. Pin Assignments, 64-Pin TQFP, Per-Channel Functions

Ckt

Name

Type

Name/Description

AGND

GND

Analog Ground. A common AGND, DGND, SGND plane is
highly recommended.

PWR

Analog Power Supply.

Voice Frequency Transmit Input. This node requires a
10 M

or 20 M

resistance to AGND. The value is dependent

upon the gain of the XAG amplifier (register 146). 20 M

can

be used for any gain setting, 10 M

can only be used for XAG

gain settings of 0 dB and +6.02 dB.

Voice Frequency Receive Output, Positive Polarity. This
pin can drive 2000

(or greater) loads.

Voice Frequency Receive Output, Negative Polarity. This
pin can drive 2000

(or greater) loads.

SLIC0

I/O

SLIC Control 0.

SLIC1

I/O

SLIC Control 1.

SLIC2

I/O

SLIC Control 2.

SLIC3

I/O

SLIC Control 3.

SLIC4

I/O

SLIC Control 4.

60 59 58 57 56 55 54 53 52

DCLK

DR1

I
C

51 50 49

I
C

SLIC0b

I
C

NDc

31 32

SLIC1b

NDb

SLIC0a

FILTV

SGND

DGND

SLIC2b

OPa

SLIC1a

AGNDa

SLIC4b

SLIC3b

ONa

SLIC1d

DX0

DGND

AGNDd

ONd

OPd

BCLK

SLIC4c

SLIC0d

DX1

TSX0

DR0

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Pin Information

(continued)

Table 8. Pin Assignments, 64-Pin TQFP, Common Functions

Pin

Name

Type

Name/Description

FILTV

PWR

Frequency Synthesizer Power (5 V). This pin must be tied to V

SGND

GND

Synthesizer Ground. Connect to digital ground. A common AGND, DGND, SGND
plane is highly recommended.

11, 32,

44, 56

DGND

GND

Digital Ground. Logic ground and return for logic power supply. A common AGND,
DGND, SGND plane is highly recommended.

15, 27,

41, 55

PWR

Digital Power Supply (5 V).

PCM Frame Strobe Input. This 8 kHz clock must be derived from the same source
as BCLK.

BCLK

PCM Bit Clock Input. This lead is used to develop internal clocks for certain clock
rates.

45 DX0

PCM Transmit Data Output 0. This is a 3-state output.

DR0

PCM Receive Data Input 0.

TSX0

Backplane Line Driver Enable 0 (Active-Low). Normally, these open-drain outputs
are floating in a high-impedance state. When a time slot is active on DX0, this output
pulls low to enable a backplane line driver.

DX1

PCM Transmit Data Output 1. This a 3-state output.

DR1

PCM Receive Data Input 1.

TSX1

Backplane Line Driver Enable 1 (Active-Low). Normally, these open-drain outputs
are floating in a high-impedance state. When a time slot is active on DX1, this output
pulls low to enable a backplane line driver.

RST

Power-On Reset. A low causes a reset of the entire chip. This pin may be con-
nected to DGND with a 0.1

F capacitor for a power-on reset function, or it may be

driven by external logic. This lead has an internal pull-up.

Serial Data Output. This is a 3-state output.

Serial Data Input.

DCLK

Serial Data Clock Input.

Chip Select Input. This lead determines the interval that the serial interface is
active.

INTS

Serial Interface Select. Leaving this lead open places the serial interface in the nor-
mal mode; grounding it places the interface into the byte-by-byte mode. This lead
has an internal pull-up.

Agere Systems Inc.

Preliminary Data Sheet
September 2001

T8535B/T8536B Quad Programmable Codec

Functional Description

Clocking Considerations

The PCM bus uses BCLK as the bit clock and the one-
going edge of FS to determine the location of the
beginning of a frame. These two clocks must be
derived from the same source. Internally, the device
develops all the internal clocks with a phase-locked
loop that uses BCLK as the timing source. BCLK and
FS must be continuously present and without gaps in
order for the device to operate correctly.

DCLK is used to clock the internal serial interface and
may be asynchronous to the other clocks. There is no
need to derive this clock from the same source as the
other clocks. The serial bus may be operated at any
speed up to 4.096 Mbits/s. DCLK can be gapped.
There is no limit on the number of devices on the same
serial bus.

The Control Interface

The device is controlled via a series of memory loca-
tions accessed by a serial data connection to the exter-
nal master controller. This interface operates using the
chip select lead to enable transmission of information.
All chip functions are enabled or disabled by setting or
clearing bits in the control memory. Filter coefficients
and gain adjustments are also stored in this memory.

The codec has both a serial input lead and a serial out-
put lead. These may be used individually for a 4-wire
serial interface, or tied together for a 2-wire interface.
The line driver circuitry is capable of driving relatively
high currents so that in the event that the line is long
enough to show significant transmission line effects, it
can be terminated in the characteristic impedance at
each end with resistors to V

and ground.

All data transfers on the serial bus are byte oriented
with the least significant bit (shown in this data sheet as
bit 0) transmitted first, followed by the more significant
bits. For data fields, the least significant byte of the first
data byte is transmitted first, followed by the more sig-
nificant bytes, each byte transmitted LSB first. This for-
mat is compatible with the serial port on most
microcontrollers.

Modes

There are two different modes of operation for the
serial interface: the normal mode and the byte-by-byte
mode. These two modes differ in the data clocking and
the manner in which CS is used to control the transfer.
Note that the CS lead is used to control the transfer of
serial data from master controller to slave codec and in
the reverse direction.

In normal mode (INTS pin open), the CS lead must go
low for the duration of the transfer. CS is latched by
DCLK on a positive-going clock edge. DI is latched by
DCLK on a negative-going clock edge. DCLK may be
continuous, but only needs to be present to clock data
when CS is low (gapped clock). When using gapped
clock, DCLK can remain high or low when CS is high.
The only error check performed by the codec is to
verify that CS is low for an integral number of bytes.
Detection of an active chip select for other than an
integral multiple of 8 bits results in the operation being
terminated. The next active excursion of chip select will
be interpreted as a new command; hence, the serial
I/O interface can always be initialized by asserting CS
for a number of clock periods that is not an integral
multiple of 8. CS is captured using DCLK, so DCLK
must be transitioned to perform this initialization.

The byte-by-byte mode (INTS pin tied to ground) uses
CS to control each byte of the transfer. In this mode,
CS goes low for exactly 8 bits at a time, corresponding
to a 1-byte transfer either to or from the codec chip.
DCLK can be continuous or gapped. When using a
gapped clock, DCLK can remain high or low when CS
is high. CS and DI are latched on a positive-going clock
edge. Repeated transitions of CS are used to control
subsequent bytes of data to/from the codec. For a write
command in this mode, CS must go low for each byte
of the transfer until the transfer is complete. For a read
command, CS will go low for each of the 3 bytes of the
read command transferred to the device, then low
again for each byte to be read. Notice that the total
number of bytes transferred (and excursions on CS) is
N + 3, where N is the number of bytes to be read in the
command. This mode of operation is useful in cases
where the master is a microprocessor with a built-in
UART that transfers 1 byte at a time. Error detection is
limited to detection of an active CS for other than an
integral multiple of 8 bits. Recovery is the same as nor-
mal mode.

Flow control can be accomplished by suspending the
transitions on DCLK by holding either state. During the
data transfer, CS must remain low while clock transi-
tions are suspended with DCLK in either state.

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Functional Description

(continued)

The Control Interface

(continued)

Protocol

The format of the command protocol is shown in Fig-
ures 6 and 7.

The control interface operates with one external master
controller and multiple slave codec devices. Each
transfer is initiated by the master, and the slave
responds for either read operations or the fast scan
mode. The slave does not check the bus for activity
prior to transmitting; it only checks for an active CS.
The master should allow for a wait between the end of
a read command until CS becomes active for the read
data. The master must refrain from sending additional
commands to the slave chip until the response is
received. On a 4-wire bus, commands to other devices
may be initiated before the response is received, but
care in generating the CS function is needed to ensure
that the multiple responses do not interfere. It should
be noted that multiple memory locations can be
accessed in the same command by setting the data

field length field to the desired number of bytes to be
transferred. If flow control is desired, it must be per-
formed by using separate commands, each transfer-
ring smaller blocks of information, or by controlling the
serial clock (gapping the serial clock), or with CS in the
case of byte-by-byte mode.

There is no response from the slave to the master for a
write operation. The response to a read operation sim-
ply includes the data to be read in the data field. Com-
mands from the master controller include data for write
operations, but not for read operations.

All data is transmitted in a byte-oriented fashion with
the least significant bit of each byte transferred first.
Multibyte fields are transferred least significant byte
first in both directions. The data field will contain the
first addressed data location first, with subsequent data
locations transmitted in ascending order.

Since the coefficients and gains are stored in volatile
memory, all the coefficients and gains must be loaded
after powerup. There is, however, no need to reload
them when switching from active to standby modes, or
vice versa.

Agere Systems Inc.

Preliminary Data Sheet
September 2001

T8535B/T8536B Quad Programmable Codec

Functional Description

(continued)

The Control Interface

(continued)

Protocol (continued)

* Location of memory bank selection. All user controls are in memory bank 0; other memory banks contain internal state information for the

device.

Note: Data field length is in bytes for all operations. All data is transmitted in bytes with the LSB for each byte transmitted first. For 16-bit mem-

ory operations, the least significant byte of the first memory location is transmitted first, followed by the most significant byte; each byte is
transmitted LSB first. Additional memory locations are loaded in ascending sequence.

Figure 6. Command Frame Format, Master to Slave, Read or Write Commands

Note: All data is transmitted in bytes with the LSB for each byte transmitted first. For memory operations, the least significant byte of the first

memory location is transmitted first, followed by the most significant byte, each byte transmitted LSB first. Additional memory locations
are loaded in ascending sequence.

Figure 7. Command Frame Format, Slave to Master, Read Commands

LSB

MSB LSB

COMMAND (8 bits)

START ADDRESS (8 bits)

DATA FIELD LENGTH (8 bits)

DATA FIELD (VARIABLE LENGTH) WRITE OPERATIONS ONLY

TIME

MSB

LSB

START ADDRESS:

MSB

LSB

DATA FIELD LENGTH:

MSB

LSB

COMMAND:

CKT

SELECT

COMMAND

CKT SELECT:

CKT a:
CKT b:
CKT c:
CKT d:

00
01
10
11

COMMANDS: FAST SCAN MODE:

WRITE MEMORY:
WRITE ALL CHANNELS:
READ MEMORY:

10
01
11
00

LSB

DATA FIELD (VARIABLE LENGTH) READ OPERATIONS ONLY

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Functional Description

(continued)

The Control Interface

(continued)

Read Command

The normal flow of information to the master controller is always in response to a read command. All control mem-
ory locations are accessed in 8-bit bytes. All read commands from the master controller require a response from
the addressed codec. It is the responsibility of the master controller to ensure that only one device is transmitting
on the serial interface line at any one time. The master controller also must ensure that the CS lead goes high after
transferring the 3-byte sequence used to initiate the read, and then it goes low again for the response. In this case,
it should be noted that the device expects that the second time CS goes low the data is to be sent to the master;
thus, it does not interpret the DI lead as containing a valid instruction during that CS excursion and a write during
this time is not recommended. Note also that the CS lead must allow the number of bytes sent in a read command
to be transferred before a subsequent command can be received by the codec. Figures 12--15 illustrate normal or
byte-by-byte operation with continuous or gapped DCLKs. Like a write command, transitions, not frequency, are
critical with regard to gapped DCLK operation.

0079B

* Provides sufficient wait time to access read data.
Allow a minimum of 244 ns before the next command frame.

Note: Data field length of 1 shown.

Figure 12. Read Operation, Normal Mode (Continuous DCLK)

COMMAND FRAME

DCLK

COMMAND

START ADDRESS

DATA

LENGTH

WAIT

1.5

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Functional Description

(continued)

The Control Interface

(continued)

Read Command (continued)

0075B

* Shows customary usage, CS not required to go high between bytes.
Provides sufficient wait time to access read data.
Allow a minimum of 244 ns before the next command frame.

Note: Data field length of 1 shown.

Figure 15. Read Operation, Byte-by-Byte Mode (Continuous DCLK)

Fast Scan Mode

The fast scan mode allows a single byte command to read two SLIC control leads for all four channels with a
1-byte reply. This mode significantly speeds up the normal scanning for off-hook, ring trip, and ring ground detec-
tion. This special command sequence allows the controlling microprocessor to fast scan 2 bits in the SLIC control
byte of each of the four channels. The command code is (00000010)

; there are no start address or length fields.

The command returns only a single byte of data, formatted as shown in Table 9.

Table 9. Bit Assignments for Fast Scan Mode

Bit

Reported Status

0 (LSB)

Channel 0, bit 0 (ckt a, address 160, bit 0)

Channel 0, bit 1 (ckt a, address 160, bit 1)

Channel 1, bit 0 (ckt b, address 160, bit 0)

Channel 1, bit 1 (ckt b, address 160, bit 1)

Channel 2, bit 0 (ckt c, address 160, bit 0)

Channel 2, bit 1 (ckt c, address 160, bit 1)

Channel 3, bit 0 (ckt d, address 160, bit 0)

7 (MSB)

Channel 3, bit 1 (ckt d, address 160, bit 1)

DCLK

COMMAND

START

LENGTH

DATA

COMMAND FRAME

WAIT

1.5

ADDRESS

Agere Systems Inc.

Preliminary Data Sheet
September 2001

T8535B/T8536B Quad Programmable Codec

Functional Description

(continued)

The Control Interface

(continued)

Write All Channels

The write all channels command causes all four channels to be loaded with the same coefficients with a single data
transfer from the master controller. This allows for a faster initialization of the device after a powerup. This com-
mand should be used with caution since it affects all four channels. The normal memory write and read commands
affect only one channel.

Reset Functionality

0071c

Figure 20. Hardware Reset Procedure

The reset function allows the internal logic of the device to be set to a known initial condition, either externally by
activating the reset lead, or on a per-channel basis through the microprocessor interface by setting and then clear-
ing bits, if required, in address RESCTRL (address 128). These two reset functions have different effects, and
each of the software reset functions is a subset of the hardware reset functionality. The primary difference is in the
treatment of the internal memory. The hardware reset is assumed to be a result of a catastrophic hardware event,
such as a loss of power, loss of BCLK, or an initial powerup. Accordingly, the assumption is made that the internal
memory does not contain valid data, and default values for all memory locations are loaded. A software reset, how-
ever, can only be initiated if the device is operational (at least the microprocessor interface), so the contents of the
memory may indeed be valid; thus, the resets may be more specific. Additionally, software resets only affect the
selected channel.

BCLK

RST

DEVICE

CAN NOW BE PROGRAMMED

RUNS CONTINUOUSLY

WAIT

5 ms

1 ms

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Functional Description

(continued)

Reset Functionality

(continued)

A 0.1

F capacitor between the RST lead and ground

will effectively hold the lead low long enough to reset
the device on powerup, allowing for a cost-effective
power-on reset function. Notice that the memory must
be reloaded through the serial interface after a hard-
ware reset function. For proper operation, it is neces-
sary for FS and BCLK to be present and stable during
a reset. A wait period for the internal PLL to stabilize is
required after reset goes high. See the timing diagram
shown in Figure 20 for the proper hardware or power-
on reset procedure.

For a software reset, the control memory should not be
accessed for a minimum of 256

s following the reset.

Memory Control Mapping

Several memory locations are used to control the
device. The software interface tables (Table 20, Mem-
ory Mapping, and Table 21, Control Bit Definition) show
the memory assignments that are useful in call pro-
cessing and system testing. It should be noted that
other memory locations are used by the device to hold
intermediate results and other device state information.
Writing to these other locations can cause serious dis-
ruptions in the operation of the device and should be
avoided.

Standby Mode

The device enters a low-power standby mode with
powerup or software reset, or by programming the
CHACTIVE register 129, bit 0. In standby mode, the
control interface is active, capable of writing or reading
registers. SLIC read and write data latches are also
active. Analog signals at VF

I and PCM signals at D

are ignored in this mode. BCLK must be present for
proper standby mode operation.

Test Capabilities

The device has several built-in test capabilities that can
be used to verify correct operation of the signal pro-
cessing of the line card. These test functions are
accessed in several different control addresses. Five
loopback modes are employed: the first for the digital
signal from the PCM bus to be looped back to the PCM
bus. This loopback facility can be used to verify correct
operation of the PCM bus interface logic, as well as
operation of the PCM bus. The second digital loopback
function allows complete testing of the digital process-
ing capability of the codec by looping the data back at
the analog/digital conversion interface. The third loop-
back function can be used to check the operation of all
the signal processing performed in the device, includ-
ing the conversions to/from analog. These digital loop-
back functions can be used with tone generation and
reception via the PCM bus.

The first analog loopback facility is at the digital side of
the delta-sigma converters and loops analog transmit
data back to the analog receive path. The second ana-
log loopback is at the PCM bus interface and loops the
transmit data from the line back to the receive path.

By assigning the transmit and receive time slots identi-
cally, a loopback arrangement at the PCM bus can be
effectively programmed for signals generated on the
line side of the codec. This mode is useful for testing
from the line side through the entire device.

SLIC Control Capabilities

Memory locations 158, 159, and 160 are used to con-
trol six bidirectional latches that are intended to allow
the serial interface to control other line card devices,
such as ringing/test switches, telecom electromechani-
cal relays, and SLIC devices. When the TTL latches
are configured as outputs, external devices should be
set up to sink current from the latch. Location 158 sets
the operational mode of these latches as either inputs
or outputs. Location 159 specifies what is to be written
on the latch leads driven by the device. Location 160
reports the actual state of these leads. It should be
noted that a channel control reset forces all of these
external leads, except those corresponding to bits 2
and 3, to the high-impedance state, so any inputs con-
nected to bits 0, 1, 4, and 5 should have appropriate
pull-up or pull-down resistors (off-chip, if required) to
force the external device into a known state at power-
up or in the event of a reset. Bits 2 and 3 will reset to
outputs with a value of zero.

Agere Systems Inc.

Preliminary Data Sheet
September 2001

T8535B/T8536B Quad Programmable Codec

Functional Description

(continued)

SLIC Control Capabilities

(continued)

The fast scan mode allows for a minimal data transfer
on the serial bus to monitor bits 0 and 1 of the SLIC
data memory location (159). If these two bits are wired
as inputs to the off-hook and/or ring ground detection
circuits, a convenient method of rapidly scanning for
these two functions is obtained. Bits 2 and 3 default to
outputs; thus, they are convenient to provide control of
the SLIC state. In any event, all six leads are program-
mable for maximum flexibility.

Suggested Initialization Procedures

It is suggested that upon powerup, a hardware reset be
used to set the device into a known state. The serial
interface should then be used to load the memory
addresses that differ from the default values (the write
all channels command is convenient for this function). If
other devices are controlled by the SLIC data memory
location, then it also should be loaded with a known
configuration. After the completion of this sequence,
the device is ready to be activated. Depending on the
application, the next step may either be normal opera-
tion or a set of test sequences. After the initialization of
the memory, the device and associated line card
devices can be controlled by using memory locations

130, 131, 145, 155, 156, 157, 158, 159, and 129; that
is, by supplying the PCM bus time-slot addresses,
switching the SLIC into the proper mode, and activat-
ing the codec. Within memory location 129, the codec
would normally be placed into active mode, with both
directions of the PCM bus enabled at the start of a call.
At the completion of a call, the codec should be placed
into standby mode and the PCM bus disabled. Great
caution should be used when changing the memory
while the codec is in active mode, since termination
impedances, balance impedances, and gains may
change. These changes are likely to yield undesirable
system effects. It is safe to refresh coefficients that are
known to be unchanging in the application. It is always
possible to read the memory to verify its contents with-
out deleterious effects on codec operation. Normal
operation would load the memory and perform all gain
adjustments while the codec is in standby mode.
Under no circumstances should memory above
address 162 be written, since this section of memory is
used for state data and intermediate results. Also, all
reserved addresses should not be written. Changing
this information may have deleterious effects on sys-
tem operation.

Signal Processing

Figure 21 details the signal processing functional
blocks of one channel of the codec.

0497F

* Programmable blocks.

Figure 21. Internal Signal Processing

SPEED

FROM

PCM

BUS

GRX1

GAIN

8 kHz

COMP

TO LIN.

TRANSFER

XLPF

GAIN

TWEAKING

GRX2

SINC

D/A

1-bit

D/A

RCF

SMF

0 dB

BAL

32 kHz

4096 kHz

LPF

DIGITAL

SLIC

PCM

BUS

GAIN

GTX2

LIN.TO

COMP

YLPF

GAIN

TWEAKING

GTX1

SINC

FROM

0 dB TO 24 dB

SLIC

TRANSFER

TEQ

A/D

LPF

RTZ

8 STEPS

IN 5 STEPS

XAG

ANALOG

CTZ

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational section of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.

1. Sparse copper, one layer test board.
2. Four layer, JEDEC test board.

Operating Ranges

Handling Precautions

Although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo-
sure to electrostatic discharge (ESD) during handling and mounting. Agere Systems Inc. employs a human-body
model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation.
ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide stan-
dard has been adopted for the CDM. A standard HBM (resistance = 1500

, capacitance = 100 pF) is widely

accepted and can be used for comparison.

Parameter

Symbol

Min Max

Unit

Storage Temperature Range

stg

150

°C

Power Supply Voltage (all leads designated power)

DDX

6.5

Negative Voltage on Any Lead with Respect to Ground

0.25

Thermal Resistance, Junction to Ambient:

68-Pin PLCC

44-Pin PLCC

64-Pin TQFP

100-Pin TQFP

--
--
--
--

43
49
40
30

°C/W
°C/W
°C/W
°C/W

Package Power Dissipation

SLIC Control Interface Latches, Current per Device

160

Parameter

Symbol

Min Max

Unit

Ambient Operating Temperature

°C

Operating Junction Temperature

125

°C

Power Supply Voltage (all leads designated power)

DDX

4.75

5.25

HBM ESD Threshold Voltage

Device

Voltage

T8535B/T8536B

>2000

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Electrical Characteristics

(continued)

Analog Interface

The following specifications pertain to the analog SLIC interface for each channel.

Table 11. Analog Interface

Table 12. Power Dissipation

Power measurements are made at BCLK = 2.048 MHz, DCLK = 2.048 MHz, no inputs from serial interface, inter-
face latches set as outputs, and outputs unloaded.

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Input Resistance

VFxI

0.25 < V

< (V

DDX

0.25) V.

100

300

dc Input Voltage

VFxI

Relative to ground.

Signal should be capacitively

coupled to VF

1.8

2.0

2.2

Load Resistance at VF

OP and VF

(differential)

5-8881F

7.5

Output Resistance

Digital input code correspond-

ing to idle PCM code (

-law).

Output Offset Voltage Between VF

and VF

Digital input code correspond-

ing to idle PCM code (

-law).

100

Output Offset Voltage Between VF

and VF

ON, Standby Mode

OSS

= 100 k

Common-mode Output Voltage, Active

Mode

OCM

Digital input code correspond-

ing to alternating ± zero

-law

PCM code.

2.0

Common-mode Output Voltage, Standby

Mode

OCMS

1.7

2.0

2.3

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

All Channels in Standby, Dissipation for One Channel

DDS

One Channel Active, Dissipation for Active Channel

DD1

225

Four Channels Active, Dissipation for One Channel

DD1

125

Agere Systems Inc.

Preliminary Data Sheet
September 2001

T8535B/T8536B Quad Programmable Codec

Electrical Characteristics

(continued)

Gain and Dynamic Range

Table 13. Gain and Dynamic Range

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Absolute Levels

GAL

Maximum 0 dBm0 levels (1004 Hz):

I (encoder milliwatt), all programma-

ble transmit gains set to 0 dB.

RCV (decoder milliwatt), termination

impedance off, all programmable

receive gains set to 0 dB.

2.80

5.29

Vp-p

Absolute Levels

GAL

Minimum 0 dBm0 levels (1004 Hz):

I (encoder milliwatt),

XAG = 24 dB, GTX1 = 6 dB,

GTX2 = 0 dB.

RCV (decoder milliwatt), termination

impedance off, GRX1

= 0 dB,

GRX2

6 dB.

87.5

2.63

mVp-p

Vp-p

Absolute Maximum Volt-

age Swings

GAL

OP to VF

ON (differential).

--
--

3.2

5.28

Vp-p
Vp-p

Transmit Gain Absolute

Accuracy

GXA

Transmit gain programmed for maxi-

mum 0 dBm0 test level, measured devi-

ation of digital code from ideal

0 dBm0 level at DX digital outputs, with

transmit gain set to 0 dB:

20 °C to 70 °C

0 °C to 85 °C

40 °C to +85 °C.

0.25

0.30

±0.15

--
--

0.25
0.30

dB
dB
dB

Transmit Gain Variation

with Programmed Gain

GXAG

Measured transmit gain over the range

from maximum to minimum, calculated

deviation from the programmed gain rel-

ative to GXA at 0 dB, V

= 5 V.

0.1

Transmit Gain Variation

with Frequency, 600

Resistive Source
Impedance and Syn-
thesized Termination
Impedance

GXAF

Relative to 1004 Hz, minimum

gain < GX < maximum gain,

I = 0 dBm0 signal, path gain

set to 0 dB:

f = 16.67 Hz

f = 40 Hz
f = 50 Hz
f = 60 Hz

f = 200 Hz

f = 300 Hz to 3000 Hz

f = 3140 Hz
f = 3380 Hz
f = 3860 Hz

f = 4600 Hz and above.

--
--
--
--

3.0

0.125

0.57

0.735

--
--

2.0

±0.04

0.01

0.03

8.8

30
0

0.135
0.125
0.015

8.98

dB
dB
dB
dB
dB
dB
dB
dB
dB
dB

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Electrical Characteristics

(continued)

Gain and Dynamic Range

(continued)

Table 13. Gain and Dynamic Range (continued)

* Applied to all four channels.

RTZ

and CTZ paths open.

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Transmit Gain Variation

with Signal Level

GXAL

Sinusoidal test method*,

reference level = 0 dBm0

I =

40 dBm0 to +3 dBm0

I =

50 dBm0 to

40 dBm0

I =

55 dBm0 to

50 dBm0.

0.25

0.50

1.40

--
--
--

0.25
0.50
1.40

dB
dB
dB

Receive Gain Absolute

Accuracy

GRA

Receive gain programmed to

6 dB,

apply 0 dBm0 signal to IPCM, mea-

sure V

RCV

, R

= 100 k

differential:

20 °C to 70 °C

0 °C to 85 °C

40 °C to +85 °C.

0.25

0.30

±0.15

--
--

0.25
0.30

dB
dB
dB

Relative Gain, VF

OP to

Digital input 0 dBm0 signal,

f = 300 Hz to 3400 Hz.

0.01

Relative Phase, VF

to VF

Digital input 0 dBm0 signal,

f = 300 Hz to 3400 Hz.

0.25

Degrees

Receive Gain Variation

with Programmed Gain

GRAG

Measure receive gain over the range

from maximum to minimum setting,

calculated deviation from the pro-

grammed gain relative to GRA at

0 dB, V

= 5 V.

0.1

Receive Gain Variation

with Frequency, 600

Resistive Termination

GRAF

Relative to 1004 Hz, digital input =

0 dBm0 code, minimum gain < GR <

maximum gain, 0 dB path gain:

f = below 3000 Hz

f = 3140 Hz
f = 3380 Hz
f = 3860 Hz

f = 4600 Hz and above.

0.125

0.57

0.735

--
--

±0.04
±0.04

0.550

10.7

0.125
0.125
0.015

8.98

dB
dB
dB
dB
dB

Receive Gain Variation

with Signal Level

GRAL

Sinusoidal test method*,

reference level = 0 dBm0:

IPCM digital level =

40 dBm0 to +3 dBm0

IPCM digital level =

50 dBm0 to

40 dBm0

IPCM digital level =

55 dBm0 to

50 dBm0.

0.25

0.50

1.40

0.25

0.50

1.40

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Timing Characteristics

Control Interface Timing

Serial Control Port Timing

Table 17. Serial Control Port Timing (See Figures 22 and 23.)

* The t

SXBDLY

delay is from either DCLK or CS, whichever transition is later, for the first bit of the byte.

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

DCLK

Clock Frequency (all commands)

4096

kHz

CSSETUP

Chip Select Setup Time, Normal Mode

CLK

= 4.096 MHz

CSHOLD

Chip Select Hold Time, Normal Mode

CLK

= 4.096 MHz

SXDLY

Output Data Delay, Normal Mode

CLK

= 4.096 MHz

SDHOLD

Input Data Hold Time, Normal Mode

CLK

= 4.096 MHz

SDSETUP

Input Data Setup Time, Normal Mode

CLK

= 4.096 MHz

SDZ

Output Data, High Impedance

CLK

= 4.096 MHz

100

RISE

Clock Edge Rise Time

CLK

= 4.096 MHz

FALL

Clock Edge Fall Time

CLK

= 4.096 MHz

RISE

FALL

Line Driver Rise/Fall Time (DO output)

= 15 mA,

LOAD

= 100 pF

30 ns

CSBHOLD

Chip Select Hold Time, Byte-by-Byte Mode

CLK

= 4.096 MHz

SXBDLY

Output Data Delay, Byte-by-Byte Mode

CLK

= 4.096 MHz*

CSBSETUP

Chip Select Setup Time, Byte-by-Byte Mode

CLK

= 4.096 MHz

SDBHOLD

Data Hold Time, Byte-by-Byte Mode

CLK

= 4.096 MHz

SDBSETUP

Data Setup Time, Byte-by-Byte Mode

CLK

= 4.096 MHz

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Timing Characteristics

(continued)

PCM Interface Timing

Single-Clocking Mode

Frame sync (FS) signifies the start of frame on the
PCM bus for all four channels. FS occurs every 125

at an 8 kHz rate. FS must be synchronous with the
PCM bus clock (BCLK) and must be high for a mini-
mum of one BCLK period. The PCM interface operates
using fixed data rate timing, data timing for both trans-
mit and receive are controlled by BCLK. BCLK can
be any value from 512 kHz (eight time slots) to
16.384 MHz (256 time slots) as defined by Table 18.

The PCM bus transfers the most significant bit of the
time slot first, consistent with normal telephony prac-
tice. Figure 24 shows FS, DX, and DR beginning on the

rising edge of BCLK and being latched on the falling
edge of BCLK. Figure 25 shows DX and DR beginning,
and FS being latched on the rising edge of BCLK, and
DX and DR being latched on the falling edge of BCLK.

Figure 24 portrays a bit offset of zero, and Figure 25
portrays a transmit bit offset of one and a receive bit
offset of two. Bit offset skews the PCM transmit and/or
receive data independently from the FS reference. Up
to seven BCLK cycles of bit offset can be employed on
a per-channel basis. This flexibility can accommodate
special timing requirements.

Linear coding is transmitted and received in two con-
secutive 8-bit time slots. TSX0 or TSX1 is active (low)
when DX data is transmitting (8 bits for companded
code, 16 bits for linear code).

Table 18. PCM Interface Timing: Single-Clocking Mode (See Figures 24 and 25.)

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

BCLK

Allowable BCLK Frequencies

--
--
--
--
--
--
--
--

512

1024
1536
2048
3072
4096
8192

16384

--
--
--
--
--
--
--
--

kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz

Jitter of BCLK

100 ns in

100 ms =

1 ppm

BCLK Duty Cycle

FSSETUP

Frame Strobe Setup Time

CLK

= 16.384 MHz

FSHOLD

Frame Strobe Hold Time

CLK

= 16.384 MHz

FSWIDTH

Frame Strobe Width

FS synchronous with

BCLK

125

BCLK

XDLY

Output Data Delay

CLK

= 16.384 MHz

IDHOLD

Input Data Hold Time

CLK

= 16.384 MHz

IDSETUP

Input Data Setup Time

CLK

= 16.384 MHz

RISE

Clock Edge Rise Time

CLK

= 16.384 MHz

FALL

Clock Edge Fall Time

CLK

= 16.384 MHz

RISE

FALL

DX Output Rise/Fall Time

= 15 mA,

LOAD

= 100 pF

DXHIGHZ

DX Output Data Float on TS Exit

LOAD

= 0

TSXDELAY

Line Driver Enable Delay

TSXHIGHZ

Line Driver Enable Float on TS Exit

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Timing Characteristics

(continued)

PCM Interface Timing

(continued)

Double-Clocking Mode

As with the single-clocking mode, FS signifies the start
of frame on the PCM bus for all four channels and
occurs every 125

s at an 8 kHz rate. FS must be

synchronous with BCLK and must be high for a mini-
mum of one BCLK period. The PCM interface operates
using fixed data rate timing; data timing for both trans-
mit and receive are controlled by BCLK. In double-
clocking mode, however, BCLK runs at twice the PCM
data rate. BCLK can be any value from 512 kHz (data
rate of 256 kbits/s, 4 time slots) to 16.384 MHz (data
rate of 8192 kbits/s, 128 time slots) as defined by Table
19.

In Figure 26, detail A, the falling edge of the first BCLK
latches FS. The falling edge of the second BCLK
latches DR (receive bit offset of 1). DX starts on the ris-
ing edge of the first BCLK. The PCM bus transfers the
most significant bit of the data first.

The codec defaults to FS and DR being latched on the
first BCLK cycle. To latch DR on the second BCLK
cycle, program receive bit offset for 1 (RXBITOFF =
0x20). For every bit programmed (0 to 7), bit offset
shifts transmit or receive data by one BCLK cycle.
Therefore, in double-clock mode, the time-slot assign-
ment and bit offset registers need to be used in tandem
in order to achieve a full range of bit offset values. For
instance, in time-slot 0, bit offset will shift data up to
four bits. To shift data 5 to 8 bits, time slot 1 needs to
be selected.

Linear coding is not allowed in double-clocking mode.
TSX0 or TSX1 (not shown in Figure 26) is active (low)
when DX data is transmitting.

Note that the device reverts back to single-clock mode
if reset (address 128, bit 0). Internal states of the codec
can be reset without going out of double-clock mode
(address 128, bit 1).

Table 19. PCM Interface Timing: Double-Clocking Mode (See Figure 26.)

Note: DX load = 150 pF.

Symbol

Parameter

Signal

Min

Typ

Max

Unit

fBCLK

Allowable BCLK Frequencies

BCLK

--
--
--
--
--
--
--
--

512

1024
1536
2048
3072
4096
8192

16384

--
--
--
--
--
--
--
--

kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz

Jitter of BCLK

BCLK

100 ns in

100 ms =

1 ppm

tBCL

Clock Period

BCLK

1953

tR, tF

Clock Rise/Fall

BCLK

tWL, tWH

Pulse Width

BCLK

tBCL x 0.4

tBCL x 0.6

tR, tF

Frame Rise/Fall

tWFH

Frame Width High

tBCL

tWFL

Frame Width Low

tBCL

tSF

Frame Setup

tBCL

tHF

Frame Hold

tDDC

Data Delay Clock

tDDF

Data Delay Frame

tSD

Data Setup

tHD

Data Hold

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Software Interface

Table 20. Memory Mapping

With the exceptions noted, all of these memory locations may be read to determine the state of the controls con-
tained therein. In the following table, bit 0 is the LSB (transmitted first on the serial interface) and bit 7 is the most
significant bit of the byte. Unused bits in an address or multibyte address should be loaded as zero. All of the mem-
ory locations can be programmed on a per-channel basis.

Note that the entire coefficient set for a channel (or all four channels) may be loaded with one command.

Control

Name

Address

(Decimal)

# of

Bits

Used

Default

Value

Description

HBALTAPS

0--27

64--91

448

See Table 21

Balance impedance tap coefficients.

Reserved

28--63

92--127

These addresses have no function.

RESCTRL

128

0x00

Reset address. Writing a one in the used positions causes a
reset as defined by the bit definition. This reset remains in
force until the bit is written as a zero.

CHACTIVE

129

0x00

Standby/active control.

RXBITOFF

130

0x00

Bit offset for receive direction.

RXOFF

131

16 * channel # Time-slot assignment for receive direction.

GRX1

132--133

0x0400

Gain transfer for receive direction.

GRX2

134--135

0x01ac

Gain tweaking. Control of gain sensitive to impedance and
SLIC parameter choices, receive direction.

Reserved

136--139

This address has no function.

CTZCTRL

140--143

07ed0000

CTZ bleed coefficients.

Reserved

144

This address has no function.

PCMCTRL2

145

0x00

PCM transmission and sampling edge control.

SDCTRL

146

0x19

RTZ, transmit analog gain (XAG), and digital loopback 3
controls.

SDTSI

147

17 * channel # Internal time-slot interchanger and loopback controls.

Default sets external pins to state referenced in this data
sheet.

GTX2

148--149

0x0400

Gain transfer for transmit direction.

ZEQTX

150--152

0x000000

Transmit line equalization.

GTX1

153--154

0x051a

Gain tweaking. Control of gain sensitive to impedance and
SLIC parameter choices, transmit direction.

TXBITOFF

155

4 or 5

0x00

Bit offset for transmit direction.

TXOFF

156

16 * channel # Time-slot assignment for transmit direction.

PCMCTRL1

157

0x00

PCM, companding, and loopback controls.

SLICTS

158

0x0c

SLIC 3-state control. Latch I/O.

SLICWR

159

0x00

Data to be written to the SLIC latches if the corresponding
bit is set in the SLICTS control word.

SLICRD

160

Current actual state of the SLIC leads. This will be the same
as SLICWR for those leads configured as outputs. All other
positions will reflect the actual state of the external lead. A
write operation to this word will be ignored, and within one
PCM frame (125

s), the data will be overwritten.

Reserved

161

This address has no function.

VERIFY

162

0x00

Test address for serial interface verification.

Agere Systems Inc.

Preliminary Data Sheet
September 2001

T8535B/T8536B Quad Programmable Codec

Software Interface

(continued)

The following table shows the control bit assignments in the memory control addresses. In all control bit cases, the
bit being set places the function into the active mode as defined in the function column.

Table 21. Control Bit Definition

Control Name

(Address, Decimal)

[Address, Hex]

Bit

Assignment(s)

Function

HBALTAPS

(0--27, 64--91)

[0x00--0x1b,

0x40--0x5b]

448

Balance impedance coefficients. Default value is 0x00 for all bytes except
for addresses 3 and 5, which are 0x80, and address 69, which is 0x88.

RESCTRL

(128)

[0x80]

2--7

Not used, load as zeros.

A one resets all other internal states. Control addresses are not reset.

A one resets all control addresses to default values. Note that setting this
bit will result in it and all others of this word becoming cleared on the next
PCM frame as a normal part of the reset functionality. Alternatively, hard-
ware reset can be used to reset all control and state functions. It is neces-
sary to wait at least 256

s after asserting this bit before initiating any

other serial I/O transactions.

CHACTIVE

(129)

[0x81]

1--7

Load as zeros.

Active/standby mode. A zero causes the channel to enter standby (low-
power) mode and disables the PCM interface for this channel. A one acti-
vates the channel and the corresponding PCM bus interface. Default is
zero.

RXBITOFF

(130)

[0x82]

5--7

Receive direction bit offset for the FS signal. Defaults to zero. These
3 bits can be thought of as the least significant bits (RXOFF contains the
more significant bits) of a bit counter that determines the location of the
first bit of the PCM data from FS.

0--4

Load as zeros.

RXOFF

(131)

[0x83]

0--7

Receive time-slot assignment. Defaults to (16 * channel number). Each
time slot represents 8 bits; allow for two time slots when using linear
mode or double-clock mode.

GRX1

(132--133)

[0x84--0x85]

0--10

Gain adjustment for gain transfer stage in receive direction. Defaults to
0x0400 (0 dB). This is an 11-bit multiply operation with a maximum gain of
two (6 dB). 0 dB is the maximum recommended setting.

GRX2

(134--135)

[0x86--0x87]

0--10

Gain adjustment for tweak gain stage in receive direction. Defaults to
0x01ac (

7.58 dB). This is an 11-bit multiply operation with a maximum

gain of two (6 dB). 0 dB is the maximum recommended setting.

CTZCTRL

(140--143)

[0x8c--0x8f]

0--30

Coefficients for the CTZ termination bleed. Defaults to 0x07ed0000.

Agere Systems Inc.

Preliminary Data Sheet

September 2001

T8535B/T8536B Quad Programmable Codec

Software Interface

(continued)

Table 21. Control Bit Definition (continued)

Control Name

(Address, Decimal)

[Address, Hex]

Bit

Assignment(s)

Function

PCMCTRL2

(145)

[0x91]

6--7

Load as zeros.

A one selects DX PCM port 1. A zero selects DX PCM port 0. Defaults
to zero. PCM port 1 is not available in all package types.

A one selects DR PCM port 1. A zero selects DR PCM port 0. Defaults
to zero. PCM port 1 is not available in all package types.

A one selects double-clocking mode. Defaults to zero (single-clocking
mode). A write to any channel affects all four channels.

A one starts transmit data on a falling BCLK edge. A zero starts transmit
data on a rising BCLK edge. Defaults to zero. A write to any channel
affects all four channels.

A one latches receive data on a rising BCLK edge. A zero latches
receive data on a falling BCLK edge. Defaults to zero. A write to any
channel affects all four channels.

A one latches FS on a rising BCLK edge. A zero latches FS on a
falling BCLK edge. Defaults to zero. A write to any channel affects all
four channels.

SDCTRL

(146)

[0x92]

Load as zero.

Enable digital loopback 3. Defaults to zero (no loopback).

3--5

RTZ gain. Defaults to 3 (equal level point value of 3 * 0.075 = 0.225).
Turn off by writing to zero.

0--2

Transmit analog gain (XAG). Defaults to
1 (6 dB) gain.

Bit Number

Function

(dB)

0.0

6.02

12.04

18.06

24.08

SDTSI

(147)

[0x93]

Load as zero.

Digital loopback, receive to transmit at the sigma-delta converters
(digital loopback 2). Defaults to zero (no loopback).

4--5

Analog channel feeding this digital channel in the transmit direction.
Defaults to channel number.

Send idle-channel code (alternating bits) to this analog receive path.
Defaults to zero (off).

Loopback from transmit to receive at the sigma-delta converters
(analog loopback 1). Defaults to zero (no loopback).

0--1

Digital channel feeding this analog receive channel. Defaults to channel
number.

GTX2

(148--149)

[0x94--0x95]

0--11

Gain control for gain transfer stage in transmit direction. Defaults to
0x0400 (0 dB). This is a 12-bit multiply operation with a maximum gain
of four (12 dB).

ZEQTX

(150--152)

[0x96--0x98]

0--20

Coefficients for the transmit equalization stage. Varies frequency
response and accommodates current-sensing SLICs. Defaults to
0x000000.

Agere Systems Inc.

Preliminary Data Sheet
September 2001

T8535B/T8536B Quad Programmable Codec

Software Interface

(continued)

Table 21. Control Bit Definition (continued)

Control Name

(Address, Decimal)

[Address, Hex]

Bit

Assignment(s)

Function

GTX1

(153--154)

[0x99--0x9a]

0--11

Gain control for tweak gain stage in transmit direction. Defaults to
0x051a (2.11 dB). This is a 12-bit multiply operation with a maximum
gain of four (12 dB).

TXBITOFF

(155)

[0x9b]

5--7

Transmit direction bit offset for the FS signal. Defaults to zero. These
3 bits can be thought of as the least significant bits (TXOFF contains the
more significant bits) of a bit counter that determines the location of the
first bit of the PCM data from FS.

0--4

Load as zeros.

TXOFF

(156)

[0x9c]

0--7

Transmit time-slot assignment. Defaults to (16 * channel number). Each
time slot represents 8 bits; allow for two time slots when using linear
mode or double-clock mode.

PCMCTRL1

(157)

[0x9d]

3-state transmit PCM interface. Defaults to zero. A one forces the PCM
interface into a high-impedance state during its assigned time-slot on
the PCM bus. Placing the channel in standby mode also forces a high-
impedance condition on the transmit interface.

Transmit zeros instead of data. Defaults to zero (off).

Linear mode significant bit. A one sets MSB first for both PCM transmit
data output and for PCM receive data input. A zero sets both PCM
paths to LSB first. Defaults to zero, LSB first.

Place idle-channel code on receive path. Defaults to zero (off).

Loopback receive to transmit at PCM conversion interface (digital
loopback 1). Defaults to zero (no loopback).

Loopback transmit to receive at PCM conversion interface (analog
loopback 2). Defaults to zero (no loopback).

Linear/companded mode. A one sets 16-bit linear mode with two adja-
cent time slots used. Linear data is in two's complement form. Linear
mode is only available when using single-clocking mode. A zero sets
companded mode with only one time slot used. Defaults to zero. Linear
mode is programmed as LSB or MSB first using bit 5 of this word.

-law or A-law. A one sets A-law mode, and a zero sets

-law mode.

Defaults to zero (

-law).

SLICTS

(158)

[0x9e]

6--7

Load as zeros.

0--5

Controls the drivers for the corresponding SLIC latches. A one enables
the lead as an output. Defaults to 0x0C (bits 2 and 3 set, the rest
cleared).

SLICWR

(159)

[0x9f]

6--7

Load as zeros.

0--5

SLIC data latches. If the corresponding bit in the SLICTS address is set
for an output, the device will drive the corresponding bit according to the
contents of this address. Writes are performed within 125

s. Wait

125

s before a subsequent write to the same channel or between write

all channel commands. Default is zero.

SLICRD

(160)

[0xa0]

6--7

Not used, ignore on read.

0--5

Reports the actual state of the SLIC leads. Anything written to this
address is ignored. Updates within 125

VERIFY

(162)

[0xa2]

0--7

Test location for serial interface. This location has no internal use, but
merely latches write data for the purpose of testing the serial interface.
This register does not clear with reset.

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