Data Addendum

May 2001

155/622/2488 Mbits/s Data Interfaces

TDAT SONET/SDH

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

May 2001

DA01-010SONT (Replaces DA00-001SONT and must accompany DS98-193SONT-4)

For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:

http://www.agere.com

E-MAIL:

docmaster@micro.lucent.com

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Tel. (65) 778 8833, FAX (65) 777 7495

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Tel. (86) 21 50471212, FAX (86) 21 50472266

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Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700

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Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
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Agere Systems Inc.

Advisory
May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

Microprocessor Interface (MPU)

MPU1. Interface to Motorola* MC68360 Processor Is Not Glueless

The interface between the Motorola MC68360 processor and TDAT042G5 requires intervening logic because of
the following incompatibilities in the specifications of these two devices. For a 33 MHz microprocessor clock rate,
the Motorola MC68360 series processors can be interfaced to TDAT042G5 without intervening glue logic, if used
without DT and if programmed for six wait-states. If a user wishes not to use the wait-states, then the chip select
applied to TDAT042G5 must be held low until the address changes. Details are given below.

Chip Select Timing

The TDAT042G5 CS input signal requirements are not compatible with the Motorola MC68360 series processor
CSx output signals. TDAT042G5 timing does not allow simultaneous deassertion of CS and ADS signals. Chip
select applied to TDAT042G5 must be held low for at least 5 ns after the MC68360 deasserts ADS.

Workaround: Use external glue logic to decode the address to generate CS, or provide microprocessor interface
signals meeting the requirements of TDAT042G5.

DT Timing

If the Motorola MC68360 processor CSx signal is used to drive the TDAT042G5 CS, then TDAT042G5 DT output
does not satisfy the MC68360 processor DSACK timing requirement. DT is not pulled to 1 before it is placed in a
high-impedance state. This causes the next MPU cycle to be terminated early.

Workaround: Place a 1 k

resistor from DT to V

DDD

Corrective Action

Corrective action for MPU1 has not been determined.

MPU2. Synchronous Microprocessor Interface Mode Is Nonfunctional

The synchronous microprocessor interface mode, MPMODE = 1 (pin D8), functions as described in the advance
data sheet, but causes data errors. Placing TDAT042G5 in the synchronous mode and placing a clock on MPCLK
(pin C8) will cause the data passing through the device to be corrupted. Data errors are generated at a rate of 1%
or less of corrupted packets.

Workaround

Use the TDAT042G5 in the asynchronous microprocessor mode, MPMODE = 0, with no clock applied to MPCLK.

Corrective Action

This condition will be resolved in version 1A of the device.

* Motorola is a registered trademark of Motorola, Inc.

Agere Systems Inc.

Advisory

May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

Path Terminator (PT)

(continued)

PT3. Remote Defect Indicator (RDI) Behavior

The SONET standards require that when an RDI changes value, it should hold the value for a minimum of
20 frames. This applies to a no error state, which should be maintained for at least 20 consecutive frames.
However, it is also intended by the SONET standard that the occurrence of an error state should be reported
immediately.

TDAT042G5 responds to error conditions within 100 ms (ANSI

T1.105 which states only that RDI-L must be gen-

erated or removed within 100 ms of detecting or terminating an incoming defect), in which case the two require-
ments become functionally the same.

Single-bit and enhanced RDI behave differently under the following conditions:

Transition from error state to no error state.

While in the error state, a subsequent error occurs.

The single-bit error RDI does not hold the no error state for 20 frames. However, the enhanced RDI does hold the
no error state for 20 consecutive frames.

Workaround

No workaround is available for this condition.

Corrective Action

The enhanced RDI indicator in future versions of the device will behave the same as the single-bit error indicator.

PT4. SS Pointer Interpretation Algorithm

The SDH standards do not require that the SS bits are set to binary 10 for SDH equipment. The SS bit values are
not used in determining a valid pointer value. Because of this, the SS pointer interpretation algorithm is not imple-
mented in the device. Bit 5 (RSSPTRNORM[A--D]) of PT control registers 0x0AA6, 0xAAE, 0x0AB6, and 0x0ABE
is not used. Bits 1 and 0 (RSSEXP[1:0]) of PT provisioning register 0x0AC7 are not used.

Workaround

No workaround is available for this condition.

Corrective Action

These bits will be removed from the PT registers in future revisions of the advance data sheet.

* ANSI is a registered trademark of American National Standards Institute, Inc.

Agere Systems Inc.

Advisory
May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

Data Engine (DE)

(continued)

DE5. Packet Behavior in POS/SDL Mode--Dry Mode

When the device is configured in POS mode with dry mode enabled, the following conditions may persist:

PPP mode; STS-48/STS-12/STS-3.
When running in PPP mode, the PPP header--0xFF03 0x0021 (provisionable)--may be incorrectly inserted at
any point in a packet within the outgoing data stream when the FIFO runs dry, thereby corrupting the packet.
Packets being sent are corrupted if the FIFO runs dry.

PPP and CRC modes; STS-48/STS-12/STS-3.
CRC, PPP, and HDLC modes; STS-48/STS-12/STS-3.
In PPP, CRC, and HDLC dry modes, some of the packet data may be corrupted when the packet length is above
a certain size where size is dependent upon UT clock rate and low watermark setting. Either sections of the
packet may be lost or additional packets may be inserted.

Workaround

Several workarounds are possible:

Do not provision dry mode for this device.

If dry mode is provisioned:

-- Do not allow the FIFO to be emptied.
-- Run the UTOPIA clock fast enough, as shown in Table 3, so that the FIFO is never empty.
-- Use a larger external FIFO to buffer the data.
-- Do not allow the packet size to exceed the low watermark.

Table 3. Required UTOPIA Clock (TxCLK) Rates

Corrective Action

This condition will be corrected in version 1A of the device.

Mode

TxCLK and Rate

STS-48/STM-16

TxCLK > 77 MHz (U3+, 32-bit mode)

STS-12/STM-4

TxCLK > 40 MHz

STS-3/STM-1

TxCLK > 10 MHz

Agere Systems Inc.

Advisory
May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

Data Engine (DE)

(continued)

DE8. Clearing DE Interrupt Register (0x1002)

DE interrupt register 0x1002 is incorrectly defined in the revision 3 of the data sheet as RO. DE interrupt register
0x1002 is correctly defined as a COR/W register. However, register 0x1002 must be used in the COR mode (regis-
ter 0x0010 bit 6 set to 1). The bits of register 0x1002 are explained in detail in Table 4.

Table 4. Register 0x1002: DE Interrupt (COR/W)

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

This behavior will be described in future revisions of the advance data sheet.

DE9. Single Packet Transmission in HDLC-CRC, SDL-CRC, and PPP Modes

When receiving in either PPP or CRC mode, a single packet may not pass through the device. This occurs when
the end of packet (which contains the CRC) never reaches the UT FIFO. The ingress channel suspends transfer to
the UT when there is no end of packet in the FIFO. These bytes are transferred to the UT when the next packet is
received. This problem will affect HDLC-CRC, SDL-CRC, and PPP modes.

Workaround

There are two possible workarounds:

Set ingress payload type and mode control registers (0x1040--0x1043) to CRC strip mode. However, in CRC-16
mode, single packets may still get stuck if CRC ends on bytes A or B.

Send a minimum 4-byte dummy packet after each packet.

Corrective Action

This condition will be addressed in future versions of the device.

Bits

Mode

Clear Behavior of Register 0x1002

15--12

To clear these SDL Rx frame state interrupt bits, read and
clear their associated interrupt source registers
(addresses 0x14E0--0x14E3).

11--0

COR or COW

(address 0x0010, bit 6)

To properly clear these bits, device must be in COR mode
(address 0x0010, bit 6 = 1).

Agere Systems Inc.

Advisory

May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

Data Engine (DE)

(continued)

DE10. Excessive HDLC Flag Characters

The following three issues refer to HDLC flag character (0x7E) problems in the data engine:

An excessive number of HDLC flag characters (0x7Es) may be inserted between packets on the transmit side if
the UTOPIA low watermark value is set above 2. This will have the effect of reducing the bandwidth of the device.

The data engine operates on 32-bit boundaries. Egress packets that are not multiples of four will be filled with
0x7Es.

Egress packets consisting of all 0x7Es as data will be corrupted.

Workaround

Set the UTOPIA egress low watermark value in the UTOPIA egress provisioning registers (0x0212, 0x0216,
0x021A, 0x021E) to either 1 or 2 to prevent excessive 0x7Es from being inserted between packets.

Corrective Action

This condition will be addressed in future versions of the device.

UTOPIA (UT)

UT1. Polling in Multidevice MPHY Mode

When the TDAT042G5 is polled and responds, the data bus becomes enabled. In a multidevice MPHY configura-
tion, if the data bus is active from a different PHY device, response to a poll from the device will corrupt a data
transfer already in progress. TDAT042G5 MPHY always functions without data corruption in a single-device
(slave), multiple-channel configuration (point-to-point).

Workaround

No workaround is available for this condition.

Corrective Action

This condition will be addressed in future versions of the device.

Agere Systems Inc.

Advisory

May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

UTOPIA (UT)

(continued)

UT4. FIFO Overflow and Error Reporting

If the RxFIFO overflows, RxEOP is not asserted as expected. Therefore, when errors occur, two packets will be
corrupted instead of one because two start of packets (SOPs) occurred without an end of packet (EOP). RxERR is
not asserted when the above overflow condition occurs. No effect is noticeable in the ATM mode. Channel A works
as expected; this problem occurs in channels B, C, and D.

Workaround

This error is detectable in the status registers. No workaround is available for this condition.

Corrective Action

This condition will be addressed in future versions of the device.

UT5. Timing Difference Between Direct and Polled Status Modes

In the receive direction of the MPHY mode, RxPA[A] shows the polled packet (or ATM) available status for all four
slices, while the RxPA[B], RxPA[C], and RxPA[D] show the direct status states of their respective FIFOs. In some
cases, the status of RxPA[A] does not agree with the status of RxPA[D:B]. The direct status indication has one
additional cycle of pipeline delay from that of the polled status.

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

No corrective action is required for this condition.

UT6. UTOPIA Interface D Nonfunctional in Some Mixed MPHY and Point-to-Point

Configurations

When TDAT042G5 is configured with slice D in a point-to-point mode, slice D is nonfunctional in one special case.
If UTOPIA interfaces A and B are configured for 32-bit MPHY operation with slice C as part of the polled channels,
interface D will be nonfunctional and cannot be independently configured in a UTOPIA Level 2 point-to-point mode.
This condition does not occur in 16-bit MPHY operation.

Workaround

For mixed MPHY and point-to-point configuration, use UTOPIA slice D for MPHY mode instead of slice C.
UTOPIA slice C will then be available for normal point-to point mode.

Corrective Action

This condition will be addressed in future versions of the device.

Agere Systems Inc.

Advisory

May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

UTOPIA (UT)

(continued)

UT9. Clock Requirements for MPHY Modes

When using the TDAT042G5 in MPHY mode, receive and transmit clocks must be provided for all channels (A, B,
C, and D). Also, the packet available (PA) signal for each channel must be provided on each channel's associated
PA pin.

Workaround

It is possible to place RxCLK[D:A] into source mode by provisioning bit 6 (CLOCK_MODE_Rx) of the UTOPIA
receive provisioning registers (addresses 0x020F, 0x0213, 0x0217, 0x021B). This will eliminate the need to supply
separate receive and transmit clocks.

Corrective Action

This is informational only. No corrective action is required for this condition.

UT10. Egress Packet Mode Overflows

In the UTOPIA modes listed below, the device will report transmit packet overflow errors when no overflows have
occurred. This occurs when the egress high watermark is set for the UTOPIA modes as shown in Table 6.

Table 6. Settings at Which Overflows Reported in Error

Workaround

Set the egress high watermark threshold as shown in Table 7. If there is a delay between TxPA deassertion and
TxENB deassertion, the additional cycles should also be accounted for when setting the threshold.

Table 7. Settings to Prevent Overflows Reported in Error

Corrective Action

This condition will be addressed in future versions of the device.

UTOPIA Modes

Egress High Watermark Thresholds

8-bit, U3+

0x3D

16-bit, U2+

0x3B

32-bit, U3+

0x37

UTOPIA Modes

Egress High Watermark Thresholds

8-bit, U3+

0x3D

16-bit, U2+

0x3B

32-bit, U3+

0x37

Agere Systems Inc.

Advisory
May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

UTOPIA (UT)

(continued)

UT11. Clearing UT Interrupt Register

When a UT interrupt event occurs and COW mode is enabled, writing to UT interrupt register 0x0201 does not
clear the register (this register is read-only). The interrupt is cleared by writing to the UT delta and event registers
(addresses 0x0202--0x0205).

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

No corrective action is required for this condition.

UT12. Incorrect Implementation of POS Multi-PHY Mode

Because the TDAT042G5 lacks a selected PA signal (SPA), the status of a channel that is transmitting data in POS
MPHY mode is not known during polling. Therefore, the PA signal cannot be used as a data valid signal. If the
channel transmitting data runs dry, the master side may receive invalid data.

Workaround

Use direct status polling mode only and ensure that the address of channel A is applied to the address bus at all
times, except during the clock cycle when another channel is being selected.

Corrective Action

No corrective action is required for this condition.

UT13. Invalid Extra Cycle Between EOP and SOP in CRC-16/32 Mode

When using the device in CRC-16 or CRC-32 mode, there is always an extra cycle between the end of packet
(EOP) of the previous packet and the start of packet (SOP) of the following packet.

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

This is condition will be addressed in the future version of the device.

Agere Systems Inc.

Advisory

May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

UTOPIA (UT)

(continued)

UT14. Nonfunctional RxPA Signal for Channels B and D in Packet Direct Status MPHY Mode

When using MPHY direct status for all operational modes (8-bit, 16-bit, and 32-bit), the RxPA signal for channels B
and D is not functional. The RxPA signal is functional only for channels A and C.

Workaround

The TDAT UTOPIA interface currently has nonfunctioning RxPAB and RxPAD output signals when used in four-
channel Multi-PHY mode as shown in Figure 1. The result of this problem is the unavailability of direct status polling
on the receive-side UTOPIA interface. To work around this problem, the following analysis is done to aid the user in
doing a round-robin data extraction procedure.

1664 (F)

Figure 1. Receive-Side UTOPIA Interface and Channel FIFOs

The rate at which data fills and drains the receive-side UTOPIA FIFOs is calculated as follows:

The data enters each UTOPIA FIFO from the data engine bytewise running on a 77.76 MHz system clock.

If we assume each channel (worst case) is filled with an STS-12c rate signal, then the amount of data (excluding
SONET overhead, both section/line, path, and three stuff columns) per second is
(87 x12 x 9 x 8000) � (4 x 9 x 8000) = 74.88 Mbytes/STS-12c/s or 599.040 Mbits/STS-12c/s.

Since each FIFO contains a maximum of 256 bytes/FIFO, it takes on average
(256/74,880,000) = 3.4188

�

s to fill a FIFO, and with a clock cycle of 77.76 MHz, it requires as a worst case,

3.2922

�

s to fill the FIFO.

Since there are four FIFOs all receiving data at 74.88 Mbytes/s, then the total bandwidth requirements of all four
channels combined is (4 x 74,880,000) = 299.52 Mbytes/s.

The servicing rate on each FIFO is based on the UTOPIA interface width and frequency. If we assume a
32-bit A/B UTOPIA interface operating at 100 MHz, then the service rate is 400 Mbytes/s to service all the
channels.

INGRESS CHANNEL A FIFO

256 bytes DEEP

INGRESS CHANNEL B FIFO

256 bytes DEEP

INGRESS CHANNEL C FIFO

256 bytes DEEP

PAA

32-bit INTERFACE (A AND B)

PAB

PAC

INGRESS CHANNEL D FIFO

256 bytes DEEP

PAD

Agere Systems Inc.

Advisory
May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

UTOPIA (UT)

(continued)

The interface can drain an entire FIFO at a rate of 400 Mbytes/s. To drain 256 bytes, it requires a maximum of
(256 / 400,000,000) = 0.64

�

s to drain a FIFO that is completely full. To drain all four FIFOs, it requires

(0.64 x 4) = 2.56

�

s total

For data to be efficiently removed from each of the Rx FIFOs, a round-robin extraction method must be employed
since the RxPAB and RxPAD signals are not available for direct status polling. Since it requires a worst case total of
3.2922

�

s to fill a FIFO, the master must service all FIFOs in a manner such that it does not allow any particular

FIFO to fill and hence overflow. Assuming equal servicing of each FIFO, the master must therefore not service any
particular FIFO for longer than (3.2922 / 4) = 0.8231

�

s. This also must account for any dead cycles in a cycling

between channels and any dead cycles on a particular channel (single dead cycle between EOP and SOP).

When servicing four FIFOs, there is a maximum clock cycle penalty for switching between channels. For two-cycle
mode, this penalty is a maximum of four UTOPIA master clock cycles; so to switch between all four channels, a
total of up to sixteen master clock cycles may be required to perform all the switching. The value of four is worst
case, and in some cases this can be as low as one cycle. The value of four results from the case where the FIFO
drains while servicing that channel, which will be common when draining at the 100 MHz frequency. In that case,
the master must first see that the FIFO has drained by observing that RxPAA is invalid on the last cycle while drain-
ing the FIFO (best case is one cycle lost). It must then deactivate RxENB and place a new channel address on the
address bus on the following cycle (best case is one cycle lost). It must then activate RxENB for the new channel
on the following cycle and have TDAT sample RxENB low (best case is one cycle lost). The TDAT will then output
data two cycles later when using a PA response mode of two cycles (one cycle lost with data output on second
cycle). Any additional delays by the master must be added to these to calculate a worst-case condition. The best-
case condition occurs when the master stops the data flow when there are still more than two data items contained
within the FIFO. In this case, the master deactivates RxENB at some predetermined maximum 32-bit word drain
value, where the PA response on the cycle prior to deactivation had valid data. For two-cycle mode, two additional
data items will be output from the FIFO for that particular channel, if available. The master deactivates RxENB,
places the new channel address on the FIFO, and activates RxENB. On the cycle where RxENB is activated, the
last valid data item from the previous channel may be output (best case), and one dead cycle will follow this before
data for the following selected channel is output.

Given the information above, assume the worst case of four cycles between channel switching. Also assume the
FIFOs are filling at a worst-case rate, 3.2922

�

s/FIFO. Assume the master is draining each FIFO using the 32-bit,

100 MHz, A/B, UTOPIA interface. Assume the master extracts a maximum of thirty 32-bit words (120 bytes) from
each FIFO before switching to an alternate channel. This requires (30 x 10) = 300 ns/FIFO, and assume that it
takes the worst-case four clock cycles to switch to alternate channels. Therefore, the total servicing time per FIFO
is (300 + 4 x 10) = 340 ns/channel, and the total servicing time per four channels is (4 x 340) = 1.36

�

s per round

robin servicing of all four channels. At this round-robin rate, a maximum of 120 bytes are serviced per channel per
1.360

�

s interval; so to service the total bytes per channel (74.88 Mbytes/s), it requires a total of 0.849 seconds,

which is sufficient bandwidth to service all channels.

Since the FIFOs fill at the maximum rate of 1 byte/13.355 ns, each FIFO will fill to a depth of 102 bytes in the
1.360

�

s interval between channel servicing. This is well below the overflow threshold, which is set by the user to a

value near the top of the FIFO (high watermark, 0x36 (216 bytes) default) and is below the number of bytes ser-
viced by the master per channel per round-robin servicing (120 bytes). Each customer's servicing characteristics
will depend on the master's behavior and how fast it performs the channel switching. If it cannot switch in the worst-
case, four-cycle manner described above, performance will degrade.

One item not accounted for in the above analysis is the fact that TDAT may place a dead cycle between packets (in
CRC and PPP modes, not in HDLC mode). In this case, there can be a maximum of three dead cycles per FIFO
(assuming 40-byte packets worst case and 102 bytes in FIFO between round-robin cycle). This will be taken up by
the slack provided above, where (102 bytes + 4 bytes/dead cycle x 3 dead cycles) = 114 bytes, which still falls
below the servicing rate of 120 bytes per round-robin servicing.

Agere Systems Inc.

Advisory
May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

Overhead Processor (OHP)

OHP1. Maximum BER Count

The maximum number of errors the device can report is limited to 5.00E-04 in STS-12/STM-4 mode and 1.00E-04
in STS-48/STM-16 mode. This applies to the SDLSET, SDLCLEAR, SFLSET, and SFLCLEAR bits of the signal
degrade and signal fail BER algorithm OHP registers. These bits are shown in Table 8.

Table 8. Signal Degrade and Signal Fail Algorithm OHP Registers [6:3]

* The OHP prefix shown here will be added to the current bit names in revision 4 of the advance data

sheet.

Workaround

This is informational only. No workaround is available for this condition.

Corrective Action

No corrective action is required for this condition.

OHP2. RDI-L Reporting

When the device is initially powered up, it defaults to STS-48/STM-16 mode. This locks a counter value into trans-
mit control registers for channels B, C, and D. When the device is configured for STS-3/STM-1 mode, the counter
does not automatically clear.

Workaround

During STS-3/STM-1 OHP configuration in the system code, manually clear transmit control registers 0x0431,
0x0433, and 0x0435 for channels B, C, and D. In order to clear these transmit control registers, the bits must be
toggled. The following pseudocode shows how to clear the bits on channels B, C, and D:

Set address 0x0431 to 0x007F # set bits on channel B

Set address 0x0431 to 0x0000 # clear bits on channel B

Set address 0x0433 to 0x007F # set bits on channel C

Set address 0x0433 to 0x0000 # clear bits on channel C

Set address 0x0435 to 0x007F # set bits on channel D

Set address 0x0435 to 0x0000 # clear bits on channel D

Corrective Action

This is informational only. No corrective action is required for this condition.

OHP Bits*

Addresses

OHP_SDLSET[A--D][3:0]

0x043B, 0x043D, 0x043F, 0x0441

OHP_SDLCLEAR[A--D][3:0]

0x0447, 0x0449, 0x044B, 0x044D

OHP_SFLSET[A--D][3:0]

0x0453, 0x0455, 0x0457, 0x0459

OHP_SFLCLEAR[A--D][3:0]

0x045F, 0x0461, 0x0463, 0x0465

Agere Systems Inc.

Advisory
May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

Packaging and Pinouts (P)

(continued)

P4. Power Dissipation

The worst-case power dissipation of TDAT042G5 is currently estimated to be 7.5 W. The minimum and maximum
power dissipation is listed in Table 9, as well as the relative package thermal characteristics.

Table 9. Power Dissipation and Relative Package Thermal Characteristics

= (T

� T

)/P

: T

= junction temperature, T

= ambient temperature of medium surrounding the package, P

= electrical power dissipated

by the device.

= (T

� T

)/P

: T

= junction temperature, T

= package temperature (top, dead-center), P

= electrical power dissipated by the device.

Maximum junction temperature of TDAT042G5 is 125 癈. Therefore, maximum case temperature under natural
convection conditions must be less than approximately 50 癈, and in this case, an external heat sink is required.

References

Jeff Weiss, 600 LBGA Thermal Test Report, February 25, 1999.

HL250C 3.3 Volt 0.25

�

m CMOS Standard-Cell Library (MN98-060ASIC-02), pages 2-2 and 2-3.

Workaround

An external heat sink is required.

Corrective Action

Power consumption will be addressed in future versions of the device.

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Power Dissipation:

Minimum
Maximum

STS-3/STM-1 line rate
STS-12/STM-4 and STS-48/

STM-16 line rates

--
--

3
6

--
--

W
W

Thermal Performance

(JEDEC standard
conditions)*

Standard JEDEC 4-layer PWB:

Standard natural convection

200 LFPM airflow

800 LFPM airflow

--
--
--

6.5

--
--
--

癈/W
癈/W
癈/W

Correlation Factor

Between Die and Case
Temperatures

Standard JEDEC 4-layer PWB:

Standard natural convection

200 LFPM airflow

800 LFPM airflow

--
--
--

0.3
0.4
0.5

--
--
--

癈/W
癈/W
癈/W

Agere Systems Inc.

Advisory
May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

AY99-013SONT-2 Replaces AY99-013SONT to Incorporate the Following Updates

1. Page 1, SP1. Required Provisioning Sequence and Clocks, added new issue.

2. Page 8, DE4. Channel Provisioning, added new issue.

3. Page 9, DE5. Packet Behavior in POS/SDL Mode--Dry Mode, added new issue.

4. Page 15, UT8. Far-End Loopback Bandwidth Limitations, added new issue.

5. Page 16, advance data sheet document number corrected.

AY99-013SONT-3 Replaces AY99-013SONT-2 to Incorporate the Following Updates

1. Page 1, notice that the advisory issues still apply to the advance data sheet which has just been updated.

AY99-013SONT-4 Replaces AY99-013SONT-3 to Incorporate the Following Updates

1. Replaced OC- designation with STS- and STM- throughout advisory.

2. Page 2, SP2. Behavior During Loss of Receive Line Clock, added new issue.

3. Page 2, SP3. PT Register Addressing, added new issue.

4. Page 4, CR1. Clear on Read/Clear on Write Behavior, added new issue.

5. Page 5, PT2. Clear-After-Write Behavior of Signal Degrade Clear Bits, corrected description.

6. Page 6, PT4. SS Pointer Interpretation Algorithm, added new issue.

7. Page 7, PT5. Delta/Event Registers in COR Mode, added new issue.

8. Page 7, DE2. Incorrect ATM Loss of Cell Delineation (LCD) Implementation, identified the specific ITU stan-

dard with which the LCD implementation does not comply.

9. Page 8, DE4. Channel Provisioning, Table Transmit DE Egress and Sequencer Cell State Registers, corrected

10. Page 9, DE5. Packet Behavior in POS/SDL Mode--Dry Mode, identified dry mode issues.

11. Page 10, DE6. Incorrect ATM Out of Cell Delineation (OCD) Implementation, added new issue.

12. Page 10, DE7. Incorrect Frame State of ATM Data Streams, added new issue.

13. Page 11, DE8. Clearing DE Interrupt Register (0x1002), added new issue.

14. Page 11, DE9. Single Packet Transmission in HDLC-CRC, SDL-CRC, and PPP Modes, added new issue.

15. Page 12, DE10. Excessive HDLC Flag Characters, added new issue.

16. Page 13, UT2. UTOPIA Clock Limitations, clarified wording.

17. Page 14, UT4. FIFO Overflow and Error Reporting, clarified wording.

18. Page 16, UT9. Clock Requirements for MPHY Modes, added new issue.

19. Page 16, UT10. Egress Packet Mode Overflows, added new issue.

20. Page 17, UT11. Clearing UT Interrupt Register, added new issue.

21. Page 17, UT12. Incorrect Implementation of POS Multi-PHY Mode, added new issue.

22. Page 21, OHP1. Maximum BER Count, added new issue. In addition, differentiated OHP bits from PT bits with

the same name; the names will be corrected in revision 4 of the advance data sheet.

Agere Systems Inc.

Advisory

May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

AY99-013SONT-4 Replaces AY99-013SONT-3 to Incorporate the Following Updates

(continued)

23. Page 21, OHP2. RDI-L Reporting, added new issue.

24. Page 22, OHP3. M1 Error Counter in STS-48/STM-16 Mode, added new issue.

25. Page 22, removed issue P1. Pin 5 (Previously JTEST) Is No Connect (NC). Pin F5 was corrected to NC in the

accompanying advance data sheet, DS98-193SONT-3.

26. Page 22, removed issue P2. Modified Pinout and Power Supply Configuration--Future Versions. Plans for 2.5 V

power ring implementation considered, but no schedule available at this time.

27. Page 22, removed issue P3. Change to TDAT042G5 Version 1 Pinout. Listed pins have been corrected to NC in

the accompanying advance data sheet, DS98-193SONT-3.

28. Page 24, DA1. Incorrect PT Control Register Mapping, added new issue.

AY01-015SONT (Replaces AY99-013SONT-4 and Must Accompany
DS98-193SONT-4) Replaces AY99-013SONT-4 to Incorporate the Following
Updates

Change List

This change list summarizes changes across the various versions of this document starting with the version dated
1/25/01.

1/25/01

1. Page 6, PT3. Remote Defect Indicator (RDI) Behavior, clarified wording.

2. Page 12, DE 11. ATM Header Error Correction (HEC) Behavior, added entire section to document.

1/29/01

1. Page 24, DA1. Incorrect PT Control Register Mapping, changed corrective action description to include the July

2000 date.

2. Page 24, DA2. Variable Change, added entire section to document.

2/13/01

1. Page 12, updated issue on DE 11. ATM Header Error Correction (HEC) Behavior, to include more information.

2. Page 17, added issue UT13. Invalid Extra Cycle Between EOP and SOP in CRC-16/32 Mode.

3. Page 18, added issue UT14. Nonfunctional RxPA Signal for Channels B and D in Packet Direct Status MPHY

Mode.

3/1/01

1. Page 12, removed DE 11 from document.

2. Page 18, UT14. Nonfunctional RxPA Signal for Channels B and D in Packet Direct Status MPHY Mode, added

workaround to document.

Advisory

May 2001

for Version 1 and 1A of the Device

TDAT042G5 Device Advisory

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

May 2001
AY01-015SONT (Replaces AY99-013SONT-4 and Must Accompany DS98-193SONT-4)

For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:

http://www.agere.com

E-MAIL:

docmaster@micro.lucent.com

N. AMERICA:

Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256

Tel. (65) 778 8833, FAX (65) 777 7495

CHINA:

Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC
Tel. (86) 21 50471212, FAX (86) 21 50472266

JAPAN:

Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700

EUROPE:

Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Technical Inquiries:GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),

FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)

Data Sheet

May 2001

TDAT042G5 SONET/SDH
155/622/2488 Mbits/s Data Interface

Features

Point-to-point path termination device for interface
termination.

Versatile IC supports 155/622/2488 Mbits/s
SONET/SDH interface solutions for packet over
SONET (POS), asynchronous transfer mode
(ATM), or simplified data link (SDL) for data over
fiber applications.

Supports point-to-point and multi-PHY UTOPIA.

Low-power 3.3 V operation, CMOS technology.

High-speed I/O is LVPECL. All other logic has 5 V
tolerant TTL-level inputs.

�40 癈 to +85 癈 temperature range.

600 LBGA package.

SONET/SDH Interface

Termination of quad STS-3/STM-1, quad STS-12/
STM-4, or single STS-48/STM-16.

Supports overhead processing for transport and
path overhead bytes.

Optional insertion and extraction of overhead bytes
via serial overhead interface.

Full path termination and SPE extraction/insertion.

SONET/SDH compliant condition and alarm
reporting.

Handles all concatenation levels of STS-3c
through STS-48c (in multiples of 3; i.e., 3c, 6c, 9c,
etc.), STM-1 through STM-16.

Built-in diagnostic loopback modes.

Compliant with the following Telcordia

(Bellcore),

ANSI*, and ITU standards:
-- GR-253 CORE: SONET Transport Systems:

Common Generic Criteria.

*ANSI is a registered trademark of American National Standards

Institute, Inc.

Telcordia is a registered trademark of Bell Communications

Research, Inc.

-- ITU-T G.707: Network Node Interface for the

Synchronous Digital Hierarchy.

-- ITU-T G.803: Architecture of Transport Net-

works Based on the Synchronous Digital Hier-
archy.

-- T1.105: SONET-Basic Description including

Multiplex Structure, Rates, and Formats.

-- T1.105.02 SONET-Payload Mappings.
-- T1.105.03 SONET-Jitter at Network Interfaces.
-- T1.105.06 SONET Physical Layer Specifica-

tions.

-- T1.105.07 SONET-Sub-STS-1 Interface Rates

and Formats Specification.

-- ITU-T I.432: B-ISDN User-Network Interface-

Physical Layer Specification.

-- IETF RFC 2615 (June 1999): PPP over

SONET/SDH.

-- IETF RFC 1661: The Point-to-Point Protocol

(PPP).

-- IETF RFC 1662: PPP in HDLC-like Framing.

Data Processing

Provisionable data engine supports payload inser-
tion/extraction and CRC-16/-32 generation/verifica-
tion for ATM cell or PPP, SDL, or HDLC streams.

Maintains counts for cell/packet traffic (e.g., total
number of cells, number of discarded cells).

Integrated UTOPIA Level 2- and UTOPIA Level 3-
compatible ATM physical layer interface with
packet extensions for all test and operations.

Insertion and extraction of up to four separate data
channels.

Compliant with 1998: ATM Forum, ITU standards,
and IETF standards.

Microprocessor Interface

16-bit address and 16-bit data interface with up to
66 MHz read and write access.

Compatible with most industry-standard proces-
sors.

Please see the Description section, page 11, for
details.

Table of Contents

Contents

Page

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Features ................................................................................................................................................................... 3

SONET/SDH Interface ........................................................................................................................................... 3
Data Processing ..................................................................................................................................................... 3
Microprocessor Interface ....................................................................................................................................... 3

Description .............................................................................................................................................................. 11
Pin Information ....................................................................................................................................................... 11
Overview ................................................................................................................................................................. 45

ATM/HDLC/HDLC-CRC/PPP Support ................................................................................................................. 47
SDL Support ........................................................................................................................................................48
Over-Fiber Mode ..................................................................................................................................................49
Test and General-Purpose I/O Support ............................................................................................................... 49
External Interfaces ............................................................................................................................................... 49

Functional Description ............................................................................................................................................ 50

Line Interface Block ............................................................................................................................................. 51
SONET Framer .................................................................................................................................................... 53
Overhead Processor (OHP) Block ....................................................................................................................... 53
Path Terminator (PT) Block ................................................................................................................................. 62
Data Engine (DE) Block ....................................................................................................................................... 70
UTOPIA (UT) Interface Block ............................................................................................................................... 84
JTAG (Boundary-Scan) Test Block .................................................................................................................... 100

Line Interface ........................................................................................................................................................ 100

LVPECL I/O Termination and Load Specifications ............................................................................................ 100

Interface Description ............................................................................................................................................. 101

Microprocessor Interface ...................................................................................................................................101
General-Purpose I/O Bus (GPIO) ...................................................................................................................... 102
Interrupts ............................................................................................................................................................ 103
Reset .................................................................................................................................................................. 104
Performance Monitor Reset (PMRST) ............................................................................................................... 104
Loopback Operation ........................................................................................................................................... 106
System Interfaces .............................................................................................................................................. 107

Register Access Description ................................................................................................................................. 111
Register Maps ......................................................................................................................................................112

Core Registers ................................................................................................................................................... 112
UT Registers ......................................................................................................................................................113
OHP Registers ................................................................................................................................................... 116
PT Registers ......................................................................................................................................................126
DE Registers ......................................................................................................................................................138

Register Descriptions ........................................................................................................................................... 147

Core Registers ................................................................................................................................................... 147
UT Registers ......................................................................................................................................................154
OHP Registers ................................................................................................................................................... 165
PT Registers ......................................................................................................................................................192
DE Registers ......................................................................................................................................................211

Absolute Maximum Ratings .................................................................................................................................. 253
Handling Precautions ........................................................................................................................................... 253
Operating Conditions ............................................................................................................................................ 254
Electrical Characteristics ...................................................................................................................................... 254

Table of Contents

(continued)

Contents

Page

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Interface Timing Specifications .............................................................................................................................255

Microprocessor Interface Timing ........................................................................................................................255
Line Interface I/O Timing ....................................................................................................................................264
UTOPIA Interface Timing ...................................................................................................................................268
Transport Overhead Access Channel (TOAC) Interface Timing ........................................................................271

Reference of SONET/SDH Terms and Comparisons ...........................................................................................273

Definitions of SONET/SDH Bytes ......................................................................................................................273
SONET/SDH Comparisons ................................................................................................................................274
SONET/SDH New Terminology .........................................................................................................................274

Outline Diagram ....................................................................................................................................................275

600-Pin LBGA ....................................................................................................................................................275

Ordering Information .............................................................................................................................................276
DS98-193SONT-4 Replaces DS98-193SONT-3 to Incorporate the Following Updates ......................................276

List of Figures

Contents

Page

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Figure 1. Pin Diagram of 600-Pin LBGA (Bottom View) .........................................................................................11
Figure 2. Overview Block Diagram .........................................................................................................................45
Figure 3. Interface Block Diagram .......................................................................................................................... 46
Figure 4. External Interface Summary Diagram ..................................................................................................... 49
Figure 5. Functional Block Diagram ....................................................................................................................... 50
Figure 6. Signal Degrade and Failure Parameters for BER ................................................................................... 56
Figure 7. Pointer Interpreter State Diagram ........................................................................................................... 62
Figure 8. STS-48 Signal Carrying One STS-48c Frame ........................................................................................ 65
Figure 9. STS-48 Signal Carrying Four STS-12c Frames ...................................................................................... 66
Figure 10. Quad STS-12 Configuration With Each STS-12 Signal Carrying One STS-3c Frame .......................... 66
Figure 11. Quad STS-12 Configuration With Each STS-12 Signal Carrying One STS-12c Frame (Channel A), One

STS-9c Frame (Channel B), One STS-6c Frame (Channel C), and One STS-3c Frame (Channel D) . 67

Figure 12. Quad STS-3 Configuration With Each STS-3 Signal Carrying One STS-2c Frame .............................. 67
Figure 13. Block Diagram of Date Engine (DE) ......................................................................................................70
Figure 14. State Diagram for the X31 Scrambler Synchronization Process ........................................................... 72
Figure 15. General Structure of SDL Packets ........................................................................................................ 72
Figure 16. Uncompressed and Compressed PPP Packets .................................................................................... 75
Figure 17. Example of Tx/Rx Sequencer Configuration: STS-48c into Single OC-48 Signal ................................. 78
Figure 18. Example of Tx/Rx Sequencer Configuration: 4xSTS-12c into Four Independent OC-12 Signals ......... 79
Figure 19. SONET Multiplexing: 2-Stage Byte Interleaving Example .....................................................................80
Figure 20. Example of Tx/Rx Sequencer Configuration: 4xSTS-3c into Four Independent OC-3 Signals ............. 81
Figure 21. TDAT042G5 Over-Fiber Modes: SDL, ATM (X31) ................................................................................ 82
Figure 22. UT Block Diagram ................................................................................................................................. 84
Figure 23. Receive-Side Interface Handshaking in Point-to-Point, Single Cycle Mode ......................................... 91
Figure 24. Receive-Side Interface Handshaking in Point-to-Point, Two-Cycle Mode ............................................92
Figure 25. Transmit-Side Interface Handshaking in Point-to-Point, Single Cycle Mode ........................................ 95
Figure 26. Multi-PHY Configuration of All Four Channels ...................................................................................... 96
Figure 27. TxPA Two-Cycle Responses of a Multi-PHY for All Four Channels ...................................................... 98
Figure 28. RxPA Responses of a Multi-PHY for All Four Channels (PA Response Configured for One Cycle) .... 99
Figure 29. GPIO Functionality .............................................................................................................................. 102
Figure 30. Interrupt Functionality .......................................................................................................................... 103
Figure 31. Miscellaneous Functionality ................................................................................................................ 104
Figure 32. Loopback Operation ............................................................................................................................ 106
Figure 33. Quad ATM UTOPIA 2 .......................................................................................................................... 107
Figure 34. Single ATM UTOPIA 3 ........................................................................................................................ 108
Figure 35. Quad POS UTOPIA 2 .......................................................................................................................... 109
Figure 36. Single POS UTOPIA 3 ........................................................................................................................ 110
Figure 37. 32-bit MPHY UTOPIA 3 .......................................................................................................................110
Figure 38. Microprocessor Interface Synchronous Write Cycle (MPMODE (Pin D8) = 1) .................................... 256
Figure 39. Microprocessor Interface Synchronous Read Cycle (MPMODE (Pin D8) = 1) ...................................258
Figure 40. Microprocessor Interface Asynchronous Write Cycle Description (MPMODE (Pin D8) = 0) ............... 260
Figure 41. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin D8) = 0) .................................. 262
Figure 42. Receive Line-Side Timing Waveform .................................................................................................. 264
Figure 43. Transmit Line-Side Timing Waveform--STS-48/STM-16 Contraclocking ........................................... 265
Figure 44. Transmit Line-Side Timing Waveform--Frame Synch ........................................................................ 265
Figure 45. Transmit Line-Side Timing Waveform--STS-48/STM-16 Forward Clocking ...................................... 265
Figure 46. Transmit UTOPIA Interface Timing ..................................................................................................... 268
Figure 47. Receive UTOPIA Interface Timing ...................................................................................................... 269
Figure 48. Transmit TOAC Interface Timing ......................................................................................................... 271
Figure 49. STS-12/STM-4 and STS-48/STM-16 Receive TOAC Interface Timing ............................................... 272
Figure 50. STS-3/STM-1 Receive TOAC Interface Timing ................................................................................... 272

List of Tables

Contents

Page

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order .......................................................................12
Table 2. Pin Assignments for 600-Pin LBGA by Signal Name ...............................................................................17
Table 3. Pin Descriptions--Line Interface Signals .................................................................................................22
Table 4. Pin Descriptions--TOH Interface Signals .................................................................................................27
Table 5. Pin Descriptions--Enhanced UTOPIA Interface Signals ..........................................................................28
Table 6. Pin Descriptions--Microprocessor Interface Signals ................................................................................40
Table 7. Pin Descriptions--General-Purpose I/O Signals: Interface Signals .........................................................41
Table 8. Pin Descriptions--JTAG Interface Signals ...............................................................................................42
Table 9. Pin Descriptions--Power Signals .............................................................................................................43
Table 10. Pin Descriptions--No Connect Pins .......................................................................................................44
Table 11. Optional Offset Field ...............................................................................................................................48
Table 12. Line Interface Modes ..............................................................................................................................51
Table 13. Clock Settings for CLKDIV Pin ...............................................................................................................52
Table 14. R/T TOH Interface Rates ........................................................................................................................53
Table 15. TOAC Byte Insertion: An STS-3/STM-1 Example ..................................................................................53
Table 16. Ns, L, M, and B Values to Set the BER Indicator ...................................................................................57
Table 17. Ns, L, M, and B Values to Clear the BER Indicator ................................................................................58
Table 18. TOAC Channel I/O vs. STS Number/Time Slot ......................................................................................59
Table 19. Types of Signal Labels ...........................................................................................................................64
Table 20. 1-bit Mode ...............................................................................................................................................64
Table 21. 3-bit Mode (Enhanced RDI) ....................................................................................................................64
Table 22. Valid Concatenation Starting Locations: STS-Mc into an STS-48c ........................................................68
Table 23. Packet Length Field ................................................................................................................................73
Table 24. UTOPIA Traffic Types ............................................................................................................................85
Table 25. Standard 53-byte ATM Cell Structure .....................................................................................................86
Table 26. Bus Format for 16-bit Interface ...............................................................................................................86
Table 27. Bus Format for 8-bit Interface .................................................................................................................87
Table 28. Bus Format for 32-bit Interface ...............................................................................................................87
Table 29. Egress High Watermark Thresholds .......................................................................................................94
Table 30. Nominal dc Power for Suggested Terminations ...................................................................................100
Table 31. MPU Modes ..........................................................................................................................................101
Table 32. PMRST Provisioning ............................................................................................................................105
Table 33. Quad ATM UTOPIA 3 Interface ............................................................................................................107
Table 34. Quad POS UTOPIA 3 Interface ............................................................................................................109
Table 35. Register Address Space .......................................................................................................................111
Table 36. Map of Core Registers ..........................................................................................................................112
Table 37. Map of UT Registers .............................................................................................................................113
Table 38. Map of OHP Registers ..........................................................................................................................116
Table 39. Map of Path Terminator Registers ........................................................................................................126
Table 40. Map of DE Registers ............................................................................................................................138
Table 41. Register 0x0000: Device Version (RO) ................................................................................................147
Table 42. Registers 0x0001--0x0005: Device Name (RO) ..................................................................................147
Table 43. Register 0x0008: Composite Interrupts (RO or COR/W) ......................................................................148
Table 44. Register 0x000A: GPIO Input (RO) ......................................................................................................148
Table 45. Register 0x000C: Block Interrupt Masks (R/W) ....................................................................................149
Table 46. Register 0x000E: Core Resets (WO) ...................................................................................................149
Table 47. Register 0x000F: GPIO Output (R/W) ..................................................................................................150
Table 48. Register 0x0010: Line Provisioning/Mode (R/W) ..................................................................................150
Table 49. Register 0x0011: Channel (A--D) Control (R/W) .................................................................................151
Table 50. Register 0x0012: Loopback Control (R/W) ...........................................................................................151
Table 51. Register 0x0013: GPIO Mode (R/W) ....................................................................................................152

List of Tables

(continued)

Contents

Page

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Table 52. Registers 0x0014, 0x0015: GPIO Output Configuration ....................................................................... 152
Table 53. Register 0x001F: Scratch (R/W) ........................................................................................................... 153
Table 54. Register 0x0200: UT Macrocell Version Number (RO) ........................................................................ 154
Table 55. Register 0x0201: UT Interrupt (RO) ..................................................................................................... 154
Table 56. Registers 0x0202, 0x0203, 0x0204, 0x0205: Channel [A--D] (COR) .................................................. 155
Table 57. Register 0x0206: Interrupt Mask (R/W) ................................................................................................ 156
Table 58. Registers 0x0207, 0x0208, 0x0209, 0x020A: Interrupt Mask--Channel [A--D] (R/W) ........................ 156
Table 59. Register 0x020B: Channel [A--D] Error Count in PMRST Mode (RO) ................................................156
Table 60. Fields of the Provisioning Registers ..................................................................................................... 157
Table 61. Registers 0x020F, 0x0213, 0x0217, 0x021B: Channel [A--D] Receive Provisioning Register (R/W) . 158
Table 62. Registers 0x0210, 0x0214, 0x0218, 0x021C: Channel [A--D] Transmit Provisioning Register (R/W) 159
Table 63. Registers 0x0211, 0x0215, 0x0219, 0x021D: Channel [A--D] Ingress Provisioning Register (R/W) .. 161
Table 64. Registers 0x0212, 0x0216, 0x021A, 0x021E: Channel [A--D] Egress Provisioning Register (R/W) ...161
Table 65. Register 0x021F: Reset Register (R/W) ............................................................................................... 162
Table 66. Register 0x0220: Channel [A--D] Error Count (RO) ............................................................................ 162
Table 67. Register 0x0224: UT_Scratch Register (R/W) ...................................................................................... 162
Table 68. Register 0x0225: PA Response Register (R/W) ................................................................................... 163
Table 69. Register 0x0226: Size Mode Register (R/W) ........................................................................................ 164
Table 70. Register 0x0400: OHP Macrocell Version Number (RO) ..................................................................... 165
Table 71. Register 0x0401: OHP Interrupt (RO) .................................................................................................. 165
Table 72. Registers 0x0402--0x0409: Delta/Event (COR/W) .............................................................................. 165
Table 73. Registers 0x040A--0x040D: Receive/Transmit State (RO) ................................................................. 168
Table 74. Registers 0x040E, 0x0410, 0x0412, 0x0414: Mask Bits (R/W) ............................................................ 169
Table 75. Registers 0x040F, 0x0411, 0x0413, 0x0415: Mask Bits (R/W) ............................................................ 170
Table 76. Registers 0x0416--0x0419: Toggles (R/W) ......................................................................................... 171
Table 77. Registers 0x041A, 0x041C, 0x041E, 0x0420: Continuous N Times Detect (CNTD) Values (R/W) ..... 171
Table 78. Registers 0x041B, 0x041D, 0x041F, 0x0421: Continuous N Times Detect (CNTD) Values (R/W) ..... 172
Table 79. Registers 0x0422--0x042D: Receive Control (R/W) ............................................................................ 173
Table 80. Registers 0x042E: Transmit Control Port A (R/W) ............................................................................... 177
Table 81. Registers 0x042F, 0x0431, 0x0433, 0x0435: Transmit Control (R/W) ................................................. 180
Table 82. Registers 0x0430, 0x0432, 0x0434: Transmit Control Port [B--D] (R/W) ............................................ 181
Table 83. Registers 0x0436--0x0439: Transmit Control (R/W) ........................................................................... 184
Table 84. Registers 0x043A--0x0451: OHP Signal Degrade BER Algorithm Parameters (R/W) ........................ 185
Table 85. Registers 0x0452--0x0469: OHP Signal Fail BER Algorithm Parameters (R/W) ................................ 186
Table 86. Ns, L, M, and B Values to Set the BER Indicator ................................................................................. 187
Table 87. Ns, L, M, and B Values to Clear the BER Indicator .............................................................................. 188
Table 88. Registers 0x046A--0x047D: B1, B2, M1 Error Count (RO) ................................................................. 189
Table 89. Registers 0x047E--0x0485: Transmit F1, S1, K2, K1 OH Insert Value (R/W) .................................... 189
Table 90. Registers 0x0486--0x0491: Receive F1, S1, K2, K1 Monitor Value (RO) ........................................... 190
Table 91. Registers 0x0492--0x04F9: Receive J0 Monitor Value (RO) .............................................................. 190
Table 92. Registers 0x0512--0x0579: Transmit J0 Insert Value (R/W) ............................................................... 190
Table 93. Registers 0x05AA--0x05C1: Transmit Z0 Insert Value (R/W) .............................................................191
Table 94. Register 0x05C2: Scratch Register (R/W) ............................................................................................ 191
Table 95. Register 0x0800: PT Macrocell Version Number (RO) ......................................................................... 192
Table 96. Register 0x0801: PT Interrupt (RO) ...................................................................................................... 192
Table 97. Registers 0x0802, 0x080F, 0x081C, 0x0829 and 0x0803, 0x0810, 0x081D, 0x082A:

PT Delta/Event Parameters (COR/W) .................................................................................................. 192

Table 98. Registers 0x0836--0x083B, 0x0868--0x0887, 0x0888--0x088D, 0x08BA--0x08D9,

0x08DA--0x08DF, 0x090C--0x092B, 0x092C--0x0931, 0x095E--0x097D:
PT State Registers (RO) ...................................................................................................................... 194

Table 99. Register 0x097E: PT Interrupt Mask Control (R/W) ............................................................................. 195

List of Tables

(continued)

Contents

Page

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Table 100. Registers 0x097F--0x0980, 0x098C--0x098D, 0x0999--0x099A, 0x09A6--0x09A7: PT Interrupt

Mask Control (R/W) ............................................................................................................................196

Table 101. Registers (0x09B3, 0x09BF, 0x09CB, 0x09D7, 0x09E3), (0x09EF, 0x09FB, 0x0A07, 0x0A14, 0x0A20),

(0x0A2C, 0x0A38, 0x0A44, 0x0A50, 0x0A5C), (0x0A68, 0x0A74, 0x0A80, 0x0A8C, 0x0A98):
Error Counters (RO) ...........................................................................................................................198

Table 102. Register 0x0AA4: PT One-Shot Control Parameters (WO) ................................................................198
Table 103. Registers 0x0AA6--0x0AAD, 0x0AAE, 0x0AB5, 0x0AB6--0x0ABD, 0x0ABE--0x0AC5:

PT Control Parameters (R/W) ............................................................................................................199

Table 104. Registers 0x0AC6--0x0AF7: PT Provisioning (R/W) .........................................................................205
Table 105. Registers 0x0ACC--0x0AD1: PT Signal Fail BER Algorithm Parameters (R/W) ...............................206
Table 106. Registers 0x0AD2--0x0AD7: PT Signal Degrade BER Algorithm Parameters (R/W) .......................207
Table 107. Ns, L, M, and B Values to Set the BER Indicator ...............................................................................208
Table 108. Ns, L, M, and B Values to Clear the BER Indicator ............................................................................209
Table 109. Registers 0x0AD8--0x0AF7: Transmit J1 Data Insert (R/W) .............................................................210
Table 110. Register 0x0AF8: Scratch Register (R/W) ..........................................................................................210
Table 111. Register 0x1000: DE Macrocell Version Number (RO) ......................................................................211
Table 112. Register 0x1001, 0x1002: DE Interrupts (0x1001 is RO, 0x1002 is RO and COR/W) .......................211
Table 113. Register 0x1004: Dry Escape Marker (R/W) ......................................................................................213
Table 114. Registers 0x1010--0x1015: Sequencer Provisioning Registers (R/W) ..............................................214
Table 115. Registers 0x1016--0x1021: Egress Configuration (R/W) ..................................................................215
Table 116. Registers 0x1022--0x102D: Ingress Configuration (R/W) .................................................................219
Table 117. Registers 0x102E--0x1031: Over-Fiber Mode (Packet-Over-Fiber or POF) Control (R/W) ..............223
Table 118. Registers 0x1032--0x1036: Sequencer Cell State Registers (R/W) ..................................................225
Table 119. Registers 0x1040--0x1043: Ingress Payload Type and Mode Control (R/W) ...................................225
Table 120. Receive Type and Mode Control Summary Table (Registers 0x1040--0x1043) ...............................226
Table 121. Registers 0x1080--0x1087: ATM Framer Idle Cell Match Mask (R/W) .............................................227
Table 122. Registers 0x1088--0x108F: ATM Idle Cell Registers (R/W) ..............................................................227
Table 123. Registers 0x1090--0x1097: ATM Unassigned Cell Match Mask (R/W) .............................................228
Table 124. Registers 0x1098--0x109F: ATM Unassigned Cell Registers (R/W) .................................................228
Table 125. Registers 0x10A0--0x10A3: ATM Framer State Registers (RO) .......................................................229
Table 126. Register 0x10A4: ATM X43 Frame Control (R/W) ..............................................................................229
Table 127. Register 0x10A5: ATM X31 Frame Control (R/W) ..............................................................................230
Table 128. Register 0x10A6: ATM X31 V/W Values (R/W) ..................................................................................230
Table 129. Register 0x10A7: ATM X31 X/Y Values (R/W) ...................................................................................231
Table 130. Register 0x10A8: ATM X31 Z Value (R/W) ........................................................................................231
Table 131. Register 0x10A9: Frame State Interrupt Mask (R/W) .........................................................................232
Table 132. Register 0x10AA: Scrambler State Interrupt Mask (R/W) ..................................................................232
Table 133. Register 0x10AB: ATM Receive Debug Register (R/W) .....................................................................233
Table 134. Registers 0x10B0--0x10B3: PPP Attach (R/W) .................................................................................234
Table 135. Registers 0x10E0--0x10E3: Egress Payload Type and Mode Control (R/W) ...................................234
Table 136. Transmit Type and Mode Control Summary Table (Registers 0x10E0--0x10E3) .............................235
Table 137. Registers 0x10F0--10FB: PPP Header Value Detach (R/W) ............................................................235
Table 138. Registers 0x10FC--0x10FF: PPP Header Detach Search (R/W) ......................................................236
Table 139. Registers 0x1100--0x1107: ATM/HDLC/SDL Framer--Condition Counter 1

(PMRST Update) (RO) .......................................................................................................................238

Table 140. Registers 0x1108--0x110F: ATM/HDLC/SDL Framer--Condition Counter 2

(PMRST Update) (RO) .......................................................................................................................239

Table 141. Registers 0x1110--0x1117: CRC Checker--Bad Packet Counter (PMRST Update) (RO) ...............240
Table 142. Registers 0x1118--0x111F: PPP Detach--Mismatched Header Counter (PMRST Update) (RO) ...241
Table 143. Registers 0x1120--0x1127: Receive Good Packet/Cell Counter (PMRST Update) (RO) .................242
Table 144. Registers 0x1128--0x112F: Transmit Good Packet/Cell Counter (PMRST Update) (RO) ................243

List of Tables

(continued)

Contents

Page

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Table 145. Registers 0x1180--0x1186: Interrupt Masks for Packet Counters (R/W) ..........................................243
Table 146. Registers 0x1181--0x1187: Interrupts for Packet Counters (COR/W) .............................................. 244
Table 147. Registers 0x1200--0x1213, 0x12F0: ATM Transmit Registers (R/W) ............................................... 244
Table 148. Registers 0x1400--0x1403: SDL State Registers (RO) ..................................................................... 246
Table 149. Registers 0x1470--0x1473: A Message Mailbox Registers (RO) ...................................................... 247
Table 150. Registers 0x1480--0x1483: A Message Mailbox Registers (RO) ...................................................... 247
Table 151. Registers 0x1490--0x1493: A Message Mailbox Registers (RO) ...................................................... 247
Table 152. Registers 0x14A0--0x14A3: B Message Mailbox Registers (RO) ..................................................... 247
Table 153. Registers 0x14B0--0x14B3: B Message Mailbox Registers (RO) ..................................................... 248
Table 154. Registers 0x14C0--0x14C3: B Message Mailbox Registers (RO) ..................................................... 248
Table 155. Registers 0x14D0--0x14D3: SDL Interrupt Masks (R/W) .................................................................. 248
Table 156. Registers 0x14E0--0x14E3: SDL Interrupts (COR/W) ...................................................................... 249
Table 157. Register 0x14F0: SDL Receive Configuration Registers (R/W) ......................................................... 249
Table 158. Registers 0x1600--0x1607: SDL Transmit Registers (R/W) .............................................................. 250
Table 159. Recommended Operating Conditions ................................................................................................ 254
Table 160. 3.3 V Logic Interface Characteristics .................................................................................................. 254
Table 161. LVPECL Interface Characteristics ...................................................................................................... 254
Table 162. LVPECL 3.3 V Logic Interface Characteristics ................................................................................... 255
Table 163. Microprocessor Interface Synchronous Write Cycle Specifications ................................................... 257
Table 164. Microprocessor Interface Synchronous Read Cycle Specifications ................................................... 259
Table 165. Microprocessor Interface Asynchronous Write Cycle Specifications .................................................. 261
Table 166. Microprocessor Interface Asynchronous Read Cycle Specifications ................................................. 263
Table 167. Receive Line-Side Timing Specifications ........................................................................................... 266
Table 168. Transmit Line-Side Timing Specifications .......................................................................................... 267
Table 169. Transmit UTOPIA Interface Timing Specifications ............................................................................. 268
Table 170. Receive UTOPIA Interface Timing Specifications .............................................................................. 269
Table 171. UTOPIA Interface Clock Specifications .............................................................................................. 270
Table 172. Transmit TOAC Interface Timing Specifications ................................................................................. 271
Table 173. Receive TOAC Interface Timing Specifications .................................................................................. 272
Table 174. SONET/SDH Comparisons ................................................................................................................ 274
Table 175. SONET/SDH New Terminology ..........................................................................................................274

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Description

The TDAT042G5 SONET/SDH interface device provides a versatile solution for quad STS-3/STM-1,
quad STS-12/STM-4, and for single STS-48/STM-16 point-to-point datacom/telecom applications. Constructed
using Agere Systems Inc.'s state-of-the-art CMOS technology, this device incorporates integrated SONET/SDH
framing, section and line overhead insertion and extraction, path termination, and generation.

The integrated circuit provides complete encapsulation and decapsulation for packet and ATM streams into and
out of SONET/SDH payloads.

Communication with the device is accomplished through a generic microprocessor interface. The device supports
separate address and data buses.

With the device, construction of all types of point-to-point STS-3/STS-12/STS-48 (STM-1/STM-4/
STM-16) data equipment is simplified and cost-reduced, allowing extremely efficient solutions.

Pin Information

TDAT042G5 is available in a 600-pin LBGA package. The pin diagram is shown in Figure 1. For convenience, pin
assignments are listed by pin order in Table 1 and by signal name in Table 2. The pin descriptions as well as the
pin assignments are listed in Table 3--Table 10 and are grouped by interface type.

5-7175(F)

Figure 1. Pin Diagram of 600-Pin LBGA (Bottom View)

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 1. Pin Assignments for 600-Pin LBGA by Pin Number Order

Note: NC refers to no connect. Do not connect pins so designated.

Pin

Signal Name

Pin

Signal Name

Pin

Signal Name

Pin

Signal Name

DDD

GND

DDD

GND

DDD

GND

DDD

DDA

GND

INT

RST

PMRST

GND

MPCLK

MPMODE

DATA[1]

DATA[0]

R/W

A10

DATA[6]

B10

DATA[5]

C10

DATA[4]

D10

DATA[3]

A11

DATA[10]

B11

DATA[9]

C11

DATA[8]

D11

DATA[7]

A12

DATA[15]

B12

DATA[14]

C12

DATA[13]

D12

DATA[12]

A13

GND

B13

ADDR[3]

C13

ADDR[2]

D13

ADDR[1]

A14

ADDR[8]

B14

ADDR[7]

C14

ADDR[6]

D14

ADDR[5]

A15

ADDR[12]

B15

ADDR[11]

C15

ADDR[10]

D15

A16

GND

B16

ADDR[15]

C16

ADDR[14]

D16

ADDR[13]

A17

DDD

B17

C17

D17

A18

DDD

B18

C18

D18

A19

B19

C19

D19

A20

GND

B20

C20

D20

A21

B21

C21

D21

A22

B22

C22

D22

A23

GND

B23

C23

D23

A24

B24

C24

D24

A25

B25

C25

D25

A26

B26

C26

D26

A27

GND

B27

C27

D27

DDD

A28

GND

B28

C28

D28

A29

GND

B29

C29

D29

A30

DDD

B30

C30

D30

A31

DDD

B31

C31

D31

A32

GND

B32

GND

C32

GND

D32

DDD

A33

GND

B33

GND

C33

DDD

D33

GND

A34

DDD

B34

DDD

C34

GND

D34

GND

A35

DDD

B35

DDD

C35

GND

D35

GND

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 1.

Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)

Note: NC refers to no connect. Do not connect pins so designated.

Pin

Signal Name

Pin

Signal Name

Pin

Signal Name

Pin

Signal Name

DDD

J31

TxEOP[A]

GND

TCK

J32

TxSOP/C[A]

TxD[6]N

DDD

PLL

GND

J33

TxPRTY[A]

TxD[6]P

GND

PLL

TMS

J34

TxDATA[A][15]

TxD[7]N

DDD

J35

TxDATA[A][14]

TxD[7]P

F31

TxD[12]N

N31

RxDATA[A][15]

ICT

F32

TxD[12]P

N32

RxDATA[A][14]

F33

TxD[13]N

N33

RxDATA[A][13]

ADS

F34

TxD[13]P

N34

RxDATA[A][12]

E10

DATA[2]

F35

DDD

N35

GND

E11

DDD

GND

K31

TxDATA[A][13]

TxD[4]N

E12

DATA[11]

TDO

K32

TxDATA[A][12]

TxD[4]P

E13

ADDR[0]

TRST

K33

TxDATA[A][11]

TxD[5]N

E14

ADDR[4]

K34

TxDATA[A][10]

DDD

E15

ADDR[9]

TDI

K35

TxDATA[A][9]

TxD[5]P

E16

DDD

G31

TxD[10]N

P31

RxDATA[A][11]

E17

G32

TxADDR[0]

TxD[10]P

P32

RxDATA[A][10]

E18

G33

TxADDR[1]

TxD[11]N

P33

RxDATA[A][9]

E19

G34

TxCLK[A]

TxD[11]P

P34

RxDATA[A][8]

E20

DDD

G35

GND

DDD

P35

RxDATA[A][7]

E21

GND

L31

DDD

E22

TxCKQP

L32

TxDATA[A][8]

TxD[2]N/TxD[B]N

E23

GND

L33

TxDATA[A][7]

TxD[2]P/TxD[B]P

E24

CLKDIV

L34

TxDATA[A][6]

TxD[3]P/TxD[A]P

E25

DDD

GND

L35

TxDATA[A][5]

TxD[3]N/TxD[A]N

E26

H31

TxSZ[A]

TxD[8]N

R31

RxDATA[A][6]

E27

H32

TxERR[A]

TxD[8]P

R32

RxDATA[A][5]

E28

H33

TxPA[A]

TxD[9]N

R33

RxDATA[A][4]

E29

H34

TxENB[A]

TxD[9]P

R34

RxDATA[A][3]

E30

H35

GND

DDD

R35

RxDATA[A][2]

E31

DDD

TxD[14]N

M31

TxDATA[A][4]

GND

E32

TxD[14]P

M32

TxDATA[A][3]

TxD[0]P/TxD[D]P

E33

TxD[15]N

M33

TxDATA[A][2]

TxD[1]N/TxD[C]N

E34

TxD[15]P

M34

TxDATA[A][1]

TxD[1]P/TxD[C]P

E35

DDD

TxCKQN

M35

TxDATA[A][0]

DDD

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 1.

Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)

Note: NC refers to no connect. Do not connect pins so designated.

Pin

Signal Name

Pin

Signal Name

Pin

Signal Name

Pin

Signal Name

T31

DDD

GND

AC31 TxDATA[B][8]

AG1

RxD[0]N

T32

RxDATA[A][1]

RxD[13]N/
RxCLK[B]N

AC32 TxDATA[B][9]

AG2

RxD[0]P

T33

RxDATA[A][0]

RxD[13]P/
RxCLK[B]P

AC33 TxDATA[B][10]

AG3

ECLREFLO

T34

RxPRTY[A]

GND

AC34 TxDATA[B][11]

AG4

ECLREFHI

T35

GND

DDD

AC35 GND

AG5

GPIO[3]

TxFSYNCN

Y31

DDD

AD1

RxD[5]N

AG31 RxDATA[B][5]

TxD[0]N/
TxD[D]N

Y32

TxSZ[B]

AD2

RxD[5]P

AG32 RxDATA[B][6]

TxFSYNCP

Y33

TxCLK[B]

AD3

RxD[6]N

AG33 RxDATA[B][7]

TxCKP

Y34

TxADDR[3]

AD4

RxD[6]P

AG34 RxDATA[B][8]

TxCKN

Y35

GND

AD5

DDD

AG35 RxDATA[B][9]

U31

RxSOP/C[A]

AA1

RxD[11]N/
RxCLK[C]N

AD31 TxDATA[B][3]

AH1

GND

U32

RxEOP[A]

AA2

RxD[11]P/RxCLK[C]P

AD32 TxDATA[B][4]

AH2

GPIO[2]

U33

AA3

RxD[12]N/RxD[C]N

AD33 TxDATA[B][5]

AH3

GPIO[1]

U34

RxENB[A]

AA4

RxD[12]P/RxD[C]P

AD34 TxDATA[B][6]

AH4

GPIO[0]

U35

DDD

AA5

GND

AD35 TxDATA[B][7]

AH5

TxTOHF

DDD

AA31 TxEOP[B]

AE1

RxD[3]N

AH31 RxDATA[B][1]

DDD

AA32 TxSOP/C[B]

AE2

RxD[3]P

AH32 RxDATA[B][2]

GND

AA33 TxENB[B]

AE3

RxD[4]N

AH33 RxDATA[B][3]

CKN/R

[A]

AA34 TxPA[B]

AE4

RxD[4]P

AH34 RxDATA[B][4]

CKP/R

[A]

AA35 TxERR[B]

AE5

DDD

AH35 GND

V31

GND

AB1

D[9]N/R

CLK[D]N

AE31 V

DDD

AJ1

GND

V32

RxERR[A]

AB2

D[9]P/R

CLK[D]P

AE32 RxDATA[B][15]

AJ2

TxTOHCK

V33

RxPA[A]

AB3

RxD[10]N/RxD[D]N

AE33 TxDATA[B][0]

AJ3

TxTOHD[A]

V34

AB4

RxD[10]P/RxD[D]P

AE34 TxDATA[B][1]

AJ4

TxTOHD[B]

V35

DDD

AB5

DDD

AE35 TxDATA[B][2]

AJ5

TxTOHD[C]

DDD

AB31 TxDATA[B][13]

AF1

RxD[1]N

AJ31

RxEOP[B]

RxD[14]N

RxCLK[A]N

AB32 TxDATA[B][12]

AF2

RxD[1]P

AJ32

RxSOP/C[B]

RxD[14]P

RxCLK[A]P

AB33 TxDATA[B][14]

AF3

RxD[2]N

AJ33

RxPRTY[B]

RxD[15]N/
RxD[B]N

AB34 TxDATA[B][15]

AF4

RxD[2]P

AJ34

RxDATA[B][0]

RxD[15]P/
RxD[B]P

AB35 TxPRTY[B]

AF5

DDD

AJ35

GND

W31

RxADDR[0]

AC1

GND

AF31 RxDATA[B][10]

AK1

DDD

W32

RxADDR[1]

AC2

RxD[7]N

AF32 RxDATA[B][11]

AK2

TxTOHD[D]

W33

RxCLK[A]

AC3

RxD[7]P

AF33 RxDATA[B][12]

AK3

RxREF

W34

TxADDR[2]

AC4

RxD[8]N

AF34 RxDATA[B][13]

AK4

RxTOHF[A]

W35

RxSZ[A]

AC5

RxD[8]P

AF35 RxDATA[B][14]

AK5

RxTOHCK[A]

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 1.

Pin Assignments for 600-Pin LBGA by Pin Number Order (continued)

Note: NC refers to no connect. Do not connect pins so designated.

Pin

Signal Name

Pin

Signal Name

Pin

Signal Name

Pin

Signal Name

AK31 RxSZ[B]

AL31

DDD

AM31 TxADDR[4]

AN31 NC

AK32 RxERR[B]

AL32

RxADDR[3]

AM32 V

DDD

AN32 GND

AK33 RxPA[B]

AL33

RxADDR[2]

AM33 GND

AN33 V

DDD

AK34 RxENB[B]

AL34

RxCLK[B]

AM34 GND

AN34 GND

AK35 V

DDD

AL35

DDD

AM35 GND

AN35 GND

AL1

DDD

AM1

GND

AN1

GND

AP1

DDD

AL2

RxTOHD[A]

AM2

GND

AN2

GND

AP2

DDD

AL3

RxTOHF[B]

AM3

GND

AN3

DDD

AP3

GND

AL4

RxTOHCK[B]

AM4

DDD

AN4

GND

AP4

GND

AL5

DDD

AM5

RxTOHD[B]

AN5

RxTOHF[C]

AP5

AL6

RxTOHCK[C]

AM6

RxTOHD[C]

AN6

GND

AP6

RxTOHF[D]

AL7

RxTOHCK[D]

AM7

AN7

RxTOHD[D]

AP7

AL8

AM8

RxCLK[D]

AN8

RxSZ[D]

AP8

RxERR[D]

AL9

RxPA[D]

AM9

RxENB[D]

AN9

RxEOP[D]

AP9

RxSOP/C[D]

AL10

RxDATA[D][0]

AM10 RxDATA[D][1]

AN10 RxDATA[D][2]

AP10 RxDATA[D][3]

AL11

DDD

AM11 RxDATA[D][5]

AN11 RxDATA[D][6]

AP11 RxDATA[D][7]

AL12

RxDATA[D][9]

AM12 RxDATA[D][10]

AN12 RxDATA[D][11]

AP12 RxDATA[D][12]

AL13

RxDATA[D][14]

AM13 RxDATA[D][15]

AN13 TxDATA[D][0]

AP13 TxDATA[D][1]

AL14

TxDATA[D][3]

AM14 TxDATA[D][2]

AN14 TxDATA[D][4]

AP14 TxDATA[D][5]

AL15

TxDATA[D][8]

AM15 TxDATA[D][7]

AN15 TxDATA[D][9]

AP15 TxDATA[D][10]

AL16

DDD

AM16 TxDATA[D][12]

AN16 TxDATA[D][13]

AP16 TxDATA[D][14]

AL17

TxSOP/C[D]

AM17 TxPRTY[D]

AN17 TxEOP[D]

AP17 TxDATA[D][15]

AL18

DDD

AM18 TxERR[D]

AN18 TxSZ[D]

AP18 TxPA[D]

AL19

AM19 NC

AN19 NC

AP19 TxCLK[D]

AL20

DDD

AM20 RxSZ[C]

AN20 RxCLK[C]

AP20 RxADDR[4]

AL21

RxSOP/C[C]

AM21 RxEOP[C]

AN21 RxENB[C]

AP21 RxPA[C]

AL22

RxDATA[C][3]

AM22 RxDATA[C][2]

AN22 RxDATA[C][1]

AP22 RxDATA[C][0]

AL23

RxDATA[C][7]

AM23 RxDATA[C][6]

AN23 RxDATA[C][5]

AP23 RxDATA[C][4]

AL24

RxDATA[C][12]

AM24 RxDATA[C][11]

AN24 RxDATA[C][10]

AP24 RxDATA[C][9]

AL25

DDD

AM25 TxDATA[C][0]

AN25 RxDATA[C][15]

AP25 RxDATA[C][14]

AL26

TxDATA[C][5]

AM26 TxDATA[C][4]

AN26 TxDATA[C][3]

AP26 TxDATA[C][2]

AL27

TxDATA[C][10]

AM27 TxDATA[C][9]

AN27 TxDATA[C][8]

AP27 TxDATA[C][7]

AL28

TxDATA[C][14]

AM28 TxDATA[C][13]

AN28 TxDATA[C][12]

AP28 TxDATA[C][11]

AL29

TxEOP[C]

AM29 TxSOP/C[C]

AN29 TxPRTY[C]

AP29 TxDATA[C][15]

AL30

TxSZ[C]

AM30 TxERR[C]

AN30 TxPA[C]

AP30 TxENB[C]

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 2. Pin Assignments for 600-Pin LBGA by Signal Name

Note: NC refers to no connect. Do not connect pins so designated.

Signal Name

Pin

Signal Name

Pin

Signal Name

Pin

Signal Name

Pin

ADDR[0]

E13

GND

AP3

ADDR[1]

D13

GND

G35

GND

AP32

ADDR[2]

C13

ECLREFHI

AG4

GND

AP33

ADDR[3]

B13

ECLREFLO

AG3

GND

AP4

ADDR[4]

E14

GND

AR3

ADDR[5]

D14

GND

H35

GND

AR4

ADDR[6]

C14

GND

AR7

ADDR[7]

B14

GND

N35

GND

AR8

ADDR[8]

A14

GND

AR13

ADDR[9]

E15

GND

A13

GND

T35

GND

AR16

ADDR[10]

C15

GND

A16

GND

AR20

ADDR[11]

B15

GND

A20

GND

V31

GND

AR23

ADDR[12]

A15

GND

A23

GND

AR28

ADDR[13]

D16

GND

A27

GND

AR29

ADDR[14]

C16

GND

A28

GND

Y35

GND

AR32

ADDR[15]

B16

GND

A29

GND

AA5

GND

AR33

ADS

GND

A32

GND

AC1

GND

PLL

CLKDIV

GND

A33

GND

AC35

GPIO[0]

AH4

GND

AH1

GPIO[1]

AH3

DATA[0]

GND

AH35

GPIO[2]

AH2

DATA[1]

GND

B32

GND

AJ1

GPIO[3]

AG5

DATA[2]

E10

GND

B33

GND

AJ35

ICT

DATA[3]

D10

GND

AM1

INT

DATA[4]

C10

GND

AM2

MPCLK

DATA[5]

B10

GND

AM3

MPMODE

DATA[6]

A10

GND

C32

GND

AM33

A19

DATA[7]

D11

GND

C34

GND

AM34

A21

DATA[8]

C11

GND

C35

GND

AM35

A22

DATA[9]

B11

GND

AN1

A24

DATA[10]

A11

GND

AN2

A25

DATA[11]

E12

GND

AN4

A26

DATA[12]

D12

GND

D33

GND

AN6

DATA[13]

C12

GND

D34

GND

AN32

B17

DATA[14]

B12

GND

D35

GND

AN34

B18

DATA[15]

A12

GND

AN35

B19

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 2.

Pin Assignments for 600-Pin LBGA by Signal Name (continued)

Note: NC refers to no connect. Do not connect pins so designated.

Signal Name

Pin

Signal Name

Pin

Signal Name

Pin

Signal Name

Pin

B20

D21

V34

RxD[6]N

AD3

B21

D22

AL8

RxD[6]P

AD4

B22

D23

AL19

RxD[7]N

AC2

B23

D24

AM7

RxD[7]P

AC3

B24

D25

AM19

RxD[8]N

AC4

B25

D26

AN19

RxD[8]P

AC5

B26

D28

AN31

D[9]N/R

CLK[D]N

AB1

B27

D29

AP5

D[9]P/R

CLK[D]P

AB2

B28

D30

AP7

RxD[10]N/RxD[D]N

AB3

B29

D31

PMRST

RxD[10]P/RxD[D]P

AB4

B30

R/W

RxD[11]N/RxCLK[C]N

AA1

B31

RST

RxD[11]P/RxCLK[C]P

AA2

E17

RxADDR[0]

W31

RxD[12]N/RxD[C]N

AA3

C17

E18

RxADDR[1]

W32

RxD[12]P/RxD[C]P

AA4

C18

E19

RxADDR[2]

AL33

RxD[13]N/RxCLK[B]N

C19

E21

RxADDR[3]

AL32

RxD[13]P/RxCLK[B]P

C20

E22

RxADDR[4]

AP20

RxD[14]N/RxCLK[A]N

C21

E23

CKN/R

[A]

RxD[14]P/RxCLK[A]P

C22

E24

CKP/R

[A]

RxD[15]N/RxD[B]N

C23

E26

RxCLK[A]

W33

RxD[15]P/RxD[B]P

C24

E27

RxCLK[B]

AL34

RxDATA[A][0]

T33

C25

E28

RxCLK[C]

AN20

RxDATA[A][1]

T32

C26

E29

RxCLK[D]

AM8

RxDATA[A][2]

R35

C27

E30

RxD[0]N

AG1

RxDATA[A][3]

R34

C28

E32

RxD[0]P

AG2

RxDATA[A][4]

R33

C29

E33

RxD[1]N

AF1

RxDATA[A][5]

R32

C30

E34

RxD[1]P

AF2

RxDATA[A][6]

R31

C31

RxD[2]N

AF3

RxDATA[A][7]

P35

F31

RxD[2]P

AF4

RxDATA[A][8]

P34

F32

RxD[3]N

AE1

RxDATA[A][9]

P33

D15

F33

RxD[3]P

AE2

RxDATA[A][10]

P32

D17

F34

RxD[4]N

AE3

RxDATA[A][11]

P31

D18

RxD[4]P

AE4

RxDATA[A][12]

N34

D19

G31

RxD[5]N

AD1

RxDATA[A][13]

N33

D20

U33

RxD[5]P

AD2

RxDATA[A][14]

N32

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 2.

Pin Assignments for 600-Pin LBGA by Signal Name (continued)

Note: NC refers to no connect. Do not connect pins so designated.

Signal Name

Pin

Signal Name

Pin

Signal Name

Pin

Signal Name

Pin

RxDATA[A][15]

N31

RxDATA[D][2]

AN10

RxSOP/C[A]

U31

TxCLK[B]

Y33

RxDATA[B][0]

AJ34

RxDATA[D][3]

AP10

RxSOP/C[B]

AJ32

TxCLK[C]

AP31

RxDATA[B][1]

AH31

RxDATA[D][4]

AR10

RxSOP/C[C]

AL21

TxCLK[D]

AP19

RxDATA[B][2]

AH32

RxDATA[D][5]

AM11

RxSOP/C[D]

AP9

TxD[0]N/TxD[D]N

RxDATA[B][3]

AH33

RxDATA[D][6]

AN11

RxSZ[A]

W35

TxD[0]P/TxD[D]P

RxDATA[B][4]

AH34

RxDATA[D][7]

AP11

RxSZ[B]

AK31

TxD[1]N/TxD[C]N

RxDATA[B][5]

AG31

RxDATA[D][8]

AR11

RxSZ[C]

AM20

TxD[1]P/TxD[C]P

RxDATA[B][6]

AG32

RxDATA[D][9]

AL12

RxSZ[D]

AN8

TxD[2]N/TxD[B]N

RxDATA[B][7]

AG33

RxDATA[D][10]

AM12

RxTOHCK[A]

AK5

TxD[2]P/TxD[B]P

RxDATA[B][8]

AG34

RxDATA[D][11]

AN12

RxTOHCK[B]

AL4

TxD[3]N/TxD[A]N

RxDATA[B][9]

AG35

RxDATA[D][12]

AP12

RxTOHCK[C]

AL6

TxD[3]P/TxD[A]P

RxDATA[B][10]

AF31

RxDATA[D][13]

AR12

RxTOHCK[D]

AL7

TxD[4]N

RxDATA[B][11]

AF32

RxDATA[D][14]

AL13

RxTOHD[A]

AL2

TxD[4]P

RxDATA[B][12]

AF33

RxDATA[D][15]

AM13

RxTOHD[B]

AM5

TxD[5]N

RxDATA[B][13]

AF34

RxENB[A]

U34

RxTOHD[C]

AM6

TxD[5]P

RxDATA[B][14]

AF35

RxENB[B]

AK34

RxTOHD[D]

AN7

TxD[6]N

RxDATA[B][15]

AE32

RxENB[C]

AN21

RxTOHF[A]

AK4

TxD[6]P

RxDATA[C][0]

AP22

RxENB[D]

AM9

RxTOHF[B]

AL3

TxD[7]N

RxDATA[C][1]

AN22

RxEOP[A]

U32

RxTOHF[C]

AN5

TxD[7]P

RxDATA[C][2]

AM22

RxEOP[B]

AJ31

RxTOHF[D]

AP6

TxD[8]N

RxDATA[C][3]

AL22

RxEOP[C]

AM21

TCK

TxD[8]P

RxDATA[C][4]

AP23

RxEOP[D]

AN9

TDI

TxD[9]N

RxDATA[C][5]

AN23

RxERR[A]

V32

TDO

TxD[9]P

RxDATA[C][6]

AM23

RxERR[B]

AK32

TMS

TxD[10]N

RxDATA[C][7]

AL23

RxERR[C]

AR21

TRST

TxD[10]P

RxDATA[C][8]

AR24

RxERR[D]

AP8

TxADDR[0]

G32

TxD[11]N

RxDATA[C][9]

AP24

RxPA[A]

V33

TxADDR[1]

G33

TxD[11]P

RxDATA[C][10]

AN24

RxPA[B]

AK33

TxADDR[2]

W34

TxD[12]N

RxDATA[C][11]

AM24

RxPA[C]

AP21

TxADDR[3]

Y34

TxD[12]P

RxDATA[C][12]

AL24

RxPA[D]

AL9

TxADDR[4]

AM31

TxD[13]N

RxDATA[C][13]

AR25

RxPRTY[A]

T34

TxCKN

TxD[13]P

RxDATA[C][14]

AP25

RxPRTY[B]

AJ33

TxCKP

TxD[14]N

RxDATA[C][15]

AN25

RxPRTY[C]

AR22

TxCKQN

TxD[14]P

RxDATA[D][0]

AL10

RxPRTY[D]

AR9

TxCKQP

TxD[15]N

RxDATA[D][1]

AM10

RxREF

AK3

TxCLK[A]

G34

TxD[15]P

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 2.

Pin Assignments for 600-Pin LBGA by Signal Name (continued)

Note: NC refers to no connect. Do not connect pins so designated.

Signal Name

Pin

Signal Name

Pin

Signal Name

Pin

Signal Name

Pin

TxDATA[A][0]

M35

TxDATA[C][3]

AN26

TxEOP[C]

AL29

DDD

A17

TxDATA[A][1]

M34

TxDATA[C][4]

AM26

TxEOP[D]

AN17

DDD

A18

TxDATA[A][2]

M33

TxDATA[C][5]

AL26

TxERR[A]

H32

DDD

A30

TxDATA[A][3]

M32

TxDATA[C][6]

AR27

TxERR[B]

AA35

DDD

A31

TxDATA[A][4]

M31

TxDATA[C][7]

AP27

TxERR[C]

AM30

DDD

A34

TxDATA[A][5]

L35

TxDATA[C][8]

AN27

TxERR[D]

AM18

DDD

A35

TxDATA[A][6]

L34

TxDATA[C][9]

AM27

TxFSYNCN

DDD

TxDATA[A][7]

L33

TxDATA[C][10]

AL27

TxFSYNCP

DDD

TxDATA[A][8]

L32

TxDATA[C][11]

AP28

TxPA[A]

H33

DDD

B34

TxDATA[A][9]

K35

TxDATA[C][12]

AN28

TxPA[B]

AA34

DDD

B35

TxDATA[A][10]

K34

TxDATA[C][13]

AM28

TxPA[C]

AN30

DDD

TxDATA[A][11]

K33

TxDATA[C][14]

AL28

TxPA[D]

AP18

DDD

C33

TxDATA[A][12]

K32

TxDATA[C][15]

AP29

TxPRTY[A]

J33

DDD

TxDATA[A][13]

K31

TxDATA[D][0]

AN13

TxPRTY[B]

AB35

DDD

D27

TxDATA[A][14]

J35

TxDATA[D][1]

AP13

TxPRTY[C]

AN29

DDD

D32

TxDATA[A][15]

J34

TxDATA[D][2]

AM14

TxPRTY[D]

AM17

DDD

TxDATA[B][0]

AE33

TxDATA[D][3]

AL14

TxSOP/C[A]

J32

DDD

TxDATA[B][1]

AE34

TxDATA[D][4]

AN14

TxSOP/C[B]

AA32

DDD

E11

TxDATA[B][2]

AE35

TxDATA[D][5]

AP14

TxSOP/C[C]

AM29

DDD

E16

TxDATA[B][3]

AD31

TxDATA[D][6]

AR14

TxSOP/C[D]

AL17

DDD

E20

TxDATA[B][4]

AD32

TxDATA[D][7]

AM15

TxSZ[A]

H31

DDD

E25

TxDATA[B][5]

AD33

TxDATA[D][8]

AL15

TxSZ[B]

Y32

DDD

E31

TxDATA[B][6]

AD34

TxDATA[D][9]

AN15

TxSZ[C]

AL30

DDD

E35

TxDATA[B][7]

AD35

TxDATA[D][10]

AP15

TxSZ[D]

AN18

DDD

TxDATA[B][8]

AC31

TxDATA[D][11]

AR15

TxTOHCK

AJ2

DDD

F35

TxDATA[B][9]

AC32

TxDATA[D][12]

AM16

TxTOHD[A]

AJ3

DDD

TxDATA[B][10]

AC33

TxDATA[D][13]

AN16

TxTOHD[B]

AJ4

DDD

TxDATA[B][11]

AC34

TxDATA[D][14]

AP16

TxTOHD[C]

AJ5

DDD

L31

TxDATA[B][12]

AB32

TxDATA[D][15]

AP17

TxTOHD[D]

AK2

DDD

TxDATA[B][13]

AB31

TxENB[A]

H34

TxTOHF

AH5

DDD

TxDATA[B][14]

AB33

TxENB[B]

AA33

DDA

DDD

TxDATA[B][15]

AB34

TxENB[C]

AP30

DDD

TxDATA[C][0]

AM25

TxENB[D]

AR17

DDD

T31

TxDATA[C][1]

AR26

TxEOP[A]

J31

DDD

U35

TxDATA[C][2]

AP26

TxEOP[B]

AA31

DDD

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Note: 3.3 V CMOS logic inputs are 5 V tolerant. Logic inputs can be driven from standard TTL levels, and logic out-

puts can drive standard TTL inputs. All LVPECL buffers are differential. LVPECL is compliant with low-volt-
age (3.3 V) pseudo-emitter-coupled logic interface levels. All PECL outputs, including ECLREFHI and
ECLREFLO require terminating resistors. The required termination for the PECL buffers is 50

to a termi-

nating voltage of V

DDD

� 2 V. The Thevenin equivalent is also acceptable (130

to V

DDD

and 82

GND

). Other termination styles are not recommended. LVPECL inputs with a / in the name indicate multiple

functionality. The name preceding the / is the function in STS-48/STM-16 mode. The name after the / is the
function in STS-3/STM-1 or STS-12/STM-4 mode.

Table 3. Pin Descriptions--Line Interface Signals

Unused LVPECL outputs should not be terminated to minimize power consumption. Unused inputs are internally
disabled whenever core registers 0x0010 and 0x0011 are properly provisioned. The unused inputs can be consid-
ered to be NC (no connect).

Pin

Symbol

Type

I/O

Name/Description

RxCKP/

RxD[A]P

LVPECL

Receive Line Clock (STS-48/STM-16)/Receive Line Data Input Channel
A. In STS-48/STM-16 mode, these pins function as receive line clock. This
155.52 MHz clock comes from an external clock data recovery circuit. This
clock is used to clock in the RxD[15:0] receive line data inputs.

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as receive
data input channel A at 155.52 Mbits/s or 622.08 Mbits/s, respectively.

This buffer is internally disabled when not in STS-48/STM-16 mode and
channel A is disabled. This buffer is internally disabled through proper pro-
visioning when the input is not active.

RxCKN/

RxD[A]N

AG2

RxD[0]P

LVPECL

Receive Line Data Inputs (STS-48/STM-16). In STS-48/STM-16 mode,
these pins function as receive line data inputs [0:8]. The remaining receive
line data inputs [9:15] are listed below and are multiplexed for use in the
STS-3/STM-1 or STS-12/STM-4 modes.

The 2.488 Gbits/s STS-48/STM-16 serial data stream is converted to a
155.52 Mbits/s parallel 16-bit word external to TDAT042G5 by a demulti-
plexer.

All 32 differential data input pins, RxD[15:0]P/N, are used as the parallel
data input bus in the STS-48/STM-16 mode. These pins constitute a
155.52 Mbits/s parallel 16-bit word-aligned to the RxCKP/N 155.52 MHz
receive line clock. RxD[15] is the most significant bit and is the first bit
received. RxD[0] is the least significant bit and is the last bit received.

This buffer is internally disabled through proper provisioning when the input
is not active.

AG1

RxD[0]N

AF2

RxD[1]P

LVPECL

AF1

RxD[1]N

AF4

RxD[2]P

LVPECL

AF3

RxD[2]N

AE2

RxD[3]P

LVPECL

AE1

RxD[3]N

AE4

RxD[4]P

LVPECL

AE3

RxD[4]N

AD2

RxD[5]P

LVPECL

AD1

RxD[5]N

AD4

RxD[6]P

LVPECL

AD3

RxD[6]N

AC3

RxD[7]P

LVPECL

AC2

RxD[7]N

AC5

RxD[8]P

LVPECL

AC4

RxD[8]N

AB2

RxD[9]P/

RxCLK[D]P

LVPECL

Receive Line Data Input [9]/Receive Line Clock Channel D. In STS-48/
STM-16 mode, these pins function as receive line data input [9] at
155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as receive
line clock channel D at either 155.52 MHz (STS-3/STM-1) or 622.08 MHz
(STS-12/STM-4).

This buffer is internally disabled when not in STS-48/STM-16 mode and
channel D is disabled. This buffer is internally disabled through proper pro-
visioning when the input is not active.

AB1

RxD[9]N/

RxCLK[D]N

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 3. Pin Descriptions--Line Interface Signals (continued)

Pin

Symbol

Type

I/O

Name/Description

AB4

RxD[10]P/

RxD[D]P

LVPECL

Receive Line Data Input [10]/Receive Line Data Input
Channel D. In STS-48/STM-16 mode, these pins function as
receive line data input [10] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as
receive line data input channel D at either 155.52 Mbits/s (STS-3/
STM-1) or 622.08 Mbits/s (STS-12/STM-4).

This buffer is internally disabled when not in STS-48/STM-16
mode and channel D is disabled. This buffer is internally disabled
through proper provisioning when the input is not active.

AB3

RxD[10]N/

RxD[D]N

AA2

RxD[11]P/

RxCLK[C]P

LVPECL

Receive Line Data Input [11]/Receive Line Clock Channel C.
In STS-48/STM-16 mode, these pins function as receive line data
input [11] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as
receive line clock channel C at either 155.52 MHz (STS-3/STM-1)
or 622.08 MHz (STS-12/STM-4).

This buffer is internally disabled when not in STS-48/STM-16
mode and channel C is disabled. This buffer is internally disabled
through proper provisioning when the input is not active.

AA1

RxD[11]N/

RxCLK[C]N

AA4

RxD[12]P/

RxD[C]P

LVPECL

Receive Line Data Input [12]/Receive Line Data Input
Channel C. In STS-48/STM-16 mode, these pins function as
receive line data input [12] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as
receive line data input channel C at either 155.52 Mbits/s (STS-3/
STM-1) or 622.08 Mbits/s (STS-12/STM-4).

This buffer is internally disabled when not in STS-48/STM-16
mode and channel C is disabled. This buffer is internally disabled
through proper provisioning when the input is not active.

AA3

RxD[12]N/

RxD[C]N

RxD[13]P/

RxCLK[B]P

LVPECL

Receive Line Data Input [13]/Receive Line Clock Channel B.
In STS-48/STM-16 mode, these pins function as receive line data
input [13] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as
receive line clock channel B at either 155.52 MHz (STS-3/STM-1)
or 622.08 MHz (STS-12/STM-4).

This buffer is internally disabled when not in STS-48/STM-16
mode and channel B is disabled. This buffer is internally disabled
through proper provisioning when the input is not active.

RxD[13]N/

RxCLK[B]N

RxD[14]P/

RxCLK[A]P

LVPECL

Receive Line Data Input [14]/Receive Line Clock Channel A.
In STS-48/STM-16 mode, these pins function as receive line data
input [14] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as
receive line clock channel A at either 155.52 MHz (STS-3/STM-1)
or 622.08 MHz (STS-12/STM-4).

This buffer is internally disabled when not in STS-48/STM-16
mode and channel A is disabled. This buffer is internally disabled
through proper provisioning when the input is not active.

RxD[14]N/

RxCLK[A]N

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 3. Pin Descriptions--Line Interface Signals (continued)

* I

= I

= 50 k

, where I

= internal pull-up resistance and I

= internal pull-down resistance.

This may be obtained from a passive voltage divider of a 130

resistor connected from V

DDD

to one end of an 82

resistor, the other end of

which is connected to GND

Pin

Symbol

Type

I/O*

Name/Description

RxD[15]P/

RxD[B]P

LVPECL

Receive Line Data Input [15]/Receive Line Data Input
Channel B. In STS-48/STM-16 mode, these pins function as
receive line data input [15] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 mode, these pins function as
receive line data input channel B at either 155.52 Mbits/s
(STS-3/STM-1) or 622.08 Mbits/s (STS-12/STM-4).

This buffer is internally disabled when not in STS-48/STM-16
mode and channel B is disabled. This buffer is internally disabled
through proper provisioning when the input is not active.

RxD[15]N/

RxD[B]N

CLKDIV

3.3 V

(5 V tolerant)

Clock Division. This pin controls a divider in the line transmit
block to create a 77.76 MHz clock from either the 155.52 MHz
STS-3/STM-1 or STS-48/STM-16 transmit line clock, or the
622.08 MHz STS-12/STM-4 transmit line clock, TxCKP/N.

CLKDIV = 1 for STS-12/STM-4 (divide by 8).
CLKDIV = 0 for STS-3/STM-1 and STS-48 /STM-16 (divide by 2).

AG3

ECLREFLO

Reference Voltage for LVPECL I/O Buffers. ECLREFLO and
ECLREFHI are buffer outputs which provide the reference for the
output level of the LVPECL output buffers. ECLREFLO and ECL-
REFHI must be connected to a 50

source of V

DDD

� 2 V.

user-accessible signal is present on these pins.

AG4

ECLREFHI

Note: The TDAT042G5 has internal circuitry that is associated with the buffer section of the chip. This section

monitors the voltage levels of REFLO and REFHI. A very low frequency calibration process, during which
the values at the ECLREFLO and ECLREFHI pins are continuously monitored, is performed to allow the
drive capactity of remaining buffers to be adjusted within true PECL levels. Therefore, it is important to ter-
minate the ECLREFLO and ECLREFHI outputs in exactly the same way as you would terminate LVPECL
outputs.

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 3. Pin Descriptions--Line Interface Signals (continued)

* I

= I

= 50 k

, where I

= internal pull-up resistance and I

= internal pull-down resistance.

Pin

Symbol

Type

I/O*

Name/Description

TxCKP

LVPECL

Transmit Line Clock. When in STS-48/STM-16 mode, this clock
is a 155.52 MHz input and clocks out TxD[15:0]P/N or TxD[D:A].

When in STS-12/STM-4 mode, this clock is a 622.08 MHz input
and clocks out TxD[D:A]P/N.

When in STS-3/STM-1 mode, this clock is a 155.52 MHz input
and clocks out TxD[D:A]P/N.

TxCKN

TxFSYNCP

LVPECL

Transmit Line Frame Sync. This input is the external 8 kHz
transmit line frame sync. Driving this input is optional. If undriven
from an external source, these pins must be no connects. When
this input is used, it must be (1) synchronized to TxCKP/N, and (2)
at least one TxCKP/N cycle wide, up to a maximum of 1 frame
period minus 2 TxCKP/N cycles wide.

TxFSYNCN

TxD[0]P/

TxD[D]P

LVPECL

Transmit Line Data Output [0]/Transmit Line Data Output
Channel D. In STS-48/STM-16 mode, the pins function as trans-
mit line data output [0] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as
transmit data output channel D at either 155.52 Mbits/s or
622.08 Mbits/s.

This buffer is internally disabled through proper provisioning when
the input is not active.

TxD[0]N/

TxD[D]N

TxD[1]P/

TxD[C]P

LVPECL

Transmit Line Data Output [1]/Transmit Line Data Output
Channel C. In STS-48/STM-16 mode, the pins function as trans-
mit line data output [1] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as
transmit data output channel C at either 155.52 Mbits/s or
622.08 Mbits/s.

This buffer is internally disabled through proper provisioning when
the input is not active.

TxD[1]N/

TxD[C]N

TxD[2]P/

TxD[B]P

LVPECL

Transmit Line Data Output [2]/Transmit Line Data Output
Channel B. In STS-48/STM-16 mode, the pins function as trans-
mit line data output [2] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as
transmit data output channel B at either 155.52 Mbits/s or
622.08 Mbits/s.

This buffer is internally disabled through proper provisioning when
the input is not active.

TxD[2]N/

TxD[B]N

TxD[3]P/

TxD[A]P

LVPECL

Transmit Line Data Output [3]/Transmit Line Data Output
Channel A. In STS-48/STM-16 mode, the pins function as trans-
mit line data output [3] at 155.52 Mbits/s.

In STS-3/STM-1 or STS-12/STM-4 mode, the pins function as
transmit data output channel A at either 155.52 Mbits/s or
622.08 Mbits/s.

This buffer is internally disabled through proper provisioning when
the input is not active.

TxD[3]N/

TxD[A]N

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 3. Pin Descriptions--Line Interface Signals (continued)

Pin

Symbol

Type

I/O

Name/Description

TxCKQP

LVPECL

Transmit Line Clock Q. This 155.52 MHz clock is used to clock
out the data in the STS-48/STM-16 mode for forward-directional
timing with the 155 Mbits/s 16-bit parallel-to-2.5 Gbits/s serial
MUX.

For an STS-48/STM-16 contra-clocking interface with the
155 Mbits/s parallel-to-2.5 Gbits/s serial MUX, this clock is not
used. In the contra-clocking mode, a phase-locked version of
TxCKP/N is used to clock out the data. In the contra-clocking
mode, the transmit line clock PLL must be active (see core regis-
ter map 0x0010, bit 5 (PLL_ MODE) on page 112).

This clock is not used in the STS-3/STM-1 or STS-12/STM-4
modes.

TxCKQN

TxD[4]P

LVPECL

Transmit Line Data Outputs (STS-48/STM-16). In STS-48/
STM-16 mode, these pins function as transmit line data outputs
[4:15]. The remaining transmit line data outputs [0:3] are listed
below and are multiplexed for use in the STS-3/STM-1 or STS-12/
STM-4 modes.

The 155.52 Mbits/s 16-bit word parallel bus is converted to a
2.488 Gbits/s serial data stream external to TDAT042G5 by a mul-
tiplexer.

All 32 differential data output pins, TxD[15:0]P/N, are used as the
parallel data output bus in the STS-48/STM-16 mode. These pins
constitute a 155.52 Mbyte/s parallel 16-bit word-aligned to the
TxCKP/N and TxCKQP/N 155.52 MHz transmit line clock.
TxD[15] is the most significant bit and is the first bit transmitted.
TxD[0] is the least significant bit and is the last bit transmitted.

This buffer is internally disabled through proper provisioning when
the input is not active.

TxD[4]N

TxD[5]P

LVPECL

TxD[5]N

TxD[6]P

LVPECL

TxD[6]N

TxD[7]P

LVPECL

TxD[7]N

TxD[8]P

LVPECL

TxD[8]N

TxD[9]P

LVPECL

TxD[9]N

TxD[10]P

LVPECL

TxD[10]N

TxD[11]P

LVPECL

TxD[11]N

TxD[12]P

LVPECL

TxD[12]N

TxD[13]P

LVPECL

TxD[13]N

TxD[14]P

LVPECL

TxD[14]N

TxD[15]P

LVPECL

TxD[15]N

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 4. Pin Descriptions--TOH Interface Signals

* I

= I

= 50 k

, where I

= internal pull-up resistance and I

= internal pull-down resistance.

Pin

Symbol

Type

I/O*

Name/Description

AK3

RxREF

3.3 V

Receive Line Frame. This output provides the receive 8 kHz
frame reference for external timing needs. RxREF is derived from
one of the received line clocks (user-selectable). It is a 50% duty
cycle clock when TDAT042G5 is in frame. This signal may be
used to implement line timing on a SONET ring. When not provi-
sioned, this signal must not be used. RxREF is valid only when
the SONET framer is in frame. Upon LOC or LOF, RxREF is
present but is free running. Because jitter may be present on this
signal when the device goes into and out of an LOC or LOF state,
it should not be used as a reference for TxFSYNCP/N.

AL7
AL6
AL4

AK5

RxTOHCK[D]
RxTOHCK[C]
RxTOHCK[B]
RxTOHCK[A]

3.3 V

Receive TOH Interface Clock. This clock is nominally a
5.184 MHz (STS-3/STM-1) or 20.736 MHz (STS-12/STM-4,
STS-48/STM-16) clock which provides timing for circuitry that
receives and externally processes the receive transport overhead
bytes. The duty cycle of the clock is not 50% (see Figure 49 and
Figure 50, page 272). In STS-48/STM-16 mode, all four of these
clocks are active.

AN7

AM6
AM5

AL2

RxTOHD[D]
RxTOHD[C]
RxTOHD[B]
RxTOHD[A]

3.3 V

Receive TOH Interface Data. This 5.184 Mbits/s or
20.736 Mbits/s signal contains all the receive transport overhead
bytes (A1, A2, J0/Z0, B1, E1, F1, D1--D3, H1--H3, K1, K2,
D4--D12, S1/Z1, M0, and E2) for all 3/12/48 STS-1s. This signal
can be used by external circuitry to process the TOH bytes.
RxTOHD is updated on the falling edge of RxTOHCK. In STS-48/
STM-16 mode, RxTOHD[A] contains all currently defined TOH
bits except for M1, which is located in RxTOHD[C].

AP6
AN5

AL3

AK4

RxTOHF[D]
RxTOHF[C]

RxTOHF[B]
RxTOHF[A]

3.3 V

Receive TOH Interface Frame. This 8 kHz framing signal is used
to locate the individual receive transport overhead bits in the
RxTOHD bit stream. RxTOHF is only high while bit 1 (MSB) of the
first framing byte (A1 during parity time in first byte) is present on
the RxTOHD output. RxTOHF is updated on the falling edge of
RxTOHCK.

AJ2

TxTOHCK

3.3 V

Transmit TOH Interface Clock. This clock is nominally a
5.184 MHz (STS-3/STM-1), 20.736 MHz (STS-12/STM-4,
STS-48/STM-16) clock which provides timing for circuitry that
externally generates and transmits the transmit transport over-
head bytes for inclusion in the transmit data stream. The duty
cycle of the clock is not 50% (see Figure 48, pag e271).

AK2

AJ5
AJ4
AJ3

TxTOHD[D]
TxTOHD[C]

TxTOHD[B]
TxTOHD[A]

3.3 V

(5 V tolerant)

Transmit TOH Interface Data. This 5.184 Mbits/s or
20.736 Mbits/s signal contains all the transmit transport overhead
bytes (A1, A2, J0/Z0, B1, E1, F1, D1--D3, H1--H3, K1, K2,
D4--D12, S1/Z1, M0, and E2) for all 3/12/48 STS-1s. This signal
is generated by external circuitry for custom TOH byte definitions.
TxTOHD is sampled on the rising edge of TxTOHCK.

AH5

TxTOHF

3.3 V

Transmit TOH Interface Frame. This 8 kHz framing signal is
used to align the individual transmit transport overhead bits in the
TxTOHD bit stream. TxTOHF is only high while bit 1 (MSB) of the
first framing byte (A1 during parity time in first byte) is expected
on the TxTOHD input. TxTOHF is updated on the falling edge of
TxTOHCK.

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Note: An external pull-up resistor of 50 k

--100 k

is required on all input pins of a disabled UTOPIA port. Either

an external pull-up resistor of 50 k

--100 k

or an external pull-down resistor of 0

--1 k

is required on all

unused inputs of an enabled UTOPIA port. Use of either a pull-up or pull-down resistor is selected to place
the unused input pin into the inactive state.

Table 5. Pin Descriptions--Enhanced UTOPIA Interface Signals

Pin

Symbol

Type

I/O

Name/Description

AM31

Y34

W34

G33
G32

TxADDR[4]
TxADDR[3]
TxADDR[2]
TxADDR[1]
TxADDR[0]

3.3 V

(5 V tolerant)

Transmit Address. The TxADDR is driven by the UTOPIA mas-
ter to poll and select the appropriate PHY channel of
TDAT042G5 to transmit data.

Note: The PHY address (0x00 to 0x1E) for each of the four

channels in TDAT042G5 is configured via software
provisioning.

J34
J35

K31
K32
K33
K34
K35

L32
L33
L34
L35

M31
M32
M33
M34
M35

TxDATA[A][15]
TxDATA[A][14]
TxDATA[A][13]
TxDATA[A][12]
TxDATA[A][11]
TxDATA[A][10]

TxDATA[A][9]
TxDATA[A][8]
TxDATA[A][7]
TxDATA[A][6]
TxDATA[A][5]
TxDATA[A][4]
TxDATA[A][3]
TxDATA[A][2]
TxDATA[A][1]
TxDATA[A][0]

3.3 V

(5 V tolerant)

Transmit Data Channel A. Used to transport data into the
UTOPIA PHY Tx block. TxDATA[A] is only valid when TxENB[A]
is asserted, and is sampled on the rising edge of TxCLK[A].
Note that TxDATA[A] is used in various UTOPIA modes. In U2 or
U2+, all 16 bits are valid. In U3 or U3+ (8-bit mode), only bits 15
to 8 are valid.

In U3 or U3+ (32-bit mode), TxDATA[A][15:0] forms the most
significant 16 bits of the combined data bus (bits 31 to 16), and
TxDATA[B][15:0] forms the least significant 16 bits of the com-
bined data bus (bits 15 to 0).

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

AB34
AB33
AB31
AB32
AC34
AC33
AC32
AC31
AD35
AD34
AD33
AD32
AD31
AE35
AE34
AE33

TxDATA[B][15]
TxDATA[B][14]
TxDATA[B][13]
TxDATA[B][12]
TxDATA[B][11]
TxDATA[B][10]

TxDATA[B][9]
TxDATA[B][8]
TxDATA[B][7]
TxDATA[B][6]
TxDATA[B][5]
TxDATA[B][4]
TxDATA[B][3]
TxDATA[B][2]
TxDATA[B][1]
TxDATA[B][0]

3.3 V

(5 V tolerant)

Transmit Data Channel B. Used to transport data into the
UTOPIA PHY Tx block. TxDATA[B] is only valid when TxENB[B]
is asserted (TxENB[A] for U3 or U3+ (32-bit mode)), and is sam-
pled on the rising edge of TxCLK[B] (TxCLK[A] for U3 or U3+
(32-bit mode). Note that TxDATA[B] is used in various UTOPIA
modes. In U2 or U2+, all 16 bits are valid. In U3 or U3+ (8-bit
mode), only bits 15 to 8 are valid.

In U3 or U3+ (32-bit mode), TxDATA[B][15:0] forms the least sig-
nificant 16 bits of the combined data bus (bits 15 to 0), and
TxDATA[A][15:0] forms the most significant 16 bits of the com-
bined data bus (bits 31 to 16). In this mode, channel B port must
be provisioned to the idle (default) state.

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 5. Pin Descriptions--Enhanced UTOPIA Interface Signals

(continued)

Pin

Symbol

Type

I/O

Name/Description

AP29

AL28

AM28

AN28

AP28

AL27

AM27

AN27

AP27

AR27

AL26

AM26

AN26

AP26

AR26

AM25

TxDATA[C][15]
TxDATA[C][14]
TxDATA[C][13]
TxDATA[C][12]
TxDATA[C][11]
TxDATA[C][10]

TxDATA[C][9]
TxDATA[C][8]
TxDATA[C][7]
TxDATA[C][6]
TxDATA[C][5]
TxDATA[C][4]
TxDATA[C][3]
TxDATA[C][2]
TxDATA[C][1]
TxDATA[C][0]

3.3 V

(5 V tolerant)

Transmit Data Channel C. Used to transport data into the
UTOPIA PHY Tx block. TxDATA[C] is only valid when TxENB[C]
is asserted, and is sampled on the rising edge of TxCLK[C].
Note that TxDATA[C] is used in various UTOPIA modes. In U2
or U2+, all 16 bits are valid. In U3 or U3+ (8-bit mode), only bits
15 to 8 are valid.

In U3 or U3+ (32-bit mode), channel C port is considered dis-
abled, and must be provisioned to the idle (default) state.

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

AP17
AP16

AN16

AM16

AR15

AP15

AN15

AL15

AM15

AR14

AP14

AN14

AL14

AM14

AP13

AN13

TxDATA[D][15]
TxDATA[D][14]
TxDATA[D][13]
TxDATA[D][12]
TxDATA[D][11]
TxDATA[D][10]

TxDATA[D][9]
TxDATA[D][8]
TxDATA[D][7]
TxDATA[D][6]
TxDATA[D][5]
TxDATA[D][4]
TxDATA[D][3]
TxDATA[D][2]
TxDATA[D][1]
TxDATA[D][0]

3.3 V

(5 V tolerant)

Transmit Data Channel D. Used to transport data into the UTO-
PIA PHY Tx block. TxDATA[D] is only valid when TxENB[D] is
asserted, and is sampled on the rising edge of TxCLK[D]
(TxCLK[A] for U3+, 32-bit mode). Note that TxDATA[D] is used in
various UTOPIA modes. In U2 or U2+, all 16 bits are valid. In U3
or U3+ (8-bit mode), only bits 15 to 8 are valid.

In U3 or U3+ (32-bit mode), channel D port is considered dis-
abled, and must be provisioned to the idle (default) state.

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

AM17

AN29

AB35

J33

TxPRTY[D]
TxPRTY[C]
TxPRTY[B]
TxPRTY[A]

3.3 V

(5 V tolerant)

Transmit Parity. This signal indicates the parity on the
TxDATA[D:A][15:0] bus. A parity error raises an alarm but does
not cause the cell/packet to be dropped. Odd or even parity may
be provisioned through a software register. TxPRTY[D:A] is con-
sidered valid only when TxENB[D:A] is asserted, and is sam-
pled on the rising edge of TxCLK[D:A].

In U3 or U3+ (32-bit mode), the TxPRTY[A] parity pin of port A
indicates the parity for the entire 32-bit data input.

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 5

Pin Descriptions--Enhanced UTOPIA Interface Signals (continued)

Pin

Symbol

Type

I/O

Name/Description

AL17

AM29

AA32

J32

TxSOP/C[D]
TxSOP/C[C]
TxSOP/C[B]
TxSOP/C[A]

3.3 V

(5 V tolerant)

Transmit Start of Packet/Cell. In ATM mode, the TxSOP/C[D:A]
signal marks the start of a cell on the TxDATA[D:A][15:0] bus.
When TxSOP/C[D:A] is active, the first word of the cell is present
on the TxDATA[D:A][15:0] bus.

In packet modes, the TxSOP/C[D:A] signal marks the start of a
packet on the TxDATA[D:A][15:0] bus. When TxSOP/C[D:A] is
active, the first word of the packet is present on the
TxDATA[D:A][15:0] bus.

TxSOP/C[D:A] is considered valid only when TxENB[D:A] is
asserted, and is sampled on the rising edge of TxCLK[D:A].

In U3 or U3+ (32-bit mode), only the TxSOP/C[A] pin of port A is
used to indicate a start of packet/cell for the 32-bit data input.

AP18
AN30
AA34

H33

TxPA[D]
TxPA[C]

TxPA[B]
TxPA[A]

3.3 V

Transmit Cell/Packet Available. This signal indicates when the
TDAT042G5 transmit FIFO can accept data from the master
device. If the FIFO is empty or more than the provisioned space is
available in the FIFO, TxPA[D:A] is set active.

One-Cycle Delay Mode. This mode follows the UTOPIA Level
2 Standard. The TxPA response occurs one cycle after the
address is polled.

Two-Cycle Delay Mode. This mode follows the UTOPIA Level
3 baselined text*. The TxPA response occurs two cycles after
the address is polled.

TxPA[D:A] Assertion. The TxPA[D:A] signal behavior relies on
the UTOPIA provisionable watermarks. In packet mode,
TxPA[D:A] goes high when the amount of data in the FIFO is
less than the high watermark setting. In ATM mode, TxPA[D:A]
goes high when the FIFO has space to receive a complete ATM
cell from the master. (This requires the high threshold to be set
appropriately by the user, i.e., set so that an entire cell can be
received once TxPA[D:A] goes active.)

* ATM Forum Technical Committee, UTOPIA Level 3, STR-PHY-UL3-01.00, July

1999.

(See further description on next page.)

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 5

Pin Descriptions--Enhanced UTOPIA Interface Signals (continued)

Pin

Symbol

Type

I/O

Name/Description

AP18

AN30

AA34

H33

TxPA[D]
TxPA[C]
TxPA[B]
TxPA[A]

3.3 V

Transmit Cell/Packet Available. (continued)

TxPA[D:A] Deassertion. In packet mode, TxPA[D:A] goes low
when the amount of data in the FIFO reaches or exceeds the
high watermark. In ATM mode, TxPA[D:A] goes low when there
is not enough space in the FIFO to receive an entire ATM cell.
(This requires the threshold values to be provisioned properly,
i.e., set low enough such that when the high watermark is
reached, the transmission of the current cell can be completed
without overflowing the FIFO). In ATM mode, TxPA[D:A] will be
deasserted four cycles before the end of the current cell trans-
fer if the FIFO cannot accept a complete ATM cell on the follow-
ing transmission.

TxPA[D:A] is updated on the rising edge of TxCLK[D:A].

In 32-bit mode, only the TxPA[A] pin of port A is used to indicate
the packet/cell available status.

MPHY Support. When the TxPA signals are used for multi-PHY
(MPHY) direct status, the corresponding TxCLK[B, C, and/or D]
must be provided. This clock will be the same as TxCLK[A].

AP19
AP31

Y33

G34

TxCLK[D]
TxCLK[C]
TxCLK[B]
TxCLK[A]

3.3 V

(5 V tolerant)

Transmit Clock. This clock is used to write cells or packets into
the transmit FIFO. TxCLK[D:A] can operate at speeds from dc to
104 MHz.

In U3 or U3+ (32-bit mode), only the TxCLK[A] input pin of port A
is used to clock the data input.

If MPHY direct status is used, then all clocks TxCLK[D:A] must be
provided.

AR17

AP30
AA33

H34

TxENB[D]
TxENB[C]
TxENB[B]
TxENB[A]

3.3 V

(5 V tolerant)

Transmit Data Enable (Active-Low). This signal is used to trans-
fer data on the TxDATA[D:A][15:0] bus into the transmit FIFOs. If
TxENB[D:A] is high, no operation is performed. If TxENB[D:A] is
low, a write occurs.

TxENB[D:A] is sampled on the rising edge of TxCLK[D:A].
TxENB[D:A] has the same meaning as data valid.

In U3 or U3+ (32-bit mode), only the TxENB[A] input pin of port A
is used to enable the transfer of data.

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 5

Pin Descriptions--Enhanced UTOPIA Interface Signals

(continued)

Pin

Symbol

Type

I/O

Name/Description

AN18

AL30

Y32
H31

TxSZ[D]
TxSZ[C]
TxSZ[B]
TxSZ[A]

3.3 V

(5 V tolerant)

Transmit Size. These pins are used only in U2+ and U3+
(packet) modes. This signal defines the valid bytes transmitted
and their packing within (1) TxDATA[D:A][15:0] for U2+ 16-bit
mode, and (2) TxDATA[A][15:0] and TxDATA[B][15:0] for the U3+
(32-bit mode). The meaning of these bits may be inverted
through UT register 0x0226 TxSIZE/RxSIZE mode, page 164.

In U3+ (8-bit mode), TxSZ[D:A] are unused.

For U2+ 16-bit mode,

TxSZ[D:A] = 0 defines the MSByte of TxDATA[D:A][15:0], i.e.,
TxDATA[D:A][15:8], to be the last byte of the packet transmit-
ted when using the default configuration.

TxSZ[D:A] = 1 defines the LSByte of TxDATA[D:A][15:0], i.e.
TxDATA[D:A][7:0], to be the last byte of the packet transmit-
ted when using the default configuration.

For U3+ (32-bit mode), TxSZ[A] and TxSZ[B] are combined to
define four states of the transmitted data stream. TxSZ[C] and
TxSZ[D] are unused. The following states are assigned by
TxSZ[A] and TxSZ[B] when TxEOP[A] is asserted when using
the default configuration. TxSZ[D:A] is ignored when
TxEOP[D:A] is not present.

TxDATA[A]

TxDATA[B]

TxDATA[A][15:8] TxDATA[A][7:0]

TxDATA[B][15:8] TxDATA[B][7:0]

TxSZ[A] TxSZ[B] DATA[31:24] DATA[23:16]

DATA[15:8]

DATA[7:0]

Valid

Not valid

Valid

Not valid

Valid

Not valid

Valid

There is no byte swapping and the data bytes are packed into
the upper transmitted bytes first.

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 5

Pin Descriptions--Enhanced UTOPIA Interface Signals (continued)

Pin

Symbol

Type

I/O

Name/Description

AN17

AL29

AA31

J31

TxEOP[D]
TxEOP[C]
TxEOP[B]
TxEOP[A]

3.3 V

(5 V tolerant)

Transmit End of Packet. These pins are used only in U2+
and U3+ (packet) modes. This signal indicates that the last
word of a packet is on the TxDATA[D:A][15:0] bus.
TxEOP[D:A] is valid only when TxENB[D:A] is asserted, and
is sampled on the rising edge of TxCLK[D:A].

In U3+ (32-bit mode), only the TxEOP[A] input pin of port A
is used to indicate the end of the incoming packet.

AM18
AM30

AA35

H32

TxERR[D]
TxERR[C]

TxERR[B]
TxERR[A]

3.3 V

(5 V tolerant)

Transmit Error. These pins are used only in U2+ and U3+
(packet) modes. TxERR[D:A] is only used in packet modes,
and indicates that the current packet is to be aborted and
discarded, if possible. TxERR[D:A] is only valid when
TxEOP[D:A] and TxENB[D:A] are asserted, and is sampled
on the rising edge of TxCLK[D:A].

In U3+ (32-bit mode), the TxERR[A] and the TxERR[B] input
pin of port A is used to indicate an error on the incoming
packet.

AP20

AL32
AL33

W32
W31

RxADDR[4]
RxADDR[3]
RxADDR[2]
RxADDR[1]
RxADDR[0]

3.3 V

(5 V tolerant)

Receive Address. Receive address is driven to the MPHY
to poll and select the appropriate MPHY channel.

Note: The address for each channel is configured by the

microprocessor.

N31
N32
N33
N34

P31
P32
P33
P34
P35

R31
R32
R33
R34
R35

T32
T33

RxDATA[A][15]
RxDATA[A][14]
RxDATA[A][13]
RxDATA[A][12]
RxDATA[A][11]
RxDATA[A][10]

RxDATA[A][9]
RxDATA[A][8]
RxDATA[A][7]
RxDATA[A][6]
RxDATA[A][5]
RxDATA[A][4]
RxDATA[A][3]
RxDATA[A][2]
RxDATA[A][1]
RxDATA[A][0]

3.3 V

Receive Data Channel A. Used to transport data out of the
UTOPIA PHY Rx block. RxDATA[A][15:0] is only valid when
RxENB[A] is asserted, and is updated on the rising edge of
RxCLK[A]. Note that RxDATA[A][15:0] is used in various
UTOPIA modes. In U2 or U2+, all 16 bits are valid. In U3 or
U3+ (8-bit mode), only bits 15 to 8 are valid.

In U3 or U3+ (32-bit mode), RxDATA[A][15:0] forms the most
significant 16 bits of the combined data bus (bits 31 to 16),
and RxDATA[B][15:0] forms the least significant 16 bits of the
combined data bus (bits 15 to 0).

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 5

Pin Descriptions--Enhanced UTOPIA Interface Signals (continued)

Pin

Symbol

Type

I/O

Name/Description

AE32

AF35
AF34
AF33
AF32
AF31

AG35
AG34
AG33
AG32
AG31
AH34
AH33
AH32
AH31

AJ34

RxDATA[B][15]
RxDATA[B][14]
RxDATA[B][13]
RxDATA[B][12]
RxDATA[B][11]
RxDATA[B][10]

RxDATA[B][9]
RxDATA[B][8]
RxDATA[B][7]
RxDATA[B][6]
RxDATA[B][5]
RxDATA[B][4]
RxDATA[B][3]
RxDATA[B][2]
RxDATA[B][1]
RxDATA[B][0]

3.3 V

Receive Data Channel B. Used to transport data out of the
UTOPIA PHY Rx block. RxDATA[B][15:0] is only valid when
RxENB[B] is asserted, and is updated on the rising edge of
RxCLK[B]. Note that RxDATA[B][15:0] is used in various UTO-
PIA modes. In U2 or U2+, all 16 bits are valid. In U3 or U3+ (8-
bit mode), only bits 15 to 8 are valid.

In U3 or U3+ (32-bit mode), RxDATA[B][15:0] forms the least sig-
nificant 16 bits of the combined data bus (bits 15 to 0), and
RxDATA[A][15:0] forms the most significant 16 bits of the com-
bined data bus (bits 31 to 16). In this mode, channel B port must
be provisioned to idle.

In this mode, RxDATA[B][15:0] is valid when RxENB[A] is
asserted, and RxDATA[B][15:0] is updated on the rising edge of
RxCLK[A].

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

AN25
AP25
AR25

AL24

AM24

AN24
AP24
AR24

AL23

AM23

AN23
AP23

AL22

AM22

AN22
AP22

RxDATA[C][15]
RxDATA[C][14]
RxDATA[C][13]
RxDATA[C][12]
RxDATA[C][11]
RxDATA[C][10]

RxDATA[C][9]
RxDATA[C][8]
RxDATA[C][7]
RxDATA[C][6]
RxDATA[C][5]
RxDATA[C][4]
RxDATA[C][3]
RxDATA[C][2]
RxDATA[C][1]
RxDATA[C][0]

3.3 V

Receive Data Channel C. Used to transport data out of the
UTOPIA PHY Rx block. RxDATA[C][15:0] is only valid when
RxENB[C] is asserted, and is updated on the rising edge of
RxCLK[C]. Note that RxDATA[C][15:0] is used in various UTO-
PIA modes. In U2 or U2+, all 16 bits are valid. In U3+ (8-bit
mode), only bits 15 to 8 are valid.

In U3 or U3+ (32-bit mode), channel C port must be provisioned
to idle mode.

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 5

Pin Descriptions--Enhanced UTOPIA Interface Signals (continued)

Pin

Symbol

Type

I/O

Name/Description

AM13

AL13

AR12

AP12

AN12

AM12

AL12

AR11

AP11

AN11

AM11

AR10

AP10

AN10

AM10

AL10

RxDATA[D][15]
RxDATA[D][14]
RxDATA[D][13]
RxDATA[D][12]
RxDATA[D][11]
RxDATA[D][10]

RxDATA[D][9]
RxDATA[D][8]
RxDATA[D][7]
RxDATA[D][6]
RxDATA[D][5]
RxDATA[D][4]
RxDATA[D][3]
RxDATA[D][2]
RxDATA[D][1]
RxDATA[D][0]

3.3 V

Receive Data Channel D. Used to transport data out of the
UTOPIA PHY Rx block. RxDATA[D][15:0] is only valid when
RxENB[D] is asserted, and is updated on the rising edge of
RxCLK[D]. Note that RxDATA[D][15:0] is used in various UTO-
PIA modes. In U2 or U2+, all 16 bits are valid. In U3+ (8-bit
mode), only bits 15 to 8 are valid.

In U3 or U3+ (32-bit mode), channel D port must be provisioned
to idle mode.

Note: [15:0] refers to a 16-bit data bus (15 = MSB, 0 = LSB).

AR9

AR22

AJ33

T34

RxPRTY[D]
RxPRTY[C]
RxPRTY[B]
RxPRTY[A]

3.3 V

Receive Parity. This signal indicates the parity on the
RxDATA[D:A][15:0]. Odd or even parity may be provisioned
through a software register. RxPRTY[D:A] is considered valid
only when RxENB[D:A] is asserted, and is updated on the rising
edge of RxCLK[D:A].

In U3 or U3+ (32-bit mode), the RxPRTY[A] parity pin of port A
indicates the parity for the entire 32-bit data output.

AP9

AL21

AJ32

U31

RxSOP/C[D]
RxSOP/C[C]
RxSOP/C[B]
RxSOP/C[A]

3.3 V

Receive Start of Packet/Cell. In ATM mode, RxSOP/C[D:A]
signal marks the start of a cell on the RxDATA[D:A][15:0] bus.
When RxSOP/C[D:A] is high on the clock cycle following the
latching of an active RxENB[D:A] signal, the first word of the cell
structure is present on the RxDATA[D:A][15:0] bus.

In packet modes, the RxSOP/C[D:A] signal marks the start of a
packet on the RxDATA[D:A][15:0] bus. When RxSOP/C[D:A] is
high, the first word of the packet is present on the
RxDATA[D:A][15:0] bus.

RxSOP/C[D:A] is considered valid only when RxENB[D:A] is
asserted, and is updated on the rising edge of RxCLK[D:A].

In U3 or U3+ (32-bit mode), only the RxSOP/C[A] pin of port A is
used to indicate a start of packet/cell for the 32-bit data output.

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 5

Pin Descriptions--Enhanced UTOPIA Interface Signals (continued)

Pin

Symbol

Type

I/O

Name/Description

AL9

AP21
AK33

V33

RxPA[D]
RxPA[C]
RxPA[B]
RxPA[A]

3.3 V

Receive Cell/Packet Available. This signal indicates when the
TDAT042G5 receive FIFO can send data to the master device.
The RxPA[D:A] signal behavior depends on the provisioned low
watermark in the UTOPIA interface.

One-Cycle Delay Mode. This mode follows the UTOPIA Level
2 Standard. The RxPA response occurs one cycle after the
address is polled. RxENB is asserted to activate the selected
PHY. RxDATA and RxSOP are output one cycle after RxENB is
sampled active by the PHY device.

Two-Cycle Delay Mode. This mode follows the UTOPIA Level
3 baselined text*. The RxPA response occurs two cycles after
the address is polled. RxENB is asserted to activate the
selected PHY. RxDATA and RxSOP are output two cycles after
RxENB is sampled active by the PHY device.

RxPA[D:A] Assertion. RxPA[D:A] goes high (is asserted)
when the amount of data in the receive FIFO has reached or
exceeded the low watermark or there is end of packet (EOP)
resident in the FIFO.

RxPA[D:A] Deassertion. In ATM mode, the RxPA[D:A] signal
goes low (is deasserted) when the FIFO has less than the low
threshold amount of data and there is no EOP inside the FIFO
(i.e., part of an ATM cell). Once the last byte of the current cell
is transmitted, and if the amount of data within the FIFO is still
less than the low threshold, RxPA[D:A] is deasserted.

In packet mode, the RxPA[D:A] signal goes low (is deasserted)
when the FIFO has less than the low threshold amount of data
and there is no EOP inside the FIFO.

Once the data transfer begins (since the amount of data has
reached or exceeded the low watermark), and if there is no
EOP below the low threshold (i.e., a long packet), the RxPA
signal is deasserted when the FIFO is drained by the UTOPIA
master device. In this case, the master must closely monitor the
RxPA[D:A] signals and use these signals as data valid indica-
tors to ensure that bad data is not read from the TDAT042G5.
TDAT042G5 will deassert the RxPA[D:A] signal immediately
when the FIFO is drained.

* ATM Forum Technical Committee, UTOPIA Level 3, STR-PHY-UL3-01.00, July

1999.

(See further description on next page.)

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 5

Pin Descriptions--Enhanced UTOPIA Interface Signals (continued)

Pin

Symbol

Type

I/O

Name/Description

AL9

AP21
AK33

V33

RxPA[D]
RxPA[C]
RxPA[B]
RxPA[A]

3.3 V

Receive Cell/Packet Available. (continued)

Data Transfer. A TDAT042G5 ingress channel sends data
when it has asserted RxPA[D:A] and the master device
requests data (via RxENB[D:A]). In ATM mode, if the master
device requests data using RxENB[D:A] and if the TDAT042G5
has less than the low watermark amount of data to send and
there is no end of cell in the FIFO (RxPA[D:A] is deasserted),
then the TDAT042G5 UTOPIA interface will send out data that
should be ignored by the master, i.e., it does not send data from
its internal FIFO.

In ATM mode, once an ATM cell transfer starts, the Tx or Rx
side must complete the transfer. If the transfer is not com-
pleted, then the cell will be corrupted. The transfer continues
until either (1) the end of cell is reached, when the end of cell
exists below the low watermark, or (2) the end of the FIFO is
reached. If the end of the FIFO is reached, no underflow is
flagged on the receive side. In ATM mode, the low watermark
should be set so that at least one entire cell is in the FIFO prior
to asserting RxPA[D:A].

In packet mode, once the data transfer begins, the RxPA[D:A]
signal will remain asserted until the FIFO is drained if there is
no EOP below the low watermark. During the time RxPA[D:A] is
asserted, valid data is being transferred.

RxPA[D:A] is updated on the rising edge of RxCLK[D:A].

In 32-bit mode, only the RxPA[A] pin of port A is used to indi-
cate the packet/cell available status.

MPHY Support. When the RxPA signals are used for MPHY
direct status, the corresponding RxCLK[B, C, and/or D] must be
provided. This clock will be the same as RxCLK[A].

AM9

AN21

AK34

U34

RxENB[D]
RxENB[C]

RxENB[B]
RxENB[A]

3.3 V

(5 V tolerant)

Receive Data Enable (Active-Low). This signal is used to indi-
cate to the UTOPIA PHY Rx block that it is selected. If
RxENB[D:A] is high, no operation is performed. If RxENB[D:A] is
low, the UTOPIA PHY Rx block sends data (not necessarily valid
data).

In U3 or U3+ (32-bit mode), only the RxENB[A] input pin of port A
is used to enable the transfer of data.

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 5

Pin Descriptions--Enhanced UTOPIA Interface Signals (continued)

* I

= I

= 50 k

, where I

= internal pull-up resistance and I

= internal pull-down resistance.

Pin

Symbol

Type

I/O*

Name/Description

AM8

AN20

AL34

W33

RxCLK[D]
RxCLK[C]
RxCLK[B]
RxCLK[A]

3.3 V

(5 V tolerant)

Receive Clock. This clock is used to read cells or packets from
the receive FIFO. RxCLK[D:A] can operate at speeds from dc to
104 MHz. For clock rates above 52 MHz, the receive clock must
be placed in source mode.

RxCLK[D:A] sourcing from the respective TxCLK[D:A] may be
provisioned by CLOCK_MODE_Rx (see registers 0x020F,
0x0213, 0x0217, 0x021B on pages 114--115).

In U3 or U3+ (32-bit mode), only the RxCLK[A] input/output pin of
port A is used to clock the data output.

If MPHY mode is used, then all clocks RxCLK[D:A] must be pro-
vided.

AN8

AM20

AK31

W35

RxSZ[D]
RxSZ[C]

RxSZ[B]
RxSZ[A]

3.3 V

Receive Size. These pins are used only in U2+ and U3+ (packet)
modes. This signal defines the valid bytes received and their
packing within (1) RxDATA[D:A][15:0] for U2+ 16-bit mode, and (2)
RxDATA[A][15:0] and RxDATA[B][15:0] for the U3+ (32-bit mode).
The meaning of these bits may be inverted through UT register
0x0226 TxSIZE/RxSIZE mode, page 164.

In U3+ (8-bit mode), RxSZ[D:A] are unused.

For U2+ 16-bit mode,

RxSZ[D:A] = 0 defines the MSByte of RxDATA[D:A][15:0], i.e.,
RxDATA[D:A][15:8], to be the last byte of the packet received
when using the default configuration.

RxSZ[D:A] = 1 defines the LSByte of RxDATA[D:A][15:0], i.e.,
RxDATA[D:A][7:0], to be the last byte of the packet received
when using the default configuration.

In U3+ (32-bit mode), the MSByte will be placed on RxDATA[A],
bits 15 to 8. In the 16-bit mode, the MSByte will be placed on
RxDATA[D:A], bits 15 to 8.

For U3+ (32-bit mode), RxSZ[A] and RxSZ[B] are combined to
define four states of the received data stream. RxSZ[C] and
RxSZ[D] are unused. The following states are assigned by
RxSZ[A] and RxSZ[B] when RxEOP[A] is asserted and the
default configuration is provisioned.

RxDATA[A] RxDATA[B]

RxDATA[A][15:8] RxDATA[A][7:0]

RxDATA[B][15:8] RxDATA[B][7:0]

RxSZ[A] RxSZ[B]DATA[31:24] DATA[23:16]

DATA[15:8]

DATA[7:0]

Valid

Not valid

Valid

Not valid

Valid

Not valid

Valid

The data bytes are packed into the upper transmitted bytes first.

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 5

Pin Descriptions--Enhanced UTOPIA Interface Signals (continued)

* I

= I

= 50 k

, where I

= internal pull-up resistance and I

= internal pull-down resistance.

Pin

Symbol

Type

I/O*

Name/Description

AN9

AM21

AJ31

U32

RxEOP[D]
RxEOP[C]
RxEOP[B]
RxEOP[A]

3.3 V

Receive End of Packet. These pins are used only in U2+ and
U3+ (packet) modes. This signal indicates that the last word of a
packet is on the RxDATA[D:A][15:0] bus. RxEOP[D:A] is valid only
when RxENB[D:A] is asserted, and is updated on the rising edge
of RxCLK[D:A].

In U3+ (32-bit mode), only the RxEOP[A] output pin of port A is
used to indicate the end of the outgoing packet.

AP8

AR21

AK32

V32

RxERR[D]
RxERR[C]
RxERR[B]
RxERR[A]

3.3 V

Receive Error. These pins are used only in U2+ and U3+
(packet) modes. RxERR[D:A] is only used in POS mode, and indi-
cates that the current packet is to be aborted and discarded, if
possible. RxERR[D:A] is only valid when RxEOP[D:A] and
RxENB[D:A] are asserted, and is updated on the rising edge of
RxCLK[D:A].

If the Rx FIFO overflows, RxERR[D:A] and RxEOP[D:A] are
asserted to indicate a corrupted packet.

RxERR is asserted when a CRC error occurs in any packet mode
using CRC-16 or CRC-32. RxERR is asserted when an incoming
packet has an abort flag at the end of its stream. In both of these
cases, an RxEOP is asserted with the RxERR.

RxERR is not asserted when a header does not match in PPP
header attaching mode. In that case, no data is sent to the UTO-
PIA interface.

In U3+ (32-bit mode), only the RxERR[A] output pin of port A is
used to indicate an error on the outgoing packet.

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 6. Pin Descriptions--Microprocessor Interface Signals

* I

= I

= 50 k

, where I

= internal pull-up resistance and I

= internal pull-down resistance.

Pin

Symbol

Type

I/O*

Name/Description

RST

3.3 V

(5 V tolerant)

Reset (Asynchronous) (Active-Low). Reset must be held
active-low for a minimum of 100 ns. After deassertion of reset, the
device is reset and available for use after 8

�

ICT

3.3 V

(5 V tolerant)

3-State Control (Active-Low). ICT has an internal 100 k

pull-

up. This control 3-states the digital outputs. It does not control the
LVPECL outputs.

PMRST

3.3 V

(5 V tolerant)

I/O

1-Second Performance Monitor (PM) Clock. PM clock can be
generated on-chip. This signal will have a 50% duty cycle.

PMRST clock may be programmed by core register 0x0013,
bit 15 (PMRST_I/O_CTRL) to be either an output or input. As an
output clock, it is derived from the transmit line clock, TxCKP/N.
This clock is divided to produce a 1 second, 50% duty cycle clock
output. As an input, PMRST is under software control and can be
activated longer or shorter than once per second. In the software
control mode with PMRST an input, the minimum pulse width of
the external PMRST signal is 10 ms.

MPMODE

3.3 V

(5 V tolerant)

MPU Mode Select. This signal is set high for a synchronous
microprocessor, or low for an asynchronous microprocessor.

MPCLK

3.3 V

(5 V tolerant)

MPU Clock. This clock can operate from 1 Hz to 66 MHz when in
synchronous mode.

3.3 V

(5 V tolerant)

Chip Select (Active-Low). This signal must be low during regis-
ter access.

INT

3.3 V

(open drain)

Interrupt (Active-Low). This signal goes low when the device
generates an unmasked interrupt.

A12
B12
C12
D12
E12
A11
B11
C11
D11
A10
B10
C10
D10
E10

A9
B9

DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]

DATA[9]
DATA[8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[0]

3.3 V

(5 V tolerant)

Data Bus. This bus is a bidirectional data bus for writing and
reading software registers. [15:0] refers to a 16-bit data bus
(15 = MSB, 0 = LSB).

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Pin Information

(continued)

Table 6. Pin Descriptions--Microprocessor Interface Signals

(continued)

* I

= I

= 50 k

, where I

= internal pull-up resistance and I

= internal pull-down resistance.

Table 7. Pin Descriptions--General-Purpose I/O Signals: Interface Signals

* I

= I

= 50 k

, where I

= internal pull-up resistance and I

= internal pull-down resistance.

Pin

Symbol

Type

I/O*

Name/Description

B16
C16
D16
A15
B15
C15
E15
A14
B14
C14
D14
E14
B13
C13
D13
E13

ADDR[15]
ADDR[14]
ADDR[13]
ADDR[12]
ADDR[11]
ADDR[10]

ADDR[9]
ADDR[8]
ADDR[7]
ADDR[6]
ADDR[5]
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[1]
ADDR[0]

3.3 V

(5 V tolerant)

Address Bus. This bus is used to address registers. [15:0] refers
to a 16-bit data bus (15 = MSB, 0 = LSB).

ADS

3.3 V

(5 V tolerant)

Address Strobe (Active-Low). This signal indicates the address
is valid for MPU access in the asynchronous mode, and transfer
start for the synchronous mode.

R/W

3.3 V

(5 V tolerant)

Read/Write. This signal is low to indicate a write operation and is
high to indicate a read operation.

3.3 V

(5 V tolerant)

Data Strobe (Active-Low). This signal used in the asynchronous
mode (MPMODE = 0) indicates that the data is valid for MPU
writes.

3.3 V

Data Transfer Acknowledge (Active-Low). This signal acknowl-
edges the data transfer cycle.

Pin

Symbol

Type

I/O*

Name/Description

AG5
AH2
AH3
AH4

GPIO[3]
GPIO[2]
GPIO[1]
GPIO[0]

3.3 V

(5 V tolerant)

General-Purpose I/O. These programmable I/O pins may be
used to monitor or control external circuitry. These pins may also
be provisioned to cause an interrupt upon a change in their val-
ues.

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Overview

This device integrates the SONET/SDH interface termination functions with a generic cell/packet delineation cir-
cuit. It supports STS-48/STM-16, quad STS-12/STM-4, and quad STS-3/STM-1 interface rates. Up to four data
channels transported within an STS-N payload are processed via the SONET/SDH termination blocks and the on-
chip data encapsulation/decapsulation engine. Packet or ATM data are transmitted/received by this device on the
equipment side via the enhanced UTOPIA interface. SONET/SDH streams are transmitted/received by this device
on the network side via the line interface.

Concatenation levels supported by this device range from STS-1 to STS-48c. Valid standard concatenated
SONET frame configurations for this device are STS-3c, STS6c, STS-9c, STS-12c, STS-15c, STS-18c, and STS-
48c. Non-standard concatenation levels (such as STS-4c, STS-5c, STS-7c, etc.) are supported as well. In STS-48
mode, four pointer processors are available. This allows an STS-48 frame to carry up to four concatenated sub-
frames (for example, mapping of four STS-12c payloads into an STS-48 frame). In quad STS-3 and STS-12
modes, only one pointer processor is available. Therefore, only a single subframe may be mapped into an STS-3
or STS-12 frame (mapping a single STS-3c payload into an STS-12 frame, for instance). For details, see Table 22
on page 68.

This device supports mapping for ATM cells into SONET/SDH, mapping for packet data via all existing or currently
proposed standards (e.g., PPP, SDL) into SONET/SDH streams. Via SDL mapping, this device also supports
packet over fiber or ATM over fiber, respectively. Figure 2 shows the overview block diagram, and Figure 3 shows
the interface block diagram for this device.

5-6680(F).ar.15

Figure 2. Overview Block Diagram

OVERHEAD

PROCESSOR

OVERHEAD

PROCESSOR

SPE

MAPPER

POINTER

INTERPRETER

I
NE I

TERF

ACE BL

LINE

TERMINATION

PATH

TERMINATION

PAYLOAD

TERMINATION

PACKET/CELL
PROCESSOR
-DELINEATION
-DECAPSULATION
-UNSCRAMBLING

SINGLE STM-16/STS-48

OR QUAD STM-4/STS-12

ENHANCED

OR QUAD STM-1/STS-3

SINGLE STM-16/STS-48

OR QUAD STM-4/STS-12

OR QUAD STM-1/STS-3

CONTROL

�

P INTERFACE

UTOPIA

INSERT

MONITOR

-CRC VERIFICATION

ENHANCED

UTOPIA

COMPATIBLE

INTERFACE

PACKET/CELL
PROCESSOR
-ENCAPSULATION
-SCRAMBLING
-CRC GENERATION

I
NE INT

ACE

(U2, U2+, U3, U3+)

INTERFACE

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Overview

(continued)

Figure 3 shows the interface diagram of the IC.

5-6746(F)r.11

Figure 3. Interface Block Diagram

The receive path terminates and processes section, line, and path overhead. It performs framing (A1, A2),
descrambling, detects alarm conditions, and monitors section, line, and path BIP-Ns (B1, B2, B3), accumulating
error counts for each level for performance monitoring purposes. Line and path remote error indications (M1, G1)
are also accumulated. The payload pointers (H1, H2) are interpreted, and the synchronous payload envelope
(SPE) is extracted.

The transmit path inserts section, line, and path overhead. It inserts the framing pattern (A1, A2), performs scram-
bling, inserts AIS (optionally), and calculates and inserts section, line, and path BIP-8s (B1, B2, B3). Line and path
remote failure indications (M1, G1) are inserted based on received BIP-8 errors. The payload pointers (H1, H2) are
generated, and the SPE is inserted.

When used to implement an ATM UNI, ATM cells are written into an internal 4-cell FIFO buffer using a generic
8-/16-/32-bit wide UTOPIA 2/3 compliant interface. Idle/unassigned cells are automatically inserted when the inter-
nal FIFO is empty. The device provides generation of the header check sequence and optionally scrambles the
ATM payload.

SPE

MAPPER

STS-3/STM-1

STS-12/STM-4

STS-48/STM-16

RECEIVE

OVERHEAD

PROCESSOR

OVERHEAD
INTERFACE

TRANSMIT

OVERHEAD

PROCESSOR

POINTER

INTERPRETER

ATM/HDLC/SDL

FRAME

UNSCRAMBLING

DECAPSULATION

UTOPIA

ENHANCED

ATM/HDLC/SDL

FRAME INSERTION

SCRAMBLING

ENCAPSULATION

UTOPIA

TOH

INTERFACE

MPU

INTERFACE

JTAG

INTERFACE

UTOPIA

I
NE INT

ACE

INTERFACE

STS-3/STM-1

STS-12/STM-4

STS-48/STM-16

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Overview

(continued)

When used to implement a POS UNI, the device writes packets into an internal 256-byte FIFO buffer using a
generic 8-/16-/32-bit wide enhanced UTOPIA 2/3 compliant interface. HDLC framing performs the insertion of
flags, control escape characters, and the FCS fields. Either the CRC-ITU or CRC-32 (in regular or reversed mode)
can be computed and added to the frame. Counts of transmitted packets and errored/dropped packets are accu-
mulated for performance monitoring purposes.

ATM/HDLC/HDLC-CRC/PPP Support

TDAT042G5 supports the transfer of ATM cells or variable-length packets. Support for 52- or 53-byte cell sizes is
provided at the UTOPIA interface through register provisioning. The following three types of packet data can be
sent and received with HLDC-like framing: transparent HDLC, CRC, and PPP. Transparent HDLC contains 0x7E
framing but no CRC. CRC mode is HDLC with an attached CRC. PPP has 0x7E framing with provisionable
attached header information and CRC.

When used to implement an ATM UNI, the device performs cell delineation on the SPE. HEC error correction is
provided. Idle/unassigned cells may be dropped according to a programmable filter. Cells are also dropped upon
detection of an uncorrectable header check sequence error. The ATM cell payloads are descrambled before being
passed to a 4-cell FIFO buffer. The received cells are read from the FIFO using a generic 8-/16-/32-bit wide
UTOPIA 2/3 compliant interface. Counts of received ATM cells, uncorrectable HEC errors, and correctable HEC
errors are accumulated independently for performance monitoring purposes.

When used to implement a POS UNI, the device descrambles the SPE before extracting HDLC frames. The con-
trol escape characters are removed. Descrambling can be performed after control escape byte destuffing (or
before to control malicious HDLC expansion)

The optional 16- or 32-bit error check sequence is verified for cor-

rectness. The packets are placed into a 256-byte FIFO buffer.* The received packets are read from the FIFO using
a generic 8-/16-/32-bit wide enhanced UTOPIA 2/3 compliant interface. Counts of received packets and errored/
dropped packets are accumulated independently for performance monitoring purposes. The device POS imple-
mentation also allows the optional attach/detach of a per-channel provisionable PPP header.

* FIFOs are 256 bytes per channel and cannot be reallocated.

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Overview

(continued)

Over-Fiber Mode

Over-fiber mode is used for packet delivery over fiber. No SONET overhead is added in this mode. Since no
SONET overhead is added, the OHP and PT blocks must be configured for the bypass mode.

In transmitting from the TDAT042G5 to the line, the data engine maps the data payload into a full SONET frame
starting at what normally would be the first A1 byte. The data engine continues to map payload into the full SONET
frame until an end of packet or end of frame is reached, at which time the data engine halts the mapping of the
incoming data stream into the SONET frame until the next start of frame.

When TDAT042G5 is receiving from the line, the data engine must be provisioned to receive the maximum packet
size, unless the location of the last byte of the packet is known in advance. If the size of the packet is not known,
one must program the data engine to receive the entire SONET frame. The external UTOPIA interface device must
then be capable of extracting the variable length packets from the full SONET frame.

Details of the over-fiber mode are given in the Data Engine (DE) Block section, page 82.

Test and General-Purpose I/O Support

The device is provisioned, controlled, and monitored using a generic 16-bit microprocessor interface. A standard
five-signal IEEE -1149.1 compliant JTAG test port is also provided for boundary-scan purposes.

A 4-bit GPIO (general-purpose input/output) interface is provided to control and/or monitor other onboard devices.

External Interfaces

Figure 4 shows the external interfaces.

5-6745(F).br.3

Figure 4. External Interface Summary Diagram

MPU AND TEST INTERFACE

TxD

ECLREF

RxD

RxCLK

4 x 24 Rx UTOPIA

4 x 24 Tx UTOPIA

INT

OHP

+5 MPHY ADDRESS

GPIO

LINE

TxFSYNC

TxCK

TxCKQ

CLKDIV

JTAG

RST

ICT

PMRST

MPMODE

MPCLK

INT

DATA

ADDR

ADS

R/W

TOHF

TOHD

TOHCK

REF

TOHF

TOHCK

TOHD

348 SIGNAL PINS

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Line Interface Block

This device is designed to work with commonly available optoelectronic converters for OC-3, OC-12, and OC-48
line rates. It will also work with available multiplexer and demultiplexer chip sets for an STS-48/STM-16 line inter-
face rate. The line interface will operate in one of three possible modes, and is provisioned through core register
0x0010 (mode), bits 4--0. These three values of the mode register are the only values allowed.

This block provides the interface between the external SONET/SDH line components and the overhead processor
(OHP) block. The line interface must provide transmit/receive functions for quad STS-3/STM-1, quad STS-12/
STM-4, and STS-48/STM-16 applications. All external inputs and outputs for the TDAT042G5 line I/O block are ref-
erenced to the positive edge of the clock. When the external devices are referenced to the negative edge, the dif-
ferential input clock will need to be reversed at the TDAT042G5 input.

Receive Line Interface Summary

The following list summarizes the receive line interface operations for each STS mode:

In quad STS-3/STM-1 mode, the receive line interface provides four separate STS-3/STM-1 input pin groups.
Each input group comprises a differential LVPECL 155.52 Mbits/s data input and a differential 155.52 MHz clock.
Each input group provides data to only one of four (A, B, C, or D) OHP blocks. This interface is synchronous and
requires an external CDR.

In quad STS-12/STM-4 mode, the receive line interface provides four separate STS-12/STM-4 input pin groups.
Each input group comprises a differential LVPECL 622.08 Mbits/s data input and a differential 622.08 MHz clock.
Each input group provides data to only one of four (A, B, C, or D) OHP blocks. This interface is synchronous and
requires an external CDR.

In the STS-48/STM-16 mode, the device provides 16 differential LVPECL data inputs at 155.52 Mbits/s with a dif-
ferential LVPECL 155.52 MHz clock. In this mode, an external 1:16 data demultiplexer with a 1/16 clock divider is
required. External barrel shifter circuitry to byte align the data is not required.

Multiplexers select between the terminal loopback data, the 32-bit parallel STS-48/STM-16 data bus, and the
four STS-12/STM-4 or STS-3/STM-1 8-bit parallel data buses. The controls for these MUXes are mode (register
0x0010) and loopback (register 0x0012) provided by the control block (see Table 48 and Table 50 on pages
150--151).

For STS-48 mode, the 155.52 MHz input clock is divided by two to 77.76 MHz and distributed to all four multi-
plexers. For the STS-12/STM-4 mode, each 622.08 MHz input clock is divided by eight to 77.76 MHz. Each
77.76 MHz clock is distributed to the appropriate clock multiplexer (A, B, C, or D). For the STS-3/STM-1 mode,
each 155.52 MHz input clock is divided by eight to 19.44 MHz. Each 19.44 MHz clock is distributed to the appro-
priate clock multiplexer (A, B, C, or D).

Table 12. Line Interface Modes

Mode[4:0]

Core Register

0x0010

Interfaces

Line Interface Signals

10000

STS-48/STM-16

RxCKP/N, RxD[15:0]P/N,

TxCKP/N, TxD[15:0]P/N

01111

STS-12/STM-4

RxCLK[D]P/N, RxD[D]P/N, TxCKP/N, TxD[D]P/N
RxCLK[C]P/N, RxD[C]P/N, TxCKP/N, TxD[C]P/N
RxCLK[B]P/N, RxD[B]P/N, TxCKP/N, TxD[B]P/N
RxCLK[A]P/N, RxD[A]P/N, TxCKP/N, TxD[A]P/N

00000

STS-3/STM-1

RxCLK[D]P/N, RxD[DP/N, TxCKP/N, TxD[D]P/N
RxCLK[C]P/N, RxD[C]P/N, TxCKP/N, TxD[C]P/N
RxCLK[B]P/N, RxD[B]P/N, TxCKP/N, TxD[B]P/N
RxCLK[A]P/N, RxD[A]P/N, TxCKP/N, TxD[A]P/N

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Line Interface Block

(continued)

Transmit Line Interface Summary

The following list summarizes the transmit line interface operations for each STS mode.

In quad STS-3/STM-1 and STS-12/STM-4 modes, the transmit line interface receives 8 bits of data from each
OHP block (A, B, C, and D) at 19.44 Mbits/s and 77.76 Mbits/s, respectively. An 8-to-1 parallel-to-serial conver-
sion produces output data at 155.52 Mbits/s for STS-3/STM-1 mode and 622.08 Mbits/s for STS-12/STM-4
mode. For facility loopback, the outputs are multiplexed with the corresponding data from the STS-12/STS-3
(STM-4/STM-1) receive block and sent to four differential LVPECL buffers.

In STS-48/STM-16 mode, a 32-bit data word at 77.76 Mbits/s is received from the OHP. Then a 2-to-1 parallel-to-
parallel conversion is performed producing a 16-bit word at 155.52 Mbits/s. In this mode, an external 16:1 data
demultiplexer is required. Facility loopback is not available for the STS-48/STM-16 mode.

There is a single clock input, TxCKP/N, in the transmit case. The clock source rates are 622.08 MHz (STS-12/
STM-4), 155.52 MHz (STS-3/STM-1), or 155.52 MHz (STS-48/STM-16).

In the STS-48/STM-16 case, two transmit clock modes are available, contra* and forward clocking. In the contra-
clocking mode, the transmit data is sent out as commanded by TxCKP/N; in addition, an internal PLL must be
activated, core register 0x0010 bit 5, to minimize the phase delay between TxCKP/N and the transmitted data. In
the forward clocking mode, the transmit data and the clock, TxCKQ (used to clock out the data), are sent in par-
allel to the transmit multiplexer.

In STS-12/STM-4 and STS-3/STM-1 modes, the input clock is divided by eight producing the internal clock at
77.76 MHz and 19.44 MHz, respectively. In STS-48/STM-16 mode, the input clock is divided by eight to produce
an internal clock at 77.76 MHz. The CLKDIV pin (H4) controls this division. Table 13 shows the required value of
CLKDIV.

Table 13. Clock Settings for CLKDIV Pin

TxFSYNCP/N is an optional external frame sync. This 8 kHz frame sync pulse must be synchronous with
TxCKP/N. It is, at minimum, a one TxCKP/N clock cycle wide pulse that is latched in at the system rate
(622.08 MHz or 155.52 MHz). TOH interface signal RxREF should not be used as a source to TxFSYNCP/N.

The active edge of the transmit clock is the positive edge.

When TDAT042G5 operates in asynchronous mode (MPMODE = 0), the line block provides the microprocessor
clock to the microprocessor interface block. The CLKDIV pin must be set to ensure that the clock is always
77.76 MHz.

Line interface timing is given in the Interface Timing Specifications section (see Table 168, page 267).

* Contra refers to a type of data transmission whereby a clock signal is received by a register before the register sends data.

CLKDIV Pin

Description

CLKDIV = 1

When in STS-12/STM-4 (622.08 MHz divide by 8).

CLKDIV = 0

When in STS-3/STM-1, STS-48/STM-16 (155.52 MHz divide by 2).

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

SONET Framer

The SONET framer consists of the overhead processor (OHP) and path terminator (PT) blocks. The receive
SONET framer requires 625

�

s to drop frame after the line input signal is lost. Once a valid receive line input is

restored, the maximum average reframe time (MART) is 250

�

Overhead Processor (OHP) Block

The OHP block terminates/generates the section and line overhead bytes of the line. The data rate of the TOH
interface is given in Table 14. Timing for the TOH interface is given in the Interface Timing Specifications section
(see Table 172 and Table 173, page 271).

Table 14. R/T TOH Interface Rates

* This STS-48/STM-16 interface is a four-line interface resulting in an effective interface rate

of 82.944 Mbits/s.

All receive transport overhead bytes are output on the RTOH interface for external processing. Transmit transport
overhead bytes can optionally be inserted from the TTOH interface.

The transmit transport overhead bytes can be inserted in one of three ways selected through software provision-
ing: (1) automatically by hardware, (2) via software provisioning, or (3) through the TOAC. Table 15 defines those
overhead bytes that can be inserted via each of the three paths. In some cases, the user has the choice to insert
the byte via software registers or through the TOAC. Superscripts in the table reference these insertion methods
which are described in the footnotes.

Table 15. TOAC Byte Insertion: An STS-3/STM-1 Example

1.Inserted via TOAC, but not part of SONET standard.
2.Inserted via software or automatically via hardware.
3.Inserted via TOAC only.
4.Inserted via software register only.
5.Inserted via TOAC or software register.
6.Inserted via TOAC hardware; should be included in TOAC interface timing.

Mode

R/T TOH Interface Rate

STS-48/STM-16

20.736* Mbits/s

STS-12/STM-4

20.736 Mbits/s

STS-3/STM-1

5.184 Mbits/s

OH Parity

(1st bit of

1st byte)

B1-2

B1-3

E1-2

E1-3

F1-2

F1-3

D1-2

D2-3

D2-2

D2-3

D3-2

D3-3

K1-2

K1-3

K2-2

K2-3

D4-2

D4-3

D5-2

D5-3

D6-2

D6-3

D7-2

D7-3

D8-2

D8-3

D9-2

D9-3

D10

D10-2

D10-3

D11

D11-2

D11-3

D12

D12-2

D12-3

Z1-2

Z1-3

Z2-2

E2-2

E2-3

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Overhead Processor (OHP) Block

(continued)

The TOAC inserter must insert the first bit of A1 at the TOAC input, TxTOHD[D:A], during the first clock cycle when
TxTOHF = 1. The TOAC has a built-in parity checker. For the parity check, the value of the first inserted bit of A1
must be set to the parity value of the previous frame. The remainder of the inserted bits of the A1, A2 bytes are
ignored by the transmit framer.

Receive OHP

Loss-of-Signal. The loss-of-signal block monitors the incoming scrambled data for the absence of transitions.
When an absence of transitions is detected for a programmable length of time, a loss-of-signal (LOS) is declared.
LOS is cleared when two valid framing patterns are detected, and during the intervening time, no LOS condition is
detected.

Framer. The frame block finds and locks onto the incoming A1 and A2 bytes of the SONET transport overhead.
Loss-of-frame (LOF) is declared when a defect persists for more than 3 ms. LOF is cleared when the defect is
absent for more than 3 ms. To prevent intermittent out-of-frame/in-frame conditions, the 3 ms timer is not reset to
zero until an in-frame (or out-of-frame) condition persists for 3 ms. The framer is also responsible for performing bit
rotations on the incoming data stream to ensure that the rest of the IC receives byte-aligned data.

While in-frame, the A1/A2 framing bytes in each frame are compared against the expected pattern. Out-of-frame
(OOF) is declared when five consecutive frames containing one or more framing pattern errors have been
received.

While out-of-frame, this block will monitor the receive data stream for an occurrence of the framing pattern. When a
framing pattern has been recognized, the framer performs the necessary bit rotation and verifies that an error-free
framing pattern is present in the next frame before declaring in-frame.

J0 Section Trace. The section trace message is extracted and stored in a 16-byte memory for access by software.
The first byte of the message can be provisioned to be either:

The byte with the most significant bit (MSB) set high (for SDH), or

The byte following a carriage return (0x0D) and line feed (0x0A) sequence (for SONET).

J0 mismatch detection is provided using one of four methods (provisionable via J0MONMODE[A--D][1:0]; see reg-
ister description, page 173).

Descrambler. The descrambler block implements the frame synchronous SONET descrambler with a generating
polynomial of 1 + x

+ x

. The framing bytes (A1, A2), the section trace bytes (J0), and the growth bytes (Z0) are

not descrambled. The descrambler may be disabled through a software register.

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Overhead Processor (OHP) Block

(continued)

Receive OHP (continued)

B1 BIP-8 Check. The SBIP block counts section BIP-8 (B1) errors. The SBIP value is calculated over the scram-
bled data of the complete previous frame. The calculated value is compared against the received B1 byte and dif-
ferences (errors) are counted. A theoretical maximum of 64,000 errors may be detected per second. The SBIP
block accumulates these errors in a 16-bit saturating counter. This counter operates in latch and clear mode to
ensure Bellcore and ITU compliance with regard to not missing any events (bit errors). It is intended that this
counter be polled at least once per second so that no error events are missed. Optionally, a maximum of only
one SBIP error per frame can be counted (provisionable via B1BITBLKCNT[A--D]; see register description,
page 174). This causes the error counter to only increment by one when one or more errors are detected.

B2 BIP-N Check. The LBIP block counts line BIP-N errors. The LBIP value is calculated over the incoming frame
and is compared to the received B2 bytes received in the next frame. The errors are counted. Optionally, a maxi-
mum of only one LBIP error per frame can be counted (B2BITBLKCNT[A--D]; see register description, page 174).
This causes the block error counter to only increment by one when one or more errors are detected. A theoretical
maximum of 3,072,000 errors may be detected per second. The LBIP block accumulates these errors in a 22-bit
saturating counter. This counter is operated in latch and clear mode to ensure Bellcore and ITU compliance with
regard to not missing any events (bit errors). It is intended that this counter be polled at least once per second so
that no error events are missed.

BER Check. The OHP block also detects provisionable signal fail (SF) and signal degrade (SD) conditions. The
SF and SD values are provisioned through a group of software registers (SF addresses 0x0452--0x0469,
SD addresses 0x043A--0x0451). The SF alarm can be provisioned for a bit error rate (BER) of between 10

�3

�5

; the SD alarm can be provisioned for a bit error rate (BER) of between 10

�5

to 10

�9

(see Table 86, page 187).

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Overhead Processor (OHP) Block

(continued)

Receive OHP (continued)

Figure 6 illustrates the parameters used in determining the bit error detection rate.

5-7934(F)

Figure 6. Signal Degrade and Failure Parameters for BER

TDAT042G5 provides a method to monitor the BER at the line and path layers. The following explains the algo-
rithm for this method to set and clear the BER. The algorithm for this method is the same for setting and clearing
the BER, the only difference is the programmed values. TDAT042G5 includes two complete sets of identical
counters, one used to determine signal fail (SF) and one used to determine signal degrade (SD). The only differ-
ence between SF and SD is the provisioned values. The same algorithm is used for both the line and path layers of
SONET.

The algorithm uses four sets of counters: labelled Ns (number of frames), L (number of errors), M (number of
errored blocks), and B (total number of blocks). Each of these counters has different values that are provisioned to
either set the BER high or clear the BER indication. The algorithm works by counting blocks, i.e., a preset number
of SONET/SDH frames (Ns). If the number of errors in the block exceeds the provisioned level (L), then the errored
block counter is incremented by 1; otherwise, the number of blocks in error stays at its current level. At this point,
the frame counter and the error counter are reset back to 0 and start counting again. At the end of a preset number
of blocks (B), the count in the errored block counter is compared against a provisioned threshold (M). If the total
number of blocks in error equals or exceeds the provisioned threshold (M), then the BER alarm is raised. If the total
number of blocks in error is less than the provisioned amount (M), then the BER alarm is cleared.

The values used by the counters are determined by the state of the algorithm. If the BER state is low, then the SET
parameters are used. If the BER state is high, then the CLEAR parameters are used.

NUMBER OF MONITORING BLOCKS SFBSET[A--D] OR SDBSET[A--D] (IN THIS CASE, 3)

NUMBER OF FRAMES IN A MONITORING BLOCK SFNSSET[A--D] OR SDNSSET[A--D],

BLOCK

BOUNDARY

ACCUMULATED BIP ERROR COUNT:

B1 OR B2 FOR LINE

B3 FOR PATH

FRAME

BOUNDARY

BLOCK GOOD/BAD COUNT

SFNSCLEAR[A--D] OR SDNSCLEAR[A--D]

SFLSET[A--D] OR SDLSET[A--D]

SFLCLEAR[A--D] OR SDLCLEAR[A--D]

SFMSET[A--D] OR SDMSET[A--D]

SFMCLEAR[A--D] OR SDMCLEAR[A--D]

(IN THIS CASE, 7)

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Overhead Processor (OHP) Block

(continued)

Receive OHP (continued)

Table 16 and Table 17 show values of Ns, L, M, and B for STS-3/STM-1, STS-12/STM-4, and STS-48/STM-16 to
set and clear the BER indicator. SF registers are 0x0452--0x0469 and SD registers are 0x043A--0x0451. All
SF/SD set and clear values are hexadecimal.

Table 16. Ns, L, M, and B Values to Set the BER Indicator

* These are the numbers to be provisioned in TDAT042G5. The actual values of the BER algorithm are 1 greater than the actual values shown.

These BER values cannot be provisioned because the maximum value of L is 0xF (i.e., L is a 4-bit register).

Mode

BER

SF/SD Set Values

Actual

Number of

Frames

Probability of

Detecting L

Errors (%)

Probability of

Declaring

SF/SD (%)

Integra-

tion

Time

(s)

Max-

imum

Number

of Frames

Ns*

@BER

@BER/2

@BER

@BER/2

STS-3/

STM-1

1.00E-03

99.96

85.13

97.68

0.00

0.008

1.00E-04

72.70

7.28

96.06

0.16

0.013

104

1.00E-05

384

71.34

10.08

95.19

0.52

0.1

800

1.00E-06

1E0

3840

71.34

10.09

95.19

0.52

8000

1.00E-07

1275

47250

69.74

9.44

95.07

0.13

80000

1.00E-08

B5A4

465000

68.07

8.82

98.47

0.82

664000

1.00E-09

3F7A0

4160000

56.90

11.25

96.52

0.60

667

5336000

1.00E-10

STS-12/

STM-4

1.00E-03

100.00

88.43

100.00

0.04

0.008

1.00E-04

84.92

9.64

98.38

0.00

0.008

1.00E-05

117

67.93

7.17

96.48

0.25

0.025

200

1.00E-06

1152

66.19

6.66

95.46

0.19

0.25

2000

1.00E-07

4FB

11475

65.75

6.53

95.16

0.18

2.5

20000

1.00E-08

31CE

114750

65.75

6.53

95.16

0.18

168000

1.00E-09

1F20C

1147500

65.75

6.53

95.16

0.18

167

1336000

1.00E-10

STS-48/

STM-16

1.00E-03

100.00

0.008

1.00E-04

99.95

58.97

96.89

0.00

0.008

1.00E-05

320

90.60

16.25

96.47

0.00

0.008

1.00E-06

480

77.55

13.09

96.69

0.00

0.0625

500

1.00E-07

13A

4710

75.80

12.15

95.17

0.00

0.625

5000

1.00E-08

C1C

46500

74.58

11.54

98.09

0.01

5.2

41600

1.00E-09

765C

333300

82.92

19.71

97.29

0.18

336000

1.00E-10

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Overhead Processor (OHP) Block

(continued)

Receive OHP (continued)

Overhead (OH) Extract. All transport overhead (TOH) bytes are extracted and sent over the RxTOH interface for
possible external processing. The number of bits sent are as follows:

STS-3/STM-1: 5,184,000 bits/s per interface

STS-12/STM-4: 20,736,000 bits/s per interface

STS-48/STM-16: 82,944,000 bits/s (over 4 serial lines (20,736 kbits/s each))

Table 17. Ns, L, M, and B Values to Clear the BER Indicator

* These are the numbers to be provisioned in TDAT042G5. The actual values of the BER algorithm are 1 greater than the actual values shown.

These BER values cannot be provisioned because the maximum value of L is 0xF (i.e., L is a 4-bit register).

Mode

BER

SF/SD Set Values

Actual

Number of

Frames

Probability of

Detecting L

Errors (%)

Probability of

Clearing

SF/SD (%)

Integra-

tion

Time

(s)

Max-

imum

Number

of Frames

Ns*

@BER*5

@BER

@BER*5

@BER

STS-3/

STM-1

1.00E-03

1.00E-04

85.13

0.39

0.27

100.00

0.013

104

1.00E-05

93.01

11.33

0.01

99.21

0.1

800

1.00E-06

384

84.42

6.84

0.34

99.88

8000

1.00E-07

1E05

3840

84.42

6.84

0.34

99.88

80000

1.00E-08

1275

47250

83.66

6.59

0.22

99.98

664000

1.00E-09

B5A4

465000

82.86

6.35

0.03

99.75

667

5336000

1.00E-10

3F7A0

4160000

46.31

1.48

0.50

99.84

6670

53360000

STS-12/

STM-4

1.00E-03

1.00E-04

100.00

51.54

0.00

99.03

0.008

1.00E-05

98.36

20.51

0.07

100.00

0.025

200

1.00E-06

117

87.99

8.23

0.02

99.59

0.25

2000

1.00E-07

1152

87.34

7.94

0.02

99.64

2.5

20000

1.00E-08

4FB

11475

87.17

7.87

0.03

99.65

168000

1.00E-09

31CE

114750

87.17

7.87

0.03

99.65

167

1336000

1.00E-10

1F20C

1147500

87.17

7.87

0.03

99.65

1670

13360000

STS-48/

STM-16

1.00E-03

1.00E-04

100.00

45.99

0.00

99.42

0.008

1.00E-05

100.00

60.11

0.00

99.47

0.008

1.00E-06

320

95.07

7.28

0.00

99.98

0.0625

500

1.00E-07

640

87.34

7.94

0.00

99.94

0.625

5000

1.00E-08

13A

6280

86.52

7.61

0.00

99.95

5.2

41600

1.00E-09

C1C

62000

85.95

7.38

0.00

99.96

336000

1.00E-10

765C

333300

84.89

7.00

0.03

99.95

420

3360000

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Overhead Processor (OHP) Block

(continued)

Receive OHP (continued)

The OH interface consists of clock, data, and frame. The data and frame signals update on the falling edge of the
clock. The frame pulse is high for the most significant bit (MSB) of the first bit of the frame. Bytes J0, Z0, and F1
(current and previous), K1, K2, and S1 can also be extracted via software registers.

Table 18 shows the ordering of the bytes for the allowed TOAC configurations.

Table 18. TOAC Channel I/O vs. STS Number/Time Slot

The overhead extract block also performs the following functions:

Error Monitors. The REI_L block counts remote error indication block errors. The M1 byte is extracted and
counted. This represents the number of LBIP errors detected by the far-end equipment. Optionally, a maximum
of only one REI-L error per frame may be counted (provisionable via M1BITBLKCNT[A--D]; register description,
page 175). This causes the block error counter to only increment by one when one or more errors are detected.

Automatic Protection Switch Signaling. The APS block filters the K1 and K2 bytes (automatic protection
switching channel) and stores the validated message in software-accessible registers. The K bytes are validated
after a programmable number of consecutive frames contain identical K1 (and K2[7:3] or K2[7:0]) values. APS
protection switching byte failure is detected within this block when a programmable number of frames have
passed without valid K bytes. The protection switching byte failure is removed upon detection of a programmable
number of frames with identical K1 (and K2[7:3] or K2[7:0]) bytes. The use of K2[7:3] or K2[7:0] is provisionable
via the K1K2_2_OR_1 register bit (see register description, page 169).

Line Remote Defect Indicator. Bits 2, 1, and 0 of the K2 byte are monitored for the pattern 110. If this pattern
appears for 3--15 (provisionable by OHP register CNTDK2) consecutive frames, RDI-L is asserted. RDI-L is
removed when any pattern other than 110 is detected for 3--15 (provisionable by OHP register CNTDK2) con-
secutive frames. (See page 171 for register description of CNTDK2[A--D][3:0].)

Line Alarm Indication Signal. Bits 6, 7, and 8 of the K2 byte are monitored for the pattern 111. If this pattern
appears for 3--15 (provisionable by OHP register CNTDK2) consecutive frames, AIS-L is asserted. AIS-L is
removed when any pattern other than 111 is detected for 3--15 (provisionable by OHP register CNTDK2) con-
secutive frames. (See page 171 for register description of CNTDK2[A--D][3:0].)

Output Rate

TOAC Channel Input vs. Input STS Number/Time Slot

Time

STS-3/STM-1

3 2 1 (Channel A)
3 2 1 (Channel B)

3 2 1 (Channel C)
3 2 1 (Channel D)

STS-12/STM-4

12 9 6 3 11 8 5 2 10 7 4 1 (Channel A)
12 9 6 3 11 8 5 2 10 7 4 1 (Channel B)
12 9 6 3 11 8 5 2 10 7 4 1 (Channel C)
12 9 6 3 11 8 5 2 10 7 4 1 (Channel D)

STS-48/STM-16

39 27

38 26

(Channel A)

42 30

41 29

(Channel B)

45 33

44 32

(Channel C)

48 36

24 12

47 35

23 11 46

22 10 (Channel D)

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Overhead Processor (OHP) Block

(continued)

Receive OHP (continued)

Rx Synchronization Message. The S1 block filters the synchronization message (S1) byte and stores the vali-
dated message in a software-accessible register. The synchronization message will be validated if a programma-
ble number (in OHP register CNTDS1) of consecutive frames contain identical S1 values. An inconsistent
synchronization message alarm will be reported if a provisional number (by OHP register CNTDS1FRAME) of
consecutive frames pass without a validated message occurring. (See page 172 for register descriptions of
CNTDS1[A--D][3:0] and CNTDS1FRAME [A--D][3:0].)

F1 User Channel. The F1 byte is extracted by the OHP. The F1 user channel is monitored for change of state
using OHP registers 0x0402, 0x0404, 0x0406, 0x0408 (see register map, page 116). The previous and current
F1 values are stored in F1DMON1[A--D][7:0] and F1DMON0[A--D][7:0], respectively (see page 122 for register
map, page 190 for register descriptions).

DCC and Orderwire Bytes. The data communication channel (D1--D3, D4--D12) and orderwire bytes (E1, E2)
can only be extracted via the TOAC.

D1/D2/D3 Section Data Communications Channels (DCC). DCC outputs are taken from the TOAC.

D4--D12 Line Data Communications Channels (DCC). DCC outputs are taken from the TOAC.

M1 REI-L. REI-L is extracted by the OHP.

Support for ATM/Packet-Over-Fiber. The transport overhead must be bypassed when operating in data-over-
fiber mode. In this mode, the TOH_BYPASS and ROH_BYPASS register bits must be set to 1. No overhead
insertion/extraction is done when in bypass mode.

Transmit OHP

Overhead Insertion. Some transport overhead (TOH) bytes can optionally be inserted via the TxTOH interface
and inserted into the TOH bytes (see Table 15, page 53). Certain bytes can be either inserted from values stored in
registers or automatically generated. The TxTOH interface controls the insertion mechanism. Software insertion
takes precedence over TOAC insertion. The number of bits received are as follows:

STS-3/STM-1: 5,184,000 bits/s per interface

STS-12/STM-4: 20,736,000 bits/s per interface

STS-48/STM-16: 82,944,000 bits/s (over 4 serial lines (20,736 kbits/s each))

S1 Synchronization Message. The S1 block controls the insertion of the S1 byte. The byte ordering is the same
as the RxTOAC and is shown in Table 18 (see pa ge59). The S1 byte can be provisioned to come from the TxTOH
interface or from a software-settable register. Control for message insertion is from software control register
TS1INS[A--D] (see register description, page 179 and page 183).

K1K2 APS Signaling. The APS block controls the insertion of the K bytes based on software provisioned K bytes,
and alarm conditions (AIS-L, RDI-L). Inconsistent APS bytes can be inserted via register provisioning by
TAPSBABBLEINS[A--D] (see register description, page 178 and page 183).

RDI_L Generation. The following six alarms contribute to RDI_L generation: LOF, OOF, LOS, LOC, AIS_L, and
SF. They can be inhibited from contributing to RDI-L via transmit control registers (addresses 0x042F, 0x0431,
0x0433, 0x0435; see register description, page 180).

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Overhead Processor (OHP) Block

(continued)

Transmit OHP (continued)

BIP-8 Generation. The SBIP block calculates the B1 value according to Bellcore and ITU standards. Insertion of
SBIP errors is possible through the use of software control register TB1ERRINS[A--D] (see register description,
page 180).

The LBIP block calculates the B2 values according to Bellcore and ITU standards. Insertion of LBIP errors is pos-
sible through the use of software control register TB2ERRINS[A--D] (see register description, page 180).

The REI_L block controls the insertion of the remote error indication block error count.

J0 Section Trace. The section trace message is inserted either from the TxTOH interface or from a message
stored in a 16-byte software-accessible memory. Control for message insertion is from software control register
TJ0INS[A--D] (see register description, page 177 and page 181).

SONET Scrambler. The scrambler block implements the frame synchronous SONET scrambler with a generating
polynomial of 1 + x

+ x

. The scrambler may be disabled through a software register.

A1/A2 Framing Bytes. A1 and A2 are automatically placed on the line. Errors can be inserted into A2 by setting
OHP register TA1A2ERRINS[A--D][4:0] (see register description, page 180).

E1/E2 Orderwire Bytes. The orderwire bytes for section and line are taken from the TOAC.

D1/D2/D3 Section Data Communications Channels (DCC). DCC inputs are taken from the TOAC.

D4--D12 Line Data Communications Channels (DCC). DCC inputs are taken from the TOAC.

F1 User Channel. The F1 byte can be optionally inserted from stored values in OHP register TF1INS[A--D]
(addresses 0x047E, 0x0480, 0x0482, 0x0484; see register description, page 179 and page 183).

M1 REI-L. REI-L can be automatically generated and inserted into the outgoing SONET frame, or can optionally
be inhibited. Errors can be inserted into M1 via OHP register TM1_ERR_INS[A--D] (addresses 0x042E, 0x0430,
0x0432, 0x0434; see register description, page 179 and page 183).

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Path Terminator (PT) Block

The path terminator performs path overhead (POH) termination and extracts the payload for further processing by
the downstream circuitry. The path terminator block interprets the incoming H1/H2 pointer of each incoming STS
channel. The pointer interpreter supports up to four channels and performs path overhead termination on each
channel. Each channel may be either an STS-1, STS-3c, STS-6c, STS-9c, . . . , STS-45c, or STS-48c.

The pointer is validated according to Bellcore and ITU specifications. The H1/H2 pointers are used to determine
the location of the first path overhead (POH) byte (J1). The pointer interpreter consists of a finite state machine
(FSM) with four steady states. These states are defined as follows:

Normal state

Loss-of-pointer (LOP)

Alarm indication signal (AIS)

Concatenation

The transition between states will require several consecutive events to protect against transient conditions caused
by bit errors during high BER conditions. The state machine is shown below in Figure 7.

5-7935(F)

Figure 7. Pointer Interpreter State Diagram

The PT block monitors for the following conditions and takes appropriate actions:

Pointer Increment. TDAT042G5 uses an 11-bit counter to count the number of pointer increments and updates
the associated counter holding register on the occurrence of PMRST (RPI_INC[A--D][10:0]; see register
description, page 198). A pointer increment can occur when in the normal pointer mode. The following two meth-
ods can be used to determine if the pointer increment operation should be performed: 6-of-10 or 8-of-10 majority
matching (selectable via software provisioning of register RINCDEC_6OR8MAJ [A--D]; see register description,
page 200).

NORMAL

AIS

CONC

LOP

NDF

POINT

OR 8 INV

ID P

OINT

I
N

IONS

AIS INDICA

IONS

1 NDF POINTER OR

3 NORMAL POINTERS

3 AIS INDICATIONS

8 INVALID POINTERS

3 CONC INDICATIONS

3 N

3 C

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Path Terminator (PT) Block

(continued)

Pointer Decrement. TDAT042G5 uses an 11-bit counter to count the number of pointer decrements and
updates the associated counter holding register on the occurrence of PMRST (RPI_DEC[A--D][10:0]; see regis-
ter description, page 198). A pointer decrement can occur when in the normal pointer mode. The following two
methods can be used to determine if the pointer decrement operation should be performed: 6-of-10 or 8-of-10
majority matching (selectable via software provisioning of register RINCDEC_6OR8MAJ [A--D]; see register
description, page 200).

Loss-of-Pointer. LOP-P is declared as shown in the above state diagram. In an LOP-P state, none of the path
overhead bytes are extracted.

AIS-P. The AIS-P is declared when the H1 and H2 bytes are set to all ones. In an AIS-P state, none of the path
overhead bytes are extracted.

Concatenated Pointer. A concatenated pointer is detected when the new data flag is set and the pointer offset
value is all ones.

New Pointer. TDAT042G5 uses a 13-bit counter to count the number of new data flags that occur and updates
the associated counter holding register on the occurrence of PMRST (RNDFCNT[A--D][12:0]; see register
description, page 198). TDAT042G5 uses a 3-of-4 majority voting scheme to determine if the new data flag is
set. Valid new data flags occur when the NDF bits are either 1001, 0001, 1101, 1011, or 1000.

Normal Pointer. A normal pointer occurs when all of the following conditions are true simultaneously:

1. NDF is not set (NDF bits are either 0110, 0111, 0100, or 0010),

2. There is no invalid pointer value,

3. There is a valid offset (0 to 782)

Invalid Pointer. An invalid pointer is declared when neither a new data flag nor a normal pointer is detected.

SPE Terminate

Receive Path Trace. The path trace message is extracted and stored in a 16-byte (SDH) or 64-byte (SONET)
memory for access by software. The first byte of the message can be provisioned to be either of the following:

For SDH mode, the byte with the most significant bit (MSB) set high (for SDH)

For SONET mode, the byte following a carriage return (0x0D) and line feed (0x0A) sequence

The framing can also be disabled.

Receive Error Monitor. The PBIP block counts path BIP-8 errors. A theoretical maximum of 64,000 errors may be
detected per second. The PBIP block accumulates these errors in a 16-bit saturating counter. This counter is oper-
ated in latch and clear mode to ensure Bellcore and ITU compliance with regard to not missing any events (bit
errors). It is intended that this counter be polled at least once per second in order that no error events are missed.
The REI_P block counts remote error indication block errors.

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Path Terminator (PT) Block

(continued)

SPE Terminate (continued)

Receive Signal Label. The C2 block will extract and validate the signal label byte (C2) and store it in a software-
accessible register. The signal label is updated when a provisionable number of consecutive detections of a new
C2 value occur (CNTDC2[A--D][3:0]; see register description, page 204). All monitoring is disabled when the
pointer is in an LOP-P or an AIS-P state. Commonly used values of C2 with their signal labels are listed below in
Table 19.

Table 19. Types of Signal Labels

Any value of C2 may be provisioned. If the provisioned value is not matched by the detected value, then data is not
passed to the DE. If the provisioned value does match the detected value, then data is passed to the DE.

TDAT042G5 will detect unequipped payloads (UNEQ-P) when a provisionable number of consecutive monitored
C2 bytes match the 0x00 unequipped STS SPE state. TDAT042G5 will detect mismatched payloads (PLM-P)
when a provisionable number of consecutive monitored C2 bytes do not match the provisioned expected payload
label (RC2EXPVAL[7:0]; see register description, page 205).

Receive Path Status. The G1 block extracts the path remote error indication (REI-P) bits of G1[7:4] and accumu-
lates the REI-P errors in a 16-bit saturating counter. This counter is operated in latch and clear mode to ensure
Bellcore and ITU compliance. It is intended that this counter be polled at least once per second in order that no
error events are missed.

RDI-P. This block will also validate the path remote defect indication (RDI-P) bits and store the result in a software-
accessible register. The receive path can monitor remote defect indications in either enhanced or single bit RDI-P
modes (provisionable via software bit RDIPMON_ENH_OR1B [A--D]; see register description, page 200). The
interpretation of the G1 byte is as follows.

Table 20. 1-bit Mode

Table 21. 3-bit Mode (Enhanced RDI)

* TIM-P must be accomplished through (microprocessor) software by reading the

transmit RDI-P state and inserting the G1 bit.

C2 Value

Signal Label

0x00

Unequipped STS SPE

0x01

Equipped nonspecific payload

0x13

Mapping for ATM

0x16

Mapping for HDLC-PPP

G1 Bytes

Description

G1[3:1] = 0xx

No RDI-P defects

G1[3:1] = 1xx

AIS-P, LOP-P

G1 Bytes

Description

G1[3:1] = 001

No RDI-P defects

G1[3:1] = 010

PLM-P or LCD-P

G1[3:1] = 101

AIS-P or LOP-P

G1[3:1] = 110

UNEQ-P or TIM-P (TIM-P is J1 mismatch*)

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Path Terminator (PT) Block

(continued)

Z5/N1, Z4/K4, Z3/F3, H4, F2 Monitoring. TDAT042G5 monitors the F2 user channel byte, the H4 VT multiframe
indicator byte, Z3/F3 growth/user byte, Z4/K4 growth/APS path byte, and the Z5/N1 tandem connection byte.
These bytes are stored in software registers. These registers are updated when a provisionable number of detec-
tions of new values occur on the associated incoming byte. All monitoring is disabled when the pointer is in an
LOP-P or an AIS-P state.

Signal Failure and Signal Degrade Monitoring. The path overhead processor also detects/clears provisionable
signal fail (SF) and signal degrade (SD) conditions. The SF and SD values are provisionable through a group of
software registers in the PT register map. The provisioning is the same as that shown in Table 16, page 57 of the
Overhead Processor (OHP) Block section.

SPE Generate

Transmit Pointer Generation. The pointer generation block generates the outgoing H1 and H2 pointer values.
Each of the four PT channels can generate one normal (valid) pointer. Therefore, in STS-3/STM-1 and STS-12/
STM-4 modes, only one normal pointer (and only one SPE) may be inserted into the transmitted SONET/SDH
frame. In STS-48/STM-12 mode, all four PT channels are used. Therefore, up to four normal pointers (and four
SPEs) may be inserted into the transmitted SONET/SDH frame.

When inserting concatenated frames, only the first H1 and H2 bytes will contain a valid pointer value. The remain-
ing H1 and H2 bytes of the channel will be set to indicate concatenation. The remaining unequipped channels will
have their H1 and H2 pointers set to a fixed pointer value.

For proper pointer generation, the appropriate values must be provisioned in the H-byte transmit state register
THx_STATE (see register description, page 203).

The following examples illustrate how the device may be configured to transmit various sub-rates and concate-
nated payloads. Each block in the following diagrams represents one STS-1 frame. Figure 8 illustrates how to pro-
vision the THx_STATE registers to transmit an STS-48c frame within an STS-48 signal. In this example, the pointer
to the first STS-1 is provisioned as a normal pointer value while the pointers to the remaining STS-1 signals are
provisioned as concatenated pointers. Figure 9 illustrates how to provision the THx_STATE registers to transmit
four STS-12c frames within an STS-48 signal. The concatenated STS-Mc frames that may be mapped into STS-N
signals (where M

N) are restricted to those listed in Table 22 (see page 68).

0351(F)

Figure 8. STS-48 Signal Carrying One STS-48c Frame

TIME-SLOT NUMBER

_STATE[A][12--1][1:0]

_STATE[B][12--1][1:0]

_STATE[D][12--1][1:0]

_STATE[C][12--1][1:0]

47 CONCATENATED POINTERS

NORMAL POINTER

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Path Terminator (PT) Block

(continued)

SPE Generate (continued)

0352(F)

Figure 9. STS-48 Signal Carrying Four STS-12c Frames

0353(F)

Figure 10. Quad STS-12 Configuration With Each STS-12 Signal Carrying One STS-3c Frame

TIME-SLOT NUMBER

_STATE[A][12--1][1:0]

_STATE[B][12--1][1:0]

_STATE[D][12--1][1:0]

_STATE[C][12--1][1:0]

44 CONCATENATED POINTERS

FOUR NORMAL POINTERS

TIME-SLOT NUMBER

_STATE[A][12--1][1:0]

_STATE[B][12--1][1:0]

_STATE[D][12--1][1:0]

_STATE[C][12--1][1:0]

UNEQUIPPED

CONCATENATED POINTERS

12a

12b

12c

12d

11a

11b

11c

11d

10a

10b

10c

10d

POINTERS

UNEQUIPPED

POINTERS

UNEQUIPPED

POINTERS

NORMAL POINTERS

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Path Terminator (PT) Block

(continued)

SPE Generate (continued)

0354(F)

Figure 11. Quad STS-12 Configuration With Each STS-12 Signal Carrying One STS-12c Frame

(Channel A), One STS-9c Frame (Channel B), One STS-6c Frame (Channel C), and
One STS-3c Frame (Channel D)

0355(F)r.1

Figure 12. Quad STS-3 Configuration With Each STS-3 Signal Carrying One STS-2c Frame

TIME-SLOT NUMBER

_STATE[A][12--1][1:0]

_STATE[B][12--1][1:0]

_STATE[D][12--1][1:0]

_STATE[C][12--1][1:0]

NORMAL POINTERS

12a

12b

12c

12d

11a

11b

11c

11d

10a

10b

10c

10d

TIME-SLOT NUMBER

_STATE[A][12--1][1:0]

_STATE[B][12--1][1:0]

_STATE[D][12--1][1:0]

_STATE[C][12--1][1:0]

UNEQUIPPED POINTERS

CONCATENATED POINTERS

NORMAL POINTERS

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Path Terminator (PT) Block

(continued)

SPE Generate (continued)

BIP-8. The PBIP block calculates the B3 value according to Bellcore and ITU standards. Insertion of PBIP errors is
possible through the use of a software control register.

REI Generation. The REI_P block controls the insertion of the remote error indication block error count. The
received PBIP error counts are inserted into the path status (G1) byte.

RDI-P Generation. The transmit path can insert remote defect indications using either single-bit or enhanced
RDI-P modes (provisionable via software register bit TRDIP_ENH_OR1B[A--D]; see register description, page
202). The highest to lowest priority of the defect code insertion is as follows:

1. AIS-P, LOP-P (applies only to the single-bit version of RDI-P),

2. UNEQ-P,

3. PLM-P, LCD-P,

4. No defects

TIM-P can be inserted using software through TRDIPSINS (registers 0x0AAA, 0x0AB2, 0x0ABA, or 0x0AC2,
bits 15--11; see register description, page 201). The LCD-P defect is observed in the data engine and passed to
the pointer block for transmission. Each particular defect can be inhibited from contributing to the transmitted
RDI-P insertion value via software registers 0x0AAA, 0x0AB2, 0x0ABA, and 0x0AC2. RDI_P can either be inserted
by software or automatically through hardware.

Z5/N1, Z4/K4, Z3/F3, H4, F2 Insertion. TDAT042G5 inserts the F2 user channel byte, the H4 VT multiframe indi-
cator byte, Z3/F3 growth/user byte, Z4/K4 growth/APS path byte, and the Z5/N1 tandem connection byte via soft-
ware provisioning.

Error Insertion Mechanisms. TDAT042G5 provides a method to inject via software REI-P
(TREIPERRINS[A--D]) and B3 (TB3ERRINS[A--D]) errors into the transmitted SONET frame (see register
descriptions, page 202).

Insertion of J1, F2, C2, Z3, H4, Z4, Z5, SS Values. TDAT042G5 provides paged provisionable registers to insert
the path overhead bytes into the outgoing SONET frame. The paging is done by first writing to the page provision-
ing register at location 0x0AC6 to set the port number and time slot to be provisioned, and then writing to the
appropriate insertion registers. Available time-slot values for TDAT042G5 are time slot 1 for STS-48c mode; time
slots 1, 2, 3, and 4 for STS-48 consisting of four STS-Mc (M

12) signals; and time slot 1 for quad STS-12c and

quad STS-3c modes (ports A, B, C, and D configured for quad STS-3c and quad STS-12c).

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Data Engine (DE) Block

The DE block processes ATM, SDL, PPP, and HDLC cells/packets at rates up to 2.488 Gbits/s. The DE block
behaves like four independent logical data channels, one for each of the four STS-12/STM-4 or STS-3/STM-1
channels, or like a separate single channel for STS-48/STM-16. The following description is for each one of these
data engines. Each of the functional elements to be described are independently provisioned.

The data engine supports both ATM cells and packet data formats.

The ATM processor functions with 52-byte, 53-byte, and 56-byte ATM cells.

The packet processor has three packet modes: HDLC, CRC, and PPP. All three modes use HDLC framing, i.e.,
0x7E delineates the packets. In HDLC mode, the 0x7E framing bytes are inserted or detected by the data
engine. In the CRC mode, a user-selectable 16-bit or 32-bit CRC word is appended or detected at the end of the
packet. The PPP mode places or detects a PPP header on the front of the packet as well as uses the CRC word.

The block diagram for the data engine is shown in Figure 13.

5-8385(F)r.2

Figure 13. Block Diagram of Date Engine (DE)

CBINT

SDL

INSERTER

ATM

INSERTER

HDLC

INSERTER

X43

POST-

SEQUENCER

SCRAMBLER

CRC

GENERATOR

PPP

ATTACH

INTERFACE

X43

PRESCRAMBLER

INTERFACE

CBINT

SDL

FRAMER

ATM

FRAMER

HDLC

FRAMER

X43

POST-

SEQUENCER

UNSCRAMBLER

CRC

CHECKER

PPP

DETACH

INTERFACE

X43

PRE-

INTERFACE

UNSCRAMBLER

RECEIVE-SIDE DE BLOCK

TRANSMIT-SIDE DE BLOCK

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Data Engine (DE) Block

(continued)

Receive Data Engine

Receive Sequencer. The receive sequencer demaps SONET framing to four logical channels, performs the phys-
ical channel byte alignment and packing, and performs appropriate payload clock domain transfer. The receive
sequencer must be provisioned properly for correct operation. There are six registers that are fixed for each partic-
ular mode of operation (STS-3/STM-1, STS-12/STM-4, or STS-48/STM-16) and must not be modified
(SEQ_CTRL, INIT_CNTS, OH_MARKER_LO, OH_MARKER_HI, SOH_MARKER_LO, SOH_MARKER_HI). See
the register descriptions for details, page 214. Also, the appropriate time slots must be provisioned for the rate of
the payload expected for each channel. This is done via the registers Rx_TS[1--12] (see register descriptions,
page 219). An example of how to configure this for STS-48c mode is shown in the section on configuring the trans-
mit/receive sequencer (see Transmit Data Engine section, page 78).

ATM Cell Processor. The cell processor performs ATM cell delineation using the ATM header error correction
(HEC) field found in the cell header. The HEC is a CRC-8 calculation over the first four octets (total of 32 bits) of
the ATM cell header. If the TDAT042G5 is in bit-synchronous mode (data is not byte-aligned), 32 separate HEC
calculations are performed to delineate an ATM cell. If the TDAT042G5 is in byte-synchronous mode (data is byte-
aligned), four separate HEC calculations are performed to delineate an ATM cell. An alpha-delta counter is used to
track the processor's ability to frame the ATM cells consistently. When a certain level of confidence is reached
(defined by the programmable delta counter threshold), the frame is declared in sync state, and data is passed to
subsequent blocks. If the framer is unable to frame ATM cells over a few cell periods (defined by the programma-
ble delta counter threshold), the framer resumes hunt state.

In SONET mode, the processor performs optional X

unscrambling of the payload. Because the X

scrambler is

self-synchronizing, the framer needs no assistance from the data in order to synchronize the scrambler. The
TDAT042G5 also supports an X

scrambler, compliant with I.432, which is mainly used for packet-over-fiber

applications. The state diagram for the X

scrambler is shown in Figure 14 on page 72. The X

scrambler uses

an x

+ x

+ 1 polynomial to scramble the data. Unlike the X

scrambler, the X

scrambler does not self-

synchronize based upon the data it receives. Thus, one-bit samples of the scrambler output are sent on the trans-
mit side and compared with the scrambler samples on the receive side every 212 bits. If the samples do not match,
the receive-side scrambler is adjusted to converge with the transmit-side scrambler. This process continues until a
certain level of confidence in the scrambler synchronization is achieved. In the X

mode, the ATM cell processor

does not send out any output until both the framer and the scrambler are synchronized, whereas in X

mode, only

the framer needs to be synchronized.

Idle ATM cells, which contain no real data, can be either left in or removed from the bit stream. The idle cell header
description can be configured, though it is set to a default value (0x00000001). ATM cells can also be filtered if the
header contents match a provisioned match register after masking with a provisionable mask register. This allows
filtering based on the contents of the GFC, PTI, and CLP fields of the header. Optionally, ATM cells may be
dropped if uncorrectable HEC errors are detected. Incoming single-bit ATM header errors can be corrected and the
cells may be passed through or dropped, depending on the software configuration.

The data engine processes only standard 53-byte ATM cells. However, the UTOPIA block processes 52-byte, 53-
byte, 54-byte, and 56-byte cells, and interfaces these to the data engine. (See UTOPIA (UT) Interface Block,
page 86, for details).

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Data Engine (DE) Block

(continued)

Receive Data Engine (continued)

5-8388(F)

Note: Even in synchronized mode, the confidence counter can continue to increase up to the Z value.

Figure 14. State Diagram for the X

Scrambler Synchronization Process

SDL Frame Processor. The SDL frame processor consists of an SDL framer, which detects the start of SDL pack-
ets, and an (optional) X

unscrambler, which is used to unscramble payload data. SDL packets can also arrive

unscrambled, in which case the unscrambler is disabled. The SDL frame processor can frame packets in SDL form
which contain a data length between 4 and 65,535 bytes.

The SDL framer uses a CRC-16 check upon 2 bytes sequences used to determine packet length in order to frame
SDL packets. Since the framer is designed to support data that is not byte-aligned, 32 separate framers may be
used to search for the CRC-16 pattern. If the data is byte-synchronized, only four framers are needed. A confi-
dence counter is used to gauge the framer's ability to frame SDL packets consistently. When the confidence
counters reaches a certain level (defined by the programmable SDL delta counter register), the framer is in sync
state. Single-bit error correction for the SDL headers is also supported. Shown below in Figure 15 is the general
structure of the SDL packets. In this figure, there is no interpacket fill.

5-8386(F)r.2

Figure 15. General Structure of SDL Packets

VERIFICATION

SYNCHRONIZED

ACQUISITION

COUNTER EQUALS Y

COUNTER LESS

COUNTER DROPS

THAN Y

BELOW V

COUNTER EQUALS X

COUNTER DROPS

BELOW W

COUNTER LESS

THAN X

PACKET PAYLOAD

PACKET
LENGTH

CRC-16

PACKET PAYLOAD

PACKET
LENGTH

PACKET PAYLOAD

CRC-16

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Data Engine (DE) Block

(continued)

Receive Data Engine (continued)

Interpacket fill separating packets always contains a multiple of 4 bytes. The SDL framer is able to detect inter-
packet fill since its value is fixed. (It has 4 bytes equal to 0x0000000, i.e., a packet length of 0x0000 with a CRC-16
of 0x0000.) Since the framer knows the length of a particular packet and can detect interpacket fill, it will predict the
start of the next frame and frame on it. The SDL frame processor supports SDL and SDL CRC modes. When oper-
ating in SDL CRC mode, a 2-byte or 4-byte CRC for the packet payload is attached to the end of the packet pay-
load prior to the next packet length. When operating in SDL mode, there is no 2-byte or 4-byte CRC for the packet
payload.

The SDL frame processor supports X

scrambling of the packet payload, which is accomplished by using a primi-

tive polynomial of x

+ x

+ x + 1. The X

scrambler is not self-synchronizing. Thus, the side transmitting

SDL packets will periodically send its 48-bit scrambler state within the data stream such that the receive side can
synchronize its scrambler. Whenever the SDL frame processor receives a scrambler state, it is immediately put
into sync state, which allows it to send data out. Upon receiving additional scrambler states, the scrambler will
compare its own state with the state received. If the scrambler states match, then the scrambler remains in sync
state. However, if there is a mismatch, the scrambler is put into postsync state. In postsync state, if an additional
scrambler state mismatch occurs, the X

scrambler is resynchronized with the scrambler state it has received.

The SDL frame processor detects scrambler state data since the packet length field of 0x001 and the length of
time separating scrambler state transmissions is programmable. Single-bit error correction for the SDL scrambler
state is incorporated within the TDAT042G5.

Both the SDL framer and the X

scrambler must be synchronized before the SDL frame processor will send data.

Besides the SDL scrambler state being transmitted, the SDL framer will also extract special A and B messages
used by the upstream device to send link layer 1 messages to the downstream hardware. The packet length field
used to detect A and B messages are 0x0002 and 0x0003, respectively.

In addition to scrambling the data, the SDL data stream coming into the SDL frame processor is dc balanced with
the 32-bit value 0xB6AB31E0.

Table 23 below is used to describe the packet length field.

Table 23. Packet Length Field

Pre-descrambler. The pre-descrambler block descrambles the payload using a self-synchronous descrambler
with a generator polynomial of 1 + x

. For ATM cell traffic, only the 48-byte cell payload (and not the cell over-

head) is descrambled. For HDLC and PPP packets, the entire frame (including header and trailer) is descrambled.
Predescrambling, post-descrambling, or no descrambling may be selected through a provisionable register.

Packet Length

Field

SDL Data Type

0x0000

Interpacket fill

0x0001

SDL scrambler state

0x0002

A message

0x0003

B message

0x0004--

0xFFFF

Length of payload region for current
packets (in bytes)

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Data Engine (DE) Block

(continued)

Receive Data Engine (continued)

HDLC Framer. The packet processor frame aligns to HDLC packets using the HDLC flag character (0x7E). Flags
are also used to fill interpacket spaces. The flags are removed and control escape destuffing is performed. The
control escape character (0x7D) is searched for and when it is found, the control escape character is removed, i.e.,
0x7D5D is unescaped to 0x7D and 0x7D5E is unescaped to 0x7E. If dry mode is enabled, then 0x7D20 is unes-
caped to a value of 0x00, which represents dry data (FIFO underflow in the middle of a packet). Any other unes-
caped sequence of 0x7D results in an errored packet.

CRC Check. An optional CRC-ITU or CRC-32 calculation on the whole POS frame is performed after byte destuff-
ing and data descrambling. The CRC-ITU generating polynomial is 1 + x

+ x

. The CRC-32 generating

polynomial is 1 + x + x

+ x

. The computation over

the whole packet, including the FCS field, should result in all zeros. A different value indicates an error. Packets
with FCS errors are marked as such and are discarded. CRC field stripping is optional. Both normal and reversed
CRC modes are supported.

Post-descrambler. The descrambler block descrambles the payload using a self-synchronous descrambler with a
generator polynomial of 1 + x

. For ATM cell traffic, this block is bypassed. For HDLC frames, the entire frame

(including header and trailer) is descrambled. The descrambler may be disabled through the use of a software reg-
ister.

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Data Engine (DE) Block

(continued)

Receive Data Engine

(continued)

PPP Header Detach. The PPP detach function matches the PPP header (corresponding to the first 4 bytes of the
PPP uncompressed frame or first 2 bytes of the PPP compressed frame) to a set of fixed or provisionable values
for each channel and outputs frames in accordance with payload control register settings. The address and control
field bytes are assumed to be 0xFF03. The block supports two fixed protocol fields (0x0021 corresponding to the
IP protocol field, and 0x8021 corresponding to the IP control protocol). Additionally, 12 provisionable registers,
PPP_Rx_HDR [0--11][15:0] (addresses 0x10F0--0x10FB), are supported on-chip to allow a large number of pro-
tocols to be recognized in the receive (ingress) data path of the chip.

The PPP detach function supports compressed or uncompressed header fields, optionally matching two fixed (one
corresponding to IP protocol) 16-bit protocol fields. This optional PPP header check allows PPP (normal or com-
pressed (i.e., no FF03)) to be checked and the header optionally stripped. Packets that fail to match one of the pro-
visioned headers or the two default headers can optionally be discarded. This function supports optionally
matching 12 programmable 16-bit protocol fields. The PPP detach function provides mismatched PPP header
count on a per-channel basis through four 28-bit counters, PM_MHC_[0--3][27:0] (addresses 0x1118--0x111F).
The function can optionally discard frames if header fields do not match on a per-channel basis. It can also option-
ally strip header fields only if they do match on a per-channel basis.

A PPP packet has the following two formats:

5-9642 (F)

* TDAT042G5 is verified to handle packets of up to 64 Kbytes. Larger packets may be processed, but no upper bound or packet size

has been determined. Packets of less than 4 bytes are discarded by the DE.

Figure 16. Uncompressed and Compressed PPP Packets

Each channel has a 16-bit register, PPP_Rx_CHK_CH [0--3][15:0] (addresses 0x10FC--0x10FF), that can be
provisioned.

If the header bytes do not match and payload control bit 7 = 0, the entire PPP packet is discarded for a given chan-
nel. Otherwise, if the header bytes do not match and payload control bit 7 = 1, the PPP packet is marked as bad
and not discarded for a given channel.

If payload control bit 6 = 0, the header is stripped, provided it matches a provisionable value; otherwise, it is left on
for a given channel.

0x7E

PROTOCOL

DATA

CRC FIELD

FIELD

1 byte

2 bytes

1 byte

64 Kbytes*

2 OR 4 bytes

PACKET

COMPRESSED PPP PACKET

NEXT PACKET

1 byte

64 Kbytes*

PACKET

UNCOMPRESSED PPP PACKET

NEXT PACKET

ADDRESS FIELD

CONTROL FIELD

0xFF

CRC FIELD

DATA

0x03

PROTOCOL

FIELD

2 OR 4 bytes

2 bytes

1 byte

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Data Engine (DE) Block

(continued)

Receive Data Engine

(continued)

The bad packet counting is based upon the following criteria:

Header Fields. The PPP mismatched header counter, PM_MHC_[0--3][27:0] (addresses 0x1118--0x111F),
counts for PPP packets with various header errors/mismatches as provisioned in the registers.

CRC Field. The CRC bad packet counter, PM_BPC_n (n = 0, 1, 2, 3), increments if a CRC error is found in
channel n.

Each PPP packet not counted as a bad packet in PM_MHC_n (n = 0, 1, 2, 3) counter or PM_BPC_n counter incre-
ments the PPP good packet counter, PM_GPC_n (n = 0, 1, 2, 3), for channel n. (See register descriptions,
page 241.)

Note that each channel only has a single pair of good and bad packet counters.

Transmit Data Engine

ATM Cell Inserter. The ATM cell inserter provides X

or X

scrambling of the payload for transport of ATM cells

over SONET. X

scrambling is suitable for the transport of ATM cells over fiber where bit-level cell delineation is

required. The state diagram for the X

scrambler is shown in Figure 14, page72. The ATM cell inserter will gener-

ate idle cells/bytes to fill the SONET/SDH payload when cells/packets are not available in the transmit direction
FIFO of the UTOPIA block. For ATM cells, the GFC, PTI, and CLP fields of the idle cell header and the idle cell pay-
load are provisionable via software registers. The idle generator generates idle cells/bytes to fill the SONET/SDH
payload when cells/packets are not available in the transmit FIFO. Idle cell HCS is automatically calculated and
inserted.

Header Check Sequence (HCS) Generator. The HCS generator performs a CRC-8 calculation over the first four
header octets of the ATM cell. The generator inserts the result into the fifth octet of the ATM header.

SDL Frame Inserter. The SDL inserter performs SDL frame generation and X

scrambling of the payload field.

An optional CRC-16/32 field can be attached (SDL-CRC mode) and is calculated over the payload. The SDL
inserter also periodically transmits scrambler state updates through a special 6-byte message. The time between
scrambler state updates can be provisioned by software using register SDLFI_INT (see register description, page
250). The packet length header of scrambler state updates is the 16-bit word, 0x0001. Special A and B messages
can be software-provisioned to send link layer 1 messages to downstream hardware. The packet length headers
for the special A and B messages are 0x0002 and 0x0003, respectively.

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Data Engine (DE) Block

(continued)

Transmit Data Engine (continued)

Prescrambler. The prescrambler block optionally scrambles the payload using a self-synchronizing scrambler with
a generator polynomial of 1 + x

for HDLC and PPP packets. For HDLC frames, the entire frame, including

header and trailer, is scrambled; however, HDLC flags are not scrambled. The scrambler may be disabled through
the use of a software register. This scrambler removes excessive 0x7D and 0x7E bytes. For ATM cell and SDL
packet traffic, this block is not used. (By randomizing the data, the scrambler prevents malicious use of the channel
due to escaping 7D and 7E sequences.)

CRC-16/-32 Generator. An optional CRC-16/-32 generator on the whole packet frame can be performed. The gen-
erating polynomial for CRC-16 is 1+ x

+ x

. The generating polynomial for CRC-32 is 1+ x + x

+ x

HDLC Inserter. The HDLC framer provides frame check sequence (FCS) generation and insertion using either the
CRC-ITU or CRC-32 generation polynomials. After optional CRC generation, the HDLC framer performs control
escape (0x7D) stuffing, flag character (0x7E) or abort character (0x7D7E) insertion, and dry mode insertion
(0x7D20, where the last two bytes (the 20 bytes of the default value of 0x7D20) are provisionable).

Postscrambler. The postscrambler block optionally scrambles the payload using a self-synchronizing scrambler
with a generator polynomial of 1 + x

for HDLC and PPP packets, in accordance with RFC1619. For HDLC and

PPP packets, the entire frame, including header and trailer, is scrambled. The scrambler may be disabled through
the use of a software register. For ATM cell and SDL packet traffic, this block is not used.*

PPP Header Attach. The PPP attach function inserts the provisionable 4-byte PPP header if payload control
bit 7 = 1 (addresses 0x10E0--0x10E3). The first and second bytes are set to 0xFF03, and the third and fourth
bytes are set to a value defined by a software register in PPP_Tx_CHAN[0--3] (see register descriptions,
page 234).

If payload control bit 7 = 0 (addresses 0x10E0--0x10E3) (compressed PPP header mode), only the two provision-
able bytes defined by the software register PPP_Tx_CHAN[0--3] can be attached. Note that there is only one soft-
ware register-defined protocol value for each channel.

The PPP attach function provides good packet count on a per-channel basis through four 28-bit counters,
PM_GPC_TX_[0--3] [27:0] (addresses 0x1128--112F).

* The ATM and SDL framer inserters have their own dedicated scramblers.

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Data Engine (DE) Block

(continued)

Transmit Data Engine (continued)

Tx Sequencer. The transmit sequencer maps logical channels into SONET frames, and must be provisioned prop-
erly for correct operation. The appropriate time slots must be provisioned for the rate of the payload expected for
each channel. This is done via the registers Tx_TS[1--12] (see register descriptions, page 215).

TDAT042G5 provides 12 time slots and four channels to define how data is mapped into the 48 synchronous trans-
port signals (STS-1) of an STS-48 frame or into the 12/3 STS signals of an STS-12/3 SONET frame.

Figure 17 illustrates the mapping of the 48 STS-1 signals into an STS-48 signal and their assigned time slots. Each
STS-1 block in the figure represents a byte of data for the specific STS-1 signal. The STS signals within the 12 time
slots are ordered such that the SONET multiplexing requirements of lower rate signals into higher rate signals are
satisfied. A value of 0x4 indicates that valid data is contained in the specific byte (STS) and the data is being
received/transmitted from/to channel 0.

5-7936(F)r.3

Figure 17. Example of Tx/Rx Sequencer Configuration: STS-48c into Single OC-48 Signal

0 x 4

TIME-SLOT NUMBER

_TS[12--1][15:12]

_TS[12--1][11:8]

_TS[12--1][3:0]

_TS[12--1][7:4]

CONFIGURE SIMILARLY

FOR R

SEQUENCER

0 x 4

PAYLOAD LOCATIONS

VALID AND DIRECTED TO CHANNEL 0

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Data Engine (DE) Block

(continued)

Transmit Data Engine (continued)

Figure 20 illustrates the configuration of the time-slot registers for four independent STS-3 signals. In this case,
there are three STS-1 signals that comprise each STS-3 signal. Since there are 12 time slots and only three are
actually required, the values in time slots 4--12 can be repetitively configured as shown in the figure or can be
configured as invalid, i.e., 0x0, 0x1, 0x2, and 0x3 for channels A, B, C, and D, respectively.

5-7937(F).ar2

Figure 20. Example of Tx/Rx Sequencer Configuration: 4xSTS-3c into Four Independent OC-3 Signals

Performance Monitoring

This block contains several cell/packet counters for receive/transmit data traffic. Two 28-bit saturating counters
count the number of good packets/cells that are sent out and received by the enhanced UTOPIA interface. There
are 28-bit counters used to count the number of corrected ATM HCS single bit errors, HDLC invalid sequences,
and SDL corrected headers. Also, 28-bit counters are used to count the number of uncorrectable HCS errored
ATM cells (discarded cells), HDLC short packets, SDL errored headers, packets with bad CRC checks, and mis-
matched PPP headers. These counters are operated in latch and clear mode (using PMRST) to ensure GR-256
standards compliance. It is intended that these counters be polled at least once per second so that no error events
are missed.

0 x 4

0 x 5

0 x 6

0 x 7

TIME-SLOT NUMBER

_TS[12--1][15:12]

_TS[12--1][11:8]

_TS[12--1][3:0]

_TS[12--1][7:4]

CONFIGURE SIMILARLY

FOR R

SEQUENCER

0 x 4

PAYLOAD VALID TO CHANNEL 0

0 x 5

PAYLOAD VALID TO CHANNEL 1

0 x 6

PAYLOAD VALID TO CHANNEL 2

0 x 7

PAYLOAD VALID TO CHANNEL 3

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Data Engine (DE) Block

(continued)

Over-Fiber Modes

In addition to the support of the normal SONET/SDH modes for different payload types such as HDLC, PPP, ATM
(X

or X

), and SDL as shown in Figure 2 on pa ge45, this device is capable of supporting the over-fiber modes

for two payload types, SDL or ATM (X

). In the over-fiber mode, a 3% payload increase can be realized because

the data stream contains no SONET/SDH overhead bytes.

In the over-fiber modes, it is possible to utilize the whole bandwidth (155 Mbits/s for OC-3, 622 Mbits/s for OC-12,
or 2.5 Gbits/s for OC-48) of the optical fiber for SDL packets or ATM cells.

As can be seen in Figure 21, for over-fiber modes the device is provisioned as follows:

The line termination (OHP) and path termination (PT) blocks of the device need to be provisioned in the
passthrough mode.

The payload termination (DE) block needs to be set to the bit synchronization mode in the payload control regis-
ter.

The transparent mode in the transmit and receive sequencers (addresses 0x102E and 0x102F; see register
description, page 223).

Bit 12 of the mode register (address 0x0010) needs to be set to 0 so that the received clock drives the entire
receive data path. In this way, there is no need to cross the clock domain boundary. As a result, only a single
channel is allowed for OC-3, OC-12, or OC-48 when the device is operated in the over-fiber modes. In contrast,
the device is capable of supporting four OC-3/OC-12 channels or one OC-8 channel in the SONET/SDH modes.

5-6680(F).cr.1

Figure 21. TDAT042G5 Over-Fiber Modes: SDL, ATM (X

)

PASSTHROUGH

I
NE I

ACE

OCK

LINE

TERMINATION

PATH

TERMINATION

PAYLOAD

TERMINATION

PACKET/CELL
PROCESSOR
-BIT SYNC
-DECAPSULATION
-UNSCRAMBLING

SINGLE OC-48
SINGLE OC-12
SINGLE OC-3

CONTROL

�

P INTERFACE

-CRC VERIFICATION

ENHANCED

UTOPIA I/O

PACKET/CELL
PROCESSOR
-ENCAPSULATION
-SCRAMBLING
-CRC GENERATION

PASSTHROUGH

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

Data Engine (DE) Block

(continued)

Transparent Payload Mode

The transparent payload mode in the payload termination data engine (DE) block is one of seven basic payload
type modes in the payload control registers and allows data to pass directly through the DE. In this mode, no fram-
ing is done on the data, and the data in the SONET frame is treated as raw data. The transparent payload mode
basically disables all the functions of the framers. In contrast, the transparent mode of the sequencer (over-fiber
mode) disables the conversion function of the sequencer between the SONET/SDH framing structure and the log-
ical channel structure.

In the transparent payload mode, the data engine processes the entire payload as a single packet with no J1 byte
or other POH. An RxSOP is generated on the UTOPIA interface on the first byte following the J1 byte. The last
byte of payload occurs at an RxEOP.

If the device is set in both the transparent payload mode in the payload control registers and the transparent mode
in the sequencer, then the whole SONET/SDH frame (overhead bytes will be overwritten with zeros) will appear at
the receive UTOPIA interface as one packet. At the transmit UTOPIA side, the whole SONET/SDH frame needs to
be supplied.

Transparent Receive Mode Control. In receiving from the line, provisioning must specify the time slot and
SONET frame byte location where the last byte in the packet will occur. The following registers are used to indicate
this location.

Rx_CHCD_FM (address 0x1030; see register description, page 224) specifies the time slot where the last byte
of a packet exists in channels C and D.

Rx_CHAB_FM (address 0x1031; see register description, page 224) specifies the time slot where the last byte
of a packet exists in channels A and B.

Rx_CELLA_FM (address 0x1032), Rx_CELLB_FM (address 0x1033), Rx_CELLC_FM (address 0x1034), and
Rx_CELLD_FM (address 0x1035) specify in which SONET location (0 to 809) the last byte in a packet exists in
channel A, B, C, or D, respectively. (See register descriptions, page 225.)

In the case where the location of the last byte in the frame is not known, the last byte should be provisioned for
location 809 and time slot 12, and external UTOPIA hardware must perform packet delineation on the data
stream.

Transparent Transmit Mode Control. In transmitting to the line, provisioning must specify the time slot and
SONET frame alignment. This is done through Tx_TRANS_CTRL (address 0x102F; see register description,
page 223) used in conjunction with Tx_TS[1--12] (addresses 0x1016--0x1021; see register descriptions,
page 215).

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

UTOPIA (UT) Interface Block

The UT core provides buffering and UTOPIA interface functionality. This enhanced UTOPIA interface will pass U2,
U2+, U3, and U3+ protocols. In the receive direction, data is buffered from the line side, and sent out of the device
via a UTOPIA/packet-over-SONET-PHY interface. In the transmit direction, data is received by the device via a
UTOPIA/packet-over-SONET-PHY interface, and buffered before being sent to the line side. Data that is sent or
received can be either packet or ATM traffic, and is configurable on a per-channel basis. The UTOPIA slave inter-
face is designed to accommodate back-to-back ATM cell and packet data transfers in point-to-point or multi-PHY
modes.

Level-2 physical interfaces (transmit and receive) support four logical data channels as shown in Figure 22. Each
of these interfaces is independently configurable for cell or packet transfers, and can support up to STS-12/STM-4
bandwidth. Optionally, two of the interfaces, specifically A and B, can be grouped together to support a 32-bit
UTOPIA level-3 interface supporting up to STS-48/STM-16 of bandwidth. The aggregate traffic that can be carried
over these interfaces is limited to STS-48/STM-16 bandwidth.

In addition to operating as separate point-to-point streams, MPHY capabilities for up to four channels can be pro-
vided from the A interface in either 16-bit or 32-bit modes. For example, when operating as a 32-bit interface, the A
interface can support either a single STS-48c channel or four STS-12c channels. As a 16-bit interface, the MPHY
interface can support either a single STS-12c channel or four STS-3c channels.

Since each channel can be configured independently, each one can carry different traffic types at different rates,
provided that the capabilities of the active interfaces and the data engine are not exceeded.

There are two basic data paths: receive side, defined to be data going from the line side to the UTOPIA side, and
transmit side, defined to be data going from the UTOPIA side to the line side as shown in Figure 22.

5-7056(F)r.5

Note: For MPHY support, channels are mapped to interface A only.

Figure 22. UT Block Diagram

EGRESS SIDE

INTERFACE A

INTERFACE B

INTERFACE C

INTERFACE D

INGRESS SIDE

INTERFACE D

INTERFACE C

INTERFACE B

INTERFACE A

SOFTWARE REGISTERS

UTOPIA 2/3 INTERFACE

NOTE: UTOPIA 32-bit MODE

COMBINES CHANNELS A & B

INTERNAL
CONTROL

BUS

I
NE

I
DE

IN BOTH DIRECTIONS (Tx & Rx)

LOOPBACKS

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

UTOPIA (UT) Interface Block

(continued)

Enhanced refers to the extensions that have been added to support packet transfers. These extensions are indica-
tions of the following: (1) an end of packet (TxEOP/RxEOP), (2) the byte on which packet ends in last word (TxSZ/
RxSZ), and (3) the signal to abort a packet early (TxERR/RxERR). An abort occurs, for example, if the check sum
at the end of a packet is bad, or the end of a packet is reached prematurely. If the receive FIFO overflows because
the master cannot process packet data fast enough, an RxERR will also be generated.

UTOPIA Loopbacks

TDAT042G5 can be placed in loopback on a channel-by-channel basis. When the TDAT042G5 is placed in far-end
loopback (FELB), data from the DE is sent to and processed by the UTOPIA interface. Instead of sending it to the
UTOPIA master, however, the data is sent to the corresponding egress channel and back to the line interface.

When the TDAT042G5 is placed in near-end loopback (NELB), data from the egress channel is transferred to the
corresponding ingress channel, instead of the DE. This data is then processed by the ingress channel and is
returned to the UTOPIA master.

UTOPIA Modes

Each UTOPIA interface mode is capable of supporting various types of traffic with different bandwidth capabilities
as summarized in Table 24. In a point-to-point operational mode, any interface can be configured independently in
any of the defined modes (e.g., channel A passes ATM cells using STS-12c, channel B passes packets, etc.).

It should be noted that the U3 or U3+ (32-bit mode) can only be supported by overloading channel A and B inter-
face pins. Only the control signals from channel A are used. The channel B size and data bits are combined with
the channel A size and data bits to form the 2-bit size and the 32-bit data words. When 32-bit mode is selected,
channels B, C, and D must be configured to be idle (so that channel B will be under the control of channel A in
32-bit mode).

Multichannel multi-PHY (MPHY) capabilities are only supported on interface A by grouping the internal FIFOs and
data paths of channels B, C, and D as needed. This operational mode is described in a later section.

Table 24. UTOPIA Traffic Types

* Maximum speed may be exceeded if nonstandard load conditions are used and the clock is sourced. See CLOCK_MODE_Rx [A--D]

(registers 0x020F, 0x0213, 0x0217, 0x021B), pages 158--159 for details.

UTOPIA Name

Interface

Width

Maximum

Speed

Aggregate

Bandwidth

Traffic Type

Maximum

Number of

Interfaces

16 bits

52 MHz*

622 Mbits/s (STS-12)

ATM cells only

U2+

16 bits

52 MHz*

622 Mbits/s (STS-12)

ATM cells/packets

U3, 8-bit mode

8 bits

104 MHz

622 Mbits/s (STS-12)

ATM cells only

U3+, 8-bit mode

8 bits

104 MHz

622 Mbits/s (STS-12)

ATM cells/packets

U3, 32-bit mode

32 bits

104 MHz

2.5 Gbits/s (STS-48)

ATM cells only

U3+, 32-bit mode

32 bits

104 MHz

2.5 Gbits/s (STS-48)

ATM cells/packets

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

UTOPIA (UT) Interface Block

(continued)

UTOPIA ATM Cell Processing

The UTOPIA block will process ATM packets of 52, 53, 54, or 56 bytes. The standard 53-byte ATM cell structure is
shown in Table 25.

Table 25. Standard 53-byte ATM Cell Structure

In the receive path, TDAT042G5 automatically calculates the HEC (byte 5) and overwrites this byte of the ATM cell.
It is therefore possible to transfer only 52-byte packets through the UTOPIA I/O to increase interface efficiency.
This mode will be referred to as the 52-byte mode. The 52-byte or 53-byte ATM mode is provisioned through
ATM_SIZE_Rx[A--D] (bit 4 of registers 0x020F, 0x0213, 0x0217, and 0x021B) and ATM_SIZE_Tx[A--D]

(

bit 4 of

registers 0x0210, 0x0214, 0x0218, and 0x021C).

U2 Modes. For U2 and U2+, both the 52-byte and 53-byte, 16-bit UTOPIA interface modes are supported for ATM
cells as shown in Table 26.

Table 26. Bus Format for 16-bit Interface

* UDF refers to the undefined H5 byte.
This option is also called the 54-byte mode.

H5 (HEC)

. . .

D48

8 bits

53 bytes

53-byte Option

52-byte Option (HEC Omitted)

TxD[15:8] or RxD[15:8]

TxD[7:0] or RxD[7:0]

TxD[15:8] or RxD[15:8]

TxD[7:0] or RxD[7:0]

H1 H2

H3 H4

H5 (HEC)

H5 (UDF*)

D3 D4

.
.
.

D47

D48

D47

D48

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

UTOPIA (UT) Interface Block

(continued)

UTOPIA ATM Cell Processing (continued)

U3 Modes. For U3 and U3+, both the 52-byte and 53-byte, and either 8-bit or 32-bit modes are supported for ATM
cells as shown below.

For the case of an 8-bit UTOPIA interface, data is placed on the UTOPIA port as shown in Table 27.

Table 27. Bus Format for 8-bit Interface

For the case of a 32-bit UTOPIA interface, parallel data is placed on the UTOPIA port as shown in Table 28.

Table 28. Bus Format for 32-bit Interface

* UDF refers to undefined H5 bytes.
This option is also called the 56-byte mode.

53-byte Option

52-byte Option (HEC Omitted)

TxD[15:8] or RxD[15:8]

TxD[7:0] or RxD[7:0]

TxD[15:8] or RxD[15:8]

TxD[7:0] or RxD[7:0]

Not used

H3 Not

used

H3 Not

used

Not used

H5 (HEC)

Not used

.
.
.

D48

Not used

D48

Not used

53-byte Option

52-byte Option (HEC Omitted)

TxD[31:24]

RxD[31:24]

TxD[23:16]

RxD[23:16]

TxD[15:8]

RxD[15:8]

TxD[7:0]

RxD[7:0]

TxD[31:24]

RxD[31:24]

TxD[23:16]

RxD[23:16]

TxD[15:8]

RxD[15:8]

TxD[7:0]

RxD[7:0]

H3 H4

H5 (HEC)

H5-UDF1

H5-UDF2

H5-UDF3

D7 D8

.
.
.

D45

D46

D47

D48

D45

D46

D47

D48

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

UTOPIA (UT) Interface Block

(continued)

UT Clocking

TDAT042G5 is compliant with the U2 standard

and several versions of the proposed U3 specification

2--6

as a UT

slave device. The U2 standard and proposed U3 specifications define the slave device transmit path (egress) clock
as an input clock. For the U2 case, the slave transmit path clock is generated by the UT master device. For the cur-
rent version of the U3 specification

, the transmit path clock for both slave and master devices is generated by the

same external clock source

. The U2 standard and current U3 proposed specification

define the slave device

receive path (ingress) clock as an input clock. In the U2 case, the slave device receive path (ingress) clock is gen-
erated by the UT master device. In the U3 case, the receive clock for both the master and slave devices is gener-
ated by same external clock source. Previous proposed versions of the U3 specification provided for the case
where the receive path clock could be generated by the slave device. TDAT042G5 can be provisioned in the con-
figuration where it sources the receive path (ingress) clock.

The timing specification for the UT clock is given in the UTOPIA Interface Timing section, pages 268--270.

UT Transmit Path (Egress) Clock

In all UTOPIA modes, the transmit path clock must be provided to TxCLK[D:A] pins as described in Table 5, page
page 31.

UT Receive Path (Ingress) Clock

The receive path clock RxCLK[D:A] pins can be provisioned to be either clock inputs or outputs as described in
Table 5, page 38. Provisioning as either an input or output is done on a per-channel basis through registers
0x020F, 0x0213, 0x0217, and 0x021B (CLOCK_MODE_Rx). In the U2 mode, RxCLK is always provisioned to be
an input. To meet the latest proposed U3 specification, RxCLK is provisioned as an input. To meet special UT
requirements, RxCLK may be provisioned to be a clock output signal. When provisioned as a clock output, the
RxCLK[D:A] is derived from the corresponding TxCLK[D:A] input.

For RxCLK rates greater than 52 MHz, RxCLK must be provisioned to be an output.

1. UTOPIA Level 2, Version 1.0, AF-PHY-0039.000, June 1995.
2. UTOPIA Level 3 Baseline Text, UL3-01.04, February 1999.
3. UTOPIA Level 3 Living List, UL3-01.04, February 1999.
4. UTOPIA Level 3 Living List, LTD-PHY-UL3-01.05, April 1999.
5. UTOPIA Level 3, STR-PHY-UL3-01.00, July 1999.
6.UTOPIA Level 3, AF-PHY-136.00, October 1999.
7.Previous proposed versions of the U3 specification were similar to the U2 standard where the slave device transmit clock was gen erated by

the UT master device.

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

UTOPIA (UT) Interface Block

(continued)

UT Receive Input Path (Ingress)

The UTOPIA Rx interface is designed to accommodate ATM cells as well as packet traffic. While the standard
UTOPIA interface transmits and receives ATM cells, this interface has been enhanced to carry non-ATM traffic.
The interfaces supported include the following: UTOPIA Level 2 (U2), enhanced UTOPIA Level 2 (U2+), UTOPIA
Level 3 (U3) in 8-bit mode or 32-bit mode, and enhanced UTOPIA Level 3 (U3+) in 8-bit mode or 32-bit mode.

In the receive direction, data arrives and is sent to one of four channels (A through D). Each channel buffers data
independently and, when sufficient data has been stored in its FIFO, sends the data out of the channel via its UTO-
PIA interface. There are four paths inside the UT core, corresponding to one path per channel. These paths are
labeled A to D. When using 32-bit modes, only the control signals of interface A and size signals of interfaces A
and B are used.

Note: 32-bit mode is supported using channels A and B only. When 32-bit mode is selected, channels B, C, and D

must be configured to be idle (channel B will be under the control of channel A in 32-bit mode).

In normal mode, data arrives into the ingress channel, and control and data information are written into the FIFO.
The data is extracted from the FIFO, and word-aligned on the first byte of data. After word alignment, the data is
sent out of the device via the UTOPIA interface.

Note: The start of packets must be word-aligned, and there can only be one packet per word (required by the defi-

nition of the UTOPIA interface).

FIFO. The 256-byte UTOPIA Rx FIFO is responsible for buffering data from the DE block to be sent to the UTOPIA
interface. The FIFO accommodates four ATM cells or 256 bytes of packet data. In STS-48/STM-16, only one
256-byte FIFO is used. The FIFO is required to manage the asynchronous nature of the UTOPIA interface. Over-
flow will only occur if the master device connected to the UTOPIA interface is having congestion problems. When
overflow occurs and head of line discard is performed, it is possible that part of one packet may be appended to
another (if, for example, an end of packet is discarded along with the data at the head of the FIFO). Because this is
not a desirable operation, it is necessary to discard until the start of the next packet is observed. Data is read from
the FIFO when there is sufficient data in the FIFO. Upon overflow, the RxERR and RxEOP signals are asserted to
indicate to the master the corruption of the current packet.

Sufficient data is defined to be a minimum amount of data in the FIFO (a programmable threshold, low watermark),
or at least one end of packet stored in the FIFO. If the FIFO overflows, the block is responsible for discarding data
until the next start of packet. When this occurs, an alarm is raised. Underflow in the receive direction can occur
when there is no data, or if only part of a packet has arrived and has been transmitted, and is normal behavior.

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

UTOPIA (UT) Interface Block

(continued)

UT Receive Input Path (Ingress) (continued)

Receive Cell/Packet Available (RxPA). This signal indicates when the TDAT042G5 receive FIFO can send data
to the master device. The RxPA[D:A] signal behavior depends on the provisioned low watermark in the UTOPIA
interface.

One-Cycle Delay Mode. This mode follows the UTOPIA Level 2 Standard. The RxPA response occurs one cycle
after the address is polled. RxENB is asserted to activate the selected PHY. RxDATA and RxSOP are output one
cycle after RxENB is sampled active by the PHY device.

Two-Cycle Delay Mode. This mode follows the UTOPIA Level 3 baselined text*. The RxPA response occurs two
cycles after the address is polled. RxENB is asserted to activate the selected PHY. RxDATA and RxSOP are out-
put two cycles after RxENB is sampled active by the PHY device.

RxPA[D:A] Assertion. RxPA[D:A] goes high (is asserted) when the amount of data in the receive FIFO has
reached or exceeded the low watermark or there is end of packet (EOP) resident in the FIFO.

RxPA[D:A] Deassertion. In ATM mode, the RxPA[D:A] signal goes low (is deasserted) when the FIFO has less
than the low threshold amount of data and there is no EOP inside the FIFO (i.e., part of an ATM cell). Once the
last byte of the current cell is transmitted, and if the amount of data within the FIFO is still less than the low
threshold, RxPA[D:A] is deasserted.

In packet mode, the RxPA[D:A] signal goes low (is deasserted) when the FIFO has less than the low threshold
amount of data and there is no EOP inside the FIFO.

Once the data transfer begins (since the amount of data has reached or exceeded the low watermark), and if
there is no EOP below the low threshold (i.e., a long packet), the RxPA signal is deasserted when the FIFO is
drained by the UTOPIA master device. In this case, the master must closely monitor the RxPA[D:A] signals and
use these signals as data valid indicators to ensure that bad data is not read from the TDAT042G5. TDAT042G5
will deassert the RxPA[D:A] signal immediately when the FIFO is drained.

Data Transfer. A TDAT042G5 ingress channel sends data when it has asserted RxPA[D:A] and the master
device requests data (via RxENB[D:A]). In ATM mode, if the master device requests data using RxENB[D:A] and
if the TDAT042G5 has less than the low watermark amount of data to send and there is no end of cell in the FIFO
(RxPA[D:A] is deasserted), then the TDAT042G5 UTOPIA interface will send out data that should be ignored by
the master, i.e., it does not send data from its internal FIFO.

In ATM mode, once an ATM cell transfer starts, the Tx or Rx side must complete the transfer. If the transfer is not
completed, then the cell will be corrupted. The transfer continues until either (1) the end of cell is reached, when
the end of cell exists below the low watermark, or (2) the end of the FIFO is reached. If the end of the FIFO is
reached, no underflow is flagged on the receive side. In ATM mode, the low watermark should be set so that at
least one entire cell is in the FIFO prior to asserting RxPA[D:A].

In packet mode, once the data transfer begins, the RxPA[D:A] signal will remain asserted until the FIFO is
drained if there is no EOP below the low watermark. During the time RxPA[D:A] is asserted, valid data is being
transferred.

RxPA[D:A] is updated on the rising edge of RxCLK[D:A].

In 32-bit mode, only the RxPA[A] pin of port A is used to indicate the packet/cell available status.

MPHY Support. When the RxPA signals are used for MPHY direct status, the corresponding
RxCLK[B, C, and/or D] must be provided. This clock will be the same as RxCLK[A].

* ATM Forum Technical Committee, UTOPIA Level 3, STR-PHY-UL3-01.00, July 1999.

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

UTOPIA (UT) Interface Block

(continued)

UT Receive Input Path (Ingress) (continued)

Figure 23 illustrates the receive-side interface handshaking when operating in point-to-point mode with the RxPA
response provisioned to be a single cycle. In two-cycle mode, the RxSOP, RxDATA, and RxPA signals are
delayed an additional cycle. In the figure, the master device initiates the transfer after observing an asserted
packet available for the channel. The TDAT042G5 samples RxENB low on the first cycle and then asserts
RxSOP/C and RxDATA on the second cycle. RxDATA is sampled on the rising edge of the second cycle by the
master device. Figure 24 illustrates receive-side interface handshaking when operating in two-cycle mode. When
operating in U3+ mode, two-cycle mode must be used.

In this example, the master stops transfer in the middle of the packet. Data with value c is valid on the cycle that
RxENB goes inactive, and when RxENB returns, data is again valid on the first cycle after the slave observes an
active RxENB (data value d).

The packet transfer is complete when the slave asserts the RxEOP signal. If an error occurs in the packet, then the
RxERR signal is asserted simultaneously with the RxEOP. RxERR is ignored if it is not asserted when RxEOP is
active.

5-7450(F).ar.2

Figure 23. Receive-Side Interface Handshaking in Point-to-Point, Single Cycle Mode

RxCLK

RxPA

RxENB

RxSOP/C

RxDATA[15:0]

RxEOP

RxERR

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

UTOPIA (UT) Interface Block

(continued)

UT Transmit Input Path (Egress)

In the transmit direction, data arrives from the various UTOPIA interfaces, and is stored in a 256-byte FIFO, one
per channel. After sufficient data has been stored into the FIFO, it is made available to be sent to the DE.

Like the UTOPIA Rx interface, the UTOPIA Tx interface is designed to accommodate ATM cells as well as packet
traffic. While the traditional UTOPIA interface only transfers ATM cells, this interface has been enhanced to carry
packet traffic. The interfaces supported include the following: UTOPIA Level 2 (U2), enhanced UTOPIA Level 2
(U2+), UTOPIA Level 3 (U3) in 4 x 8-bit mode or 32-bit mode, and enhanced UTOPIA Level 3 (U3+) in 4 x 8-bit
mode or 32-bit mode.

The UTOPIA Tx side can indicate to the ATM side to suspend the transfer, by deasserting TxPA, when necessary.
When the amount of data in the FIFO exceeds its programmable high watermark, it deasserts TxPA. This signal
causes the deassertion of TxPA on the next clock. At this point, the ATM side knows that the UTOPIA Tx block can
only accept a limited number of words, after which it will overflow. In this case, the ATM device must not exceed
writing this limited number of words before suspending the transfer. Transfer is resumed once again when the
FIFO falls below the high watermark. When transferring ATM cells, TxPA must be deasserted four clocks before
the end of cell, or else it must be prepared to accept an entire new cell. When transferring ATM cells, deasserting
TxPA does not immediately suspend the transfer of the current cell because the entire cell can be transmitted with-
out interruption.

Transmit Cell/Packet Available (TxPA). This signal indicates when the TDAT042G5 transmit FIFO can accept
data from the master device. If the FIFO is empty or more than the provisioned space is available in the FIFO,
TxPA[D:A] is set active.

One-Cycle Delay Mode. This mode follows the UTOPIA Level 2 Standard. The TxPA response occurs one cycle
after the address is polled.

Two-Cycle Delay Mode. This mode follows the UTOPIA Level 3 baselined text*. The TxPA response occurs two
cycles after the address is polled.

TxPA[D:A] Assertion. The TxPA[D:A] signal behavior relies on the UTOPIA provisionable watermarks. In
packet mode, TxPA[D:A] goes high when the amount of data in the FIFO is less than the high watermark setting.
In ATM mode, TxPA[D:A] goes high when the FIFO has space to receive a complete ATM cell from the master.
(This requires the high threshold to be set appropriately by the user, i.e., set so that an entire cell can be
received once TxPA[D:A] goes active.)

TxPA[D:A] Deassertion. In packet mode, TxPA[D:A] goes low when the amount of data in the FIFO reaches or
exceeds the high watermark. In ATM mode, TxPA[D:A] goes low when there is not enough space in the FIFO to
receive an entire ATM cell. (This requires the threshold values to be provisioned properly, i.e., set low enough
such that when the high watermark is reached, the transmission of the current cell can be completed without
overflowing the FIFO). In ATM mode, TxPA[D:A] will be deasserted four cycles before the end of the current cell
transfer if the FIFO cannot accept a complete ATM cell on the following transmission.

TxPA[D:A] is updated on the rising edge of TxCLK[D:A].

In 32-bit mode, only the TxPA[A] pin of port A is used to indicate the packet/cell available status.

MPHY Support. When the TxPA signals are used for multi-PHY (MPHY) direct status, the corresponding
TxCLK[B, C, and/or D] must be provided. This clock will be the same as TxCLK[A].

* ATM Forum Technical Committee, UTOPIA Level 3, STR-PHY-UL3-01.00, July 1999.

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

UTOPIA (UT) Interface Block

(continued)

UT Transmit Input Path (Egress) (continued)

FIFO. The UTOPIA Tx FIFO is used to create an elastic store that can buffer bursts of data received via the UTO-
PIA Tx, faster than can be transmitted out of the path. After the FIFO exceeds a programmable watermark, it indi-
cates to the UTOPIA Tx master to stop sending data. The master can choose to ignore this request causing the
risk of an overflow. The FIFO block buffers 256 bytes of cell/packet data. The FIFO accommodates four ATM cells
or 256 bytes of packet data. The FIFO is required to manage the asynchronous nature of the UTOPIA interface.

Optionally, in the case of FIFO underflow, a 0x7D207D207D20 . . . will be inserted by the data engine into the mid-
dle of the packet if dry mode is provisioned and the default dry escape sequence is used (0x7D20, where the last
two bytes (the 20 bytes of the default value of 0x7D20) are provisionable). This will be removed at the far end by
the device (provided the link is comprised of two devices and both sides of the link support dry mode).

FIFO Watermark Threshold. When carrying ATM cell traffic, this threshold, while measured in words, should be
set at least one cell's length from end of FIFO. The UTOPIA Tx interface, by definition, must be able to accept an
entire ATM cell after the current ATM cell, unless TxPA is deasserted at least four clock cycles before the end of
the current cell transfer.

When carrying packet traffic, however, the threshold can be set higher, as the UTOPIA Tx interface only needs
to accept a limited number of words after deasserting TxPA. The number of words is a programmable value for
the sender, and should be assumed to be at least 2 words for the purposes of setting the threshold.

FIFO high watermark threshold, EGRESS_WATERMARK_HIGH_[A--D][6:0] (addresses 0x0212, 0x0216,
0x021A, 0x021E), should be set as follows.

Table 29. Egress High Watermark Thresholds

Note: The high watermark threshold should be set less than the values in the above table assuming there is no

delay between TxPA deassertion and TxENB deassertion. Then the threshold values may be changed to
optimize UT egress performance and to avoid FIFO overflow.

UTOPIA Mode

Maximum Threshold Value

8-bit, U3+

0x3D

16-bit, U2+

0x3B

32-bit, U3+

0x37

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

UTOPIA (UT) Interface Block

(continued)

Multi-PHY Support

In addition to point-to-point UTOPIA mode, the TDAT042G5, as the slave device, can also be configured to support
the polled multi-PHY mode. To operate in multi-PHY mode, channel A must be configured in the polling mode,
since the control signals of channel A are used for all channels. Any combination of B, C, or D can be included in
the polling group, in which case they provide control information to channel A. Channels B, C, and D also can be
configured in any of the UTOPIA modes. In this case, the output is transferred through the channel A interface
(channel A and B interfaces for 32-bit mode). Channels not configured for polling can be operated as point-to-point
connections. If channel A is in 32-bit polling mode, channel B cannot be in point-to- point mode since its interface is
controlled by channel A, while channels C and D may be provisioned as point-to-point connections.

Figure 26 shows a multi-PHY mode when all four channels of the UT are in polling mode.

5-7349(F)r.2

Figure 26. Multi-PHY Configuration of All Four Channels

Mixed mode polling is also possible. For example, for those channels operated in polling mode, it is legitimate for
some of the channels to be in packet mode while others are in ATM mode. However, if one or more of the channels
are in packet mode, channel A should be configured as packet mode to activate control signals for packet transfer.

Multi-PHY operation can be configured by asserting the polling mode enable bit and Tx/Rx address in the respec-
tive port provisioning registers (see port provisioning registers, pages 158--161). Microprocessor provisionable
registers in each channel include a polling mode enable bit and 5-bit Rx address or 5-bit Tx address. The value for
the Tx and Rx address of an MPHY channel must be identical. Both the Rx and Tx directions have a 5-pin address
input to poll and select the appropriate PHY.

INGRESS CHANNEL A

UTOPIA _PHY_Rx

UTOPIA _PHY_Tx

�

RxPA[A]/RxDATA[A]

RxENB[A]/RxADDR

RxPA[B]

RxPA[C]

RxPA[D]

TxPA[A]

TxENB[A]/TxDATA[A]/TxADDR

TxPA[B]

TxPA[C]

TxPA[D]

INGRESS CHANNEL B

INGRESS CHANNEL C

INGRESS CHANNEL D

EGRESS CHANNEL A

EGRESS CHANNEL B

EGRESS CHANNEL C

EGRESS CHANNEL D

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

UTOPIA (UT) Interface Block

(continued)

Multi-PHY Support (continued)

In 8-bit or 16-bit multi-PHY mode, only the data bus and the control signals (except the RxPA or TxPA signal) of
channel A are active for the polled group. RxPA[A] indicates the packet/cell availability of the selected or polled
channel. Similarly, TxPA[A] indicates transmit FIFO availability for a selected or polled channel. The remaining
RxPA/TxPA signals for the polled channels are activated and indicate instantaneous or direct status of the particu-
lar channel. In 32-bit multi-PHY mode, the data bus and size control signals of channel B are also active.

TDAT042G5 does not provide a selected packet available (SPA) signal to monitor the status of the current channel
sending/receiving data to or from the master. To prevent the FIFOs from running dry or overflowing in the middle of
a packet transfer, the user must design the UT TDAT042G5 slave-to-master interface with direct status mode
rather than address polling. The direct status of each channel is provided on the associated SPA pin for that chan-
nel. In this mode, the user must guarantee that when channels are switched to receive data from a channel other
than channel A, they immediately reapply the address of channel A to the address bus after the new channel is
selected. The user then gets the direct status SPA signal from channel A. Channels B, C, and D are always directly
sent out of the TDAT042G5. In either receive or transmit, when direct status is used in addition to the direct status
pin for a given interface, its corresponding interface clock pin must be driven by the clock of the A interface.

During the cycle when the selected channel is being changed, the address of the new channel is placed on the
address bus. The user must ignore the RxPA response of the initial channel during the expected response time
(one or two cycles later, depending on the PA response bit when the address of the newly selected channel was
applied).

Figure 27 illustrates the transmit interface timing for the case when the direct status of packet available of channels
A, B, C, and D is present. In this example, channels A and C indicate they can receive data. When the SPA signal
for C is observed, a channel switch is performed by the master by deasserting TxENB and placing the address of
channel C on the address bus. On the following cycle, data is placed on the bus along with the start of packet. In
this example, the TxPA response is configured for two cycles so that the PA response of address 02 results in the
PA of channel C to appear on channel A's output two clock cycles later. Subsequent data sent to the slave will go
to channel C (i.e., data values I, J, etc.).

When the RxPA signals are used for multi-PHY (MPHY) direct status, the corresponding RxCLK[B, C, and/or D]
must be provided. They may be provided via an external UT master, or they may be sourced from the correspond-
ing TxCLK[D:A] pin by using the UT clock source mode (see UT Clocking, page 88).

Agere Systems Inc.

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

UTOPIA (UT) Interface Block

(continued)

Multi-PHY Support (continued)

The ATM side sends one RxENB (TxENB) signal to channel A for the grouped channels to select a channel which
has ATM cells/packets (or room) available. An MPHY channel is selected using the following procedures.

1.The ATM layer polls the RxPA[D:A] (TxPA[D:A]) status of a channel by placing its address on the RxADDR[4:0]

(TxADDR[4:0]) lines.

2.In the following cycle, the MPHY channel gives its status by driving RxPA[D:A] (TxPA[D:A]) of channel A.

3.The ATM side selects the MPHY channel by placing the desired MPHY address on the address bus

RxADDR[4:0] (TxADDR[4:0]) during this cycle; RxENB[D:A] (TxENB[D:A]) is deasserted.

4.During the next cycle, the ATM side asserts RxENB[D:A] (TxENB[D:A]), and the selection of an MPHY channel is

made.

Only one MPHY channel at a time is selected for a cell/packet transfer when ATM drives RxENB (TxENB) for
channel A from high to low. However, another MPHY channel can be polled for its RxPA (TxPA) status while the
selected channel transfers data.

Figure 28 shows an example of the single-cycle RxPA response of each channel. In this figure, channels A, B, C,
and D have Rx addresses 00, 01, 02, and 03, respectively. RxPA[A] shows the packet availability of all four chan-
nels. Channels A and C have available packets to send, and channels B and D do not have packets to send. By
driving RxENB[A] low at clock edge 1, the ATM side selects channel A, and packet transfer is started at
clock edge 2. The master samples this data at clock edge 3. At clock edge 4, RxPA[C] shows that channel C also
has a packet to send, and this is reflected to RxPA[A] at clock edge 5. RxPA[B] and RxPA[D] show the direct status
of channels B and D, indicating that they do not have packets to send.

5-7348(F)r.2

Figure 28. RxPA Responses of a Multi-PHY for All Four Channels

(PA Response Configured for One Cycle)

P1P2

P17P18

P3P4

P5P6

P7P8

P9P10

P11P12

P13P14

P15P16

CLK[A]

ADDR

DATA[A]

SOP/C[A]

EOP[A]

SZ[A]

ENB[A]

PA[C]

PA[B]

PA[A]

PA[D]

HIGH Z

100

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Functional Description

(continued)

JTAG (Boundary-Scan) Test Block

The JTAG test block provides an IEEE 1149.1 JTAG controller interface for memory BIST, boundary scan, and
32-bit ID register instructions. Details about JTAG (boundary-scan) functionality and interface timing specifications
can be found in MN98-060ASIC-02, HL250C 3.3 Volt 0.25

�

m CMOS Standard-Cell Library Manual, page 8-1

through page 8-31.

The instruction register length is 3 bits.

Reset of JTAG Logic

There are two events that will reset the JTAG logic:

Pulse or pull the TRST pin signal low with no TCK pin signal present. TRST is pulled high on-chip.

The TMS pin signal is driven high for five cycles of TCK. TMS is pulled high on-chip.

TRST can be held high during normal device operation only if TRST is pulled low upon powerup.

Line Interface

LVPECL I/O Termination and Load Specifications

The LVPECL buffers are compatible with the temperature independent ECL 100K levels, but the output levels that
are guaranteed are relaxed 30 mV from the actual 100K levels allowing for noise and variations in the power sup-
ply and process.

All LVPECL output buffers require a terminating resistor. These terminating resistors, which must also be con-
nected to both LVPECLREFHI and LVPECLREFLO, go to a common terminating voltage. All of the terminating
resistors used with a chip must be identical precision (1%) resistors. The value of these terminating resistors is
usually chosen to match the characteristic impedance of the board. To save on power, a terminating voltage equal
to V

DDD

� 2 V is available in most ECL systems. The minimum value of the terminating resistor that can be used on

these bufers is 50

. This is also the standard termination used in most ECL systems. Larger values of resistance

will save power, but will also slow down the high-to-low transition of the output, since it is RC limited.

if no V

DDD

� 2 V supply is available, a larger value resistor may be connected directly to GND. It should be chosen

such that the current through it does not exceed the current through a 50

resistor to V

DDD

� 2 V (21 mA in the

high state). This large resistor will most likely be a poor match to the board impedance. The match can be
improved by the user of a Thevenin equivalent resistor pair. Such a Thevenin equivalent resistor will burn much
more system power (but not on-chip power) than would a single resistor, but it does allow for impedance matching
in the absence of aV

DDD

� 2 V supply. Termination resistor options are shown in Table 30.

Experienced ECL designers sometimes use the (bipolar) ECL output buffers in a tied-OR configuration. Unfortu-
nately, this cannot be done with these LVPECL buffers.

Table 30. Nominal dc Power for Suggested Terminations

Note: The value is the average of the high and low states in LVPECL output buffer and external terminating resis-

tors, for a single-ended output. The values double for double-ended outputs.

Terminating Resistor and Voltage

Output Transistor (on-chip)

Power (mW)

Terminating Resistor (off-chip)

Power (mW)

to V

DDD

� 2 V

Standard ECL termination (parallel).

125

to V

DDD

and 83

to GND

Thevenin equivalent or 50

to V

DDD

� 2 V.

Agere Systems Inc.

101

Data Sheet
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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Line Interface

(continued)

LVPECL I/O Termination and Load Specifications

(continued)

The input common mode range for LVPECL differential buffers is from 1 V to 2.75 V; and the swing needs to be at
least 300 mV. So basically what it means is the lowest voltage on the input should be no lower than (1 V � 0.150 V)
and the highest voltage on the input shouldn't be more than (2.75 V + 0.150 V). So if the differential swing is
800 mV, then the common mode range would be 2.5 V down to 1.25 V. This is all for 3 V buffers.

Interface Description

Microprocessor Interface

This device is equipped with a generic 16-bit microprocessor interface that allows operation with most commer-
cially available microprocessors. Input MPMODE is used to configure this interface into one of two possible modes
(synchronous or asynchronous). In synchronous mode, the microprocessor interface can operate at speeds from
1 MHz up to 66 MHz.* In asynchronous mode, the internal 78 MHz system clock is used to operate this interface.

Table 31. MPU Modes

The host interface is designed to connect directly to a commonly used asynchronous or synchronous host bus.
The interface to this block includes a separate clock, MPCLK, which is used in the synchronous interface mode.
The interface is only a slave on the host bus. There is no posting of writes in the host interface; all registers are
directly accessible. The microprocessor interface pins use 3.3 V (5 V, TTL-tolerant) CMOS I/O levels. The micro-
processor interface timing specifications are given in the Interface Timing Specifications section (see Table 163--
Table 166, pages 257--263).

* All status counters must be read within the 1-second time window of the PMRST. If this is not the case, counter values will be l ost.

MPMODE

Mode

Microprocessor Interface Signals

Async

CS, INT, D[15:0], A[15:0], ADS, R/W, DS, DT

Sync

MPCLK, CS, INT, D[15:0], A[15:0], ADS, R/W, DT

102

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Interface Description

(continued)

General-Purpose I/O Bus (GPIO)

GPIO[3:0] are bidirectional pins. They can be configured individually as input or output by writing to the GPIO mode
and GPIO output configuration registers (addresses 0x0013, 0x0014, 0015; see register descriptions, page 152).
The value to be output is written into the GPIO output register (address 0x000F; see register descriptions,
page 150). To use the GPIO pins as outputs, set the GPIO output configuration bits (bits 8 and 0) to 1, and set the
GPIO mode bits GPIO[3:0]_DIRECTION_ I/O (address 0x0013, bits [3:0]) to 1.

The input value is read from the GPIO input register (address 0x000A; see register description, page148). GPIO
pins can also be used to generate an interrupt upon a change in value. An interrupt can be generated on either the
input level or edge, depending on the GPIO mode register. Figure 29 shows how the GPIO functions.

5-7058(F)r.6

Figure 29. GPIO Functionality

If a GPIO pin is an input, the logic value on the pin can be read from a software register. The GPIO pin can also be
programmed to generate a level-sensitive interrupt or a positive edge-triggered interrupt contributing to the external
interrupt pin.

If a GPIO pin is an output, the value provisioned will appear on the device pin immediately.

0000

DEVICE VERSION

0001

0002

0003

DEVICE NAME =

0004

0005

0008

COMPOSITE INTERRUPTS

000A

GPIO INPUTS

000C BLOCK INTERRUPT MASKS

000E

CORE RESETS

000F

GPIO OUTPUTS

0010

LINE PROVISIONING

0011

CHANNEL CONTROL

0012

LOOPBACK CONTROL

0013

GPIO MODE

001F

SCRATCH

3 2 1 0

2 1 0

3 2 1 0

INTERRUPTS

GPIO INPUTS

GPIO OUTPUTS

GPIO MODE

POS.

EDGE

DET.

GPIO[3:0]

ACTIVE

LEVEL EDGE

DIRECTION

TDAT042G5

CORE REGISTERS

104

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Interface Description

(continued)

Reset

If the reset pin RST (C7) is forced low, the software registers will be placed in their default powerup state. The
device will lose its previous state, and data path continuity will be lost. An internal 100 k

pull-up and a Schmitt-

trigger input is provided for this pin. Reset can be generated from software by writing 0x0005 to the core resets reg-
ister (0x000E; see register description on page 149 and timing on page 263).

Performance Monitor Reset (PMRST)

A 1 Hz clock (PMRST) is provided to all internal macrocells. This clock is used to control the 1-second binning of
coding violations (CVs) and alarms. The source of this clock is selectable from one of the three following sources:

The PMRST pin (D7)

A software controllable register (0x000E; see register description on page 149)

An internal 1-second counter (sourced from the 77.76 MHz transmit clock).

This is configured by the line provisioning register (address 0x0010). When under software control, writing 0x0080
to core resets register (address 0x000E) will generate a PMRSTX pulse.

5-7060(F)r.4

Figure 31. Miscellaneous Functionality

R R R

12 12 12

L B

INTERRUPTS

CORE RESETS

LINE PROVISIONING

LINE EQ./UNEQ.

LOOPBACKS

RST

DELTA

POS.

EDGE

DET.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

P M S

ARST

PMRST

1 SEC.

COUNT

[
1

]

[
11:

0000

DEVICE VERSION

0001

0002

0003

DEVICE NAME =

0004

0005

0008 COMPOSITE INTERRUPTS

000A

GPIO INPUTS

000C BLOCK INTERRUPT MASKS

000E

CORE RESETS

000F

GPIO OUTPUTS

0010

LINE PROVISIONING

0011

CHANNEL CONTROL

0012

LOOPBACK CONTROL

0013

GPIO MODE

001F

SCRATCH

TDAT042G5

CORE REGISTERS

PMRST I/O CONTROL

106

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Interface Description

(continued)

Loopback Operation

Figure 32 illustrates the different types of loopback provided in the device. Loopback is controlled by core register
0x0012, loopback control (see register description on page 151).

5-7061(F)r.4

Figure 32. Loopback Operation

In the following description, only the data path from Terminal A to B is discussed, but the same terms apply to the
reverse direction.

Near-End Loopback

The packet/cell payload is looped back to the data source (Layer 2 device) as soon as it crosses the Layer 1 to
Layer 2 boundary (UTOPIA block).

Far-End Loopback

The packet/cell payload is looped back to the facility (optical) data source as soon as it enters the UTOPIA block of
Terminal B. The data does not enter the Layer 2 device. The total delay from receive data input to transmit data
output in far-end loopback (FELB) mode is approximately 2

�

Terminal Loopback

The SONET/SDH signal is looped back at the terminal (line interface) block, and is returned to the Layer 2 device.
For terminal loopback of UTOPIA ports B, C, or D to function, UTOPIA port A must be provisioned for terminal loop-
back. This is because only the Tx clock from port A is used in terminal loopback mode.

Facility Loopback

The facility (optical) data signal is looped back to the facility as soon as it enters the Terminal B line interface block.
SONET facility loopback is only available in STS-3/STM-1 and STS-12/STM-4 modes.

LAY

R 2

OHP

CONT

I
C

TERMINAL B

LAY

R 2

OHP

CONT

TERMINAL A

URC

FAR

END

SINK

FACILITY

TERMINAL

NEAR

END

FACILITY
(OPTICS)

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Data Sheet
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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Access Description

Register address space is defined by the 16-bit address word of ADDR[15:0] (see Table 6, page 41). Bits 15
through 13 must be 0. Bits 12 through 9 map to the major functional blocks as shown in Table 35. The usable
address space is also shown in Table 35.

Table 36--Table 40 are the register maps. Details of the register functions are given in the following register
description tables. Note that the usable register address space is not contiguous. Register addresses not specifi-
cally identified in the following tables are reserved and must not be addressed, i.e., written or read. Registers and
bits that are reserved must not be written or must be written to the indicated default value. In Table 36--Table 40,
the registers may be read only (RO), read/write (R/W), write only (WO), or clear-on-read or clear-on-write
(COR/W).

The core registers must be written prior to provisioning any other registers (1) to establish the internal clock rates
for the device, and (2) because writing to certain core registers resets the remainder of the device. Certain clocks
must be present to read/write registers prior to provisioning the device.

One of the following clocks must be present prior to provisioning to enable register access.

TxCKP and TxCKN

MPU clock (microprocessor interface synchronous mode only)

Provisioning must be implemented in the following sequence.

Core register 0x0010 (mode) must be provisioned first

Core register 0x0011 (channel [A--D] control) second

Remainder of the core registers must then be provisioned (order does not matter)

It is recommended, but not required, that the remainder of the device be provisioned in the following order.

OHP, PT, and DE blocks (order does not matter)

UT block to turn on the data source to the master and slave

Table 35. Register Address Space

Functional Block

Address Range (Hex)

Core

0x0000--0x001F

0x0200--0x0226

OHP

0x0400--0x05C2

0x0800--0x0AF8

0x1000--0x1607

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

112

Agere Systems Inc.

Regis

t
er Maps

re Reg

i
ster

l
e

36.

Map

f
Co

r
e

Reg

i
st

r
ess

)

O),

(R/W),

O),

(COR/W)

t Num

faul

l
u

(He

)

5432

r
s

i
on Contr

000

EVI

VER

I
O

[7:

]

001

I
_

_TD

002

II_

003

I
_

_04

004

I
_

_2G

005

ASC

I
I
_

_5C

50D

0006

007

Reser

e In

t
e

t
s

008

(CO

/
W

)

r
v

(CO

/
W

)

UTI

)

r
v

)

l
-
P

rpos

put

009

Reser

000

NPUT

ter

r
u

t
Ma

sks

000

Reser

000C

I
O

[
3:

I
M

UTI

I
M

r
v

I
M

FFFF

Cor

sets

000D

Reser

000

MRS

r
v

RST

l
-
P

rpos

tput

R/W

0]_

PUT

LUE

r
o

i
n

010

R/W

Reser

MMO

[
1

:
0

]

DH/

PLL

[
A]

[
B]

[
C]

[
D]

011

R/W

EQ_CH_A

Reser

EQ_CH_B

Reser

EQ_CH_C

r
v

EQ_CH_D

r
v

012

[
3

:
0]

_CH_

[
3:

_CH_B

[
3

:
0

]
_

CH_C

[
3

:
0

]
_

CH_D

013

R/W

RST_

_CT

r
v

I
N

I
V

/
L

/
E

I
R

014

R/W

[1]_

r
v

[
0

015

R/W

[3]_

r
v

[
2

0016

001

Reser

R/W

CRA

TCH[

:
0

]

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

113

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

gister

l
e

37.

Map

f
UT

i
st

ddr

ex)

O),

(R/W),

O),

(COR/W)

t Num

faul

l
u

(He

)

98765432

UT Ma

r
oc

l
l
V

r
s

i
on

Num

200

Res

r
v

I
O

]

201

Res

r
v

I
NT

[D]

I
NT

[C]

I
NT

]

I
NT

]

Del

t
a & E

t

P

r
a

ter

Cha

nne

l
A

202

R/W

UNDER-

RxA

I
T

OR_

Cha

nne

l
B

203

R/W

UNDER-

RxB

I
T

OR_

Cha

nne

l
C

204

R/W

UNDER-

RxC

I
T

OR_

Cha

nne

l
D

205

R/W

UNDER-

RxD

I
T

OR_

t Ma

r
a

206

R/W

I
NT

I
N

[
C

]

I
NT

M[B

]

I
N

]

000

Cha

nne

l
A

207

R/W

]

UNDER-

]

ASK

[
A

]

I
T

SK[

000

Cha

nne

l
B

208

R/W

]

UNDER-

]

ASK

[
B

]

I
T

SK[

000

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

114

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

gisters

(
c

nue

ble

.

M

p of UT Re

gis

t
e

r
s

(
c

nue

ddr

ex)

O),

(R/W),

O),

(COR/W)

t Num

faul

l
u

(He

)

98765432

Cha

nne

l
C

209

R/W

ASK[

UNDER-

ASK[

I
T

ASK[

000

Cha

nne

l
D

020

Res

r
v

ASK[

UNDER-

ASK[

I
T

ASK[

000

r
r
o

r
Co

unt

T M

ode

Cha

nne

l
A

020

PMR

Cha

nne

l
B

020C

PMR

Cha

nne

l
C

020D

PMR

PEC

Cha

nne

l
D

020

PMR

PEC

r
ov

i
s

t
er

Cha

nne

l
A

R/W

LLIN

ENB_

Reser

RxA

DDR_A

[
4

:
0

]

r
v

CLO

I
T

TYPE

RxA

I
A

_MO

E_Rx

210

R/W

LLIN

Reser

TxA

DDR_A

[
4:

Reser

TxA

TYPE

[
2

:
0

]

211

R/W

I
NG

RESS

ERMARK

_HIG

H_A[

Res

r
v

ING

ESS

ERMARK_

_A[

:
0

]

361

212

R/W

GRES

S_W

RMA

K_HI

GH_A

]

GRES

S_W

RMA

_LO

W_A

[
6

:
0

]

361

Cha

nne

l
B

213

R/W

LLIN

ENB_

Reser

RxA

DDR_B

[
4

:
0

]

r
v

CLO

I
T

TYPE

RxB

I
A

_MO

E_Rx

214

R/W

LLIN

Reser

TxA

DDR_B

[
4:

Reser

TxB

TYPE

[
2

:
0

]

215

R/W

I
NG

RESS

ERMARK

_HIG

H_B[

Res

r
v

ING

ESS

ERMARK_

_B[

:
0

]

361

216

R/W

GRES

S_W

RMA

K_HI

GH_B

]

GRES

S_W

RMA

_LO

W_B

[
6

:
0

]

361

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

115

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

gisters

(
c

nue

ble

.

M

p of UT Re

gis

t
e

r
s

(

nue

ddr

ex)

O),

(R/W),

O),

(COR/W)

t Num

faul

l
u

(He

)

98765432

217

R/W

LLIN

Reser

RxA

DDR_C[

r
v

CLO

RxC

I
T

RxC

TYPE

RxC

[
2

:
0

]

218

R/W

LLIN

ENB

Res

r
v

:0]

ARI

TxC

TYPE

OPI

ODE_

219

R/W

I
NG

MARK_

I
G

]

I
NGRE

SS_

RMARK_L

C[6

:
0]

361

021

Res

r
v

RES

ERMARK

_HI

H_C[

Res

r
v

RESS

ERMARK

_LO

W_C[

361

Cha

nne

l
D

021

LLIN

Reser

RxA

DDR_D[

r
v

CLO

RxD

I
T

RxD

TYPE

RxD

[
2

:
0

]

021C

R/W

LLIN

ENB

Res

r
v

:0]

ARI

TxD

TYPE

OPI

ODE_

021D

R/W

I
NG

MARK_

I
G

]

I
NGRE

SS_

RMARK_L

D[6

:
0]

361

021

Res

r
v

RES

ERMARK

_HI

H_D[

Res

r
v

RESS

ERMARK

_LO

W_D[

361

set Reg

i
ste

R/W

UT_

UT_Tx

UT_Rx

00F

r
r
o

r
Co

unt

Cha

nne

l
A

220

PEC

Cha

nne

l
B

221

PEC

Cha

nne

l
C

222

Cha

nne

l
D

223

h Re

t
e

224

R/W

UT_

CRA

TCH

[
15

:
0

]

i
st

225

R/W

TxP

RxP

RxD

RxSOP/CD

RxP

RxD

RxSOP/CC

RxP

AB/

RxD

AB/

RxSOP/CB

RxP

AA/

RxD

AA/

RxSOP/CA

i
z

Mode

t
e

226

R/W

I
Z

TxS

I
ZE

TxS

I
ZE

TxS

I
ZE

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

116

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

P Reg

i
s

t
er

l
e

.

M

p of OHP Re

gis

t
e

r
s

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

P Macr

ell

r
s

i
o

040

OHP

RSI

15:

000

r
r
upts

040

OHP

INT

[D]

I
N

[

I
N

[

I
N

[

000

Delt

a &

ven

t P

r
a

t
e

r
s

040

OR/

RDI-

ND[A]

APS

BLE

]

[
A

]

[
A

]

ND[

]

DMO

]

ERRE

]

S1B

ABB

EE[

]

DD[

]

LOF

[
A

]

[
A]

CD[A

]

000

040

OR/

000000

000

I
S

]

000

040

OR/

RDI-

ND[B]

APS

BLE

]

[
B

]

[
B

]

ND[

]

DMO

]

ERRE

]

S1B

ABB

EE[

]

DD[

]

LOF

[
B

]

[
B]

CD[B

]

000

040

OR/

000000

000

I
S

]

000

040

OR/

RDI-

ND[

APS

BLE

]

4D[

]

8D[

]

ND[

]

DMO

ERRE

]

S1B

ABB

DD[

[
C

]

[
C

]

040

OR/

000000

000

I
S

]

000

040

OR/

RDI-

ND[

APS

BLE

]

4D[

]

8D[

]

ND[

]

DMO

ERRE

]

S1B

ABB

DD[

[
D

]

[
D

]

/
W

000000000000000

I
S

]

000

Rece

r
an

i
t
S

t
ate

l
u

e P

r
a

r
s

40A

LRDI

]

Reser

TLRDI

[
A]

]

[
A

]

[
A

]

LOC[

000

40B

LRDI

]

Reser

TLRDI

[
B]

]

[
B

]

[
B

]

LOC[

000

LRDI

[
C]

Reser

TLRDI

[
C

]

[
C

]

[
C]

000

LRDI

[
D]

Reser

TLRDI

[
D

]

[
D

]

[
D]

000

I
n

ter

r
upt Ma

r
a

ter

40E

RDI-

]

APS

BLE

]

4M[

]

8M[

]

[
A]

DMO

]

ERRM

]

S1B

ABB

LEM[

[
A]

[
A

]

OOF

]

[
A

]

[
A]

FFF

040F

INT

]

000000

000

I
S

]

800

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

117

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

Reg

i
s

t
ers

(
c

nue

ble

.

M

p of OHP Re

gis

t
e

r
s

(

ont

inu

ed)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

041

/
W

RDI-

]

APS

BLE

]

4M[

]

8M[

]

[
B]

DMO

]

ERRM

]

S1B

ABB

LEM[

[
B]

[
B

]

OOF

]

[
B

]

[
B]

FFF

041

/
W

INT

]

000000

000

I
S

]

800

041

/
W

RDI-

[
C

]

[
C

]

APS

BLE

]

4M[

]

8M[

]

[
C

]

DMO

ERRM

]

S1B

ABB

[
C

]

M[C

]

[C]

[
C

]

[C]

OCM

[
C]

FFF

041

/
W

INT

[C]

000000

000

I
S

[C]

800

041

/
W

RDI-

[
D

]

APS

BLE

]

4M[

]

8M[

]

[
D

]

DMO

ERRM

]

S1B

ABB

[
D

]

M[D

]

[D]

[
D

]

[D]

OCM

[
D]

FFF

/
W

I
N

[
D

]

00000000000000

I
S

]

800

l
e

041

/
W

Res

r
v

REN[A]

CLEAR[A]

SFSET

[A]

CLEAR[A]

SDSET

[A]

041

/
W

Res

r
v

REN[B]

CLEAR[B]

SFSET

[B]

CLEAR[B]

SDSET

[B]

041

/
W

Res

r
v

REN[C]

CLEAR[C]

SFSET

[C]

CLEAR[C]

SDSET

[C]

041

/
W

Res

r
v

REN[D]

CLEAR[D]

SFSET

[D]

CLEAR[D]

SDSET

[D]

i
n

N Ti

t
V

l
u

41A

CNTDK

]
[
3

:
0

]

CNTDK

]
[
3

:
0

]

CNTDF1[

]
[
3

:
0

]

CNTDJ0Z0[

]
[
3

:
0

]

333

41B

eser

CNTDS

[
A

]
[
3

:
0

]

CNTDS

]
[
3

:
0

]

NTDK

2FRA

[
A

]
[
3:

053

CNTDK

]
[
3

:
0

]

CNTDK

]
[
3

:
0

]

CNTDF1[

]
[
3

:
0

]

CNTDJ0Z0[

]
[
3

:
0

]

333

eser

CNTDS

[
B

]
[
3

:
0

]

CNTDS

[
B

]
3

:
0

]

TDK

FRA

[
B

]
[
3

:
0

]

053

41E

CNTDK

[
3

:
0

]

CNTDK

[
3

:
0

]

CNTDF1[

[
3

:
0

]

CNTDJ

[
3

:
0

]

333

041F

CNT

DS1F

ME[

]
[
3

:
0

]

CNT

DS1[

CNT

DK1K

RAME

[C]

[
3

:
0

]

053

042

/
W

CNTDK

[
3

:
0

]

CNTDK

[
3

:
0

]

CNTDF1[

[
3

:
0

]

CNTDJ

[
3

:
0

]

333

042

/
W

Reser

CNTDS

1FRA

[
D

]
[
3

:
0

]

CNTDS

CNTDK

2FRA

[
D

]
[
3

:
0

]

053

i
v

t
ro

l
P

r
a

t
e

[
A

]

IGN

]

[
A

]

I
NH[

]

I
S

I
NH[

]

EL[

]

SEL

[A]

CNTDB

[
A

]

S1MO

_OR_

[
A

]

R_1

]

I
T

CNT

[
A

]

CRI

]

I
T

CNT

[
A

]

ASS[

000

042

/
W

M1BITBLK

CNT[A]

Res

r
v

LOS

CNT

][

12:

000

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

118

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

Reg

i
s

t
ers

(
c

nue

ble

.

M

p of OHP Re

gis

t
e

r
s

(

ont

inu

ed)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

[
B

]

IGN

]

[
B

]

I
NH[

]

I
S

I
NH[

]

EL[

]

SEL

[B]

CNTDB

[
B

]

S1MO

_OR_

[
B

]

R_1

]

I
T

CNT

[
B

]

CRI

]

I
T

CNT

[
B

]

ASS[

000

042

/
W

M1BITBLK

CNT[B]

Res

r
v

LOS

CNT

][

12:

000

[
C

]

IGN

[
C

]

NH[

[
C

]

I
S

[
C

]

[
C

]

CNTDB

[
C

]

S1MO

_OR_

[
C

]

R_1

]

I
T

]

CRI

I
T

CNT[

]

SS[

000

042

/
W

M1BITBLK

CNT[C]

r
v

[
C

]
[1

[
D

]

IGN

[
D

]

NH[

[
D

]

I
S

[
D

]

[
D

]

CNTDB

[
D

]

S1MO

_OR_

[
D

]

R_1

]

I
T

]

CRI

I
T

CNT[

]

SS[

000

042

/
W

M1BITBLK

CNT[D]

r
v

[
D

]
[1

42A

RRE

[
1

:
0

]

RRE

Reser

I
NH[

]

RTO

NH[

]

[
A

]

RTO

EPI

]

000

42B

S-

I
NH[

]

RTO

NH[

]

[
B

]

RTO

EPI

]

000

S-

I
N

RTO

NH[

]

NH[

RTO

EPI

]

000

S-

I
N

RTO

NH[

]

NH[

RTO

EPI

]

000

r
an

it Co

t
r
o

l

P

r
a

ter

42E

I
N

TJ0

I
NS

]

EPM

]

I
N

E2[

]

S1[

]

D4T

]

[
A

]

E1[

]

PS-

AB-

I
N

]

[
A

]

L_I

[
A

]

TF1

I
N

]

I
N

]

000

042F

A2E

NS[

]
[
4

]

OH_B

ASS

]

CRI

]

RDI

I
N

]

_LR

I
NH[

]

N_LRDI

[
A

]

_LR

I
N

]

RDI

I
N

]

RDI

I
N

]

RDI

I
N

]

000

043

/
W

r
v

TJ0

I
NS

]

EPM

]

I
N

E2[

]

S1[

]

D4T

]

[
B

]

E1[

]

APS-

B-

]

[
B

]

L_I

[
B

]

TF1

I
N

]

I
N

]

000

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

119

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

Reg

i
s

t
ers

(
c

nue

ble

.

M

p of OHP Re

gis

t
e

r
s

(

ont

inu

ed)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

[
B

][4

:
0

]

ASS

]

CRI

]

RDI

I
N

]

_LR

I
NH[

]

N_LRDI

[
B

]

_LR

I
N

]

RDI

I
N

]

RDI

I
N

]

RDI

I
N

]

000

043

/
W

r
v

TJ0

I
NS

]

EPM

]

[
C

]

D4T

]

[
C

]

PS-

AB-

I
N

]

_IN

]

INH[C]

TF1

I
N

[C]

I
N

]

000

043

/
W

2ERRI

NS[

][

H_B

SS[

]

CRI

]

[
C

]

[
C

]

RDI

I
N

]

_LR

I
NH[

N_LRDI

NH[

_LR

I
N

]

RDI

I
N

]

RDI

I
N

]

RDI

I
N

]

000

043

/
W

r
v

I
N

]

EPM

]

[
D

]

D4T

]

[
D

]

PS-

AB-

I
N

]

_IN

]

INH[D]

TF1

I
N

[D]

I
N

[D]

000

043

/
W

2ERRI

NS[

][

H_B

SS[

]

CRI

]

[
D

]

[
D

]

RDI

I
N

]

_LR

I
NH[

N_LRDI

NH[

_LR

I
N

]

RDI

I
N

]

RDI

I
N

]

RDI

I
N

]

000

043

/
W

PSI

]

TK2

I
N

]

r
v

I
N

][

]

043

/
W

PSI

]

TK2

I
N

]

r
v

I
N

][

]

043

/
W

PSI

]

TK2

I
N

]

r
v

[C]

[
11:

C000

043

/
W

PSI

]

TK2

I
N

]

r
v

[D]

[
11:

C000

i
gna

l

De

R Al

gor

i
t
hm

r
s

43A

][

]

000

43B

r
v

P_S

MSET

[
A

]
[
7

:
0

]

][

[
A

]
[
2

:
0

]

000

][

]

000

r
v

P_S

MSET

[
B

]
[
7

:
0

]

][

[
B

]
[
2

:
0

]

000

43E

OHP_

SDNSS

[
C

]
[
18:

000

043F

r
v

[
C

]
[
7

:
0

]

DLS

[
C]

[
3

:
0

]

DNS

[
C]

[
2

:
0

]

000

044

/
W

OHP_

SDNSS

[
D

]
[
18:

000

044

/
W

r
v

[
D

]
[
7

:
0

]

DLS

[
D]

[
3

:
0

]

DNS

[
D]

[
2

:
0

]

000

044

/
W

BSE

[
A

]
[
1

:
0]

000

044

/
W

BSE

[
B

]
[
1

:
0]

000

044

/
W

P_S

BSE

[
C

]
[1

5:0

]

000

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

120

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

Reg

i
s

t
ers

(
c

nue

ble

.

M

p of OHP Re

gis

t
e

r
s

(

ont

inu

ed)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

044

/
W

P_S

BSE

[
D

]
[1

5:0

]

000

044

/
W

DNS

CLE

]
[
1

:
3

]

000

044

/
W

r
v

][

EAR

[
A

]
[
3

:
0

]

_SD

EAR

[
A

]
[
2

:
0

]

000

044

/
W

DNS

CLE

]
[
1

:
3

]

000

044

/
W

r
v

][

EAR

[
B

]
[
3

:
0

]

_SD

EAR

[
B

]
[
2

:
0

]

000

44A

DNS

CLE

[
1

000

44B

r
v

P_S

LEA

]
[
7

:
0

]

EAR

[
C

][

[
C

]
[
2

:
0

]

000

DNS

CLE

[
1

000

r
v

P_S

LEA

]
[
7

:
0

]

EAR

[
D

][

[
D

]
[
2

:
0

]

000

44E

EAR

[
A

]
[
15:

000

044F

EAR

[
B

]
[
15:

000

045

/
W

[
C

][

15:

000

045

/
W

[
D

][

15:

000

l F

l
g

rit

t
e

r
s

045

/
W

SSE

[
A

]
[
18:

000

045

/
W

r
v

[
A

]
[
7

:
0

]

][3

:
0

]

][

045

/
W

SSE

[
B

]
[
18:

000

045

/
W

r
v

[
B

]
[
7

:
0

]

][3

:
0

]

][

045

/
W

][

:
3

]

000

045

/
W

r
v

][

]

]
[
3

:
0

]

[
C

][2

]

045

/
W

][

:
3

]

000

045

/
W

r
v

][

]

]
[
3

:
0

]

[
D

][2

]

45A

][

]

000

45B

][

]

000

[
C

]
[
15:

000

[
D

]
[
15:

000

45E

EAR

[
A

]
[
18:

000

045F

r
v

][7

]

[
A

]
[
3

]

[
A

]
[
2

:
0

]

046

/
W

EAR

[
B

]
[
18:

000

046

/
W

r
v

][7

]

[
B

]
[
3

]

[
B

]
[
2

:
0

]

046

/
W

CLE

[
18:

000

046

/
W

r
v

OHP

MCLE

AR[

][

P_S

LEA

[C]

[
3

:
0

]

P_S

CLEA

R[C]

]

000

046

/
W

CLE

[
18:

000

046

/
W

r
v

OHP

MCLE

AR[

][

P_S

LEA

[D]

[
3

:
0

]

P_S

CLEA

R[D]

]

000

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

121

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

Reg

i
s

t
ers

(
c

nue

ble

.

M

p of OHP Re

gis

t
e

r
s

(

ont

inu

ed)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

046

/
W

P_S

][

]

000

046

/
W

P_S

][

]

000

046

/
W

[
C

][

]

000

046

/
W

[
D

][

]

000

B1,

,

and M1

r
r
o

r

Cou

t
s

46A

B1E

CNT

[
A

]
[
15:

000

46B

B1E

CNT

[
B

]
[
15:

000

[
C

][

]

000

[
D

][

]

000

46E

Res

r
v

ECNT

][

000

046F

B2E

CNT

[
A

]
[
15:

000

047

ECNT

][

000

047

B2E

CNT

[
B

]
[
15:

000

047

B2E

CNT

[
C

]
[
2

:
16]

000

047

[
C

][

]

000

047

B2E

CNT

[
D

]
[
2

:
16]

000

047

[
D

][

]

000

047

ECNT

][

20:

]

000

047

M1E

[
A

]
[
15:

000

047

ECNT

][

20:

]

000

047

M1E

[
B

]
[
15:

000

47A

Res

r
v

M1E

[
C

][

000

47B

M1ECNT

[
C

][

15:

000

Res

r
v

M1E

[
D

][

000

M1ECNT

[
D

][

15:

000

r
a

,
K

r
t
V

l
u

/
W

I
N

][7

:
0

]

I
N

][7

]

047F

DINS[

]
[
7

:
0

]

I
NS[

]
[
7

:
0

]

000

I
N

][7

:
0

]

I
N

][7

]

I
N

[
B

][7

]

I
N

][7

]

048

/
W

NS[

][

1DI

C][

:
0

]

000

048

/
W

2DI

C][

:
0

]

K1DI

NS[

][

000

048

/
W

NS[

][

1DI

D][

:
0

]

000

048

/
W

2DI

D][

:
0

]

K1DI

NS[

][

000

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

122

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

Reg

i
s

t
ers

(
c

nue

ble

.

M

p of OHP Re

gis

t
e

r
s

(

ont

inu

ed)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

cei

ve F

,

S

,

K2

, K1 Mo

i
to

r

V

048

MON1[

]
[
7

:
0

]

000

048

2DMO

N[A

]
[
7

:
0

]

1DMO

N[A

]
[
7

:
0

]

000

048

S1DMO

][

000

048

MON1[

]
[
7

:
0

]

000

48A

K2DMO

][

K1DMO

][

000

48B

Res

r
v

S1DMO

][

000

[
C

][7

]

[
C

][7

]

][

]

48E

Res

r
v

DMON[

]
[
7

:
0]

000

048F

DMO

]
[
7

:
0

]

1DMO

[D]

[
7

:
0

]

000

049

2DMO

[
D]

]

1DMON[

:0]

000

049

DMON[

]
[
7

:
0]

000

Recei

i
to

r
V

l
u

][

]

][

]

][

]

][

]

][

]

][

]

][

]

][

]

[
A

][1

][7

]

][

]

[
A

][1

][7

]

][1

][7

:
0

]

[
A

][1

][7

]

][1

][7

:
0

]

[
A

][1

][7

]

][1

][7

:
0

]

049A

Reser

000

0DMON[

][

0DMON[

][

000

0DMON[

][

0DMON[

][

000

0DMON[

][

0DMON[

][

000

0DMON[

][

0DMON[

][

000

[
B

][1

][7

]

][

]

[
B

][1

][7

]

][1

][7

:
0

]

[
B

][1

][7

]

][1

][7

:
0

]

[
B

][1

][7

]

][1

][7

:
0

]

Reser

000

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

123

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

Reg

i
s

t
ers

(
c

nue

ble

.

M

p of OHP Re

gis

t
e

r
s

(

ont

inu

ed)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

MON[

]
[
2

]
[
7

:
0]

N[C]

[
1

]
[
7:

000

MON[

]
[
4

]
[
7

:
0]

N[C]

[
3

]
[
7:

000

MON[

]
[
6

]
[
7

:
0]

N[C]

[
5

]
[
7:

000

MON[

]
[
8

]
[
7

:
0]

N[C]

[
7

]
[
7:

000

[
C

]
[1

]

J0D

[
C

][9

][

:
0

]

0DMON[

C][

]
[
7

:
0

]

DMON[

][

000

0DMON[

C][

]
[
7

:
0

]

DMON[

][

000

0DMO

N[C]

16]

[
7

:
0

]

DMON[

][

000

04F

Reser

000

][2

][

]

[
D

][1

][

:
0

]

][4

][

]

[
D

][3

][

:
0

]

][6

][

]

[
D

][5

][

:
0

]

][8

][

]

[
D

][7

][

:
0

]

04F

DMON[

][

N[D]

[
9

]
[
7:

000

04F

DMON[

][

0DMON[

D][

]
[
7

:
0

]

000

04F

DMON[

][

0DMON[

D][

]
[
7

:
0

]

000

04F

DMO

[D]

16]

[
7

:
0

]

DMON[

][

000

051

Reser

000

t
e

r
an

r
t
(

)

[
A

][2

][

]

[
A

][1

][

:
0

]

[
A

][4

][

]

[
A

][3

][

:
0

]

[
A

][6

][

]

[
A

][5

][

:
0

]

[
A

][8

][

]

[
A

][7

][

:
0

]

I
N

]

I
N

][9

][

:
0

]

051

/
W

0DINS

[
A

]
[
1

]
[
7

:
0

]

DINS

][

000

051

/
W

0DINS

[
A

]
[
1

]
[
7

:
0

]

DINS

][

000

051

/
W

0DINS

[
A

]
[
1

]
[
7

:
0

]

DINS

][

000

051A

053

Reser

000

[
B

][2

][

]

[
B

][1

][

:
0

]

[
B

][4

][

]

[
B

][3

][

:
0

]

[
B

][6

][

]

[
B

][5

][

:
0

]

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

124

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

Reg

i
s

t
ers

(
c

nue

ble

.

M

p of OHP Re

gis

t
e

r
s

(

ont

inu

ed)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

[
B

][8

][

]

[
B

][7

][

:
0

]

I
N

]

I
N

][9

][

:
0

]

053

/
W

0DINS

[
B

]
[
1

]
[
7

:
0

]

DINS

][

000

053

/
W

0DINS

[
B

]
[
1

]
[
7

:
0

]

DINS

][

000

053

/
W

0DINS

[
B

]
[
1

]
[
7

:
0

]

DINS

][

000

053A

055

Reser

000

[
C

]
[2

][7

:
0

]

I
N

]
[
1

]
[
7

:
0

]

[
C

]
[4

][7

:
0

]

I
N

]
[
3

]
[
7

:
0

]

[
C

]
[6

][7

:
0

]

I
N

]
[
5

]
[
7

:
0

]

[
C

]
[8

][7

:
0

]

I
N

]
[
7

:
0

]

055

/
W

]
[1

[7:

]

I
N

[
C

][

]

000

055

/
W

INS[

[7:

]

I
NS[

]
[
1

][

000

055

/
W

INS[

[7:

]

I
NS[

]
[
1

][

000

055

/
W

INS[

[7:

]

I
NS[

]
[
1

][

000

055A

057

Reser

000

[
D

]
[2

][7

:
0

]

I
N

]
[
1

]
[
7

:
0

]

[
D

]
[4

][7

:
0

]

I
N

]
[
3

]
[
7

:
0

]

[
D

]
[6

][7

:
0

]

I
N

]
[
5

]
[
7

:
0

]

[
D

]
[8

][7

:
0

]

I
N

]
[
7

:
0

]

057

/
W

]
[1

[7:

]

I
N

[
D

][

]

000

057

/
W

INS[

[7:

]

I
NS[

]
[
1

][

000

057

/
W

INS[

[7:

]

I
NS[

]
[
1

][

000

057

/
W

INS[

[7:

]

I
NS[

]
[
1

][

000

057A

Reser

000

Byte

r
an

it I

ser

I
N

][

]

Res

r
v

000

I
N

][

]

I
N

[
A

]
[
3

][7

]

/
W

I
N

][

]

I
N

[
A

]
[
5

][7

]

I
N

][

]

I
N

[
A

]
[
7

][7

]

I
N

][1

]
[
7

:
0

]

I
N

[
A

]
[
9

][7

]

TZ0DI

[
A

]
[
12]

[
7

:
0

]

TZ0DI

[
A

]
[
1

]
[
7

:
0

]

000

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

125

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

Reg

i
s

t
ers

(
c

nue

ble

.

M

p of OHP Re

gis

t
e

r
s

(

ont

inu

ed)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

/
W

I
N

][

]

Res

r
v

000

/
W

I
N

][

]

I
N

[
B

]
[
3

][7

]

/
W

I
N

][

]

I
N

[
B

]
[
5

][7

]

/
W

I
N

][

]

I
N

[
B

]
[
7

][7

]

/
W

I
N

][1

]
[
7

:
0

]

I
N

[
B

]
[
9

][7

]

TZ0DI

[
B

]
[
12]

[
7

:
0

]

TZ0DI

[
B

]
[
1

]
[
7

:
0

]

000

TZ0DI

[
C

]
[
2

]
[
7:

Res

r
v

000

DINS

[C]

[
4

][

INS

[
C]

][

000

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[C]

[
6

][

INS

[
C]

][

000

DINS

[C]

[
8

][

INS

[
C]

][

000

I
N

]
[
1

][7

]

I
N

[
C

][

]

I
N

]
[
1

][7

]

I
N

][1

][7

]

05BC

/
W

DINS

[D]

[
2

][

Res

r
v

000

05BD

/
W

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[D]

[
4

][

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[
D]

][

000

05B

/
W

DINS

[D]

[
6

][

INS

[
D]

][

000

DINS

[D]

[
8

][

INS

[
D]

][

000

/
W

I
N

]
[
1

][7

]

I
N

[
D

][

]

/
W

I
N

]
[
1

][7

]

I
N

][1

][7

]

P Scr

t
c

i
ste

CRA

TCH[

15:

000

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

126

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

l
e

39.

Map

f
P

t
h

r
Reg

i
st

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

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l
u

(
H

ex)

9876

5432

r
o

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r
s

080

[
7

:
0

]

000

r
r
u

080

PT_

I
NT[

]

PT_

I
NT[

]

I
N

[
B

]

I
N

]

000

Del

t
a & E

t

P

r
a

ter

r
t
A

080

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RJ1DMON

S[A]E

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I
HD[

]
[
1

]

000

080

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RDI

]

Reser

RZ5DMO

[
A

]

RZ4DMO

[
A

]

RZ3DMO

[
A

]

[
A

]

RF2DMO

[
A

]

RRDIPD

ND[A]

[
A

]

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]

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[
A

]

000

80E

Reser

000

r
t
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080F

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I
HD[

]
[
1

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]

Reser

RZ5DMO

[
B

]

RZ4DMO

[
B

]

RZ3DMO

[
B

]

[
B

]

RF2DMO

[
B

]

RRDIPD

ND[B]

[
B

]

UC2D

]

RSDD[B]

RSF

[
B

]

000

81B

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000

r
t
C

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Reser

I
HD[

[
1

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]

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ND[

RZ4DMO

ND[

RZ3DMO

ND[

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MON

[

ND[

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I
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1

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RZ4DMO

ND[

RZ3DMO

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RF2DMO

ND[

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MOND[D]

ND[

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[D]

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082B

083

Reser

000

t
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e Re

i
st

r
t

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t
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i
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083

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]
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1

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:0]

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][

:0]

IH_

][

:0]

IH_

][

:0]

IH_

][

:0]

IH_

]
[
6]

:0]

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

127

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

(
c

t
i
nu

)

ble

.

M

p of Pa

th Te

r
m

ina

t
or

gis

t
e

r
s

(
c

tin

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(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
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(
H

ex)

9876

5432

083

IH_

][

:0]

IH_

][

:0]

IH_

][

:0]

IH_

][1

:0]

IH_

][1

:0]

IH_

][

12]

:0]

I
P

I
N

][2

]

r
v

[
A

]
[
2

:
0

]

UC2

]

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]

RSDS[A]

[
A

]

000

][

]

][7

]

83A

]
[
7

:
0

]

RH4DMO

[
A

]
[
7

:
0

]

000

83B

MON[

:0]

DMON[

]
[
7:

000

83C

086

Reser

000

][

]

][

]

][

]

][

]

86A

1DMON[

][

1DMON[

][

000

86B

1DMON[

][

1DMON[

][

000

1DMON[

][

1DMON[

[
10]

[
7

]

000

[
A

][1

][7

]

][1

][7

:
0

]

[
A

][1

][7

]

][1

][7

:
0

]

086F

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N[A]

[
15]

[
7

:
0

]

DMON[

]
[
16]

[
7

]

000

[
A

][1

][7

]

][1

][7

:
0

]

[
A

][1

][7

]

][2

][7

:
0

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[
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][7

]

][2

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0

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[
A

][2

][7

]

][2

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0

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[
A

][2

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][2

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0

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[
A

][2

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]

][2

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:
0

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[
A

][2

][7

]

][3

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:
0

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[
A

][3

][7

]

][3

][7

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0

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[
A

][3

][7

]

][3

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:
0

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[
A

][3

][7

]

][3

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0

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[
A

][3

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0

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[
A

][3

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]

][4

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:
0

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[
A

][4

][7

]

][4

][7

:
0

]

[
A

][4

][7

]

][4

][7

:
0

]

[
A

][4

][7

]

][4

][7

:
0

]

087F

1DMO

N[A]

[
47]

[
7

:
0

]

DMON[

]
[
48]

[
7

]

000

[
A

][4

][7

]

][5

][7

:
0

]

[
A

][5

][7

]

][5

][7

:
0

]

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

128

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

(
c

t
i
nu

)

ble

.

M

p of Pa

th Te

r
m

ina

t
or

gis

t
e

r
s

(

tin

ued)

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(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
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ex)

9876

5432

[
A

][5

][7

]

][5

][7

:
0

]

[
A

][5

][7

]

][5

][7

:
0

]

[
A

][5

][7

]

][5

][7

:
0

]

[
A

][5

][7

]

][6

][7

:
0

]

[
A

][6

][7

]

][6

][7

:
0

]

[
A

][6

][7

]

][6

][7

:
0

]

r
t

B S

t
at

e Re

i
st

088

DRP[

]
[
1

]

IH_

][

:0]

IH_

][

:0]

IH_

][

:0]

IH_

][

:0]

IH_

][

:0]

IH_

]
[
6]

:0]

088

IH_

][

:0]

IH_

][

:0]

IH_

][

:0]

IH_

][1

:0]

IH_

][1

:0]

IH_

][

12]

:0]

I
P

I
N

][2

]

r
v

[
B

]
[
2

:
0

]

UC2

]

RPPL

]

RSDS[B]

[
B

]

000

88B

]
[
7

:
0

]

RC2DMO

[
B

]
[
7

:
0

]

000

]
[
7

:
0

]

RH4DMO

[
B

]
[
7

:
0

]

000

MON[

:0]

DMON[

]
[
7:

000

088E

Reser

000

][

]

][

]

][

]

][

]

][

]

][

]

][

]

][

]

][

]

][1

][7

:
0

]

[
B

][1

][7

]

][1

][7

:
0

]

[
B

][1

][7

]

][1

][7

:
0

]

[
B

][1

][7

]

][1

][7

:
0

]

[
B

][1

][7

]

][1

][7

:
0

]

[
B

][1

][7

]

][2

][7

:
0

]

[
B

][2

][7

]

][2

][7

:
0

]

[
B

][2

][7

]

][2

][7

:
0

]

[
B

][2

][7

]

][2

][7

:
0

]

[
B

][2

][7

]

][2

][7

:
0

]

[
B

][2

][7

]

][3

][7

:
0

]

[
B

][3

][7

]

][3

][7

:
0

]

[
B

][3

][7

]

][3

][7

:
0

]

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

129

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

(
c

t
i
nu

)

ble

.

M

p of Pa

th Te

r
m

ina

t
or

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

[
B

][3

][7

]

][3

][7

:
0

]

[
B

][3

][7

]

][3

][7

:
0

]

[
B

][3

][7

]

][4

][7

:
0

]

[
B

][4

][7

]

][4

][7

:
0

]

[
B

][4

][7

]

][4

][7

:
0

]

[
B

][4

][7

]

][4

][7

:
0

]

[
B

][4

][7

]

][4

][7

:
0

]

[
B

][4

][7

]

][5

][7

:
0

]

[
B

][5

][7

]

][5

][7

:
0

]

[
B

][5

][7

]

][5

][7

:
0

]

[
B

][5

][7

]

][5

][7

:
0

]

[
B

][5

][7

]

][5

][7

:
0

]

[
B

][5

][7

]

][6

][7

:
0

]

[
B

][6

][7

]

][6

][7

:
0

]

[
B

][6

][7

]

][6

][7

:
0

]

r
t

C S

t
at

e Re

i
st

RSS

DRP[

][

Res

r
v

I
H

[C][1

]

:0]

I
H

[C][2

]

:0]

I
H

[C][3

]

:0]

I
H

[C][4

]

:0]

IH_S

[C][5

]

:0]

IH_S

[C][6

]

:0]

08DB

I
H

[C][7

]

:0]

I
H

[C][8

]

:0]

I
H

[C][9

]

:0]

[
C

][10

]

:0]

]
[
1

:0]

]
[
1

:0]

TRDI

I
NT[

]
[
2:

Reser

RRDI

[
C]

[
2

:
0

]

UC2

[C]

RPPL

[C]

RSDS

[
C

]

[C]

000

RF2DMO

[
7

:
0

]

RC2DMO

[
C

]
[
7:

000

08DE

DMO

[C]

[
7

]

RH4DMON[

][

000

[
C

][7

:
0

]

[
C

][

08E0

90B

Reser

000

MON[

]
[
1

]
[
7

:
0]

N[C]

[
2

]
[
7:

000

MON[

]
[
3

]
[
7

:
0]

N[C]

[
4

]
[
7:

000

90E

MON[

]
[
5

]
[
7

:
0]

N[C]

[
6

]
[
7:

000

090F

MON[

]
[
7

:
0]

N[C]

[
8

]
[
7:

000

][9

][

]

[
C

]
[1

]

091

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

091

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

091

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

130

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

(
c

t
i
nu

)

ble

.

M

p of Pa

th Te

r
m

ina

t
or

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

091

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

091

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

091

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

091

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

091

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

091

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

91A

1DMON[

C][

]
[
7

:
0

]

DMON[

][

000

91B

1DMON[

C][

]
[
7

:
0

]

DMON[

][

000

1DMON[

C][

]
[
7

:
0

]

DMON[

][

000

1DMON[

C][

]
[
7

:
0

]

DMON[

][

000

91E

1DMON[

C][

]
[
7

:
0

]

DMON[

][

000

091F

1DMON[

C][

]
[
7

:
0

]

DMON[

][

000

092

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

092

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

092

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

092

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

092

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

092

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

092

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

092

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

092

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

092

DMON[

][

1DMON[

C][

]
[
7

:
0

]

000

92A

1DMON[

C][

]
[
7

:
0

]

DMON[

][

000

92B

1DMON[

C][

]
[
7

:
0

]

DMON[

][

000

r
t

D S

t
at

e Re

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st

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DRP[

][

Res

r
v

RPI

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[
D

][

]

]
[
2

]

]
[
3

]

]
[
4

]

]
[
5

]

]
[
6

]

Res

r
v

RPI

_ST

[
D

][

]

]
[
8

]

]
[
9

]

][

]

][

]

][

]

92E

TRDI

I
NT[

]
[
2:

Reser

RRDI

[
D]

[
2

:
0

]

UC2V

]

PPL

]

[
D

]

[
D

]

000

092F

2DMO

N[D]

[
7

]

RC2DMON[

][

000

093

DMO

[D]

[
7

]

RH4DMON[

][

000

[
D

][7

:
0

]

[
D

][

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

131

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

(
c

t
i
nu

)

ble

.

M

p of Pa

th Te

r
m

ina

t
or

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

Reser

000

95E

MON[

]
[
1

]
[
7

:
0]

N[D]

[
2

]
[
7:

000

095F

MON[

]
[
3

]
[
7

:
0]

N[D]

[
4

]
[
7:

000

][5

][

]

[
D

][6

][

:
0

]

][7

][

]

[
D

][8

][

:
0

]

][9

][

]

[
D

]
[1

]

096

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

096

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

096

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

096

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

096

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

096

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

096

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

96A

1DMON[

D][

]
[
7

:
0

]

DMON[

][

000

96B

1DMON[

D][

]
[
7

:
0

]

DMON[

][

000

1DMON[

D][

]
[
7

:
0

]

DMON[

][

000

1DMON[

D][

]
[
7

:
0

]

DMON[

][

000

96E

1DMON[

D][

]
[
7

:
0

]

DMON[

][

000

096F

1DMON[

D][

]
[
7

:
0

]

DMON[

][

000

097

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

097

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

097

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

097

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

097

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

097

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

097

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

097

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

097

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

097

DMON[

][

1DMON[

D][

]
[
7

:
0

]

000

97A

1DMON[

D][

]
[
7

:
0

]

DMON[

][

000

97B

1DMON[

D][

]
[
7

:
0

]

DMON[

][

000

1DMON[

D][

]
[
7

:
0

]

DMON[

][

000

1DMON[

D][

]
[
7

:
0

]

DMON[

][

000

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

132

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

(
c

t
i
nu

)

ble

.

M

p of Pa

th Te

r
m

ina

t
or

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

r
r
upt Ma

Contr

97E

UNCMO

eser

NTM[

00F

r
t

A I

r
r
upt Ma

Contr

097F

RJ1DMON

MISM[A]

r
v

[
A

][1

]

FFF

098

/
W

RDI

P-

]

Reser

RZ5DMO

NM[

]

RZ4DMO

NM[

]

RZ3DMO

NM[

]

NM[

]

RF2DMO

NM[

]

RRDIPD-

MONM[A]

UC2

]

PPL

]

RSDM

[A]

[
A]

FFF

98B

Reser

000

r
t

B I

r
r
upt Ma

Contr

RJ1DMON

MISM[B]

r
v

[
B

][1

]

FFF

RDI

]

Reser

RZ5DMO

NM[

]

RZ4DMO

NM[

]

RZ3DMO

NM[

]

NM[

]

RF2DMO

NM[

]

RRDIPD-

MONM[B]

UC2

]

PPL

]

RSDM

[B]

[
B]

FFF

098E

099

Reser

000

r
t

C I

r
r
upt Ma

Contr

099

/
W

RJ1DMON

[
C

]

Reser

I
H

[
1

12]

99A

RDI

[
C

]

Reser

RZ5DMO

NM[

]

RZ4DMO

NM[

]

RZ3DMO

NM[

]

NM[

]

RF2DMO

NM[

]

RRDIPD-

MONM[C]

UC2

]

PPL

]

RSDM

]

[
C]

FFF

099B

Reser

000

r
t

D I

r
r
upt Ma

Contr

/
W

RJ1DMON

[
D

]

Reser

I
H

[
1

12]

RDI

[
D

]

Reser

RZ5DMO

NM[

]

RZ4DMO

NM[

]

RZ3DMO

NM[

]

NM[

]

RF2DMO

NM[

]

RRDIPD-

MONM[D]

UC2

]

PPL

]

RSDM

]

[
D]

FFF

09A8

Reser

000

r
r
o

r C

ounte

r
s

r
t
A

r
v

RPI

I
N

[
A]

[
10:

000

09B4

09B

Reser

000

Res

r
v

RPI

DEC[

[
10:

000

09CA

Reser

000

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

133

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

(
c

t
i
nu

)

ble

.

M

p of Pa

th Te

r
m

ina

t
or

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

09CB

RNDFCNT[

]
[
12

:
0

]

000

Reser

000

RRCNT[

]
[
15

:
0

]

000

Reser

000

][

]

000

09E4

09E

Reser

000

r
t
B

Res

r
v

RPI

I
N

[
B]

[
10:

000

09F

Reser

000

Res

r
v

RPI

DEC[

[
10:

000

Reser

000

Res

r
v

RNDFCNT[

]
[
12

:
0

]

000

0A08

Reser

000

RRCNT[

]
[
15

:
0

]

000

0A15

Reser

000

][

]

000

0A21

0A2

Reser

000

r
t
C

0A2C

Res

r
v

I
_

I
NC[

[
1

:
0]

000

0A2

Reser

000

Res

r
v

I
_

[
10:

000

0A39

Reser

000

Res

r
v

RNDFCNT

[
C

]
[
1

:
0

]

000

0A45

Reser

000

RRCNT[

]
[
1

:
0

]

000

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

134

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

(
c

t
i
nu

)

ble

.

M

p of Pa

th Te

r
m

ina

t
or

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

0A51

0A5

Reser

000

0A5C

RRE

I
P

RRCNT[

]
[
15:

000

0A5

Reser

000

r
t
D

Res

r
v

I
_

I
NC[

[
1

:
0]

000

0A69

Reser

000

Res

r
v

I
_

[
10:

000

0A75

Reser

000

Res

r
v

RNDFCNT

[
D

]
[
1

:
0

]

000

0A81

0A8

Reser

000

0A8C

RRCNT[

]
[
1

:
0

]

000

0A8

Reser

000

RRE

I
P

RRCNT[

]
[
15:

000

0A99

0AA

Reser

000

One

-
S

t

C

ontr

DCLE

]

[
A

CLE

0AA

Reser

000

t
r
o

l
P

t
e

r
s

r
t
A

HMO

]
[
3

:
0

]

r
v

RCO

NC_

LOR

]

RJ1FRA

[
A

]
[
1

:
0

]

r
v

I
T

]

I
NCDE

C_6

[
A]

Reser

I
P

N_E

120

RCE

_LO

[
A

]
[
1

]

NCA

]
[
1

]

000

RCE

_LO

[
A

]
[
5

]

NCA

]
[
1

]

FFF

0AA

/
W

][

12]

][

12]

000

x_RE

I
P

[
A

]
[
3:

I
P

I
N

r
v

[
A

]

I
P

[
A

]

I
P

[
A

]

I
P

PPI

]

RDI

NH[

I
P

[
A

]

[
A

]

I
N

]

Res

r
v

000

AAB

/
W

I
N

SEL

][

][1

]

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

135

Agere Systems Inc.

LCDRe

gister Ma

(
c

nue

(
c

t
i
nu

)

ble

.

M

p of Pa

th Te

r
m

ina

t
or

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

CNT

DH4

Z4[

]
[
3:

THx_S

[
A

]
[
7

][

CNT

DZ5

[
A

]
[
3

:
0

]

CNTDF2[

]
[
3

:
0

]

NTDRDI

[
A

]
[
3

:
0

]

CNT

DC2

[
A

]
[
3:

333

r
t
B

AAE

HMONS

[
3

:
0

]

RCONC_

]

RJ1

[
B

][1:0

]

RJ1DMP

]

Reser

I
T

CNT

]

I
NCDE

C_6O

MAJ

[
B]

Reser

RDIPMON

_ENH

_OR1B[B]

120

RCE

_LO

[
B

]
[
1

]

NCA

]
[
1

]

000

RCE

_LO

[
B

]
[
5

]

NCA

]
[
1

]

FFF

0AB

/
W

][

12]

][

12]

000

x_RE

I
P

[
B

]
[
3:

RDI

[
B

]

r
v

TRDI

LMP

I
NH[

]

TRDIP_

UNEQ

INH[B]

TRDIP_LC

D[B]

RDIP_

PPI

]

RDI

I
NH[B]

TRDIP_

ENH

_OR1B[B]

TREIPER-

RINS[B]

RRI

[
B

]

TJ1INS[B]

r
v

000

0AB

/
W

I
N

SEL

][

][1

]

CNT

DH4

Z4[

]
[
3:

THx_S

[
B

]
[
7

][

CNT

DZ5

[
B

]
[
3

:
0

]

CNTDF2[

]
[
3

:
0

]

NTDRDI

[
B

]
[
3

:
0

]

CNT

DC2

[
B

]
[
3:

333

r
t
C

SEL

[
C

]
[
3

:
0

]

r
v

FIR

T[C

]

[
C

][1

]

r
v

I
T

]

IIN

MAJ

[
C

]

Res

r
v

I
P

N_E

[
C

]

]
[
1

]

][1

]

]
[
5

NCA

[
C]

[
1

12]

FFF

/
W

][

]

I
S

][1

]

/
W

I
P

[
C

]
[
3:

[
C

]

r
v

I
P

[
C

]

I
P

UNE

I
P

[
C

]

RDI

][C

]

RDIP_

PPI

]

RDI

SINH[C]

RDIP_

ENH

B[C]

PER-

RINS[C]

INS

[
C]

[
C

]

r
v

/
W

I
N

[
C

][3

]

][1

:
0

]

/
W

Z3Z4

]
[
3:0

]

[
C

][7

][1

]

/
W

][3

]

[
C

]
[
3

]

][

:
0

]

][3

]

r
t
D

HMO

[
3

:
0

]

eser

RCO

NC_

ALL

[
D]

[
1

:
0

]

J1DMP

Reser

I
T

CNT

]

I
NCDE

C_6O

MAJ

[
D]

Reser

RDI

N_E

_OR1

[D]

120

RCE

_LO

[
D]

[
1

NCA

[
1

12]

000

RCE

_LO

[
D]

[
5

_CO

NCA

[
1

]

FFF

RCE

[
D

]
[
9

]

]
[1

]

000

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

136

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

(
c

t
i
nu

)

ble

.

M

p of Pa

th Te

r
m

ina

t
or

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

I
P

[
D

]
[
3:

TRDI

[
D

]

r
v

TRDI

LMP

[
D

]

TRDIP_

UNEQ

INH[D]

TRDIP_LC

D[D]

I
NH[

RDI

SINH[D]

TRDIP_

ENH

_OR1B[D]

]

RRI

[
D

]

TJ1

I
NS

]

r
v

000

[
3

:
0

]

[
D

]
[
1

]

NTDH4Z3Z4

[
D

]
[
3

:
0

]

THx_S

[
D]

[
7

][1

]

CNTDZ5[

[
3

:
0

]

CNTDF2[

]
[
3

:
0

]

CNTDRDI

[
D]

[
3

:
0

]

CNTDC2[

]
[
3:

333

r
ov

t
er

eser

:0]

_PR

V_T

NUM[

:
0

]

000

RDI

PDI

2:0

]

SS[

Res

r
v

Res

r
v

000

eser

]

TF2DI

[
7

:
0

]

INS[

000

TZ3DI

[
7

:
0

]

INS[

000

TZ5DI

[
7

:
0

]

TZ4DI

[
7

:
0

]

000

l
F

il (S

)

B

R Al

r
i
t
h

m C

t
r
o

l

S

i
g

l
s

000

MSET

[
7

:
0

]

000

:
1

r
v

:
0

]

SET

[
15:

000

MCLE

AR[

]

LEAR[

:
0

]

000

T_S

[
18:

]

r
v

_SF

EAR[

:
0]

000

i
gn

r
ade

(

l
go

r
i
t
h

Con

t
r
o

l
S

i
g

l
s

000

0AD2

SDMS

]

SET

[
3

:
0

]

000

T_S

DNS

[
18:

]

r
v

_SDB

SET

[
11:

000

[
15

]

000

0AD5

MCLEA

[
7

:
0

]

SDLCLE

AR[

:
0

]

000

T_S

DNS

CLE

:
16]

r
v

DBCLE

11:

000

r
a

i
t
J1 Data

I
n

ser

t

Re

i
st

0AD8

NS[

]
[
7

:
0

]

1DI

]

000

0AD9

NS[

]
[
7

:
0

]

1DI

]

000

0AD

NS[

]
[
7

:
0

]

1DI

]

000

NS[

]
[
7

:
0

]

1DI

]

000

0ADC

NS[

]
[
7

:
0

]

INS[

][

000

[
1

[
7

:
0

]

[
1

]
[
7

:
0

]

000

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

137

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

(
c

t
i
nu

)

ble

.

M

p of Pa

th Te

r
m

ina

t
or

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

[
1

[
7

:
0

]

[
1

]
[
7

:
0

]

000

[
1

[
7

:
0

]

[
1

]
[
7

:
0

]

000

[
1

[
7

:
0

]

[
1

]
[
7

:
0

]

000

[
1

[
7

:
0

]

[
2

]
[
7

:
0

]

000

[
2

[
7

:
0

]

[
2

]
[
7

:
0

]

000

[
2

[
7

:
0

]

[
2

]
[
7

:
0

]

000

[
2

[
7

:
0

]

[
2

]
[
7

:
0

]

000

[
2

[
7

:
0

]

[
2

]
[
7

:
0

]

000

[
2

[
7

:
0

]

[
3

]
[
7

:
0

]

000

[
3

[
7

:
0

]

[
3

]
[
7

:
0

]

000

[
3

[
7

:
0

]

[
3

]
[
7

:
0

]

000

[
3

[
7

:
0

]

[
3

]
[
7

:
0

]

000

[
3

[
7

:
0

]

[
3

]
[
7

:
0

]

000

[
3

[
7

:
0

]

[
4

]
[
7

:
0

]

000

[
4

[
7

:
0

]

[
4

]
[
7

:
0

]

000

[
4

[
7

:
0

]

[
4

]
[
7

:
0

]

000

[
4

[
7

:
0

]

[
4

]
[
7

:
0

]

000

[
4

[
7

:
0

]

[
4

]
[
7

:
0

]

000

[
4

[
7

:
0

]

[
5

]
[
7

:
0

]

000

[
5

[
7

:
0

]

[
5

]
[
7

:
0

]

000

[
5

[
7

:
0

]

[
5

]
[
7

:
0

]

000

[
5

[
7

:
0

]

[
5

]
[
7

:
0

]

000

[
5

[
7

:
0

]

[
5

]
[
7

:
0

]

000

[
5

[
7

:
0

]

[
6

]
[
7

:
0

]

000

[
6

[
7

:
0

]

[
6

]
[
7

:
0

]

000

[
6

[
7

:
0

]

[
6

]
[
7

:
0

]

000

r
a

t
c

t
er

CRA

TCH[

:
0

]

000

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

138

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

DE Register

l
e

.

M

p of DE Re

gis

t
e

r
s

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

DE Macr

cel

l V

r
s

100

DE_V

ERSI

ON[

15:

000

t
e

t
s

100

DLMS

DEI

CH[

000

100

O an

I
N

T_S

I
NT_A

TMRxA

I
N

T_A

MRx

I
N

T_A

MRxF

000

100

Reser

000

sce

Reg

i
ster

100

/
W

Res

r
v

ESCA

PE[

002

100F

Reser

000

que

r

P

r
o

i
s

i
oni

ng Re

t
e

r
s

(R/

)

101

/
W

Reser

SEQ

000

101

/
W

I
N

I
T

_CNTS

221

101

/
W

_LO

043

101

/
W

OH_MA

KER_HI

002

101

/
W

H_MA

_LO

043

101

/
W

H_MA

002

r
e

/
I
n

r
es

f
ig

i
o

(
R

/
W

)

101

/
W

5:0

]
(B

its

15,

11,

7, 3 ar

r
e

r
v

ed)

444

101

/
W

5:0

]
(B

its

15,

11,

7, 3 ar

r
e

r
v

ed)

555

101

/
W

5:0

]
(B

its

15,

11,

7, 3 ar

r
e

r
v

ed)

666

101

/
W

5:0

]
(B

its

15,

11,

7, 3 ar

r
e

r
v

ed)

777

01A

[
1

] (B

its

15,

11,

7, 3 ar

r
e

r
v

ed)

444

01B

[
1

] (B

its

15,

11,

7, 3 ar

r
e

r
v

ed)

555

[
1

] (B

its

15,

11,

7, 3 ar

r
e

r
v

ed)

666

[
1

] (B

its

15,

11,

7, 3 ar

r
e

r
v

ed)

777

01E

[
1

] (B

its

15,

11,

7, 3 ar

r
e

r
v

ed)

444

101F

[
1

] (B

its

15,

11,

7, 3 ar

r
e

r
v

ed)

555

102

/
W

10[

15:

(Bit

,

1

,

7,

3 are re

r
v

)

666

102

/
W

11[

15:

(Bit

,

1

,

7,

3 are re

r
v

)

777

102

/
W

S0[

15:

(Bit

,

1

, 7,

3 are res

r
v

)

444

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

139

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

DE Register

(
c

ont

inu

ed)

ble

.

M

p of DE Re

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

102

/
W

S1[

15:

(Bit

,

1

, 7,

3 are res

r
v

)

555

102

/
W

S2[

15:

(Bit

,

1

, 7,

3 are res

r
v

)

666

102

/
W

S3[

15:

(Bit

,

1

, 7,

3 are res

r
v

)

777

102

/
W

S4[

15:

(Bit

,

1

, 7,

3 are res

r
v

)

444

102

/
W

S5[

15:

(Bit

,

1

, 7,

3 are res

r
v

)

555

102

/
W

S6[

15:

(Bit

,

1

, 7,

3 are res

r
v

)

666

102

/
W

S7[

15:

(Bit

,

1

, 7,

3 are res

r
v

)

777

02A

15:

(Bit

,

1

, 7,

3 are res

r
v

)

444

02B

15:

(Bit

,

1

, 7,

3 are res

r
v

)

555

, 11,

r
e res

r
v

ed)

666

, 11,

r
e res

r
v

ed)

777

r
a

t Mo

t
r
o

02E

_CT

15:

(Bit

,

1

, 12

, 11

, 9,

,
7,

5, 4,

3 are re

r
v

)

000

102F

[
1

:
0

] (B

its

15,

13,

12,

,

9

,
8,

,
5,

4, 3 ar

r
e

r
v

ed)

000

103

/
W

Rx_CHCD_FM[

15:

,

14

,
7 6 are

r
e

ser

ed)

000

103

/
W

_CHAB_

5:0

]
(B

its

15,

14,

r
e res

r
v

)

000

r
C

l
l
St

t
e

103

/
W

Res

r
v

_CE

LL[

M[9

:
0

]

000

103

/
W

Res

r
v

_CE

LL[

M[9

:
0

]

000

103

/
W

Res

r
v

_CEL

L[C]

000

103

/
W

Res

r
v

_CEL

L[D]

000

103

/
W

Res

r
v

_SE

I
S

]

00F

103F

Reser

000

r
ess P

l
o

t
r
o

104

/
W

Res

r
v

L_0[

]

070

104

/
W

Res

r
v

L_1[

]

070

104

/
W

Res

r
v

L_2[

]

070

104

/
W

Res

r
v

L_3[

]

070

107F

Reser

000

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

140

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

DE Register

(
c

ont

inu

ed)

ble

.

M

p of DE Re

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

M F

r
am

i
s

t
er

I
d

t
c

ask

108

/
W

M_IDM_

31:

16]

FFF

108

/
W

M_I

M_0

[
1

:
0

]

FFF

108

/
W

M_IDM_

31:

16]

FFF

108

/
W

M_I

M_1

[
1

:
0

]

FFF

108

/
W

M_IDM_

31:

16]

FFF

108

/
W

M_I

M_2

[
1

:
0

]

FFF

108

/
W

M_IDM_

31:

16]

FFF

108

/
W

M_I

M_3

[
1

:
0

]

FFF

I
d

i
s

t
e

108

/
W

M_I

DC_0[

000

108

/
W

M_I

15:

000

08A

M_I

DC_1[

000

08B

M_I

15:

000

M_I

DC_2[

000

M_I

15:

000

08E

M_I

DC_3[

000

108F

M_I

15:

000

Una

ssi

Cel

l
Ma

h Ma

109

/
W

M_USM_

0[3

:
16]

FFF

109

/
W

USM_0[

]

FFF

109

/
W

M_USM_

1[3

:
16]

FFF

109

/
W

USM_1[

]

FFF

109

/
W

M_USM_

2[3

:
16]

FFF

109

/
W

USM_2[

]

FFF

109

/
W

M_USM_

3[3

:
16]

FFF

109

/
W

USM_3[

]

FFF

assi

Reg

i
s

t
er

109

/
W

G_0

[
31

000

109

/
W

M_USG

_0[

15:

000

09A

G_1

[
31

000

09B

M_USG

_1[

15:

000

G_2

[
31

000

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

141

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

DE Register

(
c

ont

inu

ed)

ble

.

M

p of DE Re

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

M_USG

_2[

15:

000

09E

G_3

[
31

000

109F

M_USG

_3[

15:

000

M S

r
a

l
e

r
F

r
am

t
ate

r
v

_0[

000

r
v

_1[

000

r
v

_2[

000

r
v

_3[

000

r
am

e Co

t
r
o

l Reg

i
ster

M Recei

f
i
g

r
a

t
io

M_X4

11:

01C6

M_X3

11:

01C8

M_X

31V

W[1

:
0

]

021

X31

XY[

:0]

041

]

ASK

:0]

00F

10A

/
W

Res

r
v

_MAS

3:0

]

00F

10A

/
W

Res

r
v

M_Rx

_DE

G_RE

003

10A

Reser

000

M T

r
an

i
t

Co

t
r
o

l
Reg

i
s

t
er

PP A

tta

/
W

[
0]

000

/
W

[
1]

000

/
W

[
2]

000

/
W

[
3]

000

10B4

10DF

Reser

000

r
ess P

l
o

t
r
o

[
0

]
[
10

]

070

[
1

]
[
10

]

070

[
2

]
[
10

]

070

[
3

]
[
10

]

070

10E4

Reser

000

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

142

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

DE Register

(
c

ont

inu

ed)

ble

.

M

p of DE Re

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

PP D

10F

/
W

Rx_HDR0[

]
[
15

:
0

]

000

10F

/
W

Rx_HDR0[

]
[
15

:
0

]

000

10F

/
W

Rx_HDR0[

]
[
15

:
0

]

000

10F

/
W

Rx_HDR0[

]
[
15

:
0

]

000

10F

/
W

Rx_HDR0[

]
[
15

:
0

]

000

10F

/
W

Rx_HDR0[

]
[
15

:
0

]

000

10F

/
W

Rx_HDR0[

]
[
15

:
0

]

000

10F

/
W

Rx_HDR0[

]
[
15

:
0

]

000

10F

/
W

Rx_HDR0[

]
[
15

:
0

]

000

10F

/
W

Rx_HDR0[

]
[
15

:
0

]

000

Rx_HDR0[

10]

[
15:

000

Rx_HDR0[

11]

[
15:

000

10F

/
W

P_Rx

_CHK_

[
0]

[
15:

C001

10F

/
W

P_Rx

_CHK_

[
1]

[
15:

C002

P_Rx

_CHK_

[
2]

[
15:

C004

/
W

P_Rx

_CHK_

[
3]

[
15:

C008

HDLC/

L Fra

r
Condi

Counte

r
1

MRS

Upda

)

110

PM_F

C1_

[
27:

16]

000

110

C1_0

[15

:
0

]

000

110

PM_F

C1_

[
27:

16]

000

110

C1_1

[15

:
0

]

000

110

PM_F

C1_

[
27:

16]

000

110

C1_2

[15

:
0

]

000

110

PM_F

C1_

[
27:

16]

000

110

C1_3

[15

:
0

]

000

HDLC/

L Fra

r
Condi

Counte

r
2

MRS

Upda

)

110

PM_F

C2_

[
27:

16]

000

110

C2_0

[15

:
0

]

000

10A

Res

r
v

PM_F

C2_

[
27:

16]

000

10B

C2_1

[15

:
0

]

000

Res

r
v

PM_F

C2_

[
27:

16]

000

C2_2

[15

:
0

]

000

10E

Res

r
v

PM_F

C2_

[
27:

16]

000

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

143

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

DE Register

(
c

ont

inu

ed)

ble

.

M

p of DE Re

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

543210

110F

C2_3

[15

:
0

]

000

CRC Ch

ker

t
Counte

r
(

MRS

Upd

)

111

PM_B

PC_0

16]

000

111

PM_B

PC_0[

:0]

000

111

PM_B

PC_1

16]

000

111

PM_B

PC_1[

:0]

000

111

PM_B

PC_2

16]

000

111

PM_B

PC_2[

:0]

000

111

PM_B

PC_3

16]

000

111

PM_B

PC_3[

:0]

000

P D

atc

Head

r
Co

t
e

r

(P

MRST

t
e

)

111

PM_MHC_

0[2

:
16]

000

111

_MHC_0[

]

000

11A

Res

r
v

PM_MHC_

1[2

:
16]

000

11B

_MHC_1[

]

000

Res

r
v

PM_MHC_

2[2

:
16]

000

_MHC_2[

]

000

11E

Res

r
v

PM_MHC_

3[2

:
16]

000

111F

_MHC_3[

]

000

i
v

acke

t
/
C

r

(
P

t
e

)

112

M_G

C_Rx

16]

000

112

PC_Rx

_0[

]

000

112

M_G

C_Rx

16]

000

112

PC_Rx

_1[

]

000

112

M_G

C_Rx

16]

000

112

PC_Rx

_2[

]

000

112

M_G

C_Rx

16]

000

112

PC_Rx

_3[

]

000

r
a

i
t

G

t
/
C

l
l
Counte

r

(
P

MRS

Upd

)

112

M_GP

C_T

_0[

27:

]

000

112

[
15

]

000

12A

Res

r
v

_GP

_1[

27:

]

000

12B

[
15

]

000

Res

r
v

_GP

_2[

27:

]

000

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

144

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

DE Register

(
c

ont

inu

ed)

ble

.

M

p of DE Re

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

[
15

]

000

12E

Res

r
v

_GP

_3[

27:

]

000

112F

[
15

]

000

117F

Reser

000

I
n

ter

r
upts and

sks f

r
P

ket Counter

118

/
W

Res

r
v

NTM[

]

01F

118

OR/

Res

r
v

NT[

]

000

118

/
W

Res

r
v

NTM[

]

01F

118

OR/

Res

r
v

NT[

]

000

118

/
W

Res

r
v

NTM[

]

01F

118

OR/

Res

r
v

NT[

]

000

118

/
W

Res

r
v

NTM[

]

01F

118

OR/

Res

r
v

NT[

]

000

Reser

000

r
an

i
t

R

t
er

120

/
W

NUL

LCELL

[
0

][

]

000

120

/
W

NUL

LCELL

[
1

][

]

000

120

/
W

NUL

LCELL

[
2

][

]

000

120

/
W

NUL

LCELL

[
3

][

]

000

120F

Reser

000

121

/
W

NUL

LCELL

[
0

][

]

000

121

/
W

NUL

LCELL

[
1

][

]

000

121

/
W

NUL

LCELL

[
2

][

]

000

121

/
W

NUL

LCELL

[
3

][

]

000

Reser

000

12F

/
W

Res

r
v

ADER_

]

000

12F

Reser

000

Data Sheet

TDAT042G5 SONET/SDH

May 2001

155/622/2488 Mbits/s Data Interface

145

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

DE Register

(
c

ont

inu

ed)

ble

.

M

p of DE Re

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

L R

i
v

egi

t
er

140

SDL_

][

000

140

SDL_

][

000

140

SDL_

][

000

140

SDL_

][

000

146F

Reser

000

147

L_A

MM1[

][

]

000

147

L_A

MM1[

][

]

000

147

L_A

MM1[

][

]

000

147

L_A

MM1[

][

]

000

147F

Reser

000

148

L_A

MM2[

][

]

000

148

L_A

MM2[

][

]

000

148

L_A

MM2[

][

]

000

148

L_A

MM2[

][

]

000

148F

Reser

000

149

L_A

MM3[

][

]

000

149

L_A

MM3[

][

]

000

149

L_A

MM3[

][

]

000

149

L_A

MM3[

][

]

000

149F

Reser

000

L_B

MM1[

][

]

000

L_B

MM1[

][

]

000

L_B

MM1[

][

]

000

L_B

MM1[

][

]

000

14A4

Reser

000

L_B

MM2[

][

]

000

L_B

MM2[

][

]

000

L_B

MM2[

][

]

000

L_B

MM2[

][

]

000

TDAT042G5 SONET/SDH

Data Sheet

155/622/2488 Mbits/s Data Interface

May 2001

146

Agere Systems Inc.

Regis

t
er Maps

(
c

tin

ued

)

DE Register

(
c

ont

inu

ed)

ble

.

M

p of DE Re

gis

t
e

r
s

(

tin

ued)

Addre

(
H

ex)

O),

(R/W),

O),

(COR/W)

t
N

Defa

l
u

(
H

ex)

9876

5432

14B4

Reser

000

SDL_

BMM[

_3[

15:

000

SDL_

BMM[

_3[

15:

000

SDL_

BMM[

_3[

15:

000

SDL_

BMM[

_3[

15:

000

14CF

Reser

000

INT

[
0

]
[
7

:
0

]
(Bi

t
3 is

r
e

r
v

ed)

INT

[
1

]
[
7

:
0

]
(Bi

t
3 is

r
e

r
v

ed)

INT

[
2

]
[
7

:
0

]
(Bi

t
3 is

r
e

r
v

ed)

INT

[
3

]
[
7

:
0

]
(Bi

t
3 is

r
e

r
v

ed)

14DF

Reser

000

INT

[
0]

] (Bi

t
3 is

r
e

r
v

ed)

000

INT

[
1]

] (Bi

t
3 is

r
e

r
v

ed)

000

INT

[
2]

] (Bi

t
3 is

r
e

r
v

ed)

000

INT

[
3]

] (Bi

t
3 is

r
e

r
v

ed)

000

14E4

Reser

000

14F

/
W

Res

r
v

L_DE

L
T

:0]

000

14F

Reser

000

L T

r
an

t
er

160

/
W

SDLF

I
_

MSG

[
15:

000

160

/
W

SDLF

I
_

MSG

[
15:

000

160

/
W

SDLF

I
_

MSG

[
15:

000

160

/
W

SDL

Reser

SDL

CHID[1

:
0

]

000

160

/
W

[
1

:
0

]

000

160

/
W

SDLSMIE

Res

r
v

LSC

SDL

800

160

/
W

Reser

SDL

000

160

/
W

Res

r
v

SDL

LPE

[
1

:
0

]

LECI

D[1

:
0

]

000

Agere Systems Inc.

147

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

Core Registers

This section gives a brief description of each register bit and its functionality. All algorithms are described in the
main text of the document. The abbreviations after each register indicate if the register is read only (RO), read/
write (R/W), write only (WO), or clear-on-read or clear-on-write (COR/W).

Required Provisioning Sequence and Clocks

0x indicates a hexadecimal value in the Reset Default column. Otherwise, the entry is binary. This is true for every
register table in the document.

Table 41. Register 0x0000: Device Version (RO)

Reset default of register = 0x0100.

Table 42. Registers 0x0001--0x0005: Device Name (RO)

Reset default of each register is shown below.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0000

15--8

DEVICE_VERSION[7:0] Device Version Number. Device version register will

change each time the device is changed.

0x01

1. 0x02 for version 1A.

7--0

Reserved.

0x00

Address

(Hex)

Bit #

Name

Function

Reset

Default

0001

15--0

ASCII_NAME_TD

Device ASCII Name. Value = T, D.

0x5444

0002

15--0

ASCII_NAME_AT

Device ASCII Name. Value = A, T.

0x4154

0003

15--0

ASCII_NAME_04

Device ASCII Name. Value = 0, 4.

0x3034

0004

15--0

ASCII_NAME_2G

Device ASCII Name. Value = 2, G.

0x3247

0005

15--0

ASCII_NAME_5CR

Device ASCII Name. Value = 5, CR.

0x350D

148

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

Core Registers

(continued)

Table 43. Register 0x0008: Composite Interrupts (RO or COR/W)

Reset default of register = 0x0000.

Table 44. Register 0x000A: GPIO Input (RO)

Reset default of register = 0x000x (x not determined).

Address

(Hex)

Bit #

Name

Function

Reset

Default

0008

PMRSTI

Performance Monitor Reset Interrupt. Active-high
signal indicating a 1 second event has occurred.
This bit is COR/W.

14--12

Reserved. These bits must be written to their reset
default value (000).

000

11--8

GPIO[3:0]I

General-Purpose Interrupt. Signal indicating the
associated input is active. When the GPIO are out-
puts, this signal will be forced low. These interrupts
are COR/W when the interrupt is programmed to
the positive edge mode; otherwise, this is a read-
only (RO) location.

0x0

UTI

UTOPIA Composite Interrupt. Active-high signal
indicating an unmasked delta or event is active in
the UTOPIA block. This bit is RO.

DEI

Data Engine Composite Interrupt. Active-high
signal indicating an unmasked delta or event is
active in the data engine block. This bit is RO.

5--2

Reserved. These bits must be written to their reset
default value (0000).

0000

PTI

Path Terminator Composite Interrupt. Active-high
signal indicating an unmasked delta or event is
active in the path terminator block. This bit is RO.

OHPI

Overhead Processor Composite Interrupt.
Active-high signal indicating an unmasked delta or
event is active in the overhead processor block.
This bit is RO.

Address

(Hex)

Bit #

Name

Function

Reset

Default

000A

15--4

Reserved. These bits must be written to their reset
default value (0x000).

0x000

3--0

GPIO[3:0]_INPUT_VALUE General-Purpose Input Value. These are the logi-

cal values of the GPIO[3:0] I/O pins.

Value

Agere Systems Inc.

149

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

Core Registers

(continued)

Table 45. Register 0x000C: Block Interrupt Masks (R/W)

Reset default of register = 0xFFFF.

Table 46. Register 0x000E: Core Resets (WO)

Address

(Hex)

Bit #

Name

Function

Reset

Default

000C

PMRSTM

Performance Monitor Reset Mask. When set to 1,
the associated composite interrupt bit will be inhib-
ited (masked) from contributing to the interrupt pin
(INT).

14--12

Reserved. These bits must be written to their reset
default value (111).

111

11--8

GPIO[3:0]IM

General-Purpose Interrupt Mask. When set to 1,
the associated composite interrupt bits will be inhib-
ited (masked) from contributing to the interrupt pin
(INT).

0xF

UTIM

UTOPIA Composite Interrupt Mask. When set to
1, the associated composite interrupt bit will be
inhibited (masked) from contributing to the interrupt
pin (INT).

DEIM

Data Engine Composite Interrupt Mask. When
set to 1, the associated composite interrupt bit will
be inhibited (masked) from contributing to the inter-
rupt pin (INT).

5--2

Reserved. These bits must be written to their reset
default value (1111).

1111

PTIM

Path Terminator Composite Interrupt Mask.
When set to 1, the associated composite interrupt
bit will be inhibited (masked) from contributing to
the interrupt pin (INT).

OHPIM

Overhead Processor Composite Interrupt Mask.
When set to 1, the associated composite interrupt
bit will be inhibited (masked) from contributing to
the interrupt pin (INT).

Address

(Hex)

Bit #

Name

Function

Reset

Default

000E

15--8

Reserved.

PMRST

Performance Monitor Reset. When this bit is set
to 1, the PMRST signal goes high. The register will
automatically be reset to 0, and the PMRST signal
will go low after 500 ms.

6--3

Reserved.

2--0

SWRST

Software Reset. When a binary value of 101 is
written to this register, it will create a software reset
of the device. This reset has the same effect as the
hardware reset. All microprocessor registers are
reset to their default states, and all internal data
path state machines are reset.

150

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

Core Registers

(continued)

Table 47. Register 0x000F: GPIO Output (R/W)

Reset default of register = 0x0000.

Provisioning Registers

Table 48. Register 0x0010: Line Provisioning/Mode (R/W)

Reset default of register = 0x1070.

Address

(Hex)

Bit #

Name

Function

Reset

Default

000F

15--4

Reserved. These bits must be written to their reset
default value (0x000).

0x000

3--0

GPIO[3:0]_OUTPUT_VALUE General-Purpose Output Values. The value writ-

ten into these bits will appear on the GPIO[3:0] pins.

0x0

Address

(Hex)

Bit #

Name

Function

Reset

Default

0010

15--13

Reserved. These bits must be written to their reset
default value (000).

000

POF_POS

Packet/ATM Over Fiber/SONET. 0 = packet or ATM
over fiber (POF); 1 = packet or ATM over SONET
(POS).

11--10

Reserved. These bits must be written to their reset
default value (00).

9--8

PMMODE[1:0]

Performance Monitoring Mode.
00 or 10 = PMRST comes from external pin.
01 = PMRST comes from internal 1-second counter.
11 = PMRST is software controlled.

SDH/SONET

SDH or SONET Mode. 1 = SDH; 0 = SONET.

COR/W

Clear-on-Read or Clear-on-Write Control. This bit
sets the functionality of the COR/W registers.

1 = COR. Clear on read; read register to clear.
0 = COW. Clear on write; write 1 to clear.

COW mode will clear bits to which a 1 is written. Bits
written to 0 are not cleared.

PLL_MODE

PLL Mode. Control for STS-48/STM-16 mode only.
This bit controls the transmit line clock PLL. For
STS-48/STM-16 contra-clocking mode, this PLL
must be active, i.e., the bit = 0.
1 = PLL off (inactive)
0 = PLL on (active)

STS48

STS-48/STM-16 Control. 1 = STS-48/STM-16
mode; 0 = STS-3/STS-12 (STM-1/STM-4) mode.

3--0

STS12[A--D]

STS-12/STS-3 (STM-4/STM-1) Mode Control.
The only values permitted are the following:
1111 = STS-12/STM-4
0000 = STS-3/STM-1

0x0

Agere Systems Inc.

151

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

Core Registers

(continued)

Provisioning Registers (continued)

Table 49. Register 0x0011: Channel (A--D) Control (R/W)

Reset default of register = 0x0000.

Table 50. Register 0x0012: Loopback Control (R/W)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0011

EQ_CH_A

Equip Channel A. 1 = enable; 0 = disable, i.e., turns off
clock in Rx direction, except in the STS-48/STM-16
mode. This function is valid only for STS-12/STM-4 and
STS-3/STM-1 modes (no effect in Tx direction).

14--12

Reserved. These bits must be written to their reset
default value (000).

000

EQ_CH_B

Equip Channel B. 1 = enable; 0 = disable, i.e., turns off
clock in Rx direction, except in the STS-48/STM-16
mode. This function is valid only for STS-12/STM-4 and
STS-3/STM-1 modes (no effect in Tx direction).

10--8

Reserved. These bits must be written to their reset
default value (000).

000

EQ_CH_C

Equip Channel C. 1 = enable; 0 = disable, i.e., turns off
clock in Rx direction, except in the STS-48/STM-16
mode. This function is valid only for STS-12/STM-4 and
STS-3/STM-1 modes (no effect in Tx direction).

6--4

Reserved. These bits must be written to their reset
default value (000).

000

EQ_CH_D

Equip Channel D. 1 = enable; 0 = disable, i.e., turns off
clock in Rx direction, except in the STS-48/STM-16
mode. This function is valid only for STS-12/STM-4 and
OSTS-3/STM-1 modes (no effect in Tx direction).

2--0

Reserved. These bits must be written to their reset
default value (000).

000

Address

(Hex)

Bit #

Name

Function

Reset

Default

0012

15--12

LOOPBACK[3:0]_

CH_A

Loopback Control. Only the following combinations
are valid:

0000 = no loopbacks
0001 = SONET facility loopback
0010 = SONET terminal loopback
0100 = UTOPIA far-end loopback
1000 = UTOPIA near-end loopback

SONET facility loopback is only available in STS-3/
STM-1 and STS-12/STM-4 modes.

0x0

11--8

LOOPBACK[3:0]_

CH_B

0x0

7--4

LOOPBACK[3:0]_

CH_C

0x0

3--0

LOOPBACK[3:0]_

CH_D

0x0

152

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

Core Registers

(continued)

Provisioning Registers (continued)

Table 51. Register 0x0013: GPIO Mode (R/W)

Reset default of register = 0x0000.

Table 52. Registers 0x0014, 0x0015: GPIO Output Configuration

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0013

PMRST_I/O_CTRL

PMRST I/O Control. This bit is set to 1 to make
PMRST an output.

14--12

Reserved. These bits must be written to their reset
default value (000).

000

11--8

GPIO[3:0]_INTERRUPT_

ACTIVE_H/L

GPIO Interrupt Active State.
0 = report received value unchanged (level = input pin
value, positive edge = 1 when signal rises).

1 = invert received value (level = invert input pin value,
positive edge = 0 when detected).

0x0

7--4

GPIO[3:0]_INTERRUPT_

LEVEL/EDGE

GPIO Interrupt Type. 0 = positive edge; 1 = level.

0x0

3--0

GPIO[3:0]_DIRECTION_

I/O

GPIO Direction Control. 0 = input; 1 = output.

0x0

Address

(Hex)

Bit #

Name

Function

Reset

Default

0014

GPIO[1:0]_OC

GPIO[1:0] Output Configuration.

0x0000

15--9

Reserved. These bits must be written to their reset
default value (0000000).

0000

000

GPIO[1]_OC

GPIO[1] Output Configuration. Set this bit to 1 to
activate the output of the corresponding GPIO pin.

7--1

Reserved. These bits must be written to their reset
default value (0000000).

0000

000

GPIO[0]_OC

GPIO[0] Output Configuration. Set this bit to 1 to
activate the output of the corresponding GPIO pin.

0015

GPIO[3:2]_OC

GPIO[3:2] Output Configuration.

0x0000

15--9

Reserved. These bits must be written to their reset
default value (0000000).

0000

000

GPIO[3]_OC

GPIO[3] Output Configuration. Set this bit to 1 to
activate the output of the corresponding GPIO pin.

7--1

Reserved. These bits must be written to their reset
default value (0000000).

0000

000

GPIO[2]_OC

GPIO[2] Output Configuration. Set this bit to 1 to
activate the output of the corresponding GPIO pin.

154

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

UT Registers

This section gives a brief description of each register bit and its functionality. All algorithms are described in the
main text of the document. The abbreviations after each register indicate if the register is read only (RO), read/write
(R/W), write only (WO), or clear-on-read or clear-on-write (COR/W).

0x indicates a hexadecimal value in the Reset Default column. Otherwise, the entry is binary. This is true for every
register table in the document.

Version Control

Table 54. Register 0x0200: UT Macrocell Version Number (RO)

Reset default of register = 0x0000.

Interrupt

Table 55. Register 0x0201: UT Interrupt (RO)

Reset default of register = 0x0000.

Note: These registers are cleared by accessing registers 0x0202, 0x0203, 0x0204, 0x0205.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0200

15--8

Reserved. These bits must be written to their
reset default value (0x00).

0x00

7--0

UT_VERSION[7:0]

UT Macrocell Version Number. The version of
the macrocell will increment each time a
change occurs to the macrocell functionality.

0x00

Address

(Hex)

Bit #

Name

Function

Reset

Default

0201

15--4

Reserved. These bits must be written to their
reset default value (0x000).

0x000

UT_INT[D]

UT Interrupt for Channel D. If this bit is set to
1, it indicates one of the interrupt conditions for
channel D occurred.

0x0

UT_INT[C]

UT Interrupt for Channel C. If this bit is set to
1, it indicates one of the interrupt conditions for
channel C occurred.

UT_INT[B]

UT Interrupt for Channel B. If this bit is set to
1, it indicates one of the interrupt conditions for
channel B occurred.

UT_INT[A]

UT Interrupt for Channel A. If this bit is set to
1, it indicates one of the interrupt conditions for
channel A occurred.

156

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

UT Registers

(continued)

Interrupt Mask Parameters (R/W)

Table 57. Register 0x0206: Interrupt Mask (R/W)

Reset default of register = 0x000F.

Table 58. Registers 0x0207, 0x0208, 0x0209, 0x020A: Interrupt Mask--Channel [A--D] (R/W)

Reset default of registers = 0x000F.

Error Counters in PMRST Mode (RO)

Table 59. Register 0x020B: Channel [A--D] Error Count in PMRST Mode (RO)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0206

15--4

Reserved. These bits must be written to their
reset default value (0x000).

0x000

INTM[D]

Interrupt Mask D. If set to 1, masks any inter-
rupts from channel D.

0xF

INTM[C]

Interrupt Mask C. If set to 1, masks any inter-
rupts from channel C.

INTM[B]

Interrupt Mask B. If set to 1, masks any inter-
rupts from channel B.

INTM[A]

Interrupt Mask A. If set to 1, masks any inter-
rupts from channel A.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0207, 0208,

0209, 020A

15--4

Reserved. These bits must be written to their
reset default value (0x000).

0x000

FIFO_OVERFLOW_Tx_

MASK[A

--D]

FIFO Overflow Transmit Mask [A--D]. If set,
masks this interrupt from setting Int[A--D].

0xF

FIFO_UNDERFLOW_Tx_

MASK[A

--D]

FIFO Underflow Transmit Mask [A--D]. If set,
masks this interrupt from setting Int[A--D].

FIFO_OVERFLOW_Rx_

MASK[A

--D]

FIFO Overflow Receive Mask [A--D]. If set,
masks this interrupt from setting Int[A--D].

PARITY_ERROR_Tx_

MASK[A--D]

Parity Error Transmit Mask [A--D]. If set,
masks this interrupt from setting Int[A--D].

Address

(Hex)

Bit #

Name

Function

Reset

Default

020B--020E

15--0

PMRST_PECTx[A--D]

PMRST Parity Error Count Transmit
Channel [A--D]. Counts the number of parity
errors that occur for Tx channel [A--D], based
upon the PMRST interval.

0x0000

158

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

UT Registers

(continued)

UT Provisioning Registers (R/W) (continued)

Table 61. Registers 0x020F, 0x0213, 0x0217, 0x021B: Channel [A--D] Receive Provisioning Register (R/W)

Reset default of register 0x020F = 0x0020.
Reset default of register 0x0213 = 0x0120.
Reset default of register 0x0217 = 0x0220.
Reset default of register 0x021B = 0x0320.

Address

(Hex)

Bit #

Name

Function

Reset

Default

020F, 0213,
0217, 021B

POLLING_ENB_Rx

[A--D]

Polling Enable Receive Channel [A--D]. If
set to 1, receive polling mode is enabled.

14--13

Reserved. These bits must be written to their
reset default value (00).

12--8

RxADDR_A[4:0]

Polling Receive Address Channel [A--D].
Receive polling address.

00000

RxADDR_B[4:0]

00001

RxADDR_C[4:0]

00010

RxADDR_D[4:0]

00011

Reserved. This bit must be written to its reset
default value (0).

CLOCK_MODE_Rx

[A--D]

Clock Mode Receive Channel [A--D].
Defines if the RxCLK[A--D] is sourced or sunk.
If this bit = 1, the clock is sourced, and then
(1) the corresponding Tx clock is used as
RxCLK[A--D], and (2) this clock is also sent out
of the device via RxCLK[A--D].

If this bit = 0, CLOCK_MODE_Rx[A--D] is
sunk, and then RxCLK[A--D] acts as an input.
Default is sink.

PARITY_Rx[A--D]

Parity Receive Channel [A--D]. Defines if odd
(bit = 1) or even (bit = 0) parity is generated for
the data transmitted across the UTOPIA PHY
Rx interface. Default is odd.

ATM_SIZE_Rx[A--D]

ATM Packet Size Receive Channel [A--D].
Defines how many bytes are received per ATM
cell. Default is 53 bytes. Valid only when traffic
type is ATM cells.

Page 86 and page 87 give details of the func-
tion of this bit.

0 = standard 53-byte (also 54-byte and 56-byte)
ATM cell modes.
1 = 52-byte ATM cell mode (HEC omitted).

TRAFFIC_TYPE_Rx

[A--D]

Traffic Type Receive Channel [A--D]. Config-
ures channel to receive either ATM cells or
packets.

Bit Value

Traffic Type

packets (default)

ATM cells

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

UT Registers

(continued)

UT Provisioning Registers (R/W) (continued)

Table 61. Registers 0x020F, 0x0213, 0x0217, 0x021B: Channel [A--D] Receive Provisioning Register (R/W)

(continued)

Reset default of register 0x020F = 0x0020.
Reset default of register 0x0213 = 0x0120.
Reset default of register 0x0217 = 0x0220.
Reset default of register 0x021B = 0x0320.

*The value 000 for these bits places the corresponding UTOPIA outputs in the high-impedance state.

Table 62. Registers 0x0210, 0x0214, 0x0218, 0x021C: Channel [A--D] Transmit Provisioning Register (R/W)

Reset default of register 0x0210 = 0x0000.
Reset default of register 0x0214 = 0x0120.
Reset default of register 0x0218 = 0x0220.
Reset default of register 0x021C = 0x0320.

Address

(Hex)

Bit #

Name

Function

Reset

Default

020F, 0213,
0217, 021B

2--0

UTOPIA_MODE_Rx

[A--D][2:0]

UTOPIA Mode Receive Channel [A--D]. Con-
figures the Rx channel mode.

Mode

Bit Value

disabled (idle)* bits[2:0] = 000
U2

bits[2:0] = 001

U2+

bits[2:0] = 010

U3, 8-bit

bits[2:0] = 011

U3, 32-bit

bits[2:0] = 100

U3+, 8-bit

bits[2:0] = 101

U3+, 32-bit

bits[2:0] = 110

invalid

bits[2:0] = 111

U3 configuration also requires the appropriate
setting of register 0x0225 (PA response) to be
set for a two-cycle response.

000

Address

(Hex)

Bit #

Name

Function

Reset

Default

0210, 0214,

0218, 021C

POLLING_ENB_Tx

[A--D]

Polling Enable Transmit Channel [A--D]. If
set, transmit polling mode is enabled.

14--13

Reserved. These bits must be written to their
reset default value (00).

12--8

TxADDR_A[4:0]

Polling Transmit Address Channel [A--D].
Transmit polling address.

00000

TxADDR_B[4:0]

00001

TxADDR_C[4:0]

00010

TxADDR_D[4:0]

00011

7--6

Reserved. These bits must be written to their
reset default value (00).

160

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

UT Registers

(continued)

UT Provisioning Registers (R/W) (continued)

Table 62. Registers 0x0210, 0x0214, 0x0218, 0x021C: Channel [A--D] Transmit Provisioning Register (R/W)

(continued)

Reset default of register 0x0210 = 0x0000.
Reset default of register 0x0214 = 0x0120.
Reset default of register 0x0218 = 0x0220.
Reset default of register 0x021C = 0x0320.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0210, 0214,

0218, 021C

PARITY_Tx[A]

Parity Transmit Channel [A--D]. Defines if
odd (bit = 1) or even (bit = 0) parity is generated
for the data transmitted across the UTOPIA
PHY Tx interface. Default is even for channel A
and odd for channels B, C, and D.

PARITY_Tx[B--D]

ATM_SIZE_Tx[A--D]

ATM Packet Size Transmit Channel [A--D].
Defines how many bytes are transmitted per
ATM cell. Default is 53 bytes. Valid only when
traffic type is ATM cells.

Page 86 and page 87 give details of the func-
tion of this bit.

0 = standard 53-byte (also 54-byte and 56-byte)
ATM cell modes.
1 = 52-byte ATM cell mode (HEC omitted).

TRAFFIC_TYPE_Tx

[A--D]

Traffic Type Transmit Channel [A--D]. Con-
figures channel to transmit either ATM cells or
packets.

Bit Value

Traffic Type

packets (default)

ATM cells

2--0

UTOPIA_MODE_Tx

[A--D][2:0]

UTOPIA Mode Transmit Channel [A--D].
Configures the Tx channel mode.

Mode

Bit Value

disabled (idle)

bits[2:0] = 000

bits[2:0] = 001

U2+

bits[2:0] = 010

U3, 8-bit

bits[2:0] = 011

U3, 32-bit

bits[2:0] = 100

U3+, 8-bit

bits[2:0] = 101

U3+, 32-bit

bits[2:0] = 110

invalid

bits[2:0] = 111

U3 configuration also requires appropriate set-
ting of register 0x0225 (PA response) to be set
for a two-cycle response.

000

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

UT Registers

(continued)

UT Provisioning Registers (R/W) (continued)

Table 63. Registers 0x0211, 0x0215, 0x0219, 0x021D: Channel [A--D] Ingress Provisioning Register (R/W)

Reset default of registers = 0x361F.

Table 64. Registers 0x0212, 0x0216, 0x021A, 0x021E: Channel [A--D] Egress Provisioning Register (R/W)

Reset default of registers = 0x361F.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0211, 0215,

0219, 021D

15--14

Reserved. These bits must be written to their
reset default value (00).

13--8

INGRESS_WATERMARK

_HIGH_[A--D][6:0]

Ingress Watermark High for Channel
[A--D]. Defines threshold before which over-
flow is detected causing a head of FIFO dis-
card; data in the receive FIFO will be discarded
down to the next start of packet/cell.

110110

7--6

Reserved. These bits must be written to their
reset default value (00).

5--0

INGRESS_WATERMARK

_LOW_[A--D][6:0]

Ingress Watermark Low for Channel [A--D].
Defines how many words must be stored in the
ingress FIFO before transmission out of the
UTOPIA port, if an end of packet is not
received.

011111

Address

(Hex)

Bit #

Name

Function

Reset

Default

0212, 0216,
021A, 021E

15--14

Reserved. These bits must be written to their
reset default value (00).

13--8

EGRESS_WATERMARK_

HIGH_[A--D][6:0]

Egress Watermark High for Channel [A--D].
Defines how many words can be stored into the
egress FIFO before backpressure is applied to
the UTOPIA PHY Tx port to stop acceptance of
more traffic. Default value is set for packet
transfer. For ATM transfer, the value should be
configured as 0x29. For packet mode, this value
depends upon the specific user-interface char-
acteristics. The default value (110110) will work
for packet mode.

110110

7--6

Reserved. These bits must be written to their
reset default value (00).

5--0

EGRESS_WATERMARK_

LOW_[A--D][6:0]

Egress Watermark Low for Channel [A--D].
Defines how many words must be stored in the
egress FIFO before transmission to the data
engine, if an end of packet is not received.

011111

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Data Sheet

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

UT Registers

(continued)

Reset Register (R/W)

Table 65. Register 0x021F: Reset Register (R/W)

Reset default of register = 0x00FF.

Error Count Registers (RO)

Table 66. Register 0x0220: Channel [A--D] Error Count (RO)

Reset default of register = 0x0000.

Scratch Register (R/W)

Table 67. Register 0x0224: UT_Scratch Register (R/W)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

021F

UT_ARST

UTOPIA Asynchronous Reset. Active-high
signal. This must be the last signal written to
the UTOPIA interface during configuration and
must be written to the value 0x00 to enable the
particular channels.

0x00FF

15--8

Reserved. These bits must be written to their
reset default value (0x00).

0x00

UT_TxARST_D

Transmit ARST for Transmit Channel D.

UT_TxARST_C

Transmit ARST for Transmit Channel C.

UT_TxARST_B

Transmit ARST for Transmit Channel B.

UT_TxARST_A

Transmit ARST for Transmit Channel A.

UT_RxARST_D

Receive ARST for Receive Channel D.

UT_RxARST_C

Receive ARST for Receive Channel C.

UT_RxARST_B

Receive ARST for Receive Channel B.

UT_RxARST_A

Receive ARST for Receive Channel A.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0220--0223

15--0

PECTx[A--D]

Parity Error Count Transmit Channel [A--D].
Counts the instantaneous (real-time) number of
parity errors that occur for Tx channel [A--D].

0x0000

Address

(Hex)

Bit #

Name

Function

Reset

Default

0224

15--0

UT_SCRATCH

UT Scratch Register. Read/write register with
no other internal UT connections.

0x0000

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Data Sheet

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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

UT Registers

(continued)

Size Mode Register (R/W)

Table 69. Register 0x0226: Size Mode Register (R/W)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0226

Size Mode. Size mode for each channel. These
bits define the size mode for the TxSZ[D--A]
and RxSZ[D--A] pins (see Table 5, page 32
and page 38).

If this mode bit = 0 (default mode):

TxSIZE_[D--A] (or RxSIZE_[D--A]) set to 0
means the most significant byte is the last
byte of the current packet, and

TxSIZE_[D--A] (or RxSIZE_[D--A]) set to 1
means the least significant byte is the last
byte.

If this mode bit = 1:

TxSIZE_[D--A] (or RxSIZE_[D--A]) set to 1
means the most significant byte is the last
byte of the current packet, and

TxSIZE_[D--A] (or RxSIZE_[D--A]) set to 0
means the least significant byte is the last
byte.

0x0000

15--8

Reserved. These bits must be written to their
reset default value (0x00).

0x00

TxSIZE_D

TxSIZE_MODE for Transmit Channel D.

TxSIZE_C

TxSIZE_MODE for Transmit Channel C.

TxSIZE_B

TxSIZE_MODE for Transmit Channel B.

TxSIZE_A

TxSIZE_MODE for Transmit Channel A.

RxSIZE_D

RxSIZE_MODE for Receive Channel D.

RxSIZE_C

RxSIZE_MODE for Receive Channel C.

RxSIZE_B

RxSIZE_MODE for Receive Channel B.

RxSIZE_A

RxSIZE_MODE for Receive Channel A.

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

0x indicates a hexadecimal value in the Reset Default column. Otherwise, the entry is binary. This is true for every
register table in the document.

Table 70. Register 0x0400: OHP Macrocell Version Number (RO)

Reset default of register = 0x0000.

Table 71. Register 0x0401: OHP Interrupt (RO)

Reset default of register = 0x0000.

Table 72. Registers 0x0402--0x0409: Delta/Event (COR/W)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0400

15--0

OHP_VERSION[15:0]

OHP Macrocell Version Number. The version
of the macrocell will increment each time a
change occurs to the macrocell functionality.

0x0000

Address

(Hex)

Bit #

Name

Function

Reset

Default

0401

15--4

Reserved. These bits must be written to their
reset default value (0x000).

0x000

OHP_INT[D]

OHP Interrupt. Active-high interrupt bits for
channels D to A. Each bit is the ORing of all
event and delta bits of that channel. In STS-48/
STM-16 mode, INT[A] is valid.

0x0

OHP_INT[C]

0x0

OHP_INT[B]

0x0

OHP_INT[A]

0x0

Address

(Hex)

Bit #

Name

Function

Reset

Default

0402, 0404,

0406, 0408

LRDIMOND[A--D]

Line/Multiplex RDI Delta. Delta bits indicate a
change of state for the line/multiplex RDI state
bits (LRDIMON[A--D]). Their mask bits are
LRDIMONM[A--D]. Only LRDIMOND[A] is
valid for STS-48/STM-16.

LAISMOND[A--D]

Line/Multiplex AIS Delta. Delta bits indicate a
change of state for the line/multiplex AIS state
bits (LAISMON[A--D]). Their mask bits are
LAISMONM[A--D]. Only LAISMOND[A] is valid
for STS-48/STM-16.

RAPSBABLEE[A--D]

APS Babble Event. Each bit is active-high to
indicate the inconsistence in K1 byte of that
channel. Their mask bits are
RAPSBABLEM[A--D]. Only RAPSBABLEE[A]
is valid for STS-48/STM-16.

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Data Sheet

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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 72. Registers 0x0402--0x0409: Delta/Event (COR/W) (continued)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0402, 0404,

0406, 0408

S1DMON4D[A--D]

Delta Register for S1DMON[3:0] When
S1MON8or4CTL = 1. Each delta bit indicates a
change of state for S1DMON[3:0] in its channel.
Their mask bits are S1DMON4M[A--D]. In
STS-48/STM-16 mode, S1DMON4D[A] is valid.

S1DMON8D[A--D]

Delta Register for S1DMON[7:4] When
S1MON8or4CTL = 1 or S1DMON[7:0] When
S1MON8or4CTL = 0. Each delta bit indicates a
change of state for S1DMON[7:4]/
S1DMON[7:0] in its channel. Their mask bits
are S1DMON8M[A--D]. In STS-48/STM-16
mode, S1DMON8D[A] is valid.

K2DMOND[A--D]

K2[2:0] Data Monitor Delta. Each bit is active-
high to indicate a change in K2DMON[A--D]
for that channel. Their mask bits are
K2DMONM[A--D]. Only K2DMOND[A] is valid
for STS-48/STM-16.

K1K2DMOND[A--D]

K1K2 Data Monitor Delta. Each bit is active-
high to indicate a change in (K1[7:0] and
K2[7:3]) or (K1[7:0] and K2[7:0]) for that chan-
nel depending on K1K2_2_OR_1. Their mask
bits are K1K2DMONM[A--D]. Only
K1K2DMOND[A] is valid for STS-48/STM-16.

F1DMOND[A--D]

F1 Data Monitor Delta. Their mask bits are
F1DMONM[A--D]. Only F1DMOND[A] is valid
for STS-48/STM-16.

TTOAC_PERRE[A--D]

Transmit TOAC Parity Error Event. Event bit
indicates a parity error was detected on the
incoming TOAC.

S1BABBLEE[A--D]

Receive S1 Byte Babbling Event. Event bit
will be set if CNTDS1FRAME[A--D][3:0] con-
secutive frames pass without a validated S1
byte.

SFD[A--D]

Signal Fail BER Algorithm Delta. Delta bits
indicate a change of state for the signal fail BER
algorithm state bits (SF[A--D]). Their mask bits
are SFM[A--D]. Only SFD[A] is valid for STS-
48/STM-16.

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 72. Registers 0x0402--0x0409: Delta/Event (COR/W) (continued)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0402, 0404,

0406, 0408

SDD[A--D]

Signal Degrade BER Algorithm Delta. Delta
bit indicates a change of state for the signal
degrade BER algorithm state bits (SD[A--D]).
Their mask bits are SDM[A--D]. Only SDD[A] is
valid for STS-48/STM-16.

OOFD[A--D]

Receive Out-of-Frame Delta. Delta bit indi-
cates a change of state for the out-of-frame
(OOF[A--D]). Their mask bits are
OOFM[A--D]. In STS-48/STM-16 mode, only
OOFD[A] is valid.

LOFD[A--D]

Receive Loss-of-Frame Delta. Delta bit indi-
cates a change of state for the loss-of-frame
(LOF[A--D]) . Their mask bits are LOFM[A--D].
In STS-48/STM-16 mode, only LOFD[A] is
valid.

LOSD[A--D]

Receive Loss-of-Signal Delta. Delta bit indi-
cates a change of state for the loss-of-signal
(LOS[A--D]). Their mask bits are LOSM[A--D].
In STS-48/STM-16 mode, only LOSD[A] is
valid.

LOCD[A--D]

Receive Loss-of-Clock Delta. Delta bit indi-
cates a change of state for the loss-of-clock
(LOC[A--D]). Their mask bits are LOCM[A--D].
In STS-48/STM-16 mode, only LOCD[A] is
valid.

0403, 0405,

0407, 0409

15--1

Reserved. These bits must be written to their
reset default value (000000000000000).

000

0000
0000
0000

J0MISE[A--D]

J0 Mismatch Event. Their mask bits are
J0MISM[A--D]. In STS-48/STM-16 mode, only
J0MISE[A] is valid for J0 byte while J0MISE[B--
D] are used for Z0 bytes.

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 74. Registers 0x040E, 0x0410, 0x0412, 0x0414: Mask Bits (R/W)

Reset default of registers = 0xFFFF.

Address

(Hex)

Bit #

Name

Function

Reset

Default

040E, 0410,

0412, 0414

LRDIMONM[A--D]

Line/Multiplex RDI Mask. A 1 masks the cor-
responding occurrence of the alarm to the inter-
rupt. In STS-48/STM-16 mode, only
LRDIMONM[A] is valid.

LAISMONM[A--D]

Line/Multiplex AIS Mask. A 1 masks the corre-
sponding occurrence of the alarm to the inter-
rupt. In STS-48/STM-16 mode, only
LAISMONM[A] is valid.

RAPSBABLEM[A--D]

APS Babble Mask. A 1 masks the correspond-
ing occurrence of the alarm to the interrupt. In
STS-48/STM-16 mode, only
RAPSBABLEM[A] is valid.

S1DMON4M[A--D]

Mask Bits for S1DMON4D When S1MON8
or 4CTL = 1. A 1 masks the corresponding
occurrence of the alarm to the interrupt. In
STS-48/STM-16 mode, only
S1DMON4LSNM[A] is valid.

S1DMON8M[A--D]

Mask Bits for S1DMON8D. A 1 masks the cor-
responding occurrence of the alarm to the inter-
rupt. In STS-48/STM-16 mode, only
S1DMON8M[A] is valid.

K2DMONM[A--D]

K2[2:0] Data Monitor Mask. A 1 masks the
corresponding occurrence of the alarm to the
interrupt. In STS-48/STM-16 mode, only
K2DMONM[A] is valid.

K1K2DMONM[A--D]

K1K2 Data Monitor Mask. A 1 masks the cor-
responding occurrence of the alarm to the inter-
rupt. In STS-48/STM-16 mode, only
K1K2DMONM[A] is valid.

F1DMONM[A--D]

F1 Data Monitor Mask. A 1 masks the corre-
sponding occurrence of the alarm to the inter-
rupt. In STS-48/STM-16 mode, only
F1DMONM[A] is valid.

TTOAC_PERRM[A--D]

Transmit TOAC Parity Error Mask. A 1 masks
the corresponding occurrence of the alarm to
the interrupt. All 4 bits are valid in every mode.

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Data Sheet

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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 74. Registers 0x040E, 0x0410, 0x0412, 0x0414: Mask Bits (R/W)

(continued)

Reset default of registers = 0xFFFF.

Table 75. Registers 0x040F, 0x0411, 0x0413, 0x0415: Mask Bits (R/W)

Reset default of registers = 0x8001.

Address

(Hex)

Bit #

Name

Function

Reset

Default

040E, 0410,

0412, 0414

S1BABBLEM[A--D]

S1 Babbling Mask. A 1 masks the correspond-
ing occurrence of the alarm to the interrupt. In
STS-48/STM-16 mode, only S1BABBLEM[A] is
valid.

SFM[A--D]

Signal Fail Mask. A 1 masks the correspond-
ing occurrence of the alarm to the interrupt. In
STS-48/STM-16 mode, only SFM[A] is valid.

SDM[A--D]

Signal Degrade Mask. A 1 masks the corre-
sponding occurrence of the alarm to the inter-
rupt. In STS-48/STM-16 mode, only SDM[A] is
valid.

OOFM[A--D]

Out-of-Frame Mask. A 1 masks the corre-
sponding occurrence of the alarm to the inter-
rupt. In STS-48/STM-16 mode, only OOFM[A]
is valid.

LOFM[A--D]

Loss-of-Frame Mask. A 1 masks the corre-
sponding occurrence of the alarm to the inter-
rupt. In STS-48/STM-16 mode, only LOFM[A] is
valid.

LOSM[A--D]

Loss-of-Signal Mask. A 1 masks the corre-
sponding occurrence of the alarm to the inter-
rupt. In STS-48/STM-16 mode, only LOSM[A] is
valid.

LOCM[A--D]

Loss-of-Clock Mask. A 1 masks the corre-
sponding occurrence of the alarm to the inter-
rupt. In STS-48/STM-16 mode, only LOCM[A] is
valid.

Address

(Hex)

Bit #

Name

Function

Reset

Default

040F, 0411,

0413, 0415

INTM[A--D]

Interrupt Mask. The corresponding occurrence
of a 1 masks the alarm to the interrupt.

14--1

Reserved. These bits must be written to their
reset default value (00000000000000).

0000
0000
0000

J0MISM[A--D]

J0 Mismatch Mask. The corresponding occur-
rence of a 1 masks the alarm to the interrupt.

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 76. Registers 0x0416--0x0419: Toggles (R/W)

Reset default of registers = 0x0000.

Note: These registers are one-shot type registers. They are enabled by writing a 0-to-1 transition to a bit. After

being enabled, the registers must be cleared by writing all bits to 0 following access.

Table 77. Registers 0x041A, 0x041C, 0x041E, 0x0420: Continuous N Times Detect (CNTD) Values (R/W)

Reset default of registers = 0x3333.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0416--0419

15--5

Reserved. These bits must be written to their
reset default value (00000000000).

000

0000
0000

TA1A2ERREN[A--D]

Transmit A1/A2 Error Enable. Enable signal to
start the insertion of A2 errors in the outgoing
frame. The number of consecutive errors is
controlled by TA1A2ERRINS[4:0].
TA1A2ERREN[A] is valid in STS-48/STM-16
mode.

SFCLEAR[A--D]

Signal Fail Clear. Allows the signal fail algo-
rithm to be forced into the normal state.

SFSET[A--D]

Signal Fail Set. Allows the signal fail algorithm
to be forced into the failed state.

SDCLEAR[A--D]

Signal Degrade Clear. Allows the signal
degrade algorithm to be forced into the normal
state.

SDSET[A--D]

Signal Degrade Set. Allows the signal degrade
algorithm to be forced into the degraded state.

Address

(Hex)

Bit #

Name

Function

Reset

Default

041A, 041C,

041E, 0420

15--12

CNTDK2[A--D][3:0]

Continuous N Times Detect for K2[2:0] Byte.
The valid range for these bits is 0x2--0xF.
Invalid values will be mapped to a value of 0x1.
In STS-48/STM-16 mode, CNTDK2[A] is valid.

0x3

11--8

CNTDK1K2[A--D][3:0]

Continuous N Times Detect for APS (K1,
K2[7:3]) Byte. The valid range for these bits is
0x2--0xF. Invalid values will be mapped to a
value of 0x1. In STS-48/STM-16 mode,
CNTDK1K2[A] is valid.

0x3

7--4

CNTDF1[A--D][3:0]

Continuous N Times Detect for F1 Byte. The
valid range for these bits is 0x2--0xF. Invalid
values will be mapped to a value of 0x1. In
STS-48/STM-16 mode, CNTDF1[A] is valid.

0x3

3--0

CNTDJ0Z0[A--D][3:0]

Continuous N Times Detect for J0Z0 Bytes.
The valid range for these bits is 0x2--0xF.
Invalid values will be mapped to a value of 0x1.
In STS-48/STM-16 mode, CNTDJ0Z0[A] is
valid.

0x3

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 79. Registers 0x0422--0x042D: Receive Control (R/W)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0422, 0424,

0426, 0428

15--14

J0MONMODE[A--D][1:0]

J0 Monitoring Mode. The four modes are,

00 = The OHP will latch the value of the J0 byte
every frame for a total of 16 bytes. The OHP will
compare the incoming J0 byte with the next
expected value (the expected value is obtained
by cycling through the previously stored 16
received bytes in round-robin fashion) and set
the event bit if different.

01 = This is the SONET framing mode. The
hardware looks for 0x0D followed by 0x0A to
indicate that the next byte is the first byte of the
path trace message. The J0 byte is continu-
ously written into J0DMON with the first byte
residing at the first address. If any received byte
does not match the previously received byte for
its location, then the event bit is set.

10 = This is the SDH framing mode. The hard-
ware looks for the byte with the MSB set to 1,
which indicates that the next byte is the second
byte of the message. The rest of the operation
is the same as the SONET framing mode.

11 = A new J0 byte J0DMON[0][7:0] will be
detected after CNTDJ0Z0[3:0] consecutive con-
sistent occurrences of a new pattern in the J0
overhead byte. Any changes to this byte are
reported to J0MISE and J0MISM. These event
bits will act as delta bits indicating a change of
state for the J0DMON[0][7:0].

M1B7IGNORE[A--D]

Bit 7 of M1 Byte Ignore. Bit 7 of M1 byte will
be ignored if M1B7IGNORE is set to 1 for that
channel. Only M1B7IGNORE[A] is valid for
STS-48/STM-16.

LAISINS[A--D]

AIS Software Insertion. Active-high for AIS
insertion. In STS-48/STM-16 mode, only LAI-
SINS[A] is valid.

LOF_AISINH[A--D]

Loss-of-Frame AIS Inhibit. When set to logic
1, the AIS insertion will be inhibited in case of
loss-of-frame.

OOF_AISINH[A--D]

Out-of-Frame AIS Inhibit. When set to logic 1,
the AIS insertion will be inhibited in case of out-
of-frame.

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 79. Registers 0x0422--0x042D: Receive Control (R/W) (continued)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0422, 0424,

0426, 0428

LOS_AISINH[A--D]

Loss-of-Signal AIS Inhibit. When set to logic
1, the line AIS insertion will be inhibited in case
of loss-of-signal.

SFB1B2SEL[A--D]

Signal Fail B1/B2 Error Count Select. When
set to logic 0, the B1 errors will be used by the
signal fail error rate algorithm; otherwise, B2
errors are used.

SDB1B2SEL[A--D]

Signal Degrade B1/B2 Error Count Select.
When set to logic 0, the B1 errors will be used
by the signal degrade error rate algorithm; oth-
erwise, B2 errors are used.

CNTDB1SEL[A--D]

Reset CNTD Counters on B1 Error. Active-
high control bits to reset continuous N time
detect counters upon received B1 errors. Only
CNTDB1SEL[0] is valid for STS-48/STM-16.

S1MON8_OR_4CTL[A--D] S1 Byte or Nibble. When set to logic 1, the S1

byte will be monitored as two nibbles. Other-
wise, it is treated as a byte. Only
S1MON8or4CTL[A] is valid for STS-48/STM-
16.

K1K2_2_OR_1[A--D]

K1 and K2 Treated as 2 Registers or 1. When
a bit is set to 1, the K1 and K2 bytes will be
treated as one 16-bit register. Otherwise, they
will be treated as two registers of size 13
(K1[7:0] and K2[7:3]) and 3 (K2[2:0]).
K1K2_2_OR_1[A] is valid for STS-48/STM-16.

B2BITBLKCNT[A--D]

B2 Error Count in Bit or Block. When set to 0,
B2 check logic will count bit errors; otherwise, it
counts block errors. Only B2BITBLKCNT[A] is
valid for STS-48/STM-16.

DSCRINH[A--D]

Descramble Inhibit Control. When a bit is set
to 1, the descrambler for that is disabled. In
STS-48/STM-16 mode, all 4 bits need to be set
to same value.

B1BITBLKCNT[A--D]

B1 Error Count in Bit or Block. When set to 0,
B1 check logic will count bit errors; otherwise, it
counts block errors. Only B1BITBLKCNT[A] is
valid for STS-48/STM-16.

ROH_BYPASS[A--D]

Receive Overhead Bypass. Control bit, when
set to 1, causes the received data to pass
through the block retimed. In STS-48/STM-16
mode, all 4 bits need to be set to same value.

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 79. Registers 0x0422--0x042D: Receive Control (R/W) (continued)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0423, 0425,

0427, 0429

M1BITBLKCNT[A--D]

M1 Error Count in Bit or Block. When set to
0, M1 check logic will count bit errors. When set
to 1, block errors are counted. Only
M1BITBLKCNT[C] is valid for STS-48/STM-16.

14--13

Reserved. These bits must be written to their
reset default value (00).

12--0

LOSDETCNT[A--D][12:0]

Loss-of-Signal Detection Count. Set the
number of consecutive all-zeros/-ones pattern
detected to declare receive LOS state for each
channel. The time scale is in steps of 8 (for
STS-3/STM-1 and STS-12/STM-4) or 32
(STS-48/STM-16) bits at a time. Only
LOSDETCNT[A][12:0] is valid for STS-48/
STM-16.

0000
0000
0000

042A

15--14

RREFSEL[1:0]

Receive Reference Sync Select. Select refer-
ence output from channel A (00), B (01), C (10),
and D (11).

RREF_EN

Receive Reference Sync Enable. When set to
0, the receive 8 kHz (50% duty cycle) sync out-
put, RxREF (pin AK3), is placed in the high-
impedance state.

12--4

Reserved. These bits must be written to their
reset default value (000000000).

0000

00000

RTOACSINH[A]

Receive TOAC Frame (Sync) Inhibit Channel
A. When set to 1, the TOAC sync output,
RxTOHF (pin AK4), is placed in the high-imped-
ance state.

RTOACCINH[A]

Receive TOAC Clock Inhibit Channel A.
When set to 1, the TOAC clock output,
RxTOHCK (pin AK5), is placed in the high-
impedance state.

RTOACDINH[A]

Receive TOAC Data Inhibit Channel A. When
set to 1, the TOAC data output, RxTOHD (pin
AL2), is placed in the high-impedance state.

RTOAC_OEPINS[A]

Receive TOAC Odd or Even Parity Insert
Channel A. When set to 1, the output TOAC
parity bit is even. When set to 0, the parity is
odd.

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 80. Registers 0x042E: Transmit Control Port A (R/W)

Reset default of registers = 0x0003.

* TJ0INS = 1 always sets J0 to the TJ0DINS values regardless of the value of TTOAC_J0.

Address

(Hex)

Bit #

Name

Function

Reset

Default

042E

TTOACINH

Transmit TOAC Clock and Sync Inhibit Chan-
nel A. When set to 1, the transmit TOAC clock
and sync are placed in the high-impedance
state.

TJ0INS[A]

Transmit J0 Insert Control Channel A. Con-
trol bit, when set to a logic 1, inserts the value in
TJ0DINS[A--D][16:1][7:0] into the outgoing J0
bytes; otherwise, the insert value depends on
TTOAC_J0[A--D] registers. TJ0INS[A] is valid
in STS-48/STM-16 mode.*

TTOAC_J0[A]

Transmit TOAC J0 Byte Control Channel A.
Control bit, when set to logic 0, causes the
default value 00000000 for SONET or
11111111 for SDH to be inserted into the J0
byte in the transmit frame. Setting this bit to
logic 1 causes the TTOAC value to be inserted
into the J0 byte. TTOAC_J0[A] is valid for STS-
48/STM-16 mode.*

TTOAC_OEPMON[A]

Transmit TOAC Odd or Even Parity Monitor
Channel A. When set to 1, even parity is
checked for transmit TOAC channels; other-
wise, odd parity is checked.

TTOAC_INS[A]

Transmit TOAC Byte Control Channel A.
Control bit, when set to logic 0, causes the
default value 00000000 for SONET or
11111111 for SDH to be inserted into those
overhead bytes within the transmit frame that
do not have all specific insert control bits. Set-
ting these bits to logic 1 causes the TTOAC
value to be inserted into those overhead bytes
not having specific insert control bits.
TTOAC_INS[A] is valid for STS-48/STM-16
mode.

TTOAC_E2[A]

Transmit TOAC E2 Byte Control Channel A.
Control bit, when set to logic 0, causes the
default value to be inserted into the E2 byte in
the transmit frame. Setting these bits to logic 1
causes the TTOAC value to be inserted into the
E2 byte. TTOAC_E2[A] is valid for STS-48/
STM-16 mode.

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Data Sheet

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 80. Registers 0x042E: Transmit Control Port A (R/W) (continued)

Reset default of registers = 0x0003.

Address

(Hex)

Bit #

Name

Function

Reset

Default

042E

TTOAC_S1[A]

Transmit TOAC S1 Byte Control Channel A.
Control bit, when set to logic 0, causes the
default value to be inserted into the S1 byte in
the transmit frame. Setting these bits to logic 1
causes the TTOAC value to be inserted into the
S1 byte. TTOAC_S1[A] is valid for STS-48/
STM-16 mode.

TTOAC_D4TO12[A]

Transmit TOAC D4 to D12 Byte Control
Channel A. Control bit, when set to logic 0,
causes the default value to be inserted into the
D4 to D12 bytes in the transmit frame. Setting
these bits to logic 1 causes the TTOAC value to
be inserted into the D4 to D12 bytes.
TTOAC_D4TO12[A] is valid for STS-48/
STM-16 mode.

TTOAC_D1TO3[A]

Transmit TOAC D1 to D3 Byte Control Chan-
nel A. Control bit, when set to logic 0, causes
the default value to be inserted into the D1 to
D3 bytes in the transmit frame. Setting these
bits to logic 1 causes the TTOAC value to be
inserted into the D1 to D3 bytes.
TTOAC_D1TO3[A] is valid for STS-48/STM-16
mode.

TTOAC_F1[A]

Transmit TOAC F1 Byte Control Channel A.
Control bit, when set to logic 0, causes the
default value to be inserted into the F1 byte in
the transmit frame. Setting these bits to logic 1
causes the TTOAC value to be inserted into the
F1 byte. TTOAC_F1[A] is valid for STS-48/
STM-16 mode.

TTOAC_E1[A]

Transmit TOAC E1 Byte Control Channel A.
Control bit, when set to logic 0, causes the
default value to be inserted into the E1 byte in
the transmit frame. Setting this bit to logic 1
causes the TTOAC value to be inserted into the
E1 byte. TTOAC_E1[A] is valid for STS-48/
STM-16 mode.

TAPSBABBLEINS[A]

Transmit APS Babble Insert Channel A. Con-
trol bit, when set to 1, causes an inconsistent
APS byte (K1[7:0], K2[7:3]) to be inserted into
the outgoing STS-M frame until this register is
reset to 0.

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Data Sheet

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 81. Registers 0x042F, 0x0431, 0x0433, 0x0435: Transmit Control (R/W)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

042F, 0431,

0433, 0435

15--11

TA1A2ERRINS[A--D][4:0] Number of Consecutive Frames with A2

Error Insertion. These bits specify the number
of consecutive frames to be inserted with a
frame error of the first A2 byte.

0x00

TOH_BYPASS[A--D]

Transmit Overhead Bypass. Control bit, when
set to 1, causes the frame from PT pass
through untouched. In STS-48/STM-16 mode,
all 4 bits need to be set to same value.

SCRINH[A--D]

Scramble Inhibit. When set to high, the scram-
bling is inhibited. In STS-48/STM-16 mode, all
4 bits need to be set to same value.

TB1ERRINS[A--D]

Transmit B1 Error Insertion. When set to
high, the B1 output will be inverted. For
STS-48/STM-16, only TB1ERRINS[A] is valid.

TB2ERRINS[A--D]

Transmit B2 Error Insertion. When set to
high, all B2 bytes in that channel will be
inverted. All 4 bits are valid in STS-48/STM-16
mode.

TIMER_LRDIINH[A--D]

Transmit 20-Frame Line RDI Inhibit. Control
bit, when set to logic high, inhibits the require-
ment of minimum 20 frame RDI insertion.

TSF_LRDIINH[A--D]

Transmit Signal Fail Line RDI Inhibit. Active-
high.

TLAISMON_LRDIINH

[A--D]

Transmit Line-AIS-Monitored Line RDI
Inhibit. Active-high.

TLOF_LRDIINH[A--D]

Transmit Loss-of-Frame Line RDI Inhibit.
Active-high.

TOOF_LRDIINH[A--D]

Transmit Out-of-Frame Line RDI Inhibit.
Active-high.

TLOS_LRDIINH[A--D]

Transmit Loss-of-Signal Line RDI Inhibit.
Active-high.

TLOC_LRDIINH[A--D]

Transmit Loss-of-Clock Line RDI Inhibit.
Control bit, when set to a logic 1, causes the
associated failure not to contribute to the auto-
matic insertion of RDI-L; otherwise, the associ-
ated alarm contributes to the generation of
RDI-L.

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 82. Registers 0x0430, 0x0432, 0x0434: Transmit Control Port [B--D] (R/W)

Reset default of registers = 0x0003.

* TJ0INS = 1 always sets J0 to the TJ0DINS values regardless of the value of TTOAC_J0.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0430, 0432,

0434

Reserved. This bit must be written to its reset
default value (0).

TJ0INS[B--D]

Transmit J0 Insert Control Channel [B--D].
Control bit, when set to a logic 1, insert the
value in TJ0DINS[A--D][16:1][7:0] into the out-
going J0 bytes; otherwise, the insert value
depends on TTOAC_J0[A--D] registers.
TJ0INS[A] is valid in STS-48/STM-16 mode.*

TTOAC_J0[B--D]

Transmit TOAC J0 Byte Control Channel
[B--D]. Control bit, when set to logic 0, causes
the default value 00000000 for SONET or
11111111 for SDH to be inserted into the J0
byte in the transmit frame. Setting this bit to
logic 1 causes the TTOAC value to be inserted
into the J0 byte. TTOAC_J0[A] is valid for STS-
48/
STM-16 mode.*

TTOAC_OEPMON[B--D]

Transmit TOAC Odd or Even Parity Monitor
Channel [B--D]. When set to 1, even parity is
checked for transmit TOAC channels; other-
wise, odd parity is checked.

TTOAC_INS[B--D]

Transmit TOAC Byte Control Channel
[B--D]. Control bit, when set to logic 0, causes
the default value 00000000 for SONET or
11111111 for SDH to be inserted into those
overhead bytes within the transmit frame that
do not have all specific insert control bits. Set-
ting this bit to logic 1 causes the TTOAC value
to be inserted into those overhead bytes not
having specific insert control bits.
TTOAC_INS[A] is valid for STS-48/STM-16
mode.

TTOAC_E2[B--D]

Transmit TOAC E2 Byte Control Channel
[B--D]. Control bit, when set to logic 0, causes
the default value to be inserted into the E2 byte
in the transmit frame. Setting this bit to logic 1
causes the TTOAC value to be inserted into the
E2 byte. TTOAC_E2[A] is valid for STS-48/
STM-16 mode.

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 82. Registers 0x0430, 0x0432, 0x0434: Transmit Control Port [B--D] (R/W) (continued)

Reset default of registers = 0x0003.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0430, 0432,

0434

TTOAC_S1[B--D]

Transmit TOAC S1 Byte Control Channel
[B--D]. Control bit, when set to logic 0, causes
the default value to be inserted into the S1 byte
in the transmit frame. Setting this bit to logic 1
causes the TTOAC value to be inserted into the
S1 byte. TTOAC_S1[A] is valid for STS-48/
STM-16 mode.

TTOAC_D4TO12[B--D]

Transmit TOAC D4 to D12 Byte Control
Channel [B--D]. Control bit, when set to logic
0, causes the default value to be inserted into
the D4 to D12 bytes in the transmit frame. Set-
ting this bit to logic 1 causes the TTOAC value
to be inserted into the D4 to D12 bytes.
TTOAC_D4TO12[A] is valid for STS-48/STM-16
mode.

TTOAC_D1TO3[B--D]

Transmit TOAC D1 to D3 Byte Control Chan-
nel [B--D]. Control bit, when set to logic 0,
causes the default value to be inserted into the
D1 to D3 bytes in the transmit frame. Setting
this bit to logic 1 causes the TTOAC value to be
inserted into the D1 to D3 bytes.
TTOAC_D1TO3[A] is valid for STS-48/STM-16
mode.

TTOAC_F1[B--D]

Transmit TOAC F1 Byte Control Channel
[B--D]. Control bit, when set to logic 0, causes
the default value to be inserted into the F1 byte
in the transmit frame. Setting this bit to logic 1
causes the TTOAC value to be inserted into the
F1 byte. TTOAC_F1[A] is valid for STS-48/
STM-16 mode.

TTOAC_E1[B--D]

Transmit TOAC E1 Byte Control Channel
[B--D]. Control bit, when set to logic 0, causes
the default value to be inserted into the E1 byte
in the transmit frame. Setting this bit to logic 1
causes the TTOAC value to be inserted into the
E1 byte. TTOAC_E1[A] is valid for STS-48/
STM-16 mode.

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 82. Registers 0x0430, 0x0432, 0x0434: Transmit Control Port [B--D] (R/W) (continued)

Reset default of registers = 0x0003.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0430, 0432,

0434

TAPSBABBLEINS[B--D]

Transmit APS Babble Insert Channel
[B--D]. Control bit, when set to 1, causes an
inconsistent APS byte (K1[7:0], K2[7:3]) to be
inserted into the outgoing STS-M frame until
this register is reset to 0.

TM1_ERR_INS[B--D]

Transmit M1 Error Insert [B--D]. Once this
register is set to 1, an error will be inserted con-
tinuously into the outgoing M1 byte until this
register is reset to 0. In STS-48/STM-16 mode,
only TM1_ERR_INS is valid.

TM1_REIL_INH[B--D]

Transmit M1 REI-L Inhibit Channel [B--D].
Active-high to inhibit automatic insertion of
REI-L (MS-REI). In STS-48/STM-16 mode, only
TM1_REIL_INH is valid.

TF1INS[B--D]

Transmit F1 Insert Control Channel [B--D].
Control bit, when set to a logic 1, inserts the
value in TF1DINS[7:0] into the outgoing F1 byte
in the STS-M frame; otherwise, the insert value
depends on TTOAC_F1 register. TF1INS[A] is
valid in STS-48/STM-16 mode.

TS1INS[B--D]

Transmit S1 Insert Control Channel [B--D].
Control bit, when set to a logic 1, inserts the
value in TS1DINS[7:0] into the outgoing S1 byte
in the STS-M frame; otherwise, the insert value
depends on TTOAC_S1 register. TS1INS[A] is
valid in STS-48/STM-16 mode.

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 84. Registers 0x043A--0x0451: OHP Signal Degrade BER Algorithm Parameters (R/W)

Reset default of registers = 0x0000.

Notes: OHP_SDNSSET[A--D][2:0] are located in registers 0x043B, 0x043D, 0x043F, and 0x0441, respectively.

OHP_SDNSCLEAR[A--D][2:0] are located in registers 0x0447, 0x0449, 0x044B, and 0x044D, respec-
tively.

Address

(Hex)

Bit #

Name

Function

Reset

Default

043A, 043C,

043E, 0440

15--0

OHP_SDNSSET

[A--D][18:3]

Signal Degrade Ns Set [18:3]. Number of
frames in a monitoring block for SD.

0x0000

043B, 043D,

043F, 0441

Reserved. This bit must be written to its reset
default value (0).

14--7

OHP_SDMSET[A--D][7:0] Signal Degrade M Set. Threshold of the num-

ber of bad monitoring blocks in an observation
interval. If the number of bad blocks is above
this threshold, then signal degrade (SD) is set.

0000
0000

6--3

OHP_SDLSET[A--D][3:0]

Signal Degrade L Set. Error threshold for
determining if a monitoring block is bad.

0x0

2--0

OHP_SDNSSET[A--D][2:0] Signal Degrade Ns Set [2:0]. Number of

frames in a monitoring block for SD.

000

0442--0445

15--0 OHP_SDBSET[A--D][15:0] Signal Degrade B Set. Number of monitoring

blocks.

0x0000

0446, 0448,
044A, 044C

15--0

OHP_SDNSCLEAR

[A--D][18:3]

Signal Degrade Ns Clear [18:3]. Number of
frames in a monitoring block for SD.

0x0000

0447, 0449,
044B, 044D

Reserved. This bit must be written to its reset
default value (0).

14--7

OHP_SDMCLEAR

[A--D][7:0]

Signal Degrade M Clear. Threshold of the
number of bad monitoring blocks in an observa-
tion interval. If the number of bad blocks is
below this threshold, then SD (signal degrade)
is cleared.

0000
0000

6--3

OHP_SDLCLEAR

[A--D][3:0]

Signal Degrade L Clear. Error threshold for
determining if a monitoring block is bad.

0x0

2--0

OHP_SDNSCLEAR

[A--D][2:0]

Signal Degrade Ns Clear[2:0]. Number of
frames in a monitoring block for SD.

000

044E--0451

15--0

OHP_SDBCLEAR

[A--D][15:0]

Signal Degrade B Clear. Number of monitoring
blocks.

0x0000

186

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 85. Registers 0x0452--0x0469: OHP Signal Fail BER Algorithm Parameters (R/W)

Reset default of registers = 0x0000.

Notes: OHP_SFNSSET[A--D][2:0] are located in registers 0x0453, 0x0455, 0x0457, and 0x0459, respectively.

OHP_SDNSCLEAR[A--D][2:0] are located in registers 0x045F, 0x0461, 0x0463, 0x0465, respectively.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0452, 0454,

0456, 0458

15--0

OHP_SFNSSET

[A--D][18:3]

Signal Fail Ns Set [18:3]. Number of frames in
a monitoring block for SF.

0x0000

0453, 0455,

0457, 0459

Reserved. This bit must be written to its reset
default value (0).

14--7

OHP_SFMSET[A--D][7:0]

Signal Fail M Set. Threshold of the number of
bad monitoring blocks in an observation inter-
val. If the number of bad blocks is above this
threshold, then SF (signal fail) is set. (See Table
86, page 187, for register settings in terms of
corresponding BER.)

0000
0000

6--3

OHP_SFLSET[A--D][3:0]

Signal Fail L Set. Error threshold for determin-
ing if a monitoring block is bad. (See Table 86,
page 187, for register settings in terms of corre-
sponding BER.)

0x0

2--0

OHP_SFNSSET[A--D][2:0] Signal Fail Ns Set [2:0]. Number of frames in a

monitoring block for SF. (See Table 86, page
187, for register settings in terms of corre-
sponding BER.)

000

045A--045D 15--0

OHP_SFBSET[A--D][15:0] Signal Fail B Set. Number of monitoring

blocks. (See Table 86, page 187, for register
settings in terms of corresponding BER.)

0x0000

045E, 0460,

0462, 0464

15--0

OHP_SFNSCLEAR

[A--D][18:3]

Signal Fail Ns Clear [18:3]. Number of frames
in a monitoring block for SF.

0x0000

045F, 0461,

0463, 0465

Reserved. This bit must be written to its reset
default value (0).

14--7

OHP_SFMCLEAR

[A--D][7:0]

Signal Fail M Clear. Threshold of the number
of bad monitoring blocks in an observation
interval. If the number of bad blocks is below
this threshold, then SF (signal fail) is cleared.

0x00

6--3

OHP_SFLCLEAR

[A--D][3:0]

Signal Fail L Clear. Error threshold for deter-
mining if a monitoring block is bad.

0x0

2--0

OHP_SFNSCLEAR

[A--D][2:0]

Signal Fail Ns Clear [2:0]. Number of frames
in a monitoring block for SF.

000

0466--0469

15--0

OHP_SFBCLEAR

[A--D][15:0]

Signal Fail B Clear. Number of monitoring
blocks.

0x0000

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Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 86 and Table 87 show values of Ns, L, M, and B for STS-3/STM-1, STS-12/STM-4, and STS-48/STM-16 to
set and clear the BER indicator. SF registers are 0x0452--0x0469, and SD registers are 0x043A--0x0451.
All SF/SD set and clear values are hexadecimal.

Table 86. Ns, L, M, and B Values to Set the BER Indicator

* These are the numbers to be provisioned in TDAT042G5. The actual values of the BER algorithm are 1 greater than the actual values shown.

These BER values cannot be provisioned because the maximum value of L is 0xF (i.e., L is a 4-bit register).

Mode

BER

SF/SD Set Values

Actual

Number of

Frames

Probability of

Detecting L

Errors (%)

Probability of

Declaring

SF/SD (%)

Integra-

tion

Time

(s)

Max-

imum

Number

of Frames

Ns*

@BER

@BER/2

@BER

@BER/2

STS-3/

STM-1

1.00E-03

99.96

85.13

97.68

0.00

0.008

1.00E-04

72.70

7.28

96.06

0.16

0.013

104

1.00E-05

384

71.34

10.08

95.19

0.52

0.1

800

1.00E-06

1E0

3840

71.34

10.09

95.19

0.52

8000

1.00E-07

1275

47250

69.74

9.44

95.07

0.13

80000

1.00E-08

B5A4

465000

68.07

8.82

98.47

0.82

664000

1.00E-09

3F7A0

4160000

56.90

11.25

96.52

0.60

667

5336000

1.00E-10

STS-12/

STM-4

1.00E-03

100.00

88.43

100.00

0.04

0.008

1.00E-04

84.92

9.64

98.38

0.00

0.008

1.00E-05

117

67.93

7.17

96.48

0.25

0.025

200

1.00E-06

1152

66.19

6.66

95.46

0.19

0.25

2000

1.00E-07

4FB

11475

65.75

6.53

95.16

0.18

2.5

20000

1.00E-08

31CE

114750

65.75

6.53

95.16

0.18

168000

1.00E-09

1F20C

1147500

65.75

6.53

95.16

0.18

167

1336000

1.00E-10

STS-48/

STM-16

1.00E-03

100.00

0.008

1.00E-04

99.95

58.97

96.89

0.00

0.008

1.00E-05

320

90.60

16.25

96.47

0.00

0.008

1.00E-06

480

77.55

13.09

96.69

0.00

0.0625

500

1.00E-07

13A

4710

75.80

12.15

95.17

0.00

0.625

5000

1.00E-08

C1C

46500

74.58

11.54

98.09

0.01

5.2

41600

1.00E-09

765C

333300

82.92

19.71

97.29

0.18

336000

1.00E-10

188

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 87. Ns, L, M, and B Values to Clear the BER Indicator

* These are the numbers to be provisioned in TDAT042G5. The actual values of the BER algorithm are 1 greater than the actual values shown.

These BER values cannot be provisioned because the maximum value of L is 0xF (i.e., L is a 4-bit register).

Mode

BER

SF/SD Set Values

Actual

Number of

Frames

Probability of

Detecting L

Errors (%)

Probability of

Clearing

SF/SD (%)

Integra-

tion

Time

(s)

Max-

imum

Number

of Frames

Ns*

@BER*5

@BER

@BER*5

@BER

STS-3/

STM-1

1.00E-03

1.00E-04

85.13

0.39

0.27

100.00

0.013

104

1.00E-05

93.01

11.33

0.01

99.21

0.1

800

1.00E-06

384

84.42

6.84

0.34

99.88

8000

1.00E-07

1E05

3840

84.42

6.84

0.34

99.88

80000

1.00E-08

1275

47250

83.66

6.59

0.22

99.98

664000

1.00E-09

B5A4

465000

82.86

6.35

0.03

99.75

667

5336000

1.00E-10

3F7A0

4160000

46.31

1.48

0.50

99.84

6670

53360000

STS-12/

STM-4

1.00E-03

1.00E-04

100.00

51.54

0.00

99.03

0.008

1.00E-05

98.36

20.51

0.07

100.00

0.025

200

1.00E-06

117

87.99

8.23

0.02

99.59

0.25

2000

1.00E-07

1152

87.34

7.94

0.02

99.64

2.5

20000

1.00E-08

4FB

11475

87.17

7.87

0.03

99.65

168000

1.00E-09

31CE

114750

87.17

7.87

0.03

99.65

167

1336000

1.00E-10

1F20C

1147500

87.17

7.87

0.03

99.65

1670

13360000

STS-48/

STM-16

1.00E-03

1.00E-04

100.00

45.99

0.00

99.42

0.008

1.00E-05

100.00

60.11

0.00

99.47

0.008

1.00E-06

320

95.07

7.28

0.00

99.98

0.0625

500

1.00E-07

640

87.34

7.94

0.00

99.94

0.625

5000

1.00E-08

13A

6280

86.52

7.61

0.00

99.95

5.2

41600

1.00E-09

C1C

62000

85.95

7.38

0.00

99.96

336000

1.00E-10

765C

333300

84.89

7.00

0.03

99.95

420

3360000

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Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 88. Registers 0x046A--0x047D: B1, B2, M1 Error Count (RO)

Reset default of registers = 0x0000.

Table 89. Registers 0x047E--0x0485: Transmit F1, S1, K2, K1 OH Insert Value (R/W)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

046A--046D 15--0

B1ECNT[A--D][15:0]

B1 Error Count. The value of the internal run-
ning counter is transferred into this holding reg-
ister at the 0-to-1 transition of PMRST signal.
The counter is then reset to 0.

0x0000

046E, 0470,

0472, 0474

15--6

Reserved. These bits must be written to their
reset default value (0000000000).

0000
0000

5--0

B2ECNT[A--D][21:16]

B2 Error Count [21:16]. The value of the inter-
nal running counter is transferred into this hold-
ing register at the 0-to-1 transition of PMRST
signal. The counter is then reset to 0.

000000

046F, 0471,

0473, 0475

15--0

B2ECNT[A--D][15:0]

B2 Error Count [15:0]. Same description as
above.

0x0000

0476, 0478,
047A, 047C

15--5

Reserved. These bits must be written to their
reset default value (00000000000).

000

0000
0000

4--0

M1ECNT[A--D][20:16]

M1 Error Count [20:16]. The value of the inter-
nal running counter is transferred into this hold-
ing register at the 0-to-1 transition of PMRST
signal. The counter is then reset to 0.

00000

0477, 0479,
047B, 047D

15--0

M1ECNT[A--D][15:0]

M1 Error Count [15:0]. Same description as
above.

0x0000

Address

(Hex)

Bit #

Name

Function

Reset

Default

047E, 0480,

0482, 0484

15--8

TF1DINS[A--D][7:0]

Transmit F1 Byte Value. Register value is
inserted into the transmit F1 byte.

0x00

7--0

TS1DINS[A--D][7:0]

Transmit S1 Byte Value. Register value is
inserted into the transmit S1 byte.

0x00

047F, 0481,

0483, 0485

15--8

TK2DINS[A--D][7:0]

Transmit K2 Byte Value. Register value is
inserted into the transmit K2 byte.

0x00

7--0

TK1DINS[A--D][7:0]

Transmit K1 Byte Value. Register value is
inserted into the transmit K1 byte.

0x00

190

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 90. Registers 0x0486--0x0491: Receive F1, S1, K2, K1 Monitor Value (RO)

Reset default of registers = 0x0000.

Table 91. Registers 0x0492--0x04F9: Receive J0 Monitor Value (RO)

Reset default of registers = 0x0000.

Table 92. Registers 0x0512--0x0579: Transmit J0 Insert Value (R/W)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0486, 0489,

048C, 048F

15--8

F1DMON1[A--D][7:0]

Receive F1 Previous Monitor Value.

0x00

7--0

F1DMON0[A--D][7:0]

Receive F1 Current Monitor Value.

0x00

0487, 048A,

048D, 0490

15--8

K2DMON[A--D[7:0]

Receive K2 Monitor Value.

0x00

7--0

K1DMON[A--D][7:0]

Receive K1 Monitor Value.

0x00

0488, 048B,

048E, 0491

15--8

Reserved. These bits must be written to their
reset default value (0x00).

0x00

7--0

S1DMON[A--D][7:0]

Receive S1 Monitor Value.

0x00

Address

(Hex)

Bit #

Name

Function

Reset

Default

0492--0499

15--0

RJ0DMON[A][1--16][7:0]

Receive J0 Monitor Value. Registers capture
a 16-byte sequence from the J0 byte of each
channel. In STS-48/STM-16 mode,
J0DMON[A][1--16][7:0] is valid for J0 bytes
while J0DMON[B--D][1][7:0] are used for
Z0DMON[B--D][1][7:0].

0x0000

04B2--04B9 15--0

RJ0DMON[B][1--16][7:0]

04D2--04D9 15--0

RJ0DMON[C][1--16][7:0

04F2--04F9

15--0

RJ0DMON[D][1--16][7:0]

Address

(Hex)

Bit #

Name

Function

Reset

Default

0512--0519

15--0

TJ0DINS[A][1--16][7:0]

Transmit J0 Insert Value. Registers allow a
16-byte sequence to be inserted into the J0
byte of each channel. In STS-48/STM-16 mode,
TJ0DINS[A][1--16][7:0] is valid for J0 bytes
while TJ0DINS[B--D][1][7:0] are used for
TZ0DINS[B--D][1][7:0].

0x0000

0532--0539

15--0

TJ0DINS[B][1--16][7:0]

0552--0559

15--0

TJ0DINS[C][1--16][7:0]

0572--0579

15--0

TJ0DINS[D][1--16][7:0]

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Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

OHP Registers

(continued)

Table 93. Registers 0x05AA--0x05C1: Transmit Z0 Insert Value (R/W)

Reset default of registers = 0x0000.

Table 94. Register 0x05C2: Scratch Register (R/W)

Reset default of register = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

05AA--
0x05C1

TZ0DINS[A--D][2--12][7:0] Transmit Z0 Insert Value. Register values are

inserted into the transmit Z0 bytes. In STS-3/
STM-1 mode, TZ0DINS[A--D][2--3] are valid; in
STS-12/STM-4 mode, TZ0DINS[A--D][2--12]
are valid; and in STS-48/STM-16 mode, all 44
TZ0DINS bytes plus TJ0DINS[B--D][1][7:0] are
used for 47 Z0 byte values.

0x0000

05AA

15--8

TZ0DINS[A][2][7:0]

Transmit Z0 Insert A2 Value.

0x00

7--0

Reserved. These bits must be written to their
reset default value (0x00).

0x00

05AB--05AF 15--0

TZ0DINS[A][3--12][7:0]

Transmit Z0 Insert [A][3--12] Value.

0x0000

05B0

15--8

TZ0DINS[B][2][7:0]

Transmit Z0 Insert B2 Value.

0x00

7--0

Reserved. These bits must be written to their
reset default value (0x00).

0x00

05B1--05B5

15--0

TZ0DINS[B][3--12][7:0]

Transmit Z0 Insert [B][3--12] Value.

0x0000

05B6

15--8

TZ0DINS[C][2][7:0]

Transmit Z0 Insert C2 Value.

0x00

7--0

Reserved. These bits must be written to their
reset default value (0x00).

0x00

05B7--05BB 15--0

TZ0DINS[C][3--12][7:0]

Transmit Z0 Insert [C][3--12] Value.

0x0000

05BC

15--8

TZ0DINS[D][2][7:0]

Transmit Z0 Insert D2 Value.

0x00

7--0

Reserved. These bits must be written to their
reset default value (0x00).

0x00

05BD--05C1 15--0

TZ0DINS[D][3--12][7:0]

Transmit Z0 Insert [D][3--12] Value.

0x0000

Address

(Hex)

Bit #

Name

Function

Reset

Default

05C2

15--0

OHP_SCRATCH[15:0]

Scratch Register. Allows the control system to
verify read and write operations to the device
without affecting device operation.

0x0000

192

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

This section gives a brief description of each register bit and its functionality. All algorithms are described in the
main text of the document. The abbreviations after each register indicate if the register is read only (RO), read/write
(R/W), write only (WO), or clear-on-read or clear-on-write (COR/W).

0x indicates a hexadecimal value in the Reset Default column. Otherwise, the entry is binary. This is true for every
register table in the document.

Table 95. Register 0x0800: PT Macrocell Version Number (RO)

Reset default of register = 0x0000.

Table 96. Register 0x0801: PT Interrupt (RO)

Reset default of register = 0x0000.

Table 97. Registers 0x0802, 0x080F, 0x081C, 0x0829 and 0x0803, 0x0810, 0x081D, 0x082A: PT Delta/Event

Parameters (COR/W)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0800

15--8

Reserved. These bits must be written to their
reset default value (0x00).

0x00

7--0

PT_VERSION[7:0]

Macrocell Version Number. The version of the
macrocell will increment each time a change
occurs to the macrocell functionality.

0x00

Address

(Hex)

Bit #

Name

Function

Reset

Default

0801

15--4

Reserved. These bits must be written to their
reset default value (0x000).

0x000

PT_INT[D]

Interrupt. Active-high interrupt bit on a per-port
basis. These bits are the ORing of all event and
delta bits associated with a particular port. An
event or delta bit contribution can be inhibited
from contributing to the interrupt by setting the
appropriate mask bit.

0x0

PT_INT[C]

PT_INT[B]

PT_INT[A]

Address

(Hex)

Bit #

Name

Function

Reset

Default

0802, 080F,
081C, 0829

RJ1DMONMIS[A--D]E

Receive J1 Data Monitor Mismatch. Event bit
indicates a mismatch has occurred between the
expected J1 value and the received value.

14--12

Reserved. These bits must be written to their
reset default value (000).

000

11--0

RPIHD[A--D][1--12]

Receive Pointer Interpretation Hardware
Delta. Delta bits indicate a change of the
associated state bit.

0x000

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Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

(continued)

Table 97. Registers 0x0802, 0x080F, 0x081C, 0x0829 and 0x0803, 0x0810, 0x081D, 0x082A: PT Delta/Event

Parameters (COR/W) (continued)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0803, 0810,

081D, 082A

TRDIPD[A--D]

Transmit RDI-P Delta. Delta bit indicates a
change of the associated state byte.

14--11

Reserved. These bits must be written to their
reset default value (0000).

0000

RZ5DMOND[A--D]

Receive Z5 Data Monitor Delta. Delta bit
indicates a change of the associated state byte.

RZ4DMOND[A--D]

Receive Z4 Data Monitor Delta. Delta bit
indicates a change of the associated state byte.

RZ3DMOND[A--D]

Receive Z3 Data Monitor Delta. Delta bit
indicates a change of the associated state byte.

RH4DMOND[A--D]

Receive H4 Data Monitor Delta. Delta bit
indicates a change of the associated state byte.

RF2DMOND[A--D]

Receive F2 Data Monitor Delta. Delta bit
indicates a change of the associated state byte.

RRDIPDMOND[A--D]

Receive RDI-P Data Monitor Delta. Delta bit
indicates a change of the associated state bit.

RC2DMOND[A--D]

Receive C2 Data Monitor Delta. Delta bit
indicates a change of the associated state byte.

RUC2D[A--D]

Receive Unequipped C2 Values Delta. Delta
bit indicates a change of the associated state
bit.

RPPLMD[A--D]

Receive Path Payload Label Mismatch Delta.
Delta bit indicates a change of the associated
state bit.

RSDD[A--D]

Receive Signal Degrade Delta. Delta bit
indicates a change of the associated state bit.

RSFD[A--D]

Receive Signal Fail Delta. Delta bit indicates a
change of the associated state bit.

194

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

(continued)

Table 98. Registers 0x0836--0x083B, 0x0868--0x0887, 0x0888--0x088D, 0x08BA--0x08D9,

0x08DA--0x08DF, 0x090C--0x092B, 0x092C--0x0931, 0x095E--0x097D:
PT State Registers (RO)

Reset default of registers 0x0836, 0x0837, 0x0888, 0x0889, 0x08DA, 0x08DB, 0x092C, 0x092D = 0x0AAA.
Reset default of all other registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0836,
0888,

08DA,

092C

15--14

RSSDRP[A--D][1:0]

Receive SS Drop Values. SS bit values from
the four selected ports.

13--12

Reserved. These bits must be written to their
reset default value (00).

11--0

RPIH_STATE[A--D]

[1--6][1:0]

Receive Pointer Interpretation Hardware
State[Bits 1--6]. Software access to the 48
STS-1 PI state values. 00 = Normal;
01 = Concat; 10 = LOP; 11 = AIS.

0xAAA

0837,
0889,

08DB,

092D

15--12

Reserved. These bits must be written to their
reset default value (0x0).

0x0

11--0

RPIH_STATE[A--D]

[7--12][1:0]

Receive Pointer Interpretation Hardware
State[Bits 7--12]. Software access to the 48
STS-1 PI state values. 00 = Normal;
01 = Concat; 10 = LOP; 11 = AIS.

0xAAA

0838,

088A,

08DC,

092E

15--13

TRDIPINT[A--D][2:0]

Transmit RDI-P State. State bits indicating the
value of the inserted RDI-P value.

000

12--7

Reserved. These bits must be written to their
reset default value (000000).

000000

6--4

RRDIPDMON[A--D][2:0]

Receive RDI-P Data Monitor State. State bits
indicating the value of the G1[3:1] bits.

000

RUC2VS[A--D]

Receive Unequipped C2 Value State. State
bit indicating an unequipped value (0x00) has
been detected in the C2 byte.

RPPLMS[A--D]

Receive Path Payload Label Mismatch State.
State bit indicating a mismatch occurred
(logic 1).

RSDS[A--D]

Receive Signal Degrade State Bit. State bit
indicating the state of the BER algorithm.
0 = within BER programmed, 1 = exceed BER
threshold programmed.

RSF[A--D]

Receive Signal Fail State Bit. State bit
indicating the state of the BER algorithm.
0 = within BER programmed, 1 = exceed BER
threshold programmed.

0839,

088B,

08DD,

092F

15--8

RF2DMON[A--D][7:0]

Receive F2 Byte Data Monitor. State byte
indicating the value of the validated F2 byte.

0x00

7--0

RC2DMON[A--D][7:0]

Receive C2 Data Monitor. State byte holding
the accepted value for the monitored C2 byte.

0x00

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Data Sheet
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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

(continued)

Table 98. Registers 0x0836--0x083B, 0x0868--0x0887, 0x0888--0x088D, 0x08BA--0x08D9, 0x08DA--

0x08DF, 0x090C--0x092B, 0x092C--0x0931, 0x095E--0x097D: PT State Registers (RO)
(continued)

Reset default of registers 0x0836, 0x0837, 0x0888, 0x0889, 0x08DA, 0x08DB, 0x092C, 0x092D = 0x0AAA.
Reset default of all other registers = 0x0000.

Table 99. Register 0x097E: PT Interrupt Mask Control (R/W)

Reset default of register = 0x000F.

Address

(Hex)

Bit #

Name

Function

Reset

Default

083A,
088C,

08DE,

0930

15--8

RZ3DMON[A--D][7:0]

Receive Z3 Byte Data Monitor. State byte
indicating the value of the validated Z3 byte.

0x00

7--0

RH4DMON[A--D][7:0]

Receive H4 Byte Data Monitor. State byte
indicating the value of the validated H4 byte.

0x00

083B,
088D,
08DF,

0931

15--8

RZ5DMON[A--D][7:0]

Receive Z5 Byte Data Monitor. State byte
indicating the value of the validated Z5 byte.

0x00

7--0

RZ4DMON[A--D][7:0]

Receive Z4 Byte Data Monitor. State byte
indicating the value of the validated Z4 byte.

0x00

0868--0887

15--0

RJ1DMON[A][1--64][7:0]

Receive J1 Data Monitor Values. Status
registers for J1 storage.

0x0000

08BA--08D9

15--0

RJ1DMON[B][1--64][7:0]

090C--092B

15--0

RJ1DMON[C][1--64][7:0]

095E--097D

15--0

RJ1DMON[D][1--64][7:0]

Address

(Hex)

Bit #

Name

Function

Reset

Default

097E

15--14

PT_FUNCMODE

Path Terminator Functional Mode. These bits
set the functional mode of the path terminator.
Only the values below are valid.

Bit 15 Bit 14

PT Function

normal mode

pass-through mode (ATM/SDL
over fiber)

13--4

Reserved. These bits must be written to their
reset default value (0000000000).

0000
0000

PTINTM[D]

Interrupt Masks. Mask bits to inhibit the
associated composite delta/event bits for each
port from contributing to the interrupt signal
from the PT macro. Setting these bits to 1
masks the interrupts.

0xF

PTINTM[C]

PTINTM[B]

PTINTM[A]

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Data Sheet
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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

(continued)

Table 100. Registers 0x097F--0x0980, 0x098C--0x098D, 0x0999--0x099A, 0x09A6--0x09A7: PT Interrupt

Mask Control (R/W)

(continued)

Reset default of registers 0x097F, 0x098C, 0x0999, 0x09A6 = 0x8FFF.
Reset default of registers 0x0980, 0x098D, 0x099A, 0x09A7 = 0xFFFF.

Address

(Hex)

Bit #

Name

Function (All Mask Bits Are Active-High)

Reset

Default

0980, 098D,

099A, 09A7

TRDIPINTM[A--D]

Transmit RDI-P Mask. Mask bit to inhibit the
associated delta bit from contributing to the
interrupt pin (INT).

14--11

Reserved. These bits must be written to their
reset default value (1111).

1111

RZ5DMONM[A--D]

Receive Z5 Data Monitor Mask. Mask bit to
inhibit the associated delta bit from contributing
to the interrupt pin (INT).

RZ4DMONM[A--D]

Receive Z4 Data Monitor Mask. Mask bit to
inhibit the associated delta bit from contributing
to the interrupt pin (INT).

RZ3DMONM[A--D]

Receive Z3 Data Monitor Mask. Mask bit to
inhibit the associated delta bit from contributing
to the interrupt pin (INT).

RH4DMONM[A--D]

Receive H4 Data Monitor Mask. Mask bit to
inhibit the associated delta bit from contributing
to the interrupt pin (INT).

RF2DMONM[A--D]

Receive F2 Data Monitor Mask. Mask bit to
inhibit the associated delta bit from contributing
to the interrupt pin (INT).

RRDIPDMONM[A--D]

Receive RDI-P Data Monitor Mask. Mask bit
to inhibit the associated delta bit from
contributing to the interrupt pin (INT).

RC2DMONM[A--D]

Receive C2 Value Mask. Mask bit to inhibit the
associated delta bit from contributing to the
interrupt pin (INT).

RUC2VM[A--D]

Receive Unequipped C2 Values Mask. Mask
bit to inhibit the associated delta bit from
contributing to the interrupt pin (INT).

RPPLMM[A--D]

Receive Path Payload Label Mismatch Mask.
Mask bit to inhibit the associated delta bit from
contributing to the interrupt pin (INT).

RSDM[A--D]

Receive Signal Degrade Mask. Mask bit to
inhibit the associated delta bit from contributing
to the interrupt pin (INT).

RSFM[A--D]

Receive Signal Fail Mask. Mask bit to inhibit
the associated delta bit from contributing to the
interrupt pin (INT).

198

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

(continued)

Table 101. Registers (0x09B3, 0x09BF, 0x09CB, 0x09D7, 0x09E3), (0x09EF, 0x09FB, 0x0A07, 0x0A14,

0x0A20), (0x0A2C, 0x0A38, 0x0A44, 0x0A50, 0x0A5C), (0x0A68, 0x0A74, 0x0A80, 0x0A8C,
0x0A98): Error Counters (RO)

Reset default of registers = 0x0000.

Table 102. Register 0x0AA4: PT One-Shot Control Parameters (WO)

Address

(Hex)

Bit #

Name

Function

Reset

Default

09B3, 09EF,
0A2C, 0A68

15--11

Reserved. These bits must be written to their
reset default value (00000).

00000

10--0

RPI_INC[A--D][10:0]

Receive Pointer Interpreter Increment
Counter. Counter that counts the number of
increments that occurred on the selected time
slot.

000

0000
0000

09BF, 09FB,

0A38, 0A74

15--11

Reserved. These bits must be written to their
reset default value (00000).

00000

10--0

RPI_DEC[A--D][10:0]

Receive Pointer Interpreter Decrements
Counter. Counter that counts the number of
decrements that occurred on the selected time
slot.

000

0000
0000

09CB, 0A07,

0A44, 0A80

15--13

Reserved. These bits must be written to their
reset default value (000).

000

12--0

RNDFCNT[A--D][12:0]

Receive Pointer Interpreter NDF Counter.
Counter that counts the number of set NDF
(1001) values received on the selected time
slot.

0000
0000
0000

09D7, 0A14,

0A50, 0A8C

15--0

RB3ERRCNT[A--D][15:0]

B3 Error Count. Number of B3 errors detected
on the monitored STS-1 time slots.

0x0000

09E3, 0A20,

0A5C, 0A98

15--0

RREIPERRCNT

[A--D][15:0]

Receive Remote Error Indication--Path
Error Count. Count of the number of B3 errors
detected in the G1[7:4] nibble.

0x0000

Address

(Hex)

Bit #

Name

Function

Reset

Default

0AA4

15--12

SDCLEAR[A--D]

Signal Degrade Clear. One-shot clear control.

11--8

SDSET[A--D]

Signal Degrade Set. One-shot set control.

7--4

SFCLEAR[A--D]

Signal Fail Clear. One-shot clear control.

3--0

SFSET[A--D]

Signal Fail Set. One-shot set control.

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Data Sheet
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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

(continued)

Table 103. Registers 0x0AA6--0x0AAD, 0x0AAE, 0x0AB5, 0x0AB6--0x0ABD, 0x0ABE--0x0AC5: PT Control

Parameters (R/W)

Reset default of registers 0x0AA6, 0x0AAE, 0x0AB6, 0x0ABE = 0x1200.
Reset default of registers 0x0AA7, 0x0AAF, 0x0AB7, 0x0ABF = 0x0000.
Reset default of registers 0x0AA8, 0x0AB0, 0x0AB8, 0x0AC0 = 0x0FFF.
Reset default of registers 0x0AA9, 0x0AB1, 0x0AB9, 0x0AC1 = 0x0000.
Reset default of registers 0x0AAA, 0x0AB2, 0x0ABA, 0x0AC2 = 0x0000.
Reset default of registers 0x0AAB, 0x0AB3, 0x0ABB, 0x0AC3 = 0x1AAA.
Reset default of registers 0x0AAC, 0x0AB4, 0x0ABC, 0x0AC4 = 0x3AAA.
Reset default of registers 0x0AAD, 0x0AB5, 0x0ABD, 0x0AC5 = 0x3333.

* These bits maintain the validated J1 byte, place 0x0000 into all other POH bytes, and invalidate the received payload so that no data is passed

through the DE. These bits do not affect the transmit path and do not affect the transmitted G1 byte.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0AA6, 0AAE,

0AB6, 0ABE

15--12

RPOHMONSEL

[A--D][3:0]

Receive POH Monitor Select. Control bit selects which
of the 12 time-slot POH bytes are monitored in the
associated data stream. A total of four
STS-Nc streams can be monitored at any one time.
Only values from 0001 (time slot 1) to 1100
(time slot 12) are valid. For quad OC-3 and quad OC-12
mode, use the default value 0001.

0001

11--10

Reserved. These bits must be written to their reset
default value (00).

RCONC_ALLOR

FIRST[A--D]

Receive Concatenation State: Use All STS-1 Time
Slots or Just the First One. If set to 1, all STS-1 time
slots are used. If set to 0, a higher level state machine
(CONC) is used to process the individual states from
the associated time slots. The higher-order state
machine is defined as follows.

CONC State Equations (ETSI and G.783 (SDH)):

States

Concatenation States

(bold states are reported)

AISX

AIS

AND AISC

AND . . . AISC

NORMX

NORM

AND CONC

AND . . . CONC

INCX*

INC

AND CONC

AND . . . CONC

DECX*

DEC

AND CONC

AND . . . CONC

NDFX*

NDF

AND CONC

AND . . . CONC

LOPX

(Any other): NOT AISX

AND NOT NORMX
AND NOT INCX
AND NOT DECX
AND NOT NDFX

* States INCX, DECX, and NDFX are considered the same as

NORMX state in terms of reporting.

8--7

RJ1FRAMEA

[A--D][1:0]

Receive J1 Frame Algorithm. Control bits, when set to
00 or 11 = no framing; 01 = SONET framing; 10 = SDH
framing.

200

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

(continued)

Table 103. Registers 0x0AA6--0x0AAD, 0x0AAE, 0x0AB5, 0x0AB6--0x0ABD, 0x0ABE--0x0AC5: PT Con-

trol Parameters (R/W) (continued)

Reset default of registers 0x0AA6, 0x0AAE, 0x0AB6, 0x0ABE = 0xF200.
Reset default of registers 0x0AA7, 0x0AAF, 0x0AB7, 0x0ABF = 0x0000.
Reset default of registers 0x0AA8, 0x0AB0, 0x0AB8, 0x0AC0 = 0x0FFF.
Reset default of registers 0x0AA9, 0x0AB1, 0x0AB9, 0x0AC1 = 0x0000.
Reset default of registers 0x0AAA, 0x0AB2, 0x0ABA, 0x0AC2 = 0x0000.
Reset default of registers 0x0AAB, 0x0AB3, 0x0ABB, 0x0AC3 = 0x1AAA.
Reset default of registers 0x0AAC, 0x0AB4, 0x0ABC, 0x0AC4 = 0x3AAA.
Reset default of registers 0x0AAD, 0x0AB5, 0x0ABD, 0x0AC5 = 0x3333

* SS pointer interpretation algorithm is not implemented.
These bits maintain the validated J1 byte, place 0x0000 into all other POH bytes, and invalidate the received payload so that no data is passed

through the DE. These bits do not affect the transmit path and do not affect the transmitted G1 byte.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0AA6, 0AAE,

0AB6, 0ABE

RJ1DMPC[A--D]

Receive J1 Dump Control. Control bit, when set
to a logic 1, causes the device to store the J1 byte
of the selected STS-1 time slot.

Reserved. This bit must be written to its reset
default value (0).*

RB3BITBLKCNT[A--D]

Receive B3 Bit/Block Count. Control bit, when
set to a logic 0, causes the B3 error counter to
count bit errors; otherwise, block errors are
counted.

RINCDEC_6OR8MAJ

[A--D]

Receive Increment/Decrement 6-or-8 Majority
Voting. If programmed to a logic 0, uses 6 of 10
majority voting to determine a valid increment or
decrement; otherwise, uses 8 of 10 majority voting.

2--1

Reserved. These bits must be written to their reset
default value (00).

RDIPMON_ENH_OR1B

[A--D]

Remote Defect Indication Enhanced or 1-Bit
Monitoring. Control bit, when set to a logic 1,
causes the RDI-P to detect G1[3:1] bits for an
enhanced failure code; otherwise, monitors G1[3]
for a 1-bit code.

0AA7, 0AAF,

0AB7, 0ABF

15--12

RFORCE_LOP[A--D]

[1--4]

Receive FORCE_LOP. Control bits, when set to a
logic 1, force the associated time slot into the LOP

state; otherwise, does nothing.

0x0

11--0

CONCATI_EXPECTED

[A--D][1--12]

Concatenation Indication Expected. Control bits,
when set to 0 = do not expect associated time slot
to be in CONC mode; otherwise, expect CONC
mode.

0x000

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Data Sheet
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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

(continued)

Table 103. Registers 0x0AA6--0x0AAD, 0x0AAE, 0x0AB5, 0x0AB6--0x0ABD, 0x0ABE--0x0AC5: PT Con-

trol Parameters (R/W) (continued)

* These bits maintain the validated J1 byte, place 0x0000 into all other POH bytes, and invalidate the received payload so that no data is passed

through the DE. These bits do not affect the transmit path and do not affect the transmitted G1 byte.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0AA8, 0AB0,

0AB8, 0AC0

15--12

RFORCE_LOP[A--D]

[5--8]

Receive FORCE_LOP. Control bits, when set
to a logic 1, force the associated time slot into
the LOP state; otherwise, does nothing.*

0x0

11--0

MASK_CONCAT[A--D]

[1--12]

MASK_CONCATENATION Expected
Indication. When set, mask bits inhibit the
generation of AIS when the selected time slot
transitions to a state other than
CONCAT_EXPECTED[A--D].

0xFFF

0AA9, 0AB1,

0AB9, 0AC1

15--12

RFORCE_LOP[A--D]

[9--12]

Receive FORCE_LOP. Control bits, when set
to a logic 1, force the associated time slot into
the LOP state; otherwise, does nothing.*

0x0

11--0

RFORCE_AIS[A--D]

[1--12]

Receive FORCE AIS. If set, control bits insert
AIS-P into the selected STS-1 time slot.*

0x000

0AAA, 0AB2,

0ABA, 0AC2

15--12

Tx_REIP_VALUE

[A--D][3:0]

Transmit REI-P Error Value. REI software
error value. Error values are 1 to 8; all others
are interpreted as no errors.

0x0

TRDIPSINS[A--D]

Transmit RDI-P Software Insert. Control bit,
when set, forces the value in
TRDIPDINS[A--D][2:0] into the outgoing
G1[3:1] bits.

Reserved. This bit must be written to its reset
default value (0).

TRDIP_LCD[A--D]

Transmit RDI-P LCD. Control bit, when clear,
generates an LCD failure that causes an RDI-P
generation. When set, no LCD failure is
generated. LCD determination must be done
via software.

TRDIP_PLMPINH[A--D]

Transmit RDI-P PLM-P Inhibit. Control bit,
when set, causes the PLM-P failure to not
contribute to RDI-P generation.

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

(continued)

Table 103. Registers 0x0AA6--0x0AAD, 0x0AAE, 0x0AB5, 0x0AB6--0x0ABD, 0x0ABE--0x0AC5: PT Con-

trol Parameters (R/W) (continued)

Address

(Hex)

Bit #

Name

Function

Reset

Default

0AAA, 0AB2,

0ABA, 0AC2

TRDIP_UNEQUIPINH

[A--D]

Transmit RDI-P UNEQUIP Inhibit. Control bit,
when set, causes the UNEQUIP failure to not
contribute to RDI-P generation.

TRDIP_LOPPINH[A--D]

Transmit RDI-P LOP-P Inhibit. Control bit,
when set, causes the LOP-P failure to not
contribute to RDI-P generation.

TRDIP_AISINH[A--D]

Transmit RDI-P AIS-P Inhibit. Control bit,
when set, causes the AIS-P failure to not
contribute to RDI-P generation.

TRDIP_ENH_OR1B[A--D] Transmit RDI-P Enhanced or 1-Bit

Monitoring. Control bit, when set, causes
enhanced failure code insert to occur on the
G1[3:1] bits; otherwise, inserts a single bit
failure code into G1[3].

TREIPERRINS[A--D]

Transmit REI-P Error Insert. Control bit, when
set, causes an error to be continuously injected
into the G1[7:4] bits.

TB3ERRINS[A--D]

Transmit B3 Error Insert. Control bit, when
set, causes the B3 value to be inverted.

TJ1SINS[A--D]

Transmit J1 Software Insert. Control bit, when
set, causes the J1 byte stored in the
TJ1DINS[A--D][1--64][7:0] register to be
injected into the outgoing J1 byte; otherwise,
inserts 0x00 into the J1 byte.

Reserved. This bit must be written to its reset
default value (0).

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Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

(continued)

Table 103. Registers 0x0AA6--0x0AAD, 0x0AAE, 0x0AB5, 0x0AB6--0x0ABD, 0x0ABE--0x0AC5: PT Con-

trol Parameters (R/W) (continued)

Address

(Hex)

Bit #

Name

Function

Reset

Default

0AAB, 0AB3,

0ABB, 0AC3

15--12

TPOHINSSEL[A--D][3:0]

Transmit POH Insert Select. Control bits,
when set, select the STS-1 time slot into which
POH data is injected.

0x1

11--0

THx_STATE[A--D]

[1--6][1:0]

Transmit H Bytes Software State. Control
bits, when set to a logic 00 = normal state,
01 = CONC, 10 = unequipped, 11 = AIS.

0xAAA

0AAC, 0AB4,

0ABC, 0AC4

15--12

CNTDH4Z3Z4[A--D][3:0]

Continuous N Times Detect H4/Z3/Z4 Bytes.
Control signal for detecting changes in state of
the H4, Z3, and Z4 bytes. Valid values are 0 to
15. A value of 0 or 1 causes the data monitor
byte to be updated every frame.

A value of n, where 2

15, of these four bits

means that the same value of the H4, Z3, or Z4
byte must be detected n times consecutively to
declare a new value in the H4, Z3, or Z4 byte
register.

0x3

11--0

THx_STATE[A--D]

[7--12][1:0]

Transmit H Bytes Software State. Control
bits, when set to a logic 00 = normal state,
01 = CONC, 10 = unequipped, 11 = AIS.

0xAAA

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

(continued)

Table 103. Registers 0x0AA6--0x0AAD, 0x0AAE, 0x0AB5, 0x0AB6--0x0ABD, 0x0ABE--0x0AC5: PT Con-

trol Parameters (R/W) (continued)

Address

(Hex)

Bit #

Name

Function

Reset

Default

0AAD, 0AB5,

0ABD, 0AC5

15--12

CNTDZ5[A--D][3:0]

Continuous N Times Detect Z5 Byte. Control
signal for detecting changes in state of the Z5
byte. Valid values are 0 to 15. A value of 0 or 1
causes the data monitor byte to be updated
every frame.

A value of n, where 2

15, of these four bits

means that the same value of the Z5 byte must
be detected n times consecutively to declare a
new value in the Z5 byte register.

0x3

11--8

CNTDF2[A--D][3:0]

Continuous N Times Detect F2 Byte. Control
signal for detecting changes in state of the F2
byte. Valid values are 0 to 15. A value of 0 or 1
causes the data monitor byte to be updated
every frame.

A value of n, where 2

15, of these four bits

means that the same value of the F2 byte must
be detected n times consecutively to declare a
new value in the F2 byte register.

0x3

7--4

CNTDRDIP[A--D][3:0]

Continuous N Times Detect RDI-P. Control
signal for detecting changes in state of the
G1[3:1] bits. Valid values are 0 to 15. A value of
0 or 1 causes the data monitor byte to be
updated every frame.

A value of n, where 2

15, of these four bits

means that the same value of the RDI-P byte
must be detected n times consecutively to
declare a new value in the RDI-P byte register.

0x3

3--0

CNTDC2[A--D][3:0]

Continuous N Times Detect C2 Byte. Control
signal for detecting changes in state of the C2
byte. Valid values are 0 to 15. A value of 0 or 1
causes the data monitor byte to be updated
every frame.

A value of n, where 2

15, of these four bits

means that the same value of the C2 byte must
be detected n times consecutively to declare a
new value in the C2 byte register.

0x3

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Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

(continued)

Table 104. Registers 0x0AC6--0x0AF7: PT Provisioning (R/W)

Reset default of register 0x0AC6 = 0x0001.
Reset default of registers 0x0AC7--0x0ACB = 0x0000.

* SS pointer interpretation algorithm is not implemented.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0AC6

15--6

Reserved. These bits must be written to their
reset default value (0000000000).

0000
0000

5--4

PG_PROV_PNUM[1:0]

Page Provisioning Port Number. Control bit
that selects the port being provisioned. 00 =
port A, 01 = port B, 10 = port C, and 11 = port
D.

3--0

PG_PROV_TNUM[3:0]

Page Provisioning Time-Slot Number.
Control bit that selects the time slot being
provisioned. Legal values are 1 to 12, all illegal
values default to time slot 1.

0x1

0AC7

15--13

TRDIPDINS[2:0]

Transmit RDI-P Data Insert. Software insert
value.

000

12--11

TSS[1:0]

Transmit SS Value. Control values inserted
into the SS bits in the H1 byte.

10--2

Reserved. These bits must be written to their
reset default value (000000000).

0000
0000

1--0

Reserved. These bits must be written to their
reset default value (00).*

0AC8

15--8

Reserved. These bits must be written to their
reset default value (0x00).

0x00

7--0

RC2EXPVAL[7:0]

Receive C2 Expected Value. Expected value
for the C2 byte.

0x00

0AC9

15--8

TF2DINS[7:0]

Transmit F2 Data Insert. Programmable F2
byte insert value.

0x00

7--0

TC2DINS[7:0]

Transmit C2 Data Insert. Insert byte for the
outgoing C2 bytes.

Note: A value of zero causes an unequipped

signal to be generated.

0x00

0ACA

15--8

TZ3DINS[7:0]

Transmit Z3 Data Insert. Programmable Z3
byte insert value.

0x00

7--0

TH4DINS[7:0]

Transmit H4 Data Insert. Programmable H4
byte insert value.

0x00

0ACB

15--8

TZ5DINS[7:0]

Transmit Z5 Data Insert. Programmable Z5
byte insert value.

0x00

7--0

TZ4DINS[7:0]

Transmit Z4 Data Insert. Programmable Z4
byte insert value.

0x00

206

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

(continued)

Table 105. Registers 0x0ACC--0x0AD1: PT Signal Fail BER Algorithm Parameters (R/W)

Reset default of registers 0x0ACC--0x0AD1 = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0ACC

15--8

PT_SFMSET[7:0]

Signal Fail M Set. Threshold of the number of
bad monitoring blocks in an observation
interval. If the number of bad blocks is below
this threshold, then RHSSD is cleared.

0x00

7--4

Reserved. These bits must be written to their
reset default value (0x0).

0x0

3--0

PT_SFLSET[3:0]

Signal Fail L Set. Error threshold for
determining if a monitoring block is bad.

0x0

0ACD

15--13

PT_SFNSSET[18:16]

Signal Fail Ns Set. Number of frames in a
monitoring block for RHSSD.

000

Reserved. This bit must be written to its reset
default value (0).

11--0

PT_SFBSET[11:0]

Signal Fail B Set. Number of monitoring
blocks.

0x000

0ACE

15--0

PT_SFNSSET[15:0]

Signal Fail Ns Set. Number of frames in a
monitoring block for RHSSD.

0x0000

0ACF

15--8

PT_SFMCLEAR[7:0]

Signal Fail M Clear. Threshold of the number
of bad monitoring blocks in an observation
interval. If the number of bad blocks is below
this threshold, then RHSSD is cleared.

0x00

7--4

Reserved. These bits must be written to their
reset default value (0x0).

0x0

3--0

PT_SFLCLEAR[3:0]

Signal Fail L Clear. Error threshold for
determining if a monitoring block is bad.

0x0

0AD0

15--13

PT_SFNSCLEAR[18:16]

Signal Fail Ns Clear. Number of frames in a
monitoring block for RHSSD.

000

Reserved. This bit must be written to its reset
default value (0).

11--0

PT_SFBCLEAR[11:0]

Signal Fail B Clear. Number of monitoring
blocks.

0x000

0AD1

15--0

PT_SFNSCLEAR[15:0]

Signal Fail Ns Clear. Number of frames in a
monitoring block for RHSSD.

0x0000

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Data Sheet
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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

(continued)

Table 106. Registers 0x0AD2--0x0AD7: PT Signal Degrade BER Algorithm Parameters (R/W)

Reset default of registers 0x0AD2--0x0AD7 = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

0AD2

15--8

PT_SDMSET[7:0]

Signal Degrade M Set. Threshold of the number of
bad monitoring blocks in an observation interval. If
the number of bad blocks is below this threshold, then
RHSSD is cleared.

0x00

7--4

Reserved. These bits must be written to their reset
default value (0x0).

0x0

3--0

PT_SDLSET[3:0]

Signal Degrade L Set. Error threshold for
determining if a monitoring block is bad.

0x0

0AD3

15--13

PT_SDNSSET[18:16] Signal Degrade Ns Set. Number of frames in a

monitoring block for RHSSD.

000

Reserved. This bit must be written to its reset default
value (0).

11--0

PT_SDBSET[11:0]

Signal Degrade B Set. Number of monitoring blocks.

0x000

0AD4

15--0

PT_SDNSSET[15:0]

Signal Degrade Ns Set. Number of frames in a
monitoring block for RHSSD.

0x0000

0AD5

15--8

PT_SDMCLEAR[7:0]

Signal Degrade M Clear. Threshold of the number of
bad monitoring blocks in an observation interval. If
the number of bad blocks is below this threshold, then
RHSSD is cleared.

0x00

7--4

Reserved. These bits must be written to their reset
default value (0x0).

0x0

3--0

PT_SDLCLEAR[3:0]

Signal Degrade L Clear. Error threshold for
determining if a monitoring block is bad.

0x0

0AD6

15--13

PT_SDNSCLEAR

[18:16]

Signal Degrade Ns Clear. Number of frames in a
monitoring block for RHSSD.

000

Reserved. This bit must be written to its reset default
value (0).

11--0

PT_SDBCLEAR[11:0] Signal Degrade B Clear. Number of monitoring

blocks.

0x000

0AD7

15--0

PT_SDNSCLEAR

[15:0]

Signal Degrade Ns Clear. Number of frames in a
monitoring block for RHSSD.

0x0000

208

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

(continued)

Table 107 and Table 108 show values of Ns, L, M, and B for STS-3/STM-1, STS-12/STM-4, and STS-48/STM-16 to
set and clear the BER indicator. SF registers are 0x0ACC--0x0AD1, and SD registers are 0x0AD2--0x0AD7. All
SF/SD set and clear values are hexadecimal.

Table 107. Ns, L, M, and B Values to Set the BER Indicator

* These are the numbers to be provisioned in TDAT042G5. The actual values of the BER algorithm are 1 greater than the actual values shown.

These BER values cannot be provisioned because the maximum value of L is 0xF (i.e., L is a 4-bit register).

Mode

BER

SF/SD Set Values

Actual

Number of

Frames

Probability of

Detecting L

Errors (%)

Probability of

Declaring

SF/SD (%)

Integra-

tion

Time

(s)

Max-

imum

Number

of Frames

Ns*

@BER

@BER/2

@BER

@BER/2

STS-3/

STM-1

1.00E-03

99.96

85.13

97.68

0.00

0.008

1.00E-04

72.70

7.28

96.06

0.16

0.013

104

1.00E-05

384

71.34

10.08

95.19

0.52

0.1

800

1.00E-06

1E0

3840

71.34

10.09

95.19

0.52

8000

1.00E-07

1275

47250

69.74

9.44

95.07

0.13

80000

1.00E-08

B5A4

465000

68.07

8.82

98.47

0.82

664000

1.00E-09

3F7A0

4160000

56.90

11.25

96.52

0.60

667

5336000

1.00E-10

STS-12/

STM-4

1.00E-03

100.00

88.43

100.00

0.04

0.008

1.00E-04

84.92

9.64

98.38

0.00

0.008

1.00E-05

117

67.93

7.17

96.48

0.25

0.025

200

1.00E-06

1152

66.19

6.66

95.46

0.19

0.25

2000

1.00E-07

4FB

11475

65.75

6.53

95.16

0.18

2.5

20000

1.00E-08

31CE

114750

65.75

6.53

95.16

0.18

168000

1.00E-09

1F20C

1147500

65.75

6.53

95.16

0.18

167

1336000

1.00E-10

STS-48/

STM-16

1.00E-03

100.00

0.008

1.00E-04

99.95

58.97

96.89

0.00

0.008

1.00E-05

320

90.60

16.25

96.47

0.00

0.008

1.00E-06

480

77.55

13.09

96.69

0.00

0.0625

500

1.00E-07

13A

4710

75.80

12.15

95.17

0.00

0.625

5000

1.00E-08

C1C

46500

74.58

11.54

98.09

0.01

5.2

41600

1.00E-09

765C

333300

82.92

19.71

97.29

0.18

336000

1.00E-10

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Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

PT Registers

(continued)

Table 108. Ns, L, M, and B Values to Clear the BER Indicator

* These are the numbers to be provisioned in TDAT042G5. The actual values of the BER algorithm are 1 greater than the actual values shown.

These BER values cannot be provisioned because the maximum value of L is 0xF (i.e., L is a 4-bit register).

Mode

BER

SF/SD Set Values

Actual

Number of

Frames

Probability of

Detecting L

Errors (%)

Probability of

Clearing

SF/SD (%)

Integra-

tion

Time

(s)

Max-

imum

Number

of Frames

Ns*

@BER*5

@BER

@BER*5

@BER

STS-3/

STM-1

1.00E-03

1.00E-04

85.13

0.39

0.27

100.00

0.013

104

1.00E-05

93.01

11.33

0.01

99.21

0.1

800

1.00E-06

384

84.42

6.84

0.34

99.88

8000

1.00E-07

1E05

3840

84.42

6.84

0.34

99.88

80000

1.00E-08

1275

47250

83.66

6.59

0.22

99.98

664000

1.00E-09

B5A4

465000

82.86

6.35

0.03

99.75

667

5336000

1.00E-10

3F7A0

4160000

46.31

1.48

0.50

99.84

6670

53360000

STS-12/

STM-4

1.00E-03

1.00E-04

100.00

51.54

0.00

99.03

0.008

1.00E-05

98.36

20.51

0.07

100.00

0.025

200

1.00E-06

117

87.99

8.23

0.02

99.59

0.25

2000

1.00E-07

1152

87.34

7.94

0.02

99.64

2.5

20000

1.00E-08

4FB

11475

87.17

7.87

0.03

99.65

168000

1.00E-09

31CE

114750

87.17

7.87

0.03

99.65

167

1336000

1.00E-10

1F20C

1147500

87.17

7.87

0.03

99.65

1670

13360000

STS-48/

STM-16

1.00E-03

1.00E-04

100.00

45.99

0.00

99.42

0.008

1.00E-05

100.00

60.11

0.00

99.47

0.008

1.00E-06

320

95.07

7.28

0.00

99.98

0.0625

500

1.00E-07

640

87.34

7.94

0.00

99.94

0.625

5000

1.00E-08

13A

6280

86.52

7.61

0.00

99.95

5.2

41600

1.00E-09

C1C

62000

85.95

7.38

0.00

99.96

336000

1.00E-10

765C

333300

84.89

7.00

0.03

99.95

420

3360000

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Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

This section gives a brief description of each register bit and its functionality. All algorithms are described in the
main text of the document. The abbreviations after each register indicate if the register is read only (RO), read/write
(R/W), write only (WO), or clear-on-read or clear-on-write (COR/W).

0x indicates a hexadecimal value in the Reset Default column. Otherwise, the entry is binary. This is true for every
register table in the document.

Table 111. Register 0x1000: DE Macrocell Version Number (RO)

Reset default of register = 0x0001.

Table 112. Register 0x1001, 0x1002: DE Interrupts (0x1001 is RO, 0x1002 is RO and COR/W)

Reset default of registers = 0x0000.

Note: Register 0x1001 is cleared by accessing the source register of the interrupt. The source register must be

read and cleared to clear these registers.

Address

(Hex)

Bit #

Name

Function

Reset

Default

1000

15--0

DE_VERSION

Macrocell Version Number. The version of the macrocell will
increment each time a change occurs to the macrocell
functionality.

0x0001

Address

(Hex)

Bit #

Name

Function

Reset

Default

1001

15--5

Reserved. These bits must be written to their reset default
value (00000000000).

000

0000
0000

DEINT_SDLMS

SDL Message Sent Interrupt.

Note: This bit indicates that the SDL frame inserter is

experiencing an interrupt. This bit will not clear on a
read or a write of this register, but will clear when the
SDL SDLMSI register (0x1606, bit 0) is read.

These interrupts will generate a DE interrupt.

3--0

DEINTCH[3:0]

Channel Interrupt. Active-high interrupt bit on a per-
channel basis. These bits are the ORing of all interrupt bits
associated with the error counters described in registers
0x1100--0x111F (pages 238--page 143). The error counter
can be inhibited from contributing to the interrupt by setting the
appropriate mask bit in register
DEDINTM[0--3] (addresses 0x1180, 0x1182, 0x1184, 0x1186
on page 243).

The following interrupts will generate a DE interrupt:

Bit 0 corresponds to channel 0 interrupt.

Bit 1 corresponds to channel 1 interrupt.

Bit 2 corresponds to channel 2 interrupt.

Bit 3 corresponds to channel 3 interrupt.

Note: This bit indicates that the channel is experiencing an

interrupt. This bit will not clear on a read or a write of
this register, but will clear when the counter interrupt
register DEDINTM[0--3] (addresses 0x1181, 0x1183,
0x1185, 0x1187 on page 244) is read or written.

0x0

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 112. Register 0x1001, 0x1002: DE Interrupts (0x1001 is RO, 0x1002 is RO and COR/W) (continued)

Reset default of registers = 0x0000.

Notes: Register 0x1002 must be used only in the COR mode, where core register 0x0010, bit 6 = 1.

Bits 15--12, SDL Rx frame state interrupt (DEINT_SDLRxFS), are read only. Bits 15--12 are cleared by
reading and clearing the corresponding interrupt source registers, 0x14E0--0x14E3.

Address

(Hex)

Bit #

Name

Function

Reset

Default

1002

15--12

DEINT_SDLRxFS

SDL Rx Frame State Interrupt. This interrupt
is generated when the SDL frame state is
transitioned from sync to hunt. This bit is
cleared when read only.

The following interrupts will generate a DE
interrupt:

Bit 12 corresponds to channel 0 interrupt.
Bit 13 corresponds to channel 1 interrupt.
Bit 14 corresponds to channel 2 interrupt.
Bit 15 corresponds to channel 3 interrupt.

0x0

11--8

DEINT_ATMRxAC

ATM Rx All-Cool Interrupt. This interrupt is
generated when the payload of received null/
idle cells is correctly incrementing. This bit may
clear when read or written. This interrupt is
used in conjunction with the optional
incrementing payload sequence mode for
debug purposes and is used in conjunction with
DE register 0x12F0.

Bit 8 corresponds to channel 0 interrupt.
Bit 9 corresponds to channel 1 interrupt.
Bit 10 corresponds to channel 2 interrupt.
Bit 11 corresponds to channel 3 interrupt.

Note: This signal does not generate a DE

interrupt under any circumstances.

0x0

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Data Sheet
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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 112. Register 0x1001, 0x1002: DE Interrupts (0x1001 is RO, 0x1002 is RO and COR/W) (continued)

Reset default of registers = 0x0000.

Note: Register 0x1002 must be used only in the COR mode, where core register 0x0010, bit 6 = 1.

Table 113. Register 0x1004: Dry Escape Marker (R/W)

Reset default of register = 0x0020.

Address

(Hex)

Bit #

Name

Function

Reset

Default

1002

7--4

DEINT_ATMRxF

ATM Rx Frame State Interrupt. This interrupt is
generated when the ATM frame state is
transitioned from sync to hunt. This bit may clear
when read or written.

The following interrupts will generate a DE
interrupt:

Bit 0 corresponds to channel 0 interrupt.
Bit 1 corresponds to channel 1 interrupt.
Bit 2 corresponds to channel 2 interrupt.
Bit 3 corresponds to channel 3 interrupt.

0x0

3--0

DEINT_ATMRxS

ATM Rx X

Scrambler State Interrupt. This

interrupt is generated when the ATM scrambler
state is transitioned from synchronization to
verification. This bit may clear when read or
written.

The following interrupts will generate a DE
interrupt:

Bit 4 corresponds to channel 0 interrupt.
Bit 5 corresponds to channel 1 interrupt.
Bit 6 corresponds to channel 2 interrupt.
Bit 7 corresponds to channel 3 interrupt.

0x0

Address

(Hex)

Bit #

Name

Function

Reset

Default

1004

15--8

Reserved. These bits must be written to their
reset default value (0x00).

0x00

7--0

DRYESCAPE[7:0]

Dry Escape Value. This 8-bit value, attached
with 0x7D, sets the dry marker value. The default
dry marker value would then be 0x7D20.

0x20

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 114. Registers 0x1010--0x1015: Sequencer Provisioning Registers (R/W) (continued)

Reset default of register 0x1010 = 0x0002.
Reset default of register 0x1011 = 0x2210.
Reset default of registers 0x1012, 0x1014 = 0x0435.
Reset default of registers 0x1013, 0x1015 = 0x0025.

Note: The settings of these registers must be consistent with core mode register (address 0x0010).

Address

(Hex)

Bit #

Name

Function

Reset

Default

1010

SEQ_CTRL

Sequencer Control. Selects STS-3/STM-1, STS-
12/STM-4, or STS-48/STM-16 mode for the data
engine. Allowed values are as follows:
STS-3/STM-1 = 0x0001
STS-12/STM-4 = 0x0003
STS-48/STM-16 = 0x0002

0x0002

15--2

Reserved. These bits must be written to their reset
default value (00000000000000).

0000
0000
0000

SEQ_RATE

Sequencer Rate. Configures internal clock
derived from TxCKP/TxCKN.

0 = STS-3/STM-1 (internal clock = 19.440 MHz)
1 = STS-12/STM-4 or STS-48/STM-16
(internal clock = 77.760 MHz)

SEQ_MODE

Sequencer Mode. Used with bit 1 above to select
the mode.

0 = STS-48/STM-16
1 = STS-3/STM-1 or STS-12/STM-4

1011

15--0

INIT_CNTS

Initial Counts. This register must be set to the
default value (0x2210).

0x2210

1012

15--0

OH_MARKER_LO

OHP Marker Low. This register must be
programmed as follows:
STS-48/STM-16 = 0x0435
STS-12/STM-4 = 0x0435
STS-3/STM-1 = 0x010B

0x0435

1013

15--0

OH_MARKER_HI

OHP Marker High. This register must be
programmed as follows:
STS-48/STM-16 = 0x0025
STS-12/STM-4 = 0x0025
STS-3/STM-1 = 0x0007

0x0025

1014

15--0

SOH_MARKER_LO

Sequence Provisioning for OHP Marker Low.
This register must be programmed as follows:
STS-48/STM-16 = 0x0435
STS-12/STM-4 = 0x0435
STS-3/STM-1 = 0x010B

0x0435

1015

15--0

SOH_MARKER_HI

Sequence Provisioning for OHP Marker High.
This register must be programmed as follows:
STS-48/STM-16 = 0x0025
STS-12/STM-4 = 0x0025
STS-3/STM-1 = 0x0007

0x0025

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Data Sheet

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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 115. Registers 0x1016--0x1021: Egress Configuration (R/W) (continued)

Reset default of registers 0x1016, 0x101A, 0x101E = 0x4444.
Reset default of registers 0x1017, 0x101B, 0x101F = 0x5555.
Reset default of registers 0x1018, 0x101C, 0x1020 = 0x6666.
Reset default of registers 0x1019, 0x101D, 0x1021 = 0x7777.

Note: See Figures 17--20, pages 78--81. The notation X/Y means the following: X = STS-48/STM-16 byte,

Y = STS-12/STM-4 or STS-3/STM-1 byte.

Address

(Hex)

Bit #

Name

Function

Reset

Default

1016

Tx_TS1

Egress Time Slot 1.

0x444

Tx_TS1[15:12]: Byte 1/1A : Byte 1 transmit
sequence map and channel.

0x4

Reserved. This bit must be written to its reset
default value (0).

Tx_PLD1

PLD. Defines the validity of the payload in the time
slot.

1 = valid
0 = invalid

13--12

Tx_CH1

CH. Defines one of four channels (00, 01, 10, 11).

Tx_TS1[11:8]: Byte 4/1B: Byte 4 transmit
sequence map and channel.

0x4

Reserved. This bit must be written to its reset
default value (0).

Tx_PLD4

PLD. Defines the validity of the payload in the time
slot.

1 = valid
0 = invalid

9--8

Tx_CH4

CH. Defines one of four channels (00, 01, 10, 11).

Tx_TS1[7:4]: Byte 7/1C: Byte 7 transmit sequence
map and channel.

0x4

Reserved. This bit must be written to its reset
default value (0).

Tx_PLD7

PLD. Defines the validity of the payload in the time
slot.

1 = valid
0 = invalid

5--4

Tx_CH7

CH. Defines one of four channels (00, 01, 10, 11).

Tx_TS1[3:0]: Byte 10/1D: Byte 10 transmit
sequence map and channel.

0x4

Reserved. This bit must be written to its reset
default value (0x4).

Tx_PLD10

PLD. Defines the validity of the payload in the time
slot.

1 = valid
0 = invalid

1--0

Tx_CH10

CH. Defines one of four channels (00, 01, 10, 11).

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Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 115. Registers 0x1016--0x1021: Egress Configuration (R/W) (continued)

Note: See Figures 17--20, pages 78--81. The notation X/Y means the following: X = STS-48/STM-16 byte,

Y = STS-12/STM-4 or STS-3/STM-1 byte.

Address

(Hex)

Bit #

Name

Function

Reset

Default

1017

Tx_TS2

Egress Time Slot 2. Refer to egress time slot 1.

0x5555

15--12

Byte 13/4A definition.

11--8

Byte 16/4B definition.

7--4

Byte 19/4C definition.

3--0

Byte 22/4D definition.

1018

Tx_TS3

Egress Time Slot 3. Refer to egress time slot 1.

0x6666

15--12

Byte 25/7A definition.

11--8

Byte 28/7B definition.

7--4

Byte 31/7C definition.

3--0

Byte 34/7D definition.

1019

Tx_TS4

Egress Time Slot 4. Refer to egress time slot 1.

0x7777

15--12

Byte 37/10A definition.

11--8

Byte 40/10B definition.

7--4

Byte 43/10C definition.

3--0

Byte 46/10D definition.

101A

Tx_TS5

Egress Time Slot 5. Refer to egress time slot 1.

0x4444

15--12

Byte 2/2A definition.

11--8

Byte 5/2B definition.

7--4

Byte 8/2C definition.

3--0

Byte 11/2D definition.

101B

Tx_TS6

Egress Time Slot 6. Refer to egress time slot 1.

0x5555

15--12

Byte 14/5A definition.

11--8

Byte 17/5B definition.

7--4

Byte 20/5C definition.

3--0

Byte 23/5D definition.

101C

Tx_TS7

Egress Time Slot 7. Refer to egress time slot 1.

0x6666

15--12

Byte 26/8A definition.

11--8

Byte 29/8B definition.

7--4

Byte 32/8C definition.

3--0

Byte 35/8D definition.

218

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 115. Registers 0x1016--0x1021: Egress Configuration (R/W) (continued)

Note: See Figures 17--20, pages 78--81. The notation X/Y means the following: X = STS-48/STM-16 byte,

Y = STS-12/STM-4 or STS-3/STM-1 byte.

Address

(Hex)

Bit #

Name

Function

Reset

Default

101D

Tx_TS8

Egress Time Slot 8. Refer to egress time slot 1.

0x7777

15--12

Byte 38/11A definition.

11--8

Byte 41/11B definition.

7--4

Byte 44/11C definition.

3--0

Byte 47/11D definition.

101E

Tx_TS9

Egress Time Slot 9. Refer to egress time slot 1.

0x4444

15--12

Byte 3/3A definition.

11--8

Byte 6/3B definition.

7--4

Byte 9/3C definition.

3--0

Byte 12/3D definition.

101F

Tx_TS10

Egress Time Slot 10. Refer to egress time slot 1.

0x5555

15--12

Byte 15/6A definition.

11--8

Byte 18/6B definition.

7--4

Byte 21/6C definition.

3--0

Byte 24/6D definition.

1020

Tx_TS11

Egress Time Slot 11. Refer to egress time slot 1.

0x6666

15--12

Byte 27/9A definition.

11--8

Byte 30/9B definition.

7--4

Byte 33/9C definition.

3--0

Byte 36/9D definition.

1021

Tx_TS12

Egress Time Slot 12. Refer to egress time slot 1.

0x7777

15--12

Byte 39/12A definition.

11--8

Byte 42/12B definition.

7--4

Byte 45/12C definition.

3--0

Byte 48/12D definition.

220

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 116. Registers 0x1022--0x102D: Ingress Configuration (R/W) (continued)

Reset default of registers 0x1022, 0x1026, 0x102A = 0x4444.
Reset default of registers 0x1023, 0x1027, 0x102B = 0x5555.
Reset default of registers 0x1024, 0x1028, 0x102C = 0x6666.
Reset default of registers 0x1025, 0x1029, 0x102D = 0x7777.

Note: See Figures 17--20, pages 78--81. The notation X/Y means the following: X = STS-48/STM-16 byte,

Y = STS-12/STM-4 or STS-3/STM-1 byte.

Address

(Hex)

Bit #

Name

Function

Reset

Default

1022

Rx_TS1

Ingress Time Slot 1.

0x4444

Rx_TS1[15:12]. Byte 1/Byte 1A: Byte 1 receive
sequence map and channel.

0x4

Reserved. This bit must be written to its reset
default value (0).

Rx_PLD1

PLD. Defines the validity of the payload in the time
slot.

1 = valid
0 = invalid

13--12

Rx_CH1

CH. Defines one of four channels (00, 01, 10, 11).

Rx_TS1[11:8]. Byte 4/Byte 1B: Byte 4 receive
sequence map and channel.

0x4

Reserved. This bit must be written to its reset
default value (0).

Rx_PLD4

PLD. Defines the validity of the payload in the time
slot.

1 = valid
0 = invalid

9--8

Rx_CH4

CH. Defines one of four channels (00, 01, 10, 11).

Rx_TS1[7:4]. Byte 7/Byte 1C: Byte 7 receive
sequence map and channel.

0x4

Reserved. This bit must be written to its reset
default value (0).

Rx_PLD7

PLD. Defines the validity of the payload in the time
slot.

1 = valid
0 = invalid

5--4

Rx_CH7

CH. Defines one of four channels (00, 01, 10, 11).

Rx_TS1[3:0]. Byte 10/Byte 1D: Byte 10 receive
sequence map and channel.

0x4

Reserved. This bit must be written to its reset
default value (0).

Rx_PLD10

PLD. Defines the validity of the payload in the time
slot.

1 = valid
0 = invalid

1--0

Rx_CH10

CH. Defines one of four channels(00, 01, 10, 11).

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Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 116. Registers 0x1022--0x102D: Ingress Configuration (R/W) (continued)

Note: See Figures 17--20, pages 78--81. The notation X/Y means the following: X = STS-48/STM-16 byte,

Y = STS-12/STM-4 or STS-3/STM-1 byte.

Address

(Hex)

Bit #

Name

Function

Reset

Default

1023

Rx_TS2

Ingress Time Slot 2. Refer to ingress time slot 1.

0x5555

15--12

Byte 13/4A definition.

11--8

Byte 16/4B definition.

7--4

Byte 19/4C definition.

3--0

Byte 22/4D definition.

1024

Rx_TS3

Ingress Time Slot 3. Refer to ingress time slot 1.

0x6666

15--12

Byte 25/7A definition.

11--8

Byte 28/7B definition.

7--4

Byte 31/7C definition.

3--0

Byte 34/7D definition.

1025

Rx_TS4

Ingress Time Slot 4. Refer to ingress time slot 1.

0x7777

15--12

Byte 37/10A definition.

11--8

Byte 40/10B definition.

7--4

Byte 43/10C definition.

3--0

Byte 46/10D definition.

1026

Rx_TS5

Ingress Time Slot 5. Refer to ingress time slot 1.

0x4444

15--12

Byte 2/2A definition.

11--8

Byte 5/2B definition.

7--4

Byte 8/2C definition.

3--0

Byte 11/2D definition.

1027

Rx_TS6

Ingress Time Slot 6. Refer to ingress time slot 1.

0x5555

15--12

Byte 14/5A definition.

11--8

Byte 17/5B definition.

7--4

Byte 20/5C definition.

3--0

Byte 23/5D definition.

1028

Rx_TS7

Ingress Time Slot 7. Refer to ingress time slot 1.

0x6666

15--12

Byte 26/8A definition.

11--8

Byte 29/8B definition.

7--4

Byte 32/8C definition.

3--0

Byte 35/8D definition.

222

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 116. Registers 0x1022--0x102D: Ingress Configuration (R/W) (continued)

Note:See Figures 17--20, pages 78--81. The notation X/Y means the following: X = STS-48/STM-16 byte,

Y = STS-12/STM-4 or STS-3/STM-1 byte.

Address

(Hex)

Bit #

Name

Function

Reset

Default

1029

Rx_TS8

Ingress Time Slot 8. Refer to ingress time slot 1.

0x7777

15--12

Byte 38/11A definition.

11--8

Byte 41/11B definition.

7--4

Byte 44/11C definition.

3--0

Byte 47/11D definition.

102A

Rx_TS9

Ingress Time Slot 9. Refer to ingress time slot 1.

0x4444

15--12

Byte 3/3A definition.

11--8

Byte 6/3B definition.

7--4

Byte 9/3C definition.

3--0

Byte 12/3D definition.

102B

Rx_TS10

Ingress Time Slot 10. Refer to ingress time slot 1.

0x5555

15--12

Byte 15/6A definition.

11--8

Byte 18/6B definition.

7--4

Byte 21/6C definition.

3--0

Byte 24/6D definition.

102C

Rx_TS11

Ingress Time Slot 11. Refer to ingress time slot 1.

0x6666

15--12

Byte 27/9A definition.

11--8

Byte 30/9B definition.

7--4

Byte 33/9C definition.

3--0

Byte 36/9D definition.

102D

Rx_TS12

Ingress Time Slot 12. Refer to ingress time slot 1.

0x7777

15--12

Byte 39/12A definition.

11--8

Byte 42/12B definition.

7--4

Byte 45/12C definition.

3--0

Byte 48/12D definition.

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Data Sheet
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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 117. Registers 0x102E--0x1031: Over-Fiber Mode (Packet-Over-Fiber or POF) Control (R/W)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

102E

Rx_OF_CTRL

Ingress Over-Fiber Mode Register. This register
will define the channels, if any, that are carrying
over-fiber payload in the ingress direction.

0 = SONET
1 = over-fiber mode
(For specific bits, see register Rx_TS[1--12],
page 219.)

0x0000

Reserved. These bits must be written to their reset
default value (0).

Physical channel (line) A mode.

13--12

Reserved. These bits must be written to their reset
default value (00).

Physical channel (line) B mode.

9--7

Reserved. These bits must be written to their reset
default value (000).

Physical channel (line) C mode.

5--3

Reserved. These bits must be written to their reset
default value (000).

Physical channel (line) D mode.

1--0

Reserved. These bits must be written to their reset
default value (00).

102F

Tx_OF_CTRL

Egress Over-Fiber Mode Register. This register
will define the channels, if any, that are carrying
over-fiber payload in the egress direction.

0 = SONET
1 = over-fiber mode
(For specific bits, see register Tx_TS[1--12],
page 215.)

0x0000

Reserved. These bits must be written to their reset
default value (0).

Physical channel (line) A mode.

13--12

Reserved. These bits must be written to their reset
default value (00).

Physical channel (line) B mode.

9--7

Reserved. These bits must be written to their reset
default value (000).

Physical channel (line) C mode.

5--3

Reserved. These bits must be written to their reset
default value (000).

Physical channel (line) D mode.

1--0

Reserved. These bits must be written to their reset
default value (00).

224

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 117. Registers 0x102E--0x1031: Over-Fiber Mode (Packet-Over-Fiber or POF) Control (R/W)

(continued)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

1030

Rx_CHCD_FM[15:0]

Receive Channel C/D Framer Mode. This
register is used in over-fiber mode to give the Rx
sequencer prior knowledge of the time slot and
byte location within a time slot of the valid byte of a
transparent packet for a given frame.

0x0000

15--14

Reserved. These bits must be written to their reset
default value (00).

13--10

Time slot having the last payload for channel C.

9--8

Last byte location out of 4-byte output for
channel C.

7--6

Reserved. These bits must be written to their reset
default value (00).

5--2

Time slot having the last payload for channel D.

1--0

Last byte location out of 4-byte output for
channel D.

1031

Rx_CHAB_FM[15:0]

Receive Channel A/B Framer Mode. This
register is used in over-fiber mode to give the Rx
sequencer prior knowledge of the time slot and
byte location within a time slot of the valid byte of a
transparent packet for a given frame.

0x0000

15--14

Reserved. These bits must be written to their reset
default value (00).

13--10

Time slot having the last payload for channel A.

9--8

Last byte location out of 4-byte output for
channel A.

7--6

Reserved. These bits must be written to their reset
default value (00).

5--2

Time slot having the last payload for channel B.

1--0

Last byte location out of 4-byte output for
channel B.

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Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 118. Registers 0x1032--0x1036: Sequencer Cell State Registers (R/W)

Reset default of registers 0x1032--0x1035 = 0x0000.
Reset default of register 0x1036 = 0x000F.

Table 119. Registers 0x1040--0x1043: Ingress Payload Type and Mode Control (R/W)

Reset default of registers = 0x0700.

Address

(Hex)

Bit #

Name

Function

Reset

Default

1032--1035

Rx_CELL[A--D]_FM

Rx Channel [A--D] Cell Register. This register is
used in over-fiber mode to give the Rx sequencer
prior knowledge of the cell in which the last byte of
a transparent packet for a given frame is located.

0x0000

15--10

Reserved. These bits must be written to their reset
default value (000000).

0000

9--0

RxLBCF

Rx Last Byte of Current Frame. Defines which of
the 810 SONET cells has the last byte of the
current frame in channel [A--D].

0000
0000

1036

Tx_SEQ_DISABLE

Tx Sequencer Disable. This register is used to
enable or disable channels. The default is all four
channels are disabled. In other words, the disables
on the channels must be cleared or the sequencer
will not operate.

1 = the channel is disabled; 0 = the channel is
enabled.

0x000F

15--4

Reserved. These bits must be written to their reset
default value (0x000).

0x000

Channel A Disable.

Channel B Disable.

Channel C Disable.

Channel D Disable.

Address

(Hex)

Bit #

Name

Function

Reset

Default

1040--1043

Rx_PCTL_[0--3]

Channel [0--3] Payload Type and Control.

See Table 120 for receive type and mode
control summary.

0x0700

15--11

Reserved. These bits must be written to their
reset default value (00000).

00000

10--8

Payload Type. Defines the payload type being
received.

111

7--0

Payload Control. Allows for different options
when receiving data, such as pre- or post-
unscrambling, PPP header discard, etc.

0x00

226

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 120. Receive Type and Mode Control Summary Table (Registers 0x1040--0x1043)

* No discard--Pass all ATM cells with no error correction.
Discard--Discard cells with multiple-bit header errors. Correct and pass all cells with single-bit header errors.

Smart discard--Discard cells with multiple-bit header errors, and only correct and pass the first of back-to-back single-bit header errors.

� Discard, no correction--Discard all cells with header errors.

Payload

Type, Bits

[10:8]

Payload Control, Bits [7:0]

000

PPP

0 = discard

1 = no discard

0 = header
stripped

1 = header
on

0 = CRC-16

1 = CRC-32

0 = CRC
stripped

1 = CRC on

0 = CRC reversed

1 = CRC normal

0 = no dry mode

1 = dry mode

00 = no unscrambling

01 = post-unscrambling

10 = pre-unscrambling

11 = undefined

001

HDLC with

CRC

0 = CRC-16

1 = CRC-32

0 = CRC
stripped

1 = CRC on

0 = CRC reversed

1 = CRC normal

0 = no dry mode

1 = dry mode

00 = no unscrambling

01 = post-unscrambling

10 = pre-unscrambling

11 = undefined

010

HDLC

without CRC

0 = no dry mode

1 = dry mode

00 = no unscrambling

01 = post-unscrambling

10 = pre-unscrambling

11 = undefined

011

ATM

0 = byte sync

1 = bit sync

00 = X

unscrambling

01 = no unscrambling

10 = X

unscrambling

11 = no unscrambling

0 = unassigned
cell discard

1 = unassigned
cell pass-

through

0 = idle cell
discard

1 = idle cell
passthrough

00 = no discard*

01 = discard

10 = smart discard

11 = discard, no

correction

�

100

SDL without

CRC

0 = byte sync

1 = bit sync

0 = length
stripped

1 = length on

Length offset (0x0 to 0xF)

101

SDL with

CRC

0 = byte sync

1 = bit sync

0 = length
stripped

1 = length on

0 = CRC-16

1 = CRC-32

0 = CRC
stripped

1 = CRC on

Length offset (0x0 to 0xF)

110

Transparent

payload

111

Not defined

(reset mode)

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Data Sheet
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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 121. Registers 0x1080--0x1087: ATM Framer Idle Cell Match Mask (R/W)

Reset default of registers = 0xFFFF.

Table 122. Registers 0x1088--0x108F: ATM Idle Cell Registers (R/W)

Reset default of registers 0x1088, 0x108A, 0x108C, 0x108E = 0x0000.
Reset default of registers 0x1089, 0x108B, 0x108D, 0x108F = 0x0001.

Address

(Hex)

Bit #

Name

Function

Reset

Default

1080--1087

ATM_IDM_[0--3][31:0]

ATM Idle Cell Match Mask Channel [0--3].

This 32-bit register defines which of the 32 bits
will be used for comparison between the idle
cell register and the header data in the ATM
framer. A value of 1 enables the comparison
with the corresponding bit in the ATM idle cell
register.

0xFFFF

1080

15--0

ATM_IDM_0[31:16]

[31:24] is the MSByte of ATM_IDM_0.

0xFFFF

1081

15--0

ATM_IDM_0[15:0]

[7:0] is the LSByte of ATM_IDM_0.

0xFFFF

1082

15--0

ATM_IDM_1[31:16]

[31:24] is the MSByte of ATM_IDM_1.

0xFFFF

1083

15--0

ATM_IDM_1[15:0]

[7:0] is the LSByte of ATM_IDM_1.

0xFFFF

1084

15--0

ATM_IDM_2[31:16]

[31:24] is the MSByte of ATM_IDM_2.

0xFFFF

1085

15--0

ATM_IDM_2[15:0]

[7:0] is the LSByte of ATM_IDM_2.

0xFFFF

1086

15--0

ATM_IDM_3[31:16]

[31:24] is the MSByte of ATM_IDM_3.

0xFFFF

1087

15--0

ATM_IDM_3[15:0]

[7:0] is the LSByte of ATM_IDM_3.

0xFFFF

Address

(Hex)

Bit #

Name

Function

Reset Default

1088--108F

ATM_IDC_[0--3][31:0]

ATM Idle Cell Register Channel [0--3].
This 32-bit register will store the expected
header value for idle cells. If the ATM framer
sees a header for an ATM packet which
matches this register at the bit positions
designated by the ATM idle cell match mask,
the packet will be treated as an idle cell.

See below.

1088

15--0

ATM_IDC_0[31:16]

[31:24] is the MSByte of ATM_IDC_0.

0x0000

1089

15--0

ATM_IDC_0[15:0]

[7:0] is the LSByte of ATM_IDC_0.

0x0001

108A

15--0

ATM_IDC_1[31:16]

[31:24] is the MSByte of ATM_IDC_1.

0x0000

108B

15--0

ATM_IDC_1[15:0]

[7:0] is the LSByte of ATM_IDC_1.

0x0001

108C

15--0

ATM_IDC_2[31:16]

[31:24] is the MSByte of ATM_IDC_2.

0x0000

108D

15--0

ATM_IDC_2[15:0]

[7:0] is the LSByte of ATM_IDC_2.

0x0001

108E

15--0

ATM_IDC_3[31:16]

[31:24] is the MSByte of ATM_IDC_3.

0x0000

108F

15--0

ATM_IDC_3[15:0]

[7:0] is the LSByte of ATM_IDC_3.

0x0001

228

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 123. Registers 0x1090--0x1097: ATM Unassigned Cell Match Mask (R/W)

Reset default of registers = 0xFFFF.

Table 124. Registers 0x1098--0x109F: ATM Unassigned Cell Registers (R/W)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset Default

1090--1097

ATM_USM_[0--3][31:0] ATM Unassigned Cell Match Mask

Channel [0--3]. This 32-bit register defines
which of the 32 bits will be used for
comparison between the unassigned cell
register and the header data in the ATM
framer. A value of 1 enables the comparison
with the corresponding bit in the ATM
unassigned cell register.

0xFFFF

1090

15--0

ATM_USM_0[31:16]

[31:24] is the MSByte of ATM_USM_0.

0xFFFF

1091

15--0

ATM_USM_0[15:0]

[7:0] is the LSByte of ATM_USM_0.

0xFFFF

1092

15--0

ATM_USM_1[31:16]

[31:24] is the MSByte of ATM_USM_1.

0xFFFF

1093

15--0

ATM_USM_1[15:0]

[7:0] is the LSByte of ATM_USM_1.

0xFFFF

1094

15--0

ATM_USM_2[31:16]

[31:24] is the MSByte of ATM_USM_2.

0xFFFF

1095

15--0

ATM_USM_2[15:0]

[7:0] is the LSByte of ATM_USM_2.

0xFFFF

1096

15--0

ATM_USM_3[31:16]

[31:24] is the MSByte of ATM_USM_3.

0xFFFF

1097

15--0

ATM_USM_3[15:0]

[7:0] is the LSByte of ATM_USM_3.

0xFFFF

Address

(Hex)

Bit #

Name

Function

Reset

Default

1098--109F

ATM_USG_[0--3][31:0]

ATM Unassigned Cell Register Channel 0.
This 32-bit register will store the expected
header value for unassigned cells. If the ATM
framer sees a header for an ATM packet which
matches this register at the bit positions
designated by the ATM unassigned cell match
mask, the packet will be treated as an
unassigned cell.

0x0000

1098

15--0

ATM_USG_0[31:16]

[31:24] is the MSByte of ATM_USG_0.

0x0000

1099

15--0

ATM_USG_0[15:0]

[7:0] is the LSByte of ATM_USG_0.

0x0000

109A

15--0

ATM_USG_1[31:16]

[31:24] is the MSByte of ATM_USG_1.

0x0000

109B

15--0

ATM_USG_1[15:0]

[7:0] is the LSByte of ATM_USG_1.

0x0000

109C

15--0

ATM_USG_2[31:16]

[31:24] is the MSByte of ATM_USG_2.

0x0000

109D

15--0

ATM_USG_2[15:0]

[7:0] is the LSByte of ATM_USG_2.

0x0000

109E

15--0

ATM_USG_3[31:16]

[31:24] is the MSByte of ATM_USG_3.

0x0000

109F

15--0

ATM_USG_3[15:0]

[7:0] is the LSByte of ATM_USG_3.

0x0000

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 125. Registers 0x10A0--0x10A3: ATM Framer State Registers (RO)

Reset default of registers = 0x0000.

Table 126. Register 0x10A4: ATM X43 Frame Control (R/W)

Reset default of register = 0x01C6.

Address

(Hex)

Bit #

Name

Function

Reset

Default

10A0--10A3

ATM_ST_[0--3]

Channel [0--3] ATM Scrambler Framer
State.

0x0000

15--4

Reserved. These bits must be written to their
reset default value (0x000).

0x000

3--2

ATM Framer Sync State. These bits indicate
the X31 sync state of each channel.

ATM_ST_[0--3][3:2] = 00 Acquisition
ATM_ST_[0--3][3:2] = 01 Verification
ATM_ST_[0--3][3:2] = 10 Synchronized
ATM_ST_[0--3][3:2] = 11 Undefined

1--0

ATM Frame State. These bits indicate the
frame state of each channel.

ATM_ST_[0--3][1:0] = 00 Hunt
ATM_ST_[0--3][1:0] = 01 Presync
ATM_ST_[0--3][1:0] = 10 Sync
ATM_ST_[0--3][1:0] = 11 Undefined

Address

(Hex)

Bit #

Name

Function

Reset

Default

10A4

ATM_X43[11:0]

ATM X43 Frame Control.

0x01C6

15--12

Reserved. These bits must be written to their
reset default value (0x0).

0x0

11--6

X43-Alpha. This register will define the alpha
value for the X43 alpha-delta framer which is
the number of consecutive incorrect ATM cells
that must be received in order to transition from
the sync state to the hunt state.

000111

5--0

X43-Delta. This register will define the delta
value for the X43 alpha-delta framer which is
the number of consecutive correct ATM cells
that must be received in order to transition from
the presync state to the sync state.

000110

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Data Sheet

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 127. Register 0x10A5: ATM X31 Frame Control (R/W)

Reset default of register = 0x01C8.

Table 128. Register 0x10A6: ATM X31 V/W Values (R/W)

Reset default of register = 0x0210.

Address

(Hex)

Bit #

Name

Function

Reset

Default

10A5

ATM_X31[11:0]

ATM X31 Framer Control.

0x01C8

15--12

Reserved. These bits must be written to their
reset default value (0x0).

0x0

11--6

X31-Alpha. This register will define the alpha
value for the X31 alpha-delta framer which is
the number of consecutive incorrect ATM cells
that must be received in order to transition from
the sync state to the hunt state.

000111

5--0

X31-Delta. This register will define the delta
value for the X31 alpha-delta framer which is
the number of consecutive correct ATM cells
that must be received in order to transition from
the presync state to the sync state.

001000

Address

(Hex)

Bit #

Name

Function

Reset

Default

10A6

ATM_X31VW[11:0]

X31 V and W Values.

0x0210

15--12

Reserved. These bits must be written to their
reset default value (0x0).

0x0

11--6

X31 V Value. This register specifies the value

the confidence counter in the X

scrambler

synchronization process must drop below in
order to transition to the acquisition state from
the verification state. The confidence counter is
incremented every time the local scrambler
samples match the received samples, and
decremented when they do not (see standard
I.432).

001000

5--0

X31 W Value. This register specifies the value

the confidence counter in the X

scrambler

synchronization process must drop below in
order to declare loss of synchronization and
transition to the acquisition state. The
confidence counter is incremented every time
the local scrambler samples match the received
samples, and decremented when they do not
(see standard I.432).

010000

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 129. Register 0x10A7: ATM X31 X/Y Values (R/W)

Reset default of register = 0x0418.

Table 130. Register 0x10A8: ATM X31 Z Value (R/W)

Reset default of register = 0x0018.

Address

(Hex)

Bit #

Name

Function

Reset

Default

10A7

ATM_X31XY[11:0]

X31 X and Y Values.

0x0418

15--12

Reserved. These bits must be written to their
reset default value (0x0).

0x0

11--6

X31 X Value. This register specifies the
minimum value the confidence counter in the

scrambler synchronization process must

reach in order to transition to the verification
state from the acquisition state. The confidence
counter is incremented every time the local
scrambler samples match the received
samples, and decremented when they do not
(see standard I.432).

010000

5--0

X31 Y Value. This register specifies the
minimum value the confidence counter in the

scrambler synchronization process must

reach in order to transition to the synchronized
state from the verification state. The confidence
counter is incremented every time the local
scrambler samples match the received
samples, and decremented when they do not
(see standard I.432).

011000

Address

(Hex)

Bit #

Name

Function

Reset

Default

10A8

ATM_X31Z[5:0]

X31 Z Value.

0x0018

15--6

Reserved. These bits must be written to their
reset default value (0000000000).

0000
0000

5--0

X31 Z Value. This register specifies the
maximum value the confidence counter in the

scrambler synchronization process can

achieve. The confidence counter is
incremented every time the local scrambler
samples match the received samples, and
decremented when they do not (see standard
I.432).

011000

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Data Sheet

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 131. Register 0x10A9: Frame State Interrupt Mask (R/W)

Reset default of register = 0x000F.

Table 132. Register 0x10AA: Scrambler State Interrupt Mask (R/W)

Reset default of register = 0x000F.

Address

(Hex)

Bit #

Name

Function

Reset

Default

10A9

FS_INT_MASK[3:0]

Frame State Interrupt Mask. When active
(logic 1), the associated event/delta is inhibited
from contributing to the interrupt on a per-
channel basis. Otherwise, an interrupt is
generated when the ATM frame state transitions
from sync to hunt state.

0x000F

15--4

Reserved. These bits must be written to their
reset default value (0x000).

0x000

Channel 3 Mask Value.

Channel 2 Mask Value.

Channel 1 Mask Value.

Channel 0 Mask Value.

Address

(Hex)

Bit #

Name

Function

Reset

Default

10AA

SS_INT_MASK[3:0]

Scrambler State Interrupt Mask. When active
(logic 1), the associated event/delta is inhibited
from contributing to the interrupt on a per-
channel basis. Otherwise, an interrupt is
generated when the ATM frame state transitions
from synchronization to verification state.

0x000F

15--4

Reserved. These bits must be written to their
reset default value (0x000).

0x000

Channel 3 Mask Value.

Channel 2 Mask Value.

Channel 1 Mask Value.

Channel 0 Mask Value.

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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 133. Register 0x10AB: ATM Receive Debug Register (R/W)

Reset default of register = 0x003C.

Address

(Hex)

Bit #

Name

Function

Reset

Default

10AB

ATM_Rx_DEBUG_REG[5:0] ATM Receive Debug Register.

0x003C

15--6

Reserved. These bits must be written to their
reset default value (0000000000).

0000
0000

Channel 3 All Cool-Interrupt Mask Value.
When active (logic 1), the associated event/
delta is inhibited from contributing to the
interrupt on a per-channel basis.

Channel 2 All-Cool Interrupt Mask Value.
When active (logic 1), the associated event/
delta is inhibited from contributing to the
interrupt on a per-channel basis.

Channel 1 All-Cool Interrupt Mask Value.
When active (logic 1), the associated event/
delta is inhibited from contributing to the
interrupt on a per-channel basis.

Channel 0 All-Cool Interrupt Mask Value.
When active (logic 1), the associated event/
delta is inhibited from contributing to the
interrupt on a per-channel basis.

Incrementing NULL Cell Payload Sequence.
This bit governs whether 0x6A is used for the
payload of NULL cells, or whether an
incrementing 8-bit count is used (0x00

0xFF). A value of 1 selects the incrementing
sequence. This can be used with the All_Cool
interrupt.

X31_Sync_Compare. In X

mode, when this

value is 0, the ATM framer does 6-bit
comparisons of the HEC, which does not allow
for error correction. When this value is 1, all 8
bits of the HEC are used, which does allow for
error correction.

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Data Sheet
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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 136. Transmit Type and Mode Control Summary Table (Registers 0x10E0--0x10E3)

Note: In the table below, X indicates the bit may either be 0 or 1.

Table 137. Registers 0x10F0--10FB: PPP Header Value Detach (R/W)

Reset default of registers = 0x0000.

Payload

Type, Bits

[10:8]

Payload Control, Bits [7:0]

000

PPP

0 = compression

1 = no compression

0 = CRC-16

1 = CRC-32

0 = CRC reversed

1 = CRC normal

0 = no dry
mode

1 = dry mode

00 = no scrambling

01 = postscrambling

10 = pre-scrambling

11 = undefined

001

HDLC with CRC

0 = CRC-16

1 = CRC-32

0 = CRC reversed

1 = CRC normal

0 = no dry
mode

1 = dry mode

00 = no scrambling

01 = postscrambling

10 = prescrambling

11 = undefined

010

HDLC

without CRC

0 = no dry
mode

1 = dry mode

00 = no scrambling

01 = postscrambling

10 = prescrambling

11 = undefined

011

ATM

00 = X

scrambling

01 = no scrambling

10 = X

scrambling

11 = no scrambling

100

SDL without CRC

101

SDL with CRC

0 = CRC-16

1 = CRC-32

110

Transparent

payload

111

Not defined

(reset mode)

Address

(Hex)

Bit #

Name

Function

Reset Default

10F0--10FB

15--0

PPP_Rx_HDR

[0--11][15:0]

Register [0--11] PPP Header. This register
defines the 2 bytes that can be used by all
four channels to validate a PPP packet. Byte
[15:8] is the MSByte and byte [7:0] is the
LSByte. The register defining the valid PPP
header is determined by the settings of
registers 0x0FC--0x0FF. Any channel can
compare the received PPP header to this
value. If there is a mismatch, then the PPP
mismatched header counter (addresses
0x1118--0x111F) will increment.

0x0000

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Data Sheet

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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 138. Registers 0x10FC--0x10FF: PPP Header Detach Search (R/W)

Reset default of register 10FC = 0xC001.
Reset default of register 10FD = 0xC002.
Reset default of register 10FE = 0xC004.
Reset default of register 10FF = 0xC008.

Address

(Hex)

Bit #

Name

Function

Reset

Default

10FC--10FF

PPP_Rx_CHK_CH

[0--3][15:0]

Channel [0--3] PPP Header Search. This register
will control the headers that channel [0--3] PPP
detach block looks for. Mismatched headers will be
noted in a separate counter (addresses 0x1118--
0x111F).

See

below.

15--14

Controls the way the PPP headers are searched for
and passed through.

00 = Pass any 32-bit header where the first 16 bits
are 0xFF03. The 0xFF03 (2 bytes) is stripped, and
the protocol field remains.

01 = Pass only specified uncompressed patterns
(first 16 bits are 0xFF03; last 16 bits are defined by
fixed patterns and/or register values). A 32-bit match
is performed, and the 32 bits are all stripped. See
below.

10 = Pass only specified compressed pattern (all 16
bits are defined by fixed patterns and/or register
values). A search is made for one of the provisioned
headers, and those 16 bits are stripped. See below.

11 = Pass any pattern defined by fixed patterns and/
or registers values. See below.

A value of 1 in this bit will enable a search for the
16-bit fixed value 0x8021.

A value of 1 in this bit will enable a search for the
16-bit fixed value 0x0021.

A value of 1 in this bit will enable a search of the
16-bit value in register address 0x10FB.

A value of 1 in this bit will enable a search of the
16-bit value in register address 0x10FA.

A value of 1 in this bit will enable a search of the
16-bit value in register address 0x10F9.

A value of 1 in this bit will enable a search of the
16-bit value in register address 0x10F8.

A value of 1 in this bit will enable a search of the
16-bit value in register address 0x10F7.

A value of 1 in this bit will enable a search of the
16-bit value in register address 0x10F6.

A value of 1 in this bit will enable a search of the
16-bit value in register address 0x10F5.

A value of 1 in this bit will enable a search of the
16-bit value in register address 0x10F4.

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Data Sheet

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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 139. Registers 0x1100--0x1107: ATM/HDLC/SDL Framer--Condition Counter 1 (PMRST Update) (RO)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset Default

1100--1107

PM_FC1_[0--3][27:0]

ATM/HDLC/SDL Counter 1
Channel [0--3]. Keeps a count of
conditions detected by the data framer in the
particular channel. This register can
represent only one of the following based
upon the channel's payload type:

HDLC invalid sequences (as defined in
IETF RFC 1622 below)

ATM corrected cells

SDL corrected header

This value is updated upon assertion of
PMRST, and the real-time counter value is
reset to zero.

From IETF RFC 1622, invalid sequences are
the following:

1. Frames which are too short (less than 4
data bytes). See register PM_FC2_0
(addresses 0x1108--0x110F).

2. Frames which end with a control escape
octet followed immediately by a coding flag
sequence (0x7D7E).

3. Frames in which octet framing is violated
by transmitting a 0 stop bit where a 1 bit is
expected.

0x0000

1100

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_FC1_0[27:16]

[11:4] is the MSByte of PM_FC1_0.

0x000

1101

15--0

PM_FC1_0[15:0]

[7:0] is the LSByte of PM_FC1_0.

0x0000

1102

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_FC1_1[27:16]

[11:4] is the MSByte PM_FC1_1.

0x000

1103

15--0

PM_FC1_1[15:0]

[7:0] is the LSByte of PM_FC1_1.

0x0000

1104

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_FC1_2[27:16]

[11:4] is the MSByte of PM_FC1_2.

0x000

1105

15--0

PM_FC1_2[15:0]

[7:0] is the LSByte of PM_FC1_2.

0x0000

1106

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_FC1_3[27:16]

[11:4] is the MSByte of PM_FC1_3.

0x000

1107

15--0

PM_FC1_3[15:0]

[7:0] is the LSByte of PM_FC1_3.

0x0000

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Data Sheet
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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 140. Registers 0x1108--0x110F: ATM/HDLC/SDL Framer--Condition Counter 2 (PMRST Update)

(RO)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset Default

1108--110F

PM_FC2_[0--3][27:0]

ATM/HDLC/SDL Counter 2
Channel [0--3]. Keeps a count of
conditions detected by the data framer in the
particular channel. This register can
represent only one of the following based
upon the channel's payload type:

HDLC short packets (packet < 4 data
bytes)

ATM discarded cells

SDL errored header

This value is updated upon PMRST, and the
real-time counter value is reset to zero.

0x0000

1108

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_FC2_0[27:16]

[11:4] is the MSByte of PM_FC2_0.

0x000

1109

15--0

PM_FC2_0[15:0]

[7:0] is the LSByte of PM_FC2_0.

0x0000

110A

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_FC2_1[27:16]

[11:4] is the MSByte of PM_FC2_1.

0x000

110B

15--0

PM_FC2_1[15:0]

[7:0] is the LSByte of PM_FC2_1.

0x0000

110C

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_FC2_2[27:16]

[11:4] is the MSByte of PM_FC2_2.

0x000

110D

15--0

PM_FC2_2[15:0]

[7:0] is the LSByte of PM_FC2_2.

0x0000

110E

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_FC2_3[27:16]

[11:4] is the MSByte of PM_FC2_3.

0x000

110F

15--0

PM_FC2_3[15:0]

[7:0] is the LSByte of PM_FC2_3.

0x0000

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Data Sheet

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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 141. Registers 0x1110--0x1117: CRC Checker--Bad Packet Counter (PMRST Update) (RO)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset Default

1110--1117

PM_BPC_[0--3][27:0]

CRC Bad Packet Counter Channel [0--3].
Keeps a count of bad packets detected by
the CRC checker. This value is updated
upon PMRST, and the real-time counter
value is reset to zero.

0x0000

1110

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_BPC_0[27:16]

[11:4] is the MSByte of PM_BPC_0.

0x000

1111

15--0

PM_BPC_0[15:0]

[7:0] is the LSByte of PM_BPC_0.

0x0000

1112

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_BPC_1[27:16]

[11:4] is the MSByte of PM_BPC_1.

0x000

1113

15--0

PM_BPC_1[15:0]

[7:0] is the LSByte of PM_BPC_1.

0x0000

1114

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_BPC_2[27:16]

[11:4] is the MSByte of PM_BPC_2.

0x000

1115

15--0

PM_BPC_2[15:0]

[7:0] is the LSByte of PM_BPC_2.

0x0000

1116

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_BPC_3[27:16]

[11:4] is the MSByte of PM_BPC_3

0x000

1117

15--0

PM_BPC_3[15:0]

[7:0] is the LSByte of PM_BPC_3

0x0000

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Data Sheet
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TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 142. Registers 0x1118--0x111F: PPP Detach--Mismatched Header Counter (PMRST Update) (RO)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset Default

1118--111F

PM_MHC_[0--3][27:0]

PPP Mismatched Header Counter
Channel [0--3]. Keeps a count of packets
with a mismatched header detected by the
PPP detach block. This value is updated
upon PMRST, and the real-time counter
value is reset to zero.

0x0000

1118

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_MHC_0[27:16]

[11:4] is the MSByte of PM_MHC_0.

0x000

1119

15--0

PM_MHC_0[15:0]

[7:0] is the LSByte of PM_MHC_0.

0x0000

111A

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_MHC_1[27:16]

[11:4] is the MSByte of PM_MHC_1.

0x000

111B

15--0

PM_MHC_1[15:0]

[7:0] is the LSByte of PM_MHC_1.

0x0000

111C

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_MHC_2[27:16]

[11:4] is the MSByte of PM_MHC_2.

0x000

111D

15--0

PM_MHC_2[15:0]

[7:0] is the LSByte of PM_MHC_2.

0x0000

111E

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_MHC_3[27:16]

[11:4] is the MSByte of PM_MHC_3.

0x000

111F

15--0

PM_MHC_3[15:0]

[7:0] is the LSByte of PM_MHC_3.

0x0000

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 143. Registers 0x1120--0x1127: Receive Good Packet/Cell Counter (PMRST Update) (RO)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset Default

1120--1127

PM_GPC_RX_[0--3]

[27:0]

Good Packet/Cell Counter Channel
[0--3]. Keeps a count of good packets
detected by the receive data engine. This
value is updated upon PMRST, and the real-
time counter value is reset to zero. In ATM
mode, this counter counts the number of
good ATM cells received.

0x0000

1120

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_GPC_RX_0[27:16] [11:4] is the MSByte of PM_GPC_RX_0.

0x000

1121

15--0

PM_GPC_RX_0[15:0]

[7:0] is the LSByte of PM_GPC_RX_0.

0x0000

1122

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_GPC_RX_1[27:16] [11:4] is the MSByte of PM_GPC_RX_1.

0x000

1123

15--0

PM_GPC_RX_1[15:0]

[7:0] is the LSByte of PM_GPC_RX_1.

0x0000

1124

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_GPC_RX_2[27:16] [11:4] is the MSByte of PM_GPC_RX_2.

0x000

1125

15--0

PM_GPC_RX_2[15:0]

[7:0] is the LSByte of PM_GPC_RX_2.

0x0000

1126

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_GPC_RX_3[27:16] [11:4] is the MSByte of PM_GPC_RX_3.

0x000

1127

15--0

PM_GPC_RX_3[15:0]

[7:0] is the LSByte of PM_GPC_RX_3.

0x0000

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Data Sheet
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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 144. Registers 0x1128--0x112F: Transmit Good Packet/Cell Counter (PMRST Update) (RO)

Reset default of registers = 0x0000.

Table 145. Registers 0x1180--0x1186: Interrupt Masks for Packet Counters (R/W)

Reset default of registers = 0x001F.

Address

(Hex)

Bit #

Name

Function

Reset Default

1128--112F

PM_GPC_TX_[0--3]

[27:0]

Good Packet/Cell Counter Channel
[0--3]. Keeps a count of good packets
detected by the transmit data engine. This
value is updated upon PMRST, and the real-
time counter value is reset to zero. In ATM
mode, this counter counts the number of
good ATM cells transmitted.

0x0000

1128

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_GPC_TX_0[27:16]

[11:4] is the MSByte of PM_GPC_TX_0.

0x000

1129

15--0

PM_GPC_TX_0[15:0]

[7:0] is the LSByte of PM_GPC_TX_0.

0x0000

112A

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_GPC_TX_1[27:16]

[11:4] is the MSByte of PM_GPC_TX_1.

0x000

112B

15--0

PM_GPC_TX_1[15:0]

[7:0] is the LSByte of PM_GPC_TX_1.

0x0000

112C

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_GPC_TX_2[27:16]

[11:4] is the MSByte of PM_GPC_TX_2.

0x000

112D

15--0

PM_GPC_TX_2[15:0]

[7:0] is the LSByte of PM_GPC_TX_2.

0x0000

112E

15--12

Reserved. These bits must be written to
their reset default value (0x0).

0x0

11--0

PM_GPC_TX_3[27:16]

[11:4] is the MSByte of PM_GPC_TX_3.

0x000

112F

15--0

PM_GPC_TX_3[15:0]

[7:0] is the LSByte of PM_GPC_TX_3.

0x0000

Address

(Hex)

Bit #

Name

Function

Reset

Default

1180, 1182,

1184, 1186

DEDINTM[0--3]

Data Interrupt Mask Channel [0--3]. When
active (logic 1), the associated event/delta is
inhibited from contributing to the interrupt on a
per-channel basis.

0x001F

15--5

Reserved. These bits must be written to their
reset default value (00000000000).

000

0000
0000

Rx-Side Good Packet.

PPP Mismatched Header.

CRC Bad Packet.

ATM/HDLC/SDL Counter 2.

ATM/HDLC/SDL Counter 1.

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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 147. Registers 0x1200--0x1213, 0x12F0: ATM Transmit Registers (R/W) (continued)

Reset default of registers 0x1200--0x1203, 0x12F0 = 0x0000.
Reset default of registers 0x1210--0x1213 = 0x0001.

Address

(Hex)

Bit #

Name

Function

Reset

Default

12F0

ATM_HEADER_ERROR

ATM Tx Debug Control. Used for debug
purposes to inject errors, and to increment the
payload sequence for NULL cells.

0x0000

15--8

Reserved. These bits must be written to their
reset default value (0x00).

0x00

Incrementing Null (Idle) Cell Payload
Sequence. This bit governs whether 0x6A is
used for the payload of NULL cells, or whether an
incrementing 8-bit count is used (0x00

0xFF).

A value of 1 selects the incrementing sequence.
This is used with DE register 0x1002 bits [11:8].

Error Strobe. Writing a value of 1 to this register
initiates the injection of a single or double shot
error injection, assuming one of these two modes
is selected.

5--4

Error Injection Mode. These bits control the
mode of operation of the error injection.

00 = continuous injection

01 = single shot (isolated cell)

10, 11 = double shot (i.e., two back-to-back cells)

3--2

Error Type. These bits control the injection of a
walking error pattern into the headers of all
outgoing cells.

00 = no errors

01 = single bit errors

10, 11 = double bit errors

1--0

Error Channel ID. The logical channel in which
to inject the header errors.

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 148. Registers 0x1400--0x1403: SDL State Registers (RO)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

1400, 1401,

1402, 1403

SDL_ST[0--3]

SDL State Channel [0--3]. These registers
describe the SDL framer and scrambler states.

0x0000

15--4

Reserved. These bits must be written to their
reset default value (0x000).

0x000

3--2

SDL Frame State. Indicates the frame state of
each channel.

SDL_ST[0--3][3:2] = 00. Out-of-Frame. The
SDL framer is in search of a successful SDL
framing.

SDL_ST[0--3][3:2] = 01. Presync. The SDL
framer has transitioned from the out of frame to
the presync state. The SDL framer has
successfully framed one SDL header.

SDL_ST[0--3][3:2] = 10. Sync. The SDL
framer has transitioned from the presync to the
sync state. The framer has successfully
detected the second consecutive SDL packet.
The SDL framer is correctly framed on the SDL
signal. The SDL framer remains in the sync
state until a bad packet frame is detected.
Detection of a bad packet frame places the SDL
framer in the out-of-frame state.

SDL_ST[0--3][3:2] = 11. Undefined.

1--0

SDL Scram State. Indicates the X48 sync state
of each channel.

SDL_ST[0--3][1:0] = 00. Hunt. The SDL
scrambler has yet to detect a valid scrambler
state.

SDL_ST[0--3][1:0] = 01. Sync. The SDL
scrambler is in sync.

SDL_ST[0--3][1:0] = 10. Postsync. The SDL
scrambler was in sync, but detected an SDL
state that did not match the expected state. If
two consecutive nonmatching states are
detected, then (1) the SDL framer is reset with
the scrambler state received in the bit stream,
and (2) a sync slip interrupt is generated.

SDL_ST[0--3][1:0] = 11. Undefined.

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Data Sheet
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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 149. Registers 0x1470--0x1473: A Message Mailbox Registers (RO)

Reset default of registers = 0x0000.

Table 150. Registers 0x1480--0x1483: A Message Mailbox Registers (RO)

Reset default of registers = 0x0000.

Table 151. Registers 0x1490--0x1493: A Message Mailbox Registers (RO

)

Reset default of registers = 0x0000.

Table 152. Registers 0x14A0--0x14A3: B Message Mailbox Registers (RO

)

Reset default of registers = 0x0000.

Address

(Hex)

Bit #

Name

Function

Reset

Default

1470, 1471,

1472, 1473

15--0

SDL_AMM1[0--3]

A Message Mailbox 1: Channel [0--3]. These
registers will store the first 16 bits of a valid A
message header. A maskable interrupt will be
generated if the SDL framer receives an A
message.

0x0000

Address

(Hex)

Bit #

Name

Function

Reset

Default

1480, 1481,

1482, 1483

15--0

SDL_AMM2[0--3]

A Message Mailbox 2: Channel [0--3]. These
registers will store the middle 16 bits of a valid
A message header. A maskable interrupt will be
generated if the SDL framer receives an A
message.

0x0000

Address

(Hex)

Bit #

Name

Function

Reset

Default

1490, 1491,

1492, 1493

15--0

SDL_AMM3[0--3]

A Message Mailbox 3: Channel [0--3]. These
registers will store the last 16 bits of a valid A
message header. A maskable interrupt will be
generated if the SDL framer receives an A
message.

0x0000

Address

(Hex)

Bit #

Name

Function

Reset

Default

14A0, 14A1,

14A2, 14A3

15--0

SDL_BMM1[0--3]

B Message Mailbox 1: Channel [0--3]. These
registers will store the first 16 bits of a valid B
message header. A maskable interrupt will be
generated if the SDL framer receives a B
message.

0x0000

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 153. Registers 0x14B0--0x14B3: B Message Mailbox Registers (RO

)

Reset default of registers = 0x0000.

Table 154. Registers 0x14C0--0x14C3: B Message Mailbox Registers (RO)

Reset default of registers = 0x0000.

Table 155. Registers 0x14D0--0x14D3: SDL Interrupt Masks (R/W)

Reset default of registers = 0x00FF.

Address

(Hex)

Bit #

Name

Function

Reset

Default

14B0, 14B1,

14B2, 14B3

15--0

SDL_BMM2[0--3]

B Message Mailbox 2: Channel [0--3]. These
registers will store the middle 16 bits of a valid
B message header. A maskable interrupt will be
generated if the SDL framer receives a B
message.

0x0000

Address

(Hex)

Bit #

Name

Function

Reset

Default

14C0, 14C1,

14C2, 14C3

15--0

SDL_BMM3[0--3]

B Message Mailbox 3: Channel [0--3]. These
registers will store the last 16 bits of a valid B
message header. A maskable interrupt will be
generated if the SDL framer receives a B
message.

0x0000

Address

(Hex)

Bit #

Name

Function

Reset

Default

14D0, 14D1,

14D2, 14D3

SDLINTM[0--3]

SDL Interrupt Mask Channel [0--3]. When
active (logic 1), the associated event/delta is
inhibited from contributing to the interrupt on a
per-channel basis.

0x00FF

15--8

Reserved. These bits must be written to their
reset default value (0x00).

0x00

B_Message Reception.

A_Message Reception.

Uncorrectable Special Payload Error.

Uncorrectable Bit Error.

Reserved. This bit must be written to its reset
default value (1).

Single Bit Error.

Scrambler Out of Sync.

Framer Out of Sync.

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Data Sheet
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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 156. Registers 0x14E0--0x14E3: SDL Interrupts (COR/W)

Reset default of registers = 0x0000.

Table 157. Register 0x14F0: SDL Receive Configuration Registers (R/W)

Reset default of registers = 0x0001.

Address

(Hex)

Bit #

Name

Function

Reset

Default

14E0, 14E1,

14E2, 14E3

SDLINT[0--3]

SDL Interrupt Channel [0--3]. Used to record
various occurrences within the SDL framer. The
bits will generate an interrupt if defined by the
interrupt mask, but the register values here are
independent of the interrupt mask values.

0x0000

15--8

Reserved. These bits must be written to their
reset default value (0x00).

0x00

B_Message Reception.

A_Message Reception.

Uncorrectable Special Payload Error.
Indicates occurrence of two or more special
payload errors.

Uncorrectable Header Bit Error. Indicates
occurrence of two or more header errors.

Reserved. This bit must be written to its reset
default value (0).

Single Bit Header Error.

Scrambler Out of Sync. Indicates a scrambler
sync slip.

Framer Out of Sync.

Address

(Hex)

Bit #

Name

Function

Reset

Default

14F0

SDL_DELTA

SDL Receive Frame Configuration Register.

0x0001

15--7

Reserved. These bits must be written to their
reset default value (000000000).

0000

00000

Disable Scrambling. When this value is 1, the
SDL framer will not unscramble the data prior to
framing.

Reserved. These bits must be written to their
reset default value (0).

Sync Mode. When bit 4 has a value of 1, then
only one framer is used at all times to frame
SDL data. Normally, this bit is 0, and four
coordinated framers are active simultaneously
to synchronize the scrambler process.

3--0

Framer Delta. This register will define the delta
value for the CRC-16 framer.

0x1

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Data Sheet

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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 158. Registers 0x1600--0x1607: SDL Transmit Registers (R/W)

Reset default of registers 0x1600, 0x1601, 0x1602, 0x1603, 0x1606 = 0x0000.
Reset default of register 0x1604 = 0x0008.
Reset default of register 0x1605 = 0x8000.

Note: These registers must be written in the following order: 0x1603, then 0x1600, 0x1601, 0x1602. Register

0x1603 is a clear-on-write (COW) register.

Address

(Hex)

Bit #

Name

Function

Reset

Default

1600

15--0

SDLFI_MSG1

SDL Message. These registers will store the
first 16 bits of a header of an outgoing A or B
message.

0x0000

1601

15--0

SDLFI_MSG2

SDL Message. These registers will store the
middle 16 bits of a header of an outgoing A or B
message.

0x0000

1602

15--0

SDLFI_MSG3

SDL Message. These registers will store the
last 16 bits of a header of an outgoing A or B
message. Writing to this register causes the
message to be sent.

0x0000

1603

SDLFI_MSG_TYPE

SDL Message Type.

0x0000

SDLMTB

Message Type Bit.

0 = A Message

1 = B Message

14--2

Reserved. These bits must be written to their
reset default value (00000000000000).

0000
0000
0000

1--0

SDLCHID[1:0]

Channel ID. Defines on which channel the
special message will be transmitted.

1604

15--0

SDLFI_INT

SDL State Transmit Interval. Defines the
number of packets (or dWords) separating
scrambler state transmissions. Use register
0x1605 to determine if units are packets or
dwords.

0x0008

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Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Register Descriptions

(continued)

DE Registers

(continued)

Table 158. Registers 0x1600--0x1607: SDL Transmit Registers (R/W)

(continued)

Reset default of registers 0x1600, 0x1601, 0x1602, 0x1603, 0x1606 = 0x0000.
Reset default of register 0x1604 = 0x0008.
Reset default of register 0x1605 = 0x8000.

Note: These registers must be written in the following order: 0x1603, then 0x1600, 0x1601, 0x1602. Register

0x1603 is a clear-on-write (COW) register

Address

(Hex)

Bit #

Name

Function

Reset

Default

1606

SDLFI_INTR

Status Register.

0x0000

15--2

Reserved. These bits must be written to their
reset default value (000000000000000).

0000
0000
0000

SDLFDO

SDLFIFO Depth Out. When this bit has a value
of 1, it indicates that the FIFO in the SDL Tx
data buffer is over half full.

SDLMSI

Message Sent Interrupt. When this bit has a
value of 1, it indicates that an SDL A/B
message has been sent. This value may be
cleared when read or written.

1607

SDLFI_DEBUG

SDL Debug Register.

0x0000

15--6

Reserved. These bits must be written to their
reset default value (0000000000).

0000
0000

5--4

SDLHE[1:0]

Header Error. This value indicates the number
of errors to insert into the SDL header on a
given channel for debug purposes. The error
injection is done using a walking ones pattern
to cover all possibilities.

0x0 = no errors
0x1 = single error
0x2 = double error
0x3 = double error

3--2

SDLPE[1:0]

Payload Error. This value indicates the number
of errors to insert into the payload of special
packets on a given channel for debug purposes.
The error injection is done using a walking ones
pattern to cover all possibilities.

00 = no errors
01 = single error
10 = double error
11 = double error

1--0

SDLECID[1:0]

Error Channel ID. This value specifies the
channel on which the errors are to be sent.

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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.

Note: V

= V

DDA

= V

DDD.

Handling Precautions

Although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo-
sure to electrostatic discharge (ESD) during handling and mounting. Agere employs a human-body model (HBM)
and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage
thresholds are dependent on the circuit parameters used in the defined model. No industry-wide standard has
been adopted for the CDM. However, a standard HBM (resistance = 1500

, capacitance = 100 pF) is widely used

and, therefore, can be used for comparison purposes:

Operating Conditions

Table 159. Recommended Operating Conditions

Note: V

= V

DDA

= V

DDD.

Parameter

Min

Max

Unit

Power Supply Voltage

�0.5

4.2

Storage Temperature

�65

125

癈

Pin Voltage (3.3 V)

GND � 0.5

+ 0.5

Pin Voltage (5 V tolerant)

GND � 0.5

5.5

Device

Voltage

TDAT042G5

TBD

TDAT042G51A

TBD

Parameter

Symbol

Min

Typ

Max

Unit

Power Supply (dc voltage)

3.135

3.465

Ground

Input Voltage:

Low
High

GND

� 1.0

1.0

Ambient Temperature

�40

癈

Power Dissipation (V

= 3.465 V)

7.5

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Data Sheet
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155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Interface Timing Specifications

(continued)

Line Interface I/O Timing

(continued)

Table 168. Transmit Line-Side Timing Specifications

* TxCKQP/N is used in STS-48/STM-16 mode only.

TxFSYNCP/N must be synchronized to TxCKP/N; it must be at least one TxCKP/N clock-cycle wide, but less than one frame

period minus two TxCKP/N clock-cycles wide.

Symbol

Parameter

Min

Typ

Max

Units

t50

Transmit Clock-Cycle Period:

STS-3/STM-1 and STS-48/STM-16
STS-12/STM-4

--
--

6.4300

1.60751

--
--

ns
ns

t51

Transmit Clock Rise

500

t52

Transmit Clock Fall

500

t53

Transmit Clock Pulse Low (for P input):

STS-3/STM-1 and STS-48/STM-16
STS-12/STM-4

2.800

700

3.2150
803.75

3.630

907

ns
ps

t54

Transmit Clock Pulse High (for P input):

STS-3/STM-1 and STS-48/STM-16
STS-12/STM-4

2.800

700

3.2150
803.75

3.630

907

ns
ps

t55

Propagation Delay--contra clocking:

(TxCKP/N to TxD[15:0]P/N, with PLL)

t56

Propagation Delay--forward clocking:

(TxCKP/N to TxCKQP/N)*

1.5

4.5

t57

Propagation Delay--forward clocking:

(TxCKQP/N to TxD[15:0]P/N, no PLL)*

0.5

1.5

t58

Propagation Delay--forward clocking:

(TxCKP/N to TxD[15:0]P/N, no PLL)

t59

TxFSYNC Setup

100

t60

TxFSYNC Hold

100

t61

Transmit TxFSYNC width

STS-3/STM-1 and STS-48/STM-16
STS-12/STM-4

6.430
1.608

--
--

19,438
77,758

clock cycles
clock cycles

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Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

DS98-193SONT-4 Replaces DS98-193SONT-3 to Incorporate the Following Updates

1. Globally numbered all the transmit sequencer time slots the same, from 1 to 12. Affects Figures 13, 14,

and 16, DE egress configuration registers Tx_TS (0x1016--0x1021), and DE ingress configuration registers
Rx_TS (0x1022--0x102D).

2. Bad PPP header counter changed to mismatched PPP header counter globally.

3. Changed bit TRDIP_LCDINH[A--D] to TRDIP_LCD[A--D] thorughout document.

4. Page 1, the number of the IETF RFC standard was corrected from 1619 to 2615; the title is still the same.

5. Page 11, moved Description section from page 1 for readability.

6. Page 24, added the note about the TDAT042G5's internal circuitry under Table 3.

7. Page 25, Table 3, Pin Descriptions--Line Interface Signals, TxFSYNCP and TxFSYNCN pins. Corrected the

inadvertent switch of I

and I

in the I/O column, provided values for all I

and I

, corrected cycle width in last

sentence.

8. Page 27, Table 4, Pin Descriptions--TOH Interface Signals, clarified RxREF pin.

9. Pages 32, 38, and 164, TxSIZE_[D:A] and RxSIZE_[D:A] bits (address 0x0226), corrected bit and pin names in

the register description and pin descriptions.

10.Page 33, Table 5, Pin AM18, AM30, AA35, and H32, under the Name/Description column, second paragraph,

changed the wording to include the TxERR[A] and the TxERR[B] input pins.

11.Page 33--page 39, Table 5, Pin Descriptions--Enhanced UTOPIA Interface Signals, added "These pins are

used only in U2+ and U3+ (packet) modes" to size, end-of-packet, and error receive pins and transmit pins.

12.Page 38, Table 5, Pin Descriptions--Enhanced UTOPIA Interface Signals, corrected "must be placed" to "will be

placed" in the paragraph beginning with, "In U3+ (32-bit mode). . ."

13.Page 39, Table 5, Pin Descriptions--Enhanced UTOPIA Interface Signals, clarified RxERR pin.

14.Page 40, Table 6, Pin Descriptions--Microprocessor Interface Signals, clarified PMRST pin.

15.Page 42, Table 8, Pin Descriptions--JTAG Interface Signals, corrected TMS pin to be active-high.

16.Page 42, Table 8, Pin Descriptions--JTAG Interface Signals, expanded TRST description.

17.Page 45, Overview, corrected and expanded second paragraph.

18.Page 46, Overview, deleted any reference to cell-based UNI since not supported by this device.

19.Page 49, Overview, Over-Fiber Mode section, corrected transparent mode to over-fiber mode in this section.

20.Page 52, Transmit Line Interface Summary section, updated TxFSYNCP/N bullet item.

21.Page 53, SONET Framer, added section.

22.Page 55 (in revision 3 of data sheet), Table 16, Values of SFNSSET[A--D][18:0], SFMSET[A--D][7:0],

SFLSET[A--D][3:0], SFBSET[A--D][15:0] in Terms of Equivalent BER for BIP-24 Case, removed table.

23.Pages 57--58, pages 187--188, and pages 208--209; Table 16, Table 17, Table 86, Table 87, Table 107, and

Table 108; Ns, L, M, and B Values to Set the BER Indicator, Ns, L, M, and B Values to Clear the BER Indicator,
updated tables and added them to the PT Registers section, also.

24.Pages 63, 200, and 205, SS pointer interpretation algorithm not implemented. Affects bit 5 of registers 0x0AA6,

0x0AAE, 0x0AB6, 0x0ABE; corrected from RSSPTRNORM[A--D] to Reserved in Register Maps and Register
Descriptions sections. Also affects bits 1--0 of register 0x0AC7; corrected from RSSEXP[1:0] to Reserved in
Register Maps and Register Descriptions sections. Removed item 4 from the normal pointer description on
page 63.

25.Page 65--Page 68, SPE Generate section, corrected and expanded.

26.Page 70, Data Engine (DE) Block section, expanded second paragraph.

278

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

DS98-193SONT-4 Replaces DS98-193SONT-3 to Incorporate the Following
Updates

(continued)

27.Page 71, ATM Cell Processor section under Data Engine (DE) Block, expanded.

28.Page 75, PPP Header Detach section, added footnote and updated Figure 16, Uncompressed and Com-

pressed PPP Packets.

29.Page 77 and page 94, HDLC Inserter in the Data Engine (DE) Block section and FIFO in the UT Transmit Input

Path (Egress) section, corrected description of 0x7D20.

30.Page 82, Data Engine (DE) Block, Over-Fiber Modes section, clarified description.

31.Page 83, Transparent Payload Mode section, updated.

32.Page 85, Table 24, UTOPIA Traffic Types, updated.

33.Page 86, UTOPIA ATM Cell Processing section, added.

34.Page 88, added UT Clocking, UT Transmit Path (Egress) Clock, UT Receive Path (Ingress) Clock sections;

removed Clocks section on page 91.

35.Page 90, Two-Cycle Delay Mode section, provided reference for RxPA[D:A] definition.

36.Page 91 and page 92, updated Figure 23, Receive-Side Interface Handshaking in Point-to-Point, Single Cycle

Mode; added Figure 24, Receive-Side Interface Handshaking in Point-to-Point, Two-Cycle Mode.

37.Page 93, Transmit Cell/Packet Available (TxPA) section, expanded definition.

38.Page 94, Table 29, Egress High Watermark Thresholds, added.

39.Page 95, Figure 25, Transmit-Side Interface Handshaking in Point-to-Point, Single Cycle Mode, updated.

40.Page 96, Multi-PHY Support section, clarified the concept of point-to-point vs. polled mode configuration.

41.Page 100, JTAG (Boundary-Scan) Test Block section, added second paragraph.

42.Page 100, Reset of JTAG Logic section, added.

43.Page 100, Line Interface section added to document (including Table 30).

44.Page 102, General-Purpose I/O Bus (GPIO) section, expanded.

45.Page 105, Performance Monitor Reset (PMRST) section, expanded.

46.Page 106, Far-End Loopback, Terminal Loopback, Facility Loopback, expanded sections.

47.Page 108--page 110, Figur e34, Single ATM UTOPIA 3; Figur e36, Single POS UTOPIA 3, updated.

48.Page 112 and p age152, GPIO Output Configuration register (addresses 0x0014 and 0x0015), updated in Reg-

ister Maps and Register Descriptions sections.

49.Pages 124--125, 191, TZ0DINS[A--D][2--12][7:0] registers (addresses 0x05AA--0x05C1), updated in the

50.Page 119, Register Maps section, corrected subtitle in OHP map from Signal Degrade Set/Clear Control Regis-

ters to Signal Degrade BER Algorithm Parameters.

51.Page 120, Register Maps section, corrected subtitle in OHP map from Signal Fail Set/Clear Control Registers to

Signal Fail BER Algorithm Parameters.

52.Pages 119--121, 136, 185--186, 198, Register Maps and Register Descriptions sections, differentiated bit-

names in OHP sections from bitnames in PT sections for signal degrade and signal fail BER algorithm parame-
ters.

53.Pages 134--135, 199, changed bits [15:9] from Reserved to RPOHMONSEL[A--D][3:0] and RCONC_ALLOR

FIRST[A--D] in the Register Maps and Register Descriptions sections.

Agere Systems Inc.

279

Data Sheet
May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

DS98-193SONT-4 Replaces DS98-193SONT-3 to Incorporate the Following
Updates

(continued)

54.Page 143, Register Maps section, corrected subtitle in DE map from PPP Detach--Rx Good Packet/Cell

Counter (PMRST Update) to Receive Good Packet/Cell Counter (PMRST Update).

55.Page 143, Register Maps section, corrected subtitle in DE map from PPP Attach--Tx Good Packet/Cell

Counter (PMRST Update) to Transmit Good Packet/Cell Counter (PMRST Update).

56.Page 150, updated register description of PLL_MODE bit (address 0x0010).

57.Page 151, Table 50, Register 0x0012: Loopback Control (R/W), updated description of valid combinations.

58.Page 157 and page158, clarified UTOPIA_MODE_Rx bit (addresses 0x020F, 0x0213, 0x0217, 0x021B) in the

59.Page 158, Table 61, Registers 0x020F, 0x0213, 0x0217, 0x021B: Channel [A--D] Receive Provisioning Regis-

ter (R/W), corrected the reset default value of register 0x0217 from 0x0020 to 0x0220.

60.Page 158, clarified ATM_SIZE_Rx[A--D] bits (addresses 0x020F, 0x0213, 0x0217, 0x021B).

61.Page 160, corrected description of PARITY_Tx[A] bit (addresses 0x0210, 0x0214, 0x0218, 0x021C). Corrected

even parity from bit = 1 to bit = 0.

62.Page 160, clarified PARITY_Tx[B--D] bits (addresses 0x0210, 0x0214, 0x0218, 0x021C).

63.Page 160, clarified ATM_SIZE_Tx[A--D] bits (addresses 0x0210, 0x0214, 0x0218, 0x021C) and corrected

"received" to "transmitted."

64.Page 161, Table 63, Bits 13--8, INGRESS_WATERMARK_HIGH_[A--D][6:0], changed the function definition

to current one.

65.Pages 165--page 167, Table 72, Registers 0x0402--0x0409: Delta/Event (COR/W), deleted statement that the

delta bits clear when read (or written).

66.Page 171, Table 76, Registers 0x0416--0x0419: Toggles (R/W), corrected and expanded note.

67.Page 173, LOS_AISINH[A--D] bit (addresses 0x0422, 0x0424, 0x0426, 0x0428), clarified the description.

68.Page 177 and page181, TJ0INS and TTOAC_J0 bits (addresses 0x042E, 0x0430, 0x0432, 0x0434), updated

description.

69.Page 179 and page183, TM1_ERR_INS and TM1_REIL_INH bits (addresses 0x042E, 0x0430, 0x0432,

0x0434), updated description.

70.Page 200 and page201, RFORCE_LOP[A--D][1--12] and RFORCE_AIS[A--D] [1--12] bits

(addresses 0x0AA7, 0x0AA8, 0x0AA9), updated description.

71.Page 201, Table 103, address 0AAA, 0AB2, 0ABA, OAC2, bit 9, name TRDIP_LCD[A--D], changed the func-

tion definition to the current one.

72.Page 201 and page 202, TRDIP_LCD[A--D], TRDIP_PLMPINH[A--D], TRDIP_UNEQUIPINH [A--D] bits, cor-

rected the bit numbers from 7, 9, 8, to the bit numbers 9, 8, 7, respectively.

73.Page 212 and page 213, Table 112, Register 0x1001, 0x1002: DE Interrupts (0x1001 is RO, 0x1002 is RO and

COR/W), register 0x1002, updated note, added footnote, and corrected the placement of bits of 7--4 and 3--0
which were interposed.

74.Page 226, Table 120, Receive Type and Mode Control Summary Table (Registers 0x1040--0x1043), clarified

bits [1:0] for ATM.

75.Page 235, PPP_Rx_HDR [0--11][15:0] registers (addresses 0x10F0--0x10FB), corrected name and descrip-

tion.

76.Page 236, PPP_Rx_CHK_CH [0--3][15:0] registers (addresses 0x10FC--0x10FF), bits 15--14, updated

description.

280

Agere Systems Inc.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

DS98-193SONT-4 Replaces DS98-193SONT-3 to Incorporate the Following
Updates

(continued)

77.Page 241, PM_MHC_[0--3][27:0] registers (addresses 0x1118--0x111F), updated name and description.

78.Page 250, Table 158, Registers 0x1600--0x1607: SDL Transmit Registers (R/W), updated note.

79.Page 253, Absolute Maximum Ratings, corrected text above table to refer to permanent damage and to the data

sheet; removed typical power supply value.

80.Page 253, Table 159, Recommended Operating Conditions, updated power dissipation.

81.Page 254, Table 160, 3.3 V Logic Interface Characteristics, updated load capacitance.

82.Page 255, Table 162, added table to document.

83.Pages 256, 258, 262, Microprocessor Interface Timing section, updated figures (Figure 38, Figure 39,

Figure 41) and text in section.

84.Page 260, Asynchronous Mode in Microprocessor Interface Timing section, updated text and corrected t28 in

Table 165, Microprocessor Interface Asynchronous Write Cycle Specifications. Corrected t28 min from 0 ns to
77 ns. Corrected t28 max from 72 ns to 103 ns.

85.Page 263, Asynchronous Mode in Microprocessor Interface Timing section, corrected t38 in Table 166, Micro-

processor Interface Asynchronous Read Cycle Specifications. Corrected t38 min from 0 ns to 90 ns. Corrected
t38 max from 34 ns to 115 ns.

86.Pages 264--page 265, Figure 42, Receive Line-Side Timing Waveform--Figure 45, Transmit Line-Side Timing

Waveform--STS-48/STM-16 Forward Clocking, updated.

87.Page 266, Table 167, Receive Line-Side Timing Specifications and Table 168, Transmit Line-Side Timing Spec-

ifications; replaced tables labeled Clock Input Specifications, Line Input Specifications, and Line Output Specifi-
cations with these tables.

88.Page 268 and page 269, UTOPIA Interface Timing section, updated receive and transmit figures and tables.

89.Page 271, Transport Overhead Access Channel (TOAC) Interface Timing section, updated transmit and receive

figures and tables.

90.Page 275, updated 600-pin LBGA package outline.

Data Sheet

May 2001

155/622/2488 Mbits/s Data Interface

TDAT042G5 SONET/SDH

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

May 2001
DS98-193SONT-04 (Replaces DS98-193SONT-03 Must Acompany DA01-010SONT and AY01-015SONT)

For additional information, contact your Agere Systems Account Manager or the following:
INTERNET: http://www.agere.com
E-MAIL: docmaster@micro.lucent.com
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Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256

Tel. (65) 778 8833, FAX (65) 777 7495

CHINA: Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC

Tel. (86) 21 50471212, FAX (86) 21 50472266

JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan

Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700

EUROPE: Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148

Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),

FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: TDAT04622

Document Outline

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: TDAT04622

Document Outline

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: TDAT04622