Product Brief
September 2000
TDCS6440G SONET/SDH
40 Gbits/s Cross Connect
Features
s
Versatile IC which supports an aggregate band-
width of 40 Gbits/s.
s
Supports flexible 64-port STS-12 data links.
s
Supports full nonblocking fabric with switching
granularity of STS-1/STM-1.
s
Support for line/path switching.
s
Supports any valid mix of STS-1 and concatenated
payloads from STS-3c to STS-192c.
s
Provides a standard 5-pin P1149.1 JTAG port with
memory BIST scan, and boundary scan.
s
Low-power 1.5 V operation with 3.3 V inputs and
outputs.
s
Configurable on-chip TSI block for switching of
STS-1s.
s
On-chip connection memory for flexible configura-
tion of working connections and protect connec-
tions for each STS-1.
s
792 LBGA package.
s
40
C to +85 C industrial temperature range.
Interface
s
Provides 64 STS-12 interfaces which can be used
as sixteen STS-48 interfaces or as four STS-192
interfaces.
s
Robust receiver interface capable of handling
STS-12 streams having combined static- and
dynamic-frame offsets of up to 24 bytes without
creating traffic disruption.
s
Frames to and performs integrity check on each
STS-12 interface.
s
Each STS-12 input interface consists of an LVDS
data input with integral clock and data recovery
(CDR).
s
Each STS-12 output interface consists of an LVDS
output.
s
Ability to insert on an AIS-L or pass-through when
an LOF condition occurs.
s
Interfaces have A1/A2 framing, link trace, parity,
and a communications link.
Cross Connect
s
Supports up to 768 STS-1 time slots.
s
64 input channels and 64 output channels.
s
Each input time slot can be connected to any/all
output time slots.
s
Each output time slot can be connected to all the
input time slot or be assigned AIS-P or UNEQ-P.
s
Fully programmable and nonblocking cross con-
nect.
s
Supports drop-and-continue and full broadcast
capabilities.
s
Ability to insert path AIS and UNEQ indications on
any STS-1 under software control.
Protection Switching
s
Supports 1 + 1, 1:1, 1:N, UPSR, and BLSR protec-
tion mechanisms with four-connection memory.
s
Separate line and path protection mechanisms.
s
Supports equipment protection switching.
s
On-chip working/protected memory paths for easy
switch configurations.
Microprocessor Interface
s
Microprocessor interface supports both synchro-
nous and asynchronous operations.
s
16-bit wide data bus interface and 13-bit wide
address bus.
Product Brief
September 2000
40 Gbits/s Cross Connect
TDCS6440G SONET/SDH
Applications
s
SONET/SDH digital cross connect equipment.
s
SONET/SDH add-drop multiplex equipment.
s
High-speed core switches.
s
SONET/SDH test equipment.
s
TDCS6440G will interface seamlessly to a number of Lucent Microelectronics existing/next-generation high-
speed framers.
Description
The TDCS6440G has four sections: receive interface channels, a cross connect fabric core, transmit channels,
and a microprocessor interface. The block diagram of the TDCS6440G is shown in Figure 1.
All data stream channels must be synchronous in frequency, but can be asynchronous in phase.
The TDCS6440G does not perform pointer processing functions. These are performed by the line and tributary
cards, which align the payload at known positions relative to a common frame signal.
The TDCS6440G is able to support SONET and SDH cross connects.
The A1, A2, B1, H1, H2, H3, K1, and K2 bytes are used for their original SONET/SDH purposes.
Note: Throughout this document, the term channel always refers to an STS-12 data stream that is carried on a sin-
gle LVDS link.
5-8022(F)r. 4
Figure 1. TDCS6440G Block Diagram
FABRIC CORE
TRANSMIT
TRANSMIT
CONNECTION
MICROPROCESSOR
JTAG INTERFACE
D_OUT0_[15:0]
D
_
OU
T
1_[
15:
0]
D
_
I
N
1_[
15:
0]
D_OUT2_[15:0]
D_IN2_[15:0]
D_IN3
_
[1
5:0
]
TD
O
TD
I
TC
K
TM
S
TR
S
T
_N
D
A
TA
_[
15:0
]
CS_
N
TS
_N
DS_
N
INT
_
N
MP
MO
D
E
[1:0
]
P
A
R
I
TY
_[
1:0
]
INTERFACE
PORT 0
RECEIVE
INTERFACE
PORT 0
TRANSMIT
INTERFACE
PORT 2
RECEIVE
INTERFACE
PORT 2
INTERFACE
PORT 1
RECEIVE
INTERFACE
PORT 1
TRANSMIT
INTERFACE
PORT 3
RECEIVE
INTERFACE
PORT 3
MEMORY
D_IN0_[15:0]
D_OUT
3
_
[
15
:0]
PC
L
K
A
D
D
R
E
S
S
_
[12:
0]
TA
_N
RW_
N
T
EA_
N
HIZ_N
RST_N
SYS_FP
SYS_CLK
TST
M
D
_
N
SCANEN_
N
Product Brief
September 2000
40 Gbits/s Cross Connect
TDCS6440G SONET/SDH
Supervisory Features
Supervisory features built into the TDCS6440G provide
diagnostic capabilities and fault coverage.
s
Frame pulse integrity
s
LVDS link integrity
s
Framer monitoring
s
FIFO aligner monitoring
s
Frame offset monitoring
s
Microprocessor interface monitoring
Test Features
Test features built into the LVDS transceivers are a key
element in providing testing and debugging capabilities
for the many aspects of chip level, board level, and
system level functionality.
s
A1/A2 error insert
s
B1 error insert
s
Scrambler/descrambler disable
Software Reset
An asynchronous software reset is provided. The soft-
ware reset is self-clearing, and it resets the whole
device.
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.
Copyright 2000 Lucent Technologies Inc.
All Rights Reserved
September 2000
PB01-007SONT (Replaces PN99-129SONT)
For additional information, contact your Microelectronics Group Account Manager or the following:
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Tel. (65) 778 8833, FAX (65) 777 7495
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200233 P. R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652
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Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
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