Product Brief

March 2001

TFEC0410G 40 Gbits/s Optical Networking Interface
With Strong FEC and Digital Wrapper

Features

Versatile IC supports single 2488 Mbits/s (16 bits
at 155 Mbits/s), quad 2488 Mbits/s (4 bits at
622 Mbits/s), and single 9952 Mbits/s (16 bits at
622 Mbits/s) system payload rates.

G.975 RS (255, 239) strong FEC over 16 inter-
leaved frames in quad 2488 Mbits/s and 16/64
interleaved frames in single 9952 Mbits/s payload
rate (2666 Mbits/s and 10663 Mbits/s line rate
respectively).

Supports a digital wrapper (OCh) superframe with
overhead transport and flexible overhead mapping.

Weak BCH-3 FEC (4359, 4320) in quad STS-48/
STM-16 and single STS-192/STM-64 SONET/
SDH frame with provisionable check bit allocation.

Section/RS and line/MS termination and genera-
tion for quad STS-48/STM-16 and single STS-192/
STM-64 SONET/SDH signals.

Facility/terminal loopback capabilities at both the
line and system interfaces. Internal loopbacks for
diagnostic applications, etc.

Provisionable 16 x 622/666 Mbits/s LVDS line and
system interfaces for asymmetric operation (i.e.,
10 Gbits/s system interface to quad 2.5 Gbits/s line
interface).

Supports any combination of strong FEC, weak
FEC, and digital wrapper (OCh).

Supports any clock frequencies on the system and
line sides that meet the 15/14 or 14/15 ratios
respectively. This applies for data mapping/demap-
ping into/from a strong FEC frame or digital wrap-
per (OCh) frame only.

Automatic clock switch during loss-of-clock condi-
tions (nonhitless).

Programmable error inserter/monitor (PRBS gen-
erator/monitor) for test and debug. Works on
SONET/SDH and FEC/digital wrapper (OCh) sig-
nals without the need of pointer interpreters (PI).

Seamless interface to other Lucent Microelectronic
devices (TSOT0410G--ISIS, TTRN0110G,
TTRCV0110G, TDAT0410G).

Low-power 1.5 V core operation with 3.3 V I/O (5 V
tolerant).

40 °C--85 °C industrial temperature range.

Strong FEC--Out-of-Band

G.975 (255, 239) RS code (T = 8) capable of cor-
recting eight symbols (bytes) in 255 symbols
(bytes).

x16 interleaving for 2488 Mbits/s and x16 or x64
interleaving for 9952 Mbits/s system payload rates.

Provisionable framer parameters allows compati-
bility with changing standards and non-standard
framing algorithms.

Programmable framing parameters: alpha and
delta value, framing pattern, independent program-
mability of the number of framing bytes examined
to determine in-frame/out-of-frame conditions, and
framing byte location.

Detects OOF, LOF, LOS, and AIS conditions. Can
optionally generate an AIS signal under user con-
trol.

Internal phase detectors (Rx/Tx) to lock 666 MHz
line clock and 622 MHz system clock.

Provides FEC frame scrambling/descrambling.

Counts corrected bits (raw error count)/block, and
uncorrectable blocks.

Under software control two encoding modes are
selectable: encode and bypass.

Under software control four modes are selectable:
monitor mode (decode no correction, no data
delay), decoder off with no delay, decode with no
correction with data delay, and decode and correct
with data delay. Transition between decode with
correction with data delay and decode and correct
with data delay are hitless.

Agere Systems Inc.

Product Brief

March 2001

With Strong FEC and Digital Wrapper

TFEC0410G 40 Gbits/s Optical Networking Interface

Strong FEC--Out-of-Band

(continued)

When uncorrectable errors are detected, correction
operation is disabled automatically on a block-by-
block basis resulting in no miscorrections.

Report current input BER and detect prepro-
grammed BER thresholds.

Byte interleaving/deinterleaving of DW/FEC frames
provided.

Digital Wrapper (OCh)--Out-of-Band

All strong FEC--out-of-band features are supported
in digital wrapper (OCh) mode in addition to the extra
features associated with processing/monitoring the
extra overhead bytes.

Superframe size of four blocks of 16 FEC frames.

Provisionable internal mapping/monitoring of over-
head bytes in Tx/Rx directions respectively.

Provisionable BIP-8 insertion over previous super-
frame. Provisionable BIP-8 count provided on a bit or
block basis.

Optional insertion and extraction of overhead bytes
via serial overhead interfaces (DWAC).

Optional AIS insertion/monitoring into payload (provi-
sionable).

Weak FEC--in-band.

Per draft recommendation G.707 (2/00).

Bit-interleaved (x8) BCH-3 (4359, 4320) triple error-
correcting code.

Operates on quad STS-48/STM-16 and single
STS192/STM-64 signals.

Separate 622 MHz Rx and Tx clock inputs.

Process FEC status indication (FSI) bits.

Counts corrected bits/blocks, and uncorrectable
blocks.

Under software control five decode/correct modes are
provided: hardware mode, correct with delay, do not
correct with delay, don't correct without delay (dis-
able), and monitor only (no data path delay).

In hardware mode, two correction modes are based
on the FSI values: correct with delay, and do not cor-
rect with delay. Transition between these states is hit-
less.

BER algorithms provided before and after error cor-
rection based on B1/B2 errors or BCH correct bit
errors.

Section/Line Overhead Termination/
Generation

Synchronizes to the receive SONET/SDH frames
and detects severely errored framing (SEF) and loss
of frame (LOF). Also inserts Tx A1A2.

Supports enhanced framing (A1, A1, A2, A2).

Provides frame synchronous scrambling and
descrambling of the SONET/SDH data and LOS is
detected.

Extracts the 16 byte or 64 byte section trace mes-
sage (J0) and optionally stores it in, or compares it
to, an internal register. Unstable or mismatched mes-
sages are detected and path AIS may be optionally
inserted in the drop data.

Optionally inserts a 16 byte or 64 byte section trace
message (or fixed pattern) into the J0 byte of the Tx
data from internal registers.

Extracts, and outputs on a serial link all transport
overhead bytes or the first STS-1 TOH bytes along
with the M1 byte in the receive direction, and inserts
any or all transport overhead bytes in the transmit
data using a corresponding serial input.

Extracts, integrates, and stores the automatic protec-
tion switch (APS) channel bytes (K1, K2) for the
receive data and detects protection switch failure
alarms (inconsistent APS bytes). Inserts provision-
able APS bytes in the transmit channels.

Detects line AIS and RDI based on the K2 byte of the
receive data. Optionally inserts line RDI automati-
cally due to LOS, LOF, or line AIS defects in the
transmit direction.

Extracts, integrates, and stores the synchronization
status byte (S1) for the receive data. Inserts the syn-
chronization status byte into the transmit data from
an internal register.

Calculates, detects, and counts section and line
BIP-8 errors (B1, B2) for the receive data, and
inserts BIP-8 in the transmit data. Supports either bit
or block error accumulation, each of which are sepa-
rately provisionable.

Extracts and counts (bit/block) line remote errors
(REI) for the receive data (M1), and inserts REI in the
transmit data based on B2 errors.

Performs alignment for multiplexing quad STS-48/
STM-16 into a STS-192/STM-64 signal.

Agere Systems Inc.

Product Brief
March 2001

With Strong FEC and Digital Wrapper

TFEC0410G 40 Gbits/s Optical Networking Interface

Microprocessor Interface

Intel

Motorola

processor support.

66 MHz read and write access.

16-bit address, 8-bit/16-bit data interface.

Description

The TFEC0410G optical networking interface provides
a versatile interface for a single 2488 Mbits/s, quad
2488 Mbits/s, and single 9952 Mbits/s applications. It
can function in section termination applications as well
as in regenerator applications.

It is provisionable to operate in the following modes:
single 2488 mode (16-bit line/system interfaces), quad
2488 Mbits/s (4-bit interfaces), or 9952 Mbits/s (16-bit
interfaces) optical networking modes (i.e., no SONET/
SDH payload frame required).

Strong FEC.

Flexible digital wrapper (OCh).

Pass through.

OTN adaptor.

In the digital wrapper (OCh) mode, the overhead byte
locations are provisionable, allowing this chip to be
used in various optical networking applications. The
overhead bytes can be accessed through either a serial
overhead channel, or a subset (4 bytes) can be pro-
cessed internally. The final mode (OTN adaptor) allows
the TFEC0410G to be used as a SONET/SDH to opti-
cal network adaptor.

The TFEC0410G is also provisionable to operate in
weak FEC mode at either single STS-48/STM-16, quad
STS-48/STM-16, or STS-192/STM-64 mode.

From a timing perspective, the TFEC0410G is capable
of running as a regenerator or ADM (i.e., separate Tx
and Rx clocks) at both 2488 Mbits/s and 9952 Mbits/s.

Product Applications

TFEC0410G block diagram (Figure 1 on page 4).

Strong FEC: terminal (Figure 2 on page 5).

Strong FEC: regenerator (SONET/SDH section mon-
itoring possible) (Figure 3 on page 6).

Digital wrapper (OCh) with strong FEC: OTN adapter
(Figure 4 on page 7).

Digital wrapper (OCh) with strong FEC: OTN regen-
erator (Figure 5 on page 8).

Strong FEC or digital wrapper (OCh) with strong
FEC: bidirectional mode (Figure 6 on page 9).

Weak FEC: SONET/SDH terminal (Figure 7 on
page 10).

Weak FEC: SONET/SDH regenerator (Figure 8 on
page 11).

Strong/weak FEC: SONET/SDH terminal (Figure 9
on page 12).

Strong/weak FEC: SONET/SDH regenerator
(Figure 10 on page 13).

Digital wrapper (OCh) with strong/weak FEC: OTN
with SONET/SDH termination (Figure 11 on
page 14).

Asymmetric multiplex mode: SONET/SDH terminal
with/without strong/weak FEC (Figure 12 on
page 15).

Single 2.5 Gbits/s mode: SONET/SDH, terminal/
regenerator, with strong or weak FEC (Figure 13 on
page 16).

Intel

is a registered trademark of Intel Corporation.

Motorola

is a registered trademark of Motorola, Inc.

Agere Systems Inc.

Product Brief

March 2001

With Strong FEC and Digital Wrapper

TFEC0410G 40 Gbits/s Optical Networking Interface

Product Applications

(continued)

1150 (F)

Figure 1. Block Diagram

BCH-3

SONET/

SDH

BCH

SONET/

SDH

SONET/SDH

MICROPROCESSOR INTERFACE AND CONTROL

OTN OH/

OTN OH

OTN

STATS

DIGITAL WRAPPER (OCH)

DECODE

AND

CORRECT

FEC/DW

X16

INTERLEAVE

STRONG FEC

10.66 (9.953) Gbits/s

OR QUAD

2.66 (2.488) Gbits/s

10.66 (9.953) Gbits/s

OR QUAD

2.66 (2.488) Gbits/s

9.953 Gbits/s
OR QUAD
2.488 Gbits/s

FRAMER

DECODE/

CORRECT

BCH

SECTION

MONITORING

STATS

MONITOR

ENCODER

FRAME

INSERT

WITH OPTICAL CHANNEL

OVERHEAD PROCESSING

(REED-SOLOMON

OUT-OF-BAND)

WITH WEAK FEC
(BCH-3 IN-BAND)

SDH

BCH OH

INSERT

FRAMER AND

X16 DE-INT

SONET/

SDH

FRAMER

STATS

Agere Systems Inc.

Product Brief

March 2001

With Strong FEC and Digital Wrapper

TFEC0410G 40 Gbits/s Optical Networking Interface

Product Applications

(continued)

1154 (F)

Figure 9. Strong/Weak FEC Application: SONET/SDH Terminal

BCH-3

SONET/

SDH

BCH

SONET/

SDH

SONET/SDH

MICROPROCESSOR INTERFACE AND CONTROL

DIGITAL WRAPPER (OCH)

DECODE

AND

CORRECT

FEC/DW

X16

INTERLEAVE

STRONG FEC

10.66 Gbits/s

OR QUAD

2.66 Gbits/s

10.66 Gbits/s

OR QUAD

2.66 Gbits/s

9.953 Gbits/s
OR QUAD
2.488 Gbits/s

FRAMER

DECODE/

CORRECT

BCH

SECTION

MONITORING

STATS

ENCODER

WITH OPTICAL CHANNEL

OVERHEAD PROCESSING

(REED-SOLOMON

OUT-OF-BAND)

WITH WEAK FEC
(BCH-3 IN-BAND)

SDH

BCH OH

INSERT

FRAMER AND

X16 DE-INT

SONET/

SDH

FRAMER

STATS

Agere Systems Inc.

Product Brief
March 2001

With Strong FEC and Digital Wrapper

TFEC0410G 40 Gbits/s Optical Networking Interface

Product Applications

(continued)

1155 (F)

Figure 10. Strong/Weak FEC Application: SONET/SDH Regenerator

BCH-3

SONET/

SDH

BCH

SONET/

SDH

SONET/SDH

MICROPROCESSOR INTERFACE AND CONTROL

DIGITAL WRAPPER (OCH)

DECODE

AND

CORRECT

FEC/DW

X16

INTERLEAVE

STRONG FEC

10.66 Gbits/s

OR QUAD

2.66 Gbits/s

10.66 Gbits/s

OR QUAD

2.66 Gbits/s

9.953 Gbits/s
OR QUAD
2.488 Gbits/s

FRAMER

DECODE/

CORRECT

BCH

SECTION

MONITORING

STATS

ENCODER

WITH OPTICAL CHANNEL

OVERHEAD PROCESSING

(REED-SOLOMON

OUT-OF-BAND)

WITH WEAK FEC
(BCH-3 IN-BAND)

SDH

BCH OH

INSERT

FRAMER AND

X16 DE-INT

SONET/

SDH

FRAMER

STATS

Agere Systems Inc.

Product Brief

March 2001

With Strong FEC and Digital Wrapper

TFEC0410G 40 Gbits/s Optical Networking Interface

Product Applications

(continued)

1156 (F)

Figure 11. Digital Wrapper (OCh)/Weak FEC: OTN with SONET/SDH Termination

BCH-3

SONET/

SDH

BCH

SONET/

SDH

SONET/SDH

MICROPROCESSOR INTERFACE AND CONTROL

OTN OH/

OTN OH

OTN

STATS

DIGITAL WRAPPER (OCH)

DECODE

AND

CORRECT

FEC/DW

X16

INTERLEAVE

STRONG FEC

10.66 Gbits/s

OR QUAD

2.66 Gbits/s

10.66 Gbits/s

OR QUAD

2.66 Gbits/s

9.953 Gbits/s
OR QUAD
2.488 Gbits/s

FRAMER

DECODE/

CORRECT

BCH

SECTION

MONITORING

STATS

MONITOR

ENCODER

FRAME

INSERT

WITH OPTICAL CHANNEL

OVERHEAD PROCESSING

(REED-SOLOMON

OUT-OF-BAND)

WITH WEAK FEC
(BCH-3 IN-BAND)

SDH

BCH OH

INSERT

FRAMER AND

X16 DE-INT

SONET/

SDH

FRAMER

STATS

Agere Systems Inc.

Product Brief
March 2001

With Strong FEC and Digital Wrapper

TFEC0410G 40 Gbits/s Optical Networking Interface

Product Applications

(continued)

1157 (F)

Figure 12. Asymmetric Multiplex Mode: SONET/SDH Terminal with/without Strong/Weak FEC

BCH-3

SONET/

SDH

BCH

SONET/

SDH

SONET/SDH

MICROPROCESSOR INTERFACE AND CONTROL

OTN OH/

OTN OH

OTN

STATS

DIGITAL WRAPPER (OCH)

DECODE

AND

CORRECT

FEC/DW

X16

INTERLEAVE

STRONG FEC

10.66 Gbits/s

9.953 Gbits/s

10.66 Gbits/s

9.953 Gbits/s

QUAD
2.488 Gbits/s

FRAMER

DECODE/

CORRECT

BCH

SECTION

MONITORING

STATS

MONITOR

ENCODER

FRAME

INSERT

WITH OPTICAL CHANNEL

OVERHEAD PROCESSING

(REED-SOLOMON

OUT-OF-BAND)

WITH WEAK FEC
(BCH-3 IN-BAND)

SDH

BCH OH

INSERT

FRAMER AND

X16 DE-INT

SONET/

SDH

FRAMER

STATS

Agere Systems Inc.

Product Brief

March 2001

With Strong FEC and Digital Wrapper

TFEC0410G 40 Gbits/s Optical Networking Interface

Product Applications

(continued)

1158 (F)

Figure 13. Single 2.5 Gbits/s Mode: SONET/SDH, Terminal/Regenerator, with Strong or Weak FEC

BCH-3

SONET/

SDH

BCH

SONET/

SDH

SONET/SDH

MICROPROCESSOR INTERFACE AND CONTROL

OTN OH/

OTN OH

OTN

STATS

DIGITAL WRAPPER (OCH)

DECODE

AND

CORRECT

FEC/DW

X16

INTERLEAVE

STRONG FEC

SINGLE

2.488/2.66 Gbits/s

FRAMER

DECODE/

CORRECT

BCH

SECTION

MONITORING

STATS

MONITOR

ENCODER

FRAME

INSERT

WITH OPTICAL CHANNEL

OVERHEAD PROCESSING

(REED-SOLOMON

OUT-OF-BAND)

WITH WEAK FEC
(BCH-3 IN-BAND)

SDH

BCH OH

INSERT

FRAMER AND

X16 DE-INT

SONET/

SDH

FRAMER

STATS

(16 bits)

SINGLE

2.488/2.66 Gbits/s

(16 bits)

SINGLE
2.488/2.66 Gbits/s

(16 bits)

SINGLE
2.488/2.66 Gbits/s

(16 bits)

Agere Systems Inc.

Product Brief
March 2001

With Strong FEC and Digital Wrapper

TFEC0410G 40 Gbits/s Optical Networking Interface

Device Overview

The following diagram (Figure 14) shows a simplified picture of the major blocks and I/O information of the
TFEC0410G device. The device has a flexible setup to allow operation in terminal and regenerator applications.

1159 (F)

Figure 14. TFEC Block Diagram and I/O

Device Modes Overview

The TFEC0410G has several functional modes to allow operation in terminal and regenerator applications. Table 1
outlines the system and line interface rate requirements in different applications. Other combinations can be pro-
grammed which may be acceptable operating modes of the device.

RECEIVE

STS-192

SYSTEM

INTERFACE

RDSO_1_[3:0]

RDSO_2_[3:0]

RDSO_3_[3:0]

RDSO_4_[3:0]

TRANSMIT

STS-192

SYSTEM

INTERFACE

TDSI_1_[3:0]

TDSI_2_[3:0]

TDSI_3_[3:0]

TDSI_4_[3:0]

STS-48 TRANSMIT

SECTION/LINE OVERHEAD

STS-48 RECEIVE

SECTION/LINE OVERHEAD

JTAG INTERFACE

ST_

MICROPROCESSOR INTERFACE

I
T

[
1:0]

15:0]

RCL

KSI[1

--4

]

RCLKSO_[1--4]

PCL

TEA

INT

/L_N

RST_N

IDDQ_N

TCLKSI_[1--4]

MONITOR/INSERT

BCH-3 ENCODE

MONITOR/INSERT

BCH-3 DECODE/CORRECT

I
_[1--4]

OAC_

NCO_

[
1

]

C_DA

[
1--4][3

:0]

OAC_

--4

]

OAC_

SYN

[
1

]

_[1--4

[
3:0]

I_[1--4]

WRAPPER

DIGITAL

WITH

OPTICAL

CHANNEL

OVERHEAD

PROCESSING

T/R

O_[

--4]

T/R

_[1--4]

/
RDW

_DA

I/O_

[1--4]

DENI_

[
1

]

TDLO_1_[3:0]

TDLO_2_[3:0]

TDLO_3_[3:0]

TDLO_4_[3:0]

TCLKLO_[1--4]

RDLI_1_[3:0]

RDLI_2_[3:0]

RDLI_3_[3:0]

RDLI_4_[3:0]

RCLKLI_[1--4]

INT.

LINE

INT.

LINE

LINE SIDE

SYSTEM SIDE

STRONG

FEC

(REED-

SOLOMON)

OUT-OF-BAND

PHASE DET.

SE_

[
1

]

SE_

[
1

]

HAS

--4

]

RPHAS

--4

]

RXREFO_[1--4]

LI[

--4]

OAC_

[
1

--4

]

IO_

[47--0]

MPMODE_AS,
MPTYPE_IM,
MPDB_8_16,
MPPAREN

N, . . .

PHASE DET.

Product Brief

March 2001

With Strong FEC and Digital Wrapper

TFEC0410G 40 Gbits/s Optical Networking Interface

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liab ility is assumed as a result of their use or application. No rights
under any patent accompany the sale of any such product(s) or information.

March 2001
PB01-014SONT (Replaces PN00-024SONT)

For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:

http://www.agere.com

E-MAIL:

docmaster@micro.lucent.com

N. AMERICA:

Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256

Tel. (65) 778 8833, FAX (65) 777 7495

CHINA:

Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC
Tel. (86) 21 50471212, FAX (86) 21 50472266

JAPAN:

Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700

EUROPE:

Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),

FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)

Device Overview

(continued)

Table 1. TFEC0410G Operating Modes

Mode

Receive Interface

Transmit Interface

Rx--Line

(Gbits/s)

Rx--System

(Gbits/s)

Tx--System

(Gbits/s)

Tx--Line

(Gbits/s)

Strong FEC/Digital

Wrapper--Terminal

10G

10.66

9.953

10.66

Quad 2.5G

2.66

2.48

2.66

Strong FEC/Digital

Wrapper--Regenerator

10G

10.66

Internal Loopback (10.66)

10.66

Quad 2.5G

2.66

Internal Loopback (2.66)

2.66

Strong FEC or Digital

Wrapper with Strong
FEC--Bidirectional Mode

10G

10.66

Quad 2.5G

2.66

Weak FEC--Terminal

10G

9.953

Quad 2.5G

2.488

Weak FEC--Regenerator

10G

9.953

Internal Loopback (9.953)

9.953

Quad 2.5G

2.488

Internal Loopback (2.488)

2.488

Strong/Weak--Terminal

10G

10.66

9.953

10.66

Quad 2.5G

2.66

2.488

2.66

Strong/Weak--

Regenerator

10G

10.66

Internal Loopback (9.953)

9.953

Quad 2.5G

2.66

Internal Loopback (2.488)

9.953

Digital Wrapper/Weak--

Terminal

10G

10.66

9.953

10.66

Quad 2.5G

2.66

2.488

2.66

Asymmetric Multiplex

Mode

10G

Quad 2.5G

10.66/9.953

2.488

10.66/9.953

Single 2.5 Gbits/s Mode

(16-Bit Line/System
Interface)

2.5G to/from 2.5G

2.66/2.488

Asymmetric:

Strong/Digital Wrapper
with/without Weak

10G

Quad 2.5G

10.66

Quad--2.488

9.953

Quad--2.66

Asymmetric--Weak

10G

Quad 2.5G

9.953

Quad--2.488

9.953

Quad--2.488

Asymmetric--Tx/Rx

Directions

E.g., Rx = 10G

Weak,

Tx = Quad 2.5G

Strong

9.953

2.488

2.66

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TFEC0410G

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TFEC0410G