Document Outline

• Features
  • SONET/SDH Interface
  • STS/STM Pointer Interpreter
  • Telecom Bus Interface
  • VT Termination/Generation (x28/21)
• suprmapr_front_cont.pdf
  • Mapping/Multiplexing Modes (x28/21)
  • M13 Features
  • DS3/DS2/DS1/E1 Cross Connect
  • Jitter Attenuation
  • PDH Interfaces
  • T1/E1/J1 Framing Features (x28/21)
  • System Test and Maintenance
  • Microprocessor Interface
  • Chip Testing and Maintenance
  • Interface to Other Lucent ME Devices
• suprmapr_preface.pdf
  • Preface
    • Introductory Sections
    • Functional Sections
    • Characteristics Sections
    • Parts that Make Up the Functional Sections
    • Naming Convention for Registers and Parameters
• suprmapr_overview.pdf
  • Overview
    • Figure 1. Functional Diagram of Super Mapper
    • Application Diagrams
    • Figure 2. Switching Application of the Super Mapper
    • Figure 3. Transport Application of the Super Mapper
    • High-Speed Line Interfaces and Clock and Data Recovery
    • STS-3/STM-1 Overhead Processing
    • Multiplex Section Protection (MSP 1+1)
    • Pointer Interpreter
    • Path Termination Function
    • STS-3/STM-1 Mux-Demux
    • Telecom Bus Interface�Interfacing to Mate Devices
    • SPE/AU-3 Mapper (DS3 Mapper)
    • VT/VC Mapper
    • M13/M23 Multiplexer
    • Cross Connect Block
    • Digital Jitter Attenuator
    • Test Pattern Generator
    • 28 Channel Framer
    • Figure 4. Super Mapper Switching Mode for Framer in Concentration Highway Interface (CHI) Configu...
    • Figure 5. Super Mapper Switching Mode for Framer in Parallel System Bus Configuration
    • Figure 6. Super Mapper Switching Mode CHI Configuration with Byte-Synchronous VT Mapping Enabled
    • Figure 7. Super Mapper Byte-Synchronous Transport Mode: Passive Performance Monitoring
    • Figure 8. Super Mapper Byte-Synchronous Transport Mode: Intrusive Performance Monitoring
    • Line Decoder/Encoder
    • Receive Frame Aligner/Transmit Frame Formatter
    • Receive Performance Monitor
    • Signaling Processor
    • Facility Data Link (FDL) Processor
    • HDLC Unit
    • System Interface
• suprmapr_pin_info.pdf
  • Pin Information
    • Figure 9. Pin Diagram of 456-Pin PBGA (Bottom View)
    • Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order
    • Table 2. Pin Assignments for 456-Pin PBGA by Signal Name
    • Table 3. Pin Descriptions
• suprmapr_mpu.pdf
  • Microprocessor Interface and Super Mapper Global Control and Status Registers
    • Introduction
    • Features
    • Microprocessor Interface
    • MPU Block Diagram
    • Figure 10. Microprocessor Interface
    • Super Mapper Register Address Mapping
    • Table 4. Super Mapper Register Address Mapping
    • Performance Monitoring (PM) Counters Operation
    • Figure 11. PM Reset Counter
    • Figure 12. PM Reset Signal Generation
    • Super Mapper Global Interrupt Status and Control
    • Global Control
    • Super Mapper Global Control and Status Register Descriptions
    • Table 5. SMPR_VCR, Super Mapper Version Control Register (RO)
    • Table 6. SMPR_SYMR[4], Super Mapper Symbol Register4 SMPR(RO)
    • Table 7. SMPR_SYMR[3], Super Mapper Symbol Register3 (RO)
    • Table 8. SMPR_SYMR[2], Super Mapper Symbol Register2 (RO)
    • Table 9. SMPR_SYMR[1], Super Mapper Symbol Register1 (RO)
    • Table 10. SMPR_SYMR[0], Super Mapper Symbol Register0 (RO)
    • Table 11. SMPR_ISR, Super Mapper Interrupt Status Register (RO)
    • Table 12. SMPR_IMR, Super Mapper Interrupt Mask Register (RW)
    • Table 13. SMPR_GTR, Global Trigger Register (RW)
    • Table 14. SMPR_MSRR, Block Software Reset Register (RW)
    • Table 15. SMPR_GCR, Global Control Register (RW)
    • Table 16. SMPR_TSCR, TMUX and SPEMPR Control Register (RW)
    • Table 17. SMPR_FCR, Framer Control Register (RW)
    • Table 18. SMPR_CLCR, CDR and LVDS Control Register (RW)
    • Table 19. SMPR_CPCR, Clock and Power Control Register (RW)
    • Table 20. SMPR_PMRCHR, PM Reset Count High Register (RW)
    • Table 21. SMPR_PMRCLR, PM Reset Count Low Register (RW)
    • Table 22. SMPR_SR, Scratch Register (RW)
    • Table 23. SMPR_TX_LINE_EN1
    • Microprocessor Interface Register Map
    • Table 24. Microprocessor Interface Register Map
    • Microprocessor Interface Register Map
• suprmapr_tmux.pdf
  • TMUX Functional Description
    • TMUX Introduction
    • TMUX Features
    • TMUX Receive Path Overview
    • Figure 13. TMUX RTOAC Timing Diagram
    • TMUX Transmit Path Overview
    • Figure 14. TMUX TTOAC and RTOAC Timing Digram
    • TMUX High-Level Block Interconnect Diagram
    • Figure 15. High-Level TMUX Interconnect
    • TMUX Detailed Block Diagram
    • Figure 16. Detailed Block Diagram of the TMUX
    • Receive Direction Functional Block Diagram
    • Figure 17. Receive Direction Functional Block Diagram
    • Receive Direction (Receive Path from Sonet Global/SDH)
    • Table 25. Receive TOAC Modes
    • Table 26. Transport Overhead Byte Access�Receive Direction
    • Figure 18. Pointer Interpretation State Diagram
    • Table 27. STS Signal Label Defect Conditions
    • Table 28. STS-1 P-REI Interpretation
    • Table 29. Signal Degrade (SD) Parameters
    • Table 30. Signal Fail Parameters
    • Table 31. Signal Fail/Signal Degrade Recommended Programming Values
    • Table 32. Path Overhead Byte Access
    • Figure 19. Receive Low-Speed Bus Interface Signals for STS-3/STM-1 Signals
    • Transmit Direction (Transmit path to SONET/SDH line)
    • Figure 20. Transmit Low-Speed Bus Interface Signals for STS-3/STM-1 Signals
    • Figure 21. Transmit Direction POH and TOH Insertion Diagram
    • Table 33. Path Overhead Byte Access�Transmit Direction
    • Table 34. TPOAC Control Bits
    • Table 35. RDI-P Defects for Enhanced RDI-P Mode
    • Table 36. Transmit TOAC Modes
    • Table 37. Transmit Transport Overhead Byte Full Access Mode
    • Table 38. TTOAC Control Bits in Full Access Mode
    • TMUX Register Descriptions
    • Table 39. TMUX_ID_R, TMUX Identification Register (RO)
    • Table 40. TMUX_ONESHOT, TMUX One-Shot Register 0 to 1 (R/W)
    • Table 41. TMUX_RCV_TX_MODE, TMUX Receive/Transmit Mode (R/W)
    • Table 42. TMUX_TX_DLT, Delta/Event (COR/COW)
    • Table 43. TMUX_RPS_DLT, Delta/Event (COR/COW)
    • Table 44. TMUX_RHS_DLT, Delta/Event (COR/COW)
    • Table 45. TMUX_RPOH[1�3]_DLT, Delta/Event (COR/COW)
    • Table 46. TMUX_TX_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
    • Table 47. TMUX_RPS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
    • Table 48. TMUX_RHS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
    • Table 49. TMUX_RPOH[1�3]_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
    • Table 50. TMUX_APSINT_MSK, Mask Bits for APSINT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)
    • Table 51. TMUX_TX_STATE, State Parameters (RO)
    • Table 52. TMUX_RPS_STATE, State and Value Parameters (RO)
    • Table 53. TMUX_RHS_STATE, State and Value Parameters (RO)
    • Table 54. TMUX_RPOH[1�3]_STATE, State and Value Parameters (RO)
    • Table 55. TMUX_RHS_CTL, Receive High-Speed Control Parameters (R/W)
    • Table 56. TMUX_RLS_BITBLK_CTL, Receive Low-Speed Control Parameters (R/W)
    • Table 57. TMUX_RLS_MODE_CTL, Receive Low-Speed Control Parameters (R/W)
    • Table 58. TMUX_RAISINH_CTL, Receive Low-Speed Control Parameters (R/W)
    • Table 59. TMUX_LOSDETCNT, Receive Low-Speed Control Parameters (R/W)
    • Table 60. TMUX_CNTD_TOH_[A�B], Continuous N Times Detect Control Parameters (R/W)
    • Table 61. TMUX_CNTD_POH_[A�B], Continuous N Times Detect Control Parameters (R/W)
    • Table 62. TMUX_C2EXP[1�2_3], Continuous N Times Detect Control Parameters (R/W)
    • Table 63. TMUX_RF1MON, Receive Monitor Values (RO)
    • Table 64. TMUX_RAPSMON, Receive Monitor Values (RO)
    • Table 65. TMUX_RS1MON, Receive Monitor Values (RO)
    • Table 66. TMUX_RPOHMON[1�3][A�D], Receive Monitor Values (RO)
    • Table 67. TMUX_TLS_CTL, Transmit Low-Speed Control Parameters (R/W)
    • Table 68. TMUX_THS_PORT_CTL, Transmit High-Speed Port Control Parameters (R/W)
    • Table 69. TMUX_THS_TOH_CTL, Transmit High-Speed Control Parameters (R/W)
    • Table 70. TMUX_THS_POH[1�3]_CTL, Transmit High-Speed Control Parameters (R/W)
    • Table 71. TMUX_TLRDI_CTL, Transmit High-Speed Line RDI Control Parameters (R/W)
    • Table 72. TMUX_TPRDI_CTL, Transmit High-Speed Path RDI Control Parameters (R/W)
    • Table 73. TMUX_TZ0_INS_VAL, Transmit TOH and POH Insert Values (R/W)
    • Table 74. TMUX_TS1_F1_INS_VAL, Transmit TOH and POH Insert Values (R/W)
    • Table 75. TMUX_TAPS_INS_VAL, Transmit TOH and POH Insert Values (R/W)
    • Table 76. TMUX_TPOH[1�3]_INS_[A�C], Transmit TOH and POH Insert Values (R/W)
    • Table 77. TMUX_TBERINS_CTL, Transmit High-Speed Error Insertion Control Parameters (R/W)
    • Table 78. TMUX_THS_ERR_CTL, Transmit High-Speed Error Insertion Control Parameters (R/W)
    • Table 79. TMUX_TOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W)
    • Table 80. TMUX_RPOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W)
    • Table 81. TMUX_TFRAMEOFFSET, Transmit High-Speed Offset Control Parameters (R/W)
    • Table 82. TMUX_SD_CTL[1�6], B1/B2 Signal Degrade Set/Clear Control Registers (R/W)
    • Table 83. TMUX_SF_CTL[1�6], B1/B2 Signal Fail Set/Clear Control Registers (R/W)
    • Table 84. TMUX_B3SD_CTL[1�6], B3 Signal Degrade Set/Clear Control Registers (R/W)
    • Table 85. TMUX_B3SF_CTL[1�6], B3 Signal Fail Set/Clear Control Registers (R/W)
    • Table 86. TMUX_B1ECNT, Receive B1 Error Counts (RO)
    • Table 87. TMUX_B2ECNT_17_16 and TMUX_B2ECNT_15_0, Receive B2 Error Counts (RO)
    • Table 88. TMUX_B3ECNT[1�3], Receive B3 Error Counts (RO)
    • Table 89. TMUX_M1ECNT_17_16 and TMUX_M1ECNT_15_0, Receive M1 Error Counts (RO)
    • Table 90. TMUX_G1ECNT[1�3], Receive G1 Error Counts (RO)
    • Table 91. TMUX_RPTR_INCCNT[1�3], Receive Pointer Increment Count (RO)
    • Table 92. TMUX_RPTR_DECCNT[1�3], Receive Pointer Decrement Count (RO)
    • Table 93. TMUX_RJ0EXPECTED[1�8], Expected J0 Byte Sequence (R/W)
    • Table 94. TMUX_RJ0CAPTURED[1�8], Captured J0 Receive Value (RO)
    • Table 95. TMUX_TJ0VALUE[1�8], J0 Byte Transmit Insert (R/W)
    • Table 96. TMUX_RJ1EXPECTED1_[1�32], Expected J1 Byte Value for Port 1 (R/W)
    • Table 97. TMUX_RJ1EXPECTED2_[1�32], Expected J1 Byte Value for Port 2 (R/W)
    • Table 98. TMUX_RJ1EXPECTED3_[1�32], Expected J1 Byte Value for Port 3 (R/W)
    • Table 99. TMUX_RJ1CAPTURED1_[1�32], Captured J1 Value for STS #1 (RO)
    • Table 100. TMUX_RJ1CAPTURED2_[1�32], Captured J1 Value for STS #2 (RO)
    • Table 101. TMUX_RJ1CAPTURED3_[1�32], Captured J1 Value for STS #3 (RO)
    • Table 102. TMUX_TJ1VALUE_1[1�32], J1 Byte Transmit Insert for STS #1 (R/W)
    • Table 103. TMUX_TJ1VALUE_2[1�32], J1 Byte Transmit Insert for STS #2 (R/W)
    • Table 104. TMUX_TJ1VALUE_3[1�32], J1 Byte Transmit Insert for STS #3 (R/W)
    • TMUX Register Map
    • Table 105. TMUX Register Map
• suprmapr_spe_mapr.pdf
  • SPE Mapper Functional Description
    • Introduction
    • Features
    • SPE Mapper Functional Description (continued)
    • SPE Mapper Functional Block Diagram
    • Figure 22. SPE Mapper Block with Connections to External Pins and Other Blocks in the Device
    • Basic Functional Flow of the SPE Mapper Transmit Section
    • Figure 23. Basic Functional Flow of the SPE Mapper Transmit Section
    • Basic Functional Flow Of The SPE Mapper Receive Section
    • Figure 24. Basic Functional Flow of the SPE Mapper Receive Section
    • TUG-2 to AU-3/STS-1 SPE Mapping (Used in North American Systems)
    • TUG-2 to TUG-3 Mapping (Used in ITU/ETSI standard based systems)
    • DS3 to AU-3/STS-1 SPE Mapping (Used in Telcordia*/ANSI� Standards Based Systems)
    • DS3 to TUG-3 Mapping (Used in ITU/ETSI Standard Based Systems)
    • SPE Mapper Basic Configuration
    • DS3 Configuration
    • Phase Detector for External DS3 PLL
    • Serial STS-1 SPE Channel (NSMI)
    • Figure 25. STS-1 NSMI Receive Operation
    • Figure 26. STS-1 NSMI Transmit Operation
    • TMUX Interface to the SPE Mapper
    • PATH Termination Block
    • Figure 27. Receive Direction Path Termination Block
    • Figure 28. Pointer Interpretation State Diagram
    • SPE Mapper Receive Direction Requirements
    • Table 106. J1 Monitor
    • Table 107. C2MON Processing
    • Table 108. F2 Monitor
    • Table 109. F3 Monitor
    • Table 110. N1 Monitor
    • Table 111. K3 Monitor
    • Table 112. AIS-P and RDI-P Detect
    • Table 113. STS-1 P-REI Interpretation
    • Table 114. Signal Degrade Parameters
    • Table 115. Signal Fail Parameters
    • Table 116. Path Overhead Byte Access
    • Transmit Direction (to SONET/SDH Line)
    • Figure 29. Transmit Direction Path Insertion Block
    • Table 117. RDI-P Defects for Enhanced RDI-P Mode
    • POAC Insert
    • Table 118. Path Overhead Byte Access�Transmit Direction
    • Table 119. TPOAC Control Bits
    • AIS Path Generation
    • SPE Mapper Register Descriptions
    • Table 120. SPE_VERSION_R, SPE Version and Identification Register (RO)
    • Table 121. SPE_ONESHOT, One-Shot (R/W)
    • Table 122. SPE_EVENT1�SPE_EVENT3, SPE Deltas/Events (COR/COW)
    • Table 123. SPE_MASK1�SPE_MASK3, Mask Bits (R/W)
    • Table 124. SPE_STATE1�SPE_STATE2, Receive/Transmit State and Value Parameters (RO)
    • Table 125. SPE_RAOH_CTL1�SPE_RAOH_CTL3, Receive Control for Alarm and OH Functions (R/W)
    • Table 126. SPE_CNTD1�SPE_CNTD2, Continuous N Times Detect Values (R/W)
    • Table 127. SPE_ROHC2, Receive Overhead Expected Value for C2 Byte (R/W)
    • Table 128. SPE_RMON1�SPE_RMON5, Receive Monitor Values (RO)
    • Table 129. SPE_MAP_CTL1�SPE_MAP_CTL3, Transmit/Receive Control for Mapping Functions (R/W)
    • Table 130. SPE_TAOH_CTL1�SPE_TAOH_CTL3, Transmit Control for Alarm and OH Functions (R/W)
    • Table 131. SPE_TRDIREI_CTL, Transmit Path RDI and REI Control Register (R/W)
    • Table 132. SPE_TERRINS_CTL, Transmit Error Insertion Control (R/W)
    • Table 133. SPE_TOHINS1�SPE_TOHINS4, Transmit OH Insert Value (R/W)
    • Table 134. SPE_SIGDEG_CTL1�SPE_SIGDEG_CTL6, Signal Degrade BER Algorithm Parameters (R/W)
    • Table 135. SPE_SIGFAIL_CTL1�SPE_SIGFAIL_CTL6, Signal Fail BER Algorithm Parameters (R/W)
    • Table 136. SPE_ERRCNT1�SPE_ERRCNT6, B3, G1, Bipolar Violation, and Excess Zero Error Count (RO)
    • Table 137. SPE_PTRCNT1�SPE_PTRCNT3, Receive Pointer Increment and Decrement Count (RO)
    • Table 138. SPE_RJ1MON_R1�SPE_RJ1MON_R32, Receive J1 Monitor Values (RO)
    • Table 139. SPE_TJ1DINS_R1�SPE_TJ1DINS_R32, Transmit J1 Insert Values (R/W)
    • Table 140. SPE_RJ1DEXP_R1�SPE_RJ1DEXP_R32, Receive J1 Expected Values (R/W)
    • Table 141. SPE_SCRATCH_R, Scratch Pad (R/W)
    • SPE Mapper Register Map
    • Table 142. SPE Mapper Register Map
• suprmapr_vt_tu_mapr.pdf
  • Figure 30. VT Mapper Interface Diagram
  • Figure 31. VT Mapper Functional Block Diagram
  • Table 143. VT2/TU-12 Payload Mapping
  • Table 144. VT1.5/TU-11 Payload Mapping
  • Table 145. VT2/TU-12 Locations
  • Table 146. VT1.5/TU-11 Locations
  • Figure 32. Pointer Interpretation State Diagram
  • Table 147. Receive VT/TU Demapping Selection
  • Table 148. Rx Signaling Behavior per Channel
  • Table 149. Data Type Header Definitions
  • Table 150. Transmit VT/TU Mapping Selection per Channel, VT_TX_MAPTYPE[1�28][3:0]
  • Table 151. V5 Overhead Byte Format
  • Table 152. BIP-2 Error Insertion Modes
  • Table 153. RDI-V, RFI-V, and REI-V Automatic Generation
  • Table 154. VT Signal Label Definition
  • Table 155. J2 Overhead Byte Insertion Modes per Channel
  • Table 156. Z6/N2 Overhead Byte Insertion Modes per Channel
  • Table 157. Z7/K4 Overhead Byte Insertion Modes per Channel
  • Table 158. O-Bit Insertion Modes per Channel
  • Table 159. Asynchronous VT1.5
  • Table 160. Bit Synchronous VT1.5
  • Table 161. Byte Synchronous VT1.5
  • Table 162. Asynchronous VT2
  • Table 163. Bit Synchronous VT2
  • Table 164. Byte Synchronous VT2
  • Table 165. VC-11 to TU-12 Conversion
  • Table 166. Framing Byte Generation per Channel
  • Figure 33. DS1 Mode Gapped Clocking Scheme
  • Figure 34. E1 Mode Gapped Clocking Scheme
  • Figure 35. DS1 Interface
  • Figure 36. E1 Interface
  • Figure 37. VT Mapper Receive Path Overhead Serial Access Channel
  • Figure 38. VT Mapper Transmit Path Overhead Serial Access Channel
  • Table 167. VT_VERSION_R, VT Mapper Ready, Version, and Identification (RO)
  • Table 168. VT_GDELTA, VT Global Deltas (COR/COW)
  • Table 169. VT_REVENT_DELTA[1�28], Receive Event and Delta Per Channel (COR/COW)
  • Table 170. VT_LOPOHFAIL_EVENT, Low-Order Path Overhead Failure Event (COR/COW)
  • Table 171. VT_TEVENT_DELTA[1�28], Transmit Event and Delta Per Channel (COR/COW)
  • Table 172. VT_GMASK, VT Global Masks (R/W)
  • Table 173. VT_RMASK[1�28], Receive Masks Per Channel (R/W)
  • Table 174. VT_LOPOHFAIL_MASK, Low-Order Path Overhead Failure Mask (R/W)
  • Table 175. VT_TMASK[1�28], Transmit Masks Per Channel (R/W)
  • Table 176. VT_GSTATE, VT Global State (RO)
  • Table 177. VT_RSTATE[1�28], Receive State Per Channel (RO)
  • Table 178. VT_RAPSSTATE[1�28], Receive APS State Per Channel (RO)
  • Table 179. VT_TSTATE[1�28], Transmit State Per Channel (RO)
  • Table 180. VT_GCTL1, VT Global Control Register 1 (R/W)
  • Table 181. VT_GCTL2, VT Global Control Register 2 (R/W)
  • Table 182. VT_GCTL3, VT Global Control Register 3 (R/W)
  • Table 183. VT_GCTL4, VT Global Control Register 4 (R/W)
  • Table 184. VT_GCTL5, VT Global Control Register 5 (R/W)
  • Table 185. VT_SIGDEG_CTL1, Signal Degrade Control Register 1 (R/W)
  • Table 186. VT_SIGDEG_CTL2, Signal Degrade Control Register 2 (R/W)
  • Table 187. VT_SIGDEG_CTL3, Signal Degrade Control Register 3 (R/W)
  • Table 188. VT_SIGDEG_CTL4, Signal Degrade Control Register 4 (R/W)
  • Table 189. VT_SIGDEG_CTL5, Signal Degrade Control Register 5 (R/W)
  • Table 190. VT_SIGDEG_CTL6, Signal Degrade Control Register 6 (R/W)
  • Table 191. VT_SIGDEG_CTL7, Signal Degrade Control Register 7 (R/W)
  • Table 192. VT_SIGFAIL_CTL1, Signal Fail Control Register 1 (R/W)
  • Table 193. VT_SIGFAIL_CTL2, Signal Fail Control Register 2 (R/W)
  • Table 194. VT_SIGFAIL_CTL3, Signal Fail Control Register 3 (R/W)
  • Table 195. VT_SIGFAIL_CTL4, Signal Fail Control Register 4 (R/W)
  • Table 196. VT_SIGFAIL_CTL5, Signal Fail Control Register 5 (R/W)
  • Table 197. VT_SIGFAIL_CTL6, Signal Fail Control Register 6 (R/W)
  • Table 198. VT_TCTL[1�28], Transmit Control Per Channel (R/W)
  • Table 199. VT_TTUOH_CTL[1�28], Transmit TU Overhead Control Per Channel (R/W)
  • Table 200. VT_TAPSRIVAL[1�28], Transmit APS and Remote Indication Per Channel (R/W)
  • Table 201. VT_TSWOW[1�28], Transmit Software Overwrite Per Channel (R/W)
  • Table 202. VT_TSIG_CTL[1�28], Transmit Signaling Control Per Channel (R/W)
  • Table 203. VT_J2BYTE_INS_R[1�28][1�16], J2 Insert Values Per Channel (R/W)
  • Table 204. VT_RCTL[1�28], Receive Control Per Channel (R/W)
  • Table 205. VT_RTUOH_CTL[1�28], Receive TU Overhead Control Per Channel (RO)
  • Table 206. VT_RBIP2_CNT[1�28], Receive BIP-2 Error Count Per Channel (RO)
  • Table 207. VT_RREIV_CNT[1�28], Receive REI-V Error Count Per Channel (RO)
  • Table 208. VT_RPTR_CNT[1�28], Receive Pointer and Count Per Channel (RO)
  • Table 209. VT_J2BYTE_EXP_R[1�28][1�16], J2 Expected Values Per Channel (R/W, RO)
  • Table 210. VT_THRES_CTL[1�28], Transmit Elastic Store Threshold Control (R/W)
  • Table 211. VT/TU Mapper Register Map
• suprmapr_m13_mux_demux.pdf
  • M13/M23 Mux/Demux Block Functional Description
    • M13 Introduction
    • Features
    • Block Diagram
    • Figure 39. M13 Block Diagram
    • Figure 40. M12 Functional Block Diagram
    • Figure 41. M23 Functional Block Diagram
    • M13 Functional Description
    • M13 Multiplexing Path
    • DS2 Frame Generation
    • Figure 42. DS3 NSMI Transmit Operation
    • Figure 43. DS3 NSMI Receive Operation
    • M23 Multiplexer
    • Table 212. C-Bit Parity Description and Transmit Value
    • AIS/Idle Insertion
    • B3ZS Encoder (GR-499)
    • DS3 R-to-T Loopback
    • M13/M23 Demultiplexer
    • M13 Block Register Descriptions
    • Table 213. M13_ID_R, M13 Block Identification (RO)
    • Table 214. M13_VERSION_R, M13 Version (RO)
    • Table 215. M13_DELTA1, Delta (RO)
    • Table 216. M13_DELTA2, Delta (RO)
    • Table 217. M13_DELTA3, Delta (RO)
    • Table 218. M13_DELTA4, Delta (RO)
    • Table 219. M13_DELTA5, Delta (RO)
    • Table 220. M13_MASK1, Mask (R/W)
    • Table 221. M13_MASK2, Mask (R/W)
    • Table 222. M13_MASK3, Mask (R/W)
    • Table 223. M13_MASK4, Mask (R/W)
    • Table 224. M13_MASK5, Mask (R/W)
    • Table 225. M13_DS3_STATUS1, Status (RO)
    • Table 226. M13_DS3_STATUS2, Status (RO)
    • Table 227. M13_XC_DS2_LOCD_R, DS2 Loss of Clock Delta (RO)
    • Table 228. M13_XC_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detection Delta (RO)
    • Table 229. M13_DS2_OOFD_R, DS2 Out of Frame Delta (RO)
    • Table 230. M13_DS2_LOFD_R, DS2 Loss of Frame Delta (RO)
    • Table 231. M13_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detect Delta (RO)
    • Table 232. M13_DS2_RAI_DETD_R, DS2 Remote Alarm Indication Detection Delta (RO)
    • Table 233. M13_DS2_LB_DETD_R, DS2 Loopback Detect Delta (RO)
    • Table 234. M13_DS2_RSV_RCVD_R, DS2 Receive Reserved Bit Delta (RO)
    • Table 235. M13_DS2DMX_LOCD_R, DS2 Demux Loss of Clock Delta (RO)
    • Table 236. M13_DS1_LOCD_R[1�4], DS1 Loss of Clock Delta Registers (RO)
    • Table 237. M13_DS1_AIS_DETD_R[1�4], DS1 Alarm Indication Signal Delta Registers (RO)
    • Table 238. M13_DS1_LB_DETD_R[1�4], DS1 Loopback Detect Delta Registers (RO)
    • Table 239. M13__XC_DS2_LOC_R, DS2 Loss of Clock Status (RO)
    • Table 240. M13_XC_DS2_AIS_DET_R, DS2 Alarm Indication Signal Detect Status (RO)
    • Table 241. M13_DS2_OOF_R, DS2 Out of Frame Status (RO)
    • Table 242. M13_DS2_LOF_R, DS2 Loss of Frame Status (RO)
    • Table 243. M13_DS2_AIS_DET_R, DS2 Alarm Indication Signal Detect Status (RO)
    • Table 244. M13_DS2_RAI_DET_R, DS2 Remote Alarm Indication Detect Status (RO)
    • Table 245. M13_DS2_LB_DET_R, DS2 Loopback Detect Status (RO)
    • Table 246. M13_DS2_RSV_RCV_R, DS2 Receive Reserved Bit Delta Status (RO)
    • Table 247. M13_DS2DMX_LOC_R, DS2 Demux Loss of Clock Status (RO)
    • Table 248. M13_DS1_LOC_R[1�4], DS1 Loss of Clock Status Registers (RO)
    • Table 249. M13_DS1_AIS_DET_R[1�4], DS1 Alarm Indication Signal Detect Status Registers (RO)
    • Table 250. M13_DS1_LB_DET_R[1�4], DS1 Loopback Detect Status Registers (RO)
    • Table 251. M13_DS1_FEAC_LB_DETD_R[1�4], DS1 Far-End Alarm and Control Loopback Detect Delta Regis...
    • Table 252. M13_DS1_FEAC_LB_DET_R[1�4], DS1 Far-End Alarm and Control Loopback Detect Status Regis...
    • Table 253. M13_RFEAC_CODE_R, Receive Far-End Alarm and Control Code Status (RO)
    • Table 254. M13_RDL_STATUS, Receive Data-Link Status (RO)
    • Table 255. M13_RDL_DATA_R, Receive Data-Link Data (RO)]
    • Table 256. M13_RDL_FRAME_SIZE_R, Receive Data-Link Frame Size (RO)]
    • Table 257. M13_RHDLC_STATUS_R, Receive High-Level Data-Link Control Status (RO)]
    • Table 258. M13_DS2_FORCE_OOF_R, DS2 Force Out of Frame (One Shot R/W)
    • Table 259. M13_CONTROL1, Control 1 (One Shot R/W)
    • Table 260. M13_CONTROL2, Control 2 (R/W)
    • Table 261. M13_CONTROL3, Control 3 (R/W)
    • Table 262. M13_SP_OFFSET_R, Sync Pulse Offset (R/W)
    • Table 263. M13_SP_D_OFFSET_R, Sync Pulse D Offset (R/W)
    • Table 264. M13_M12_MUX_CONTROL1_R[1�7], M12 MUX CONTROL 1 Registers [1�7] (R/W)
    • Table 265. M13_M12_MUX_CONTROL2_R[1�7], M12 MUX CONTROL 2 Registers [1�7] (R/W)
    • Table 266. M13_DS2_RAI_SEND_R, DS2 Remote Alarm Indication Send (R/W)
    • Table 267. M13_DS2_RSV_SEND_R, DS2 Reserve Bit Send (R/W)
    • Table 268. M13_DS2_MPINV_R, DS2 M-Frame Alignment or Parity Error (R/W)
    • Table 269. M13_DS2_FINV_R, DS2 Frame Error (R/W)
    • Table 270. M13_DS2_P_BER_R, Parity Bit Error Rate (R/W)
    • Table 271. M13_DS2M12_EDGE_R, DS2 M12 Edge (R/W)
    • Table 272. M13_DS2_FORCE_AIS_R, DS2 Force Alarm Indication Signal (R/W)
    • Table 273. M13_M12_DEMUX_CONTROL1_R[1�7], M12 Demux Control 1 Registers [1�7] (R/W)
    • Table 274. M13_M12_DEMUX_CONTROL2_R[1�7], M12 Demux Control 2 Registers [1�7] (R/W)
    • Table 275. M13_M12_DEMUX_CONTROL3, DS2 M12 Demux Control 3 (R/W)
    • Table 276. M13_DMDS2_EDGE_R, DS2 Edge for M12 Demux (R/W)
    • Table 277. M13_DS3_CONTROL1, DS3 Control 1 (R/W)
    • Table 278. M13_DS3_CONTROL2, DS3 Control 2 (R/W)
    • Table 279. M13_TFEAC_CONTROL, Tx FEAC Control (R/W)
    • Table 280. M13_THDLC_CONTROL1, Tx HDLC Control 1 (R/W)
    • Table 281. M13_THDLC_CONTROL2, Tx HDLC Control 2 (R/W)
    • Table 282. M13_DS2_LB_REQ_R, DS2 Loopback Request (R/W)
    • Table 283. M13_SEL_DS2_LB_R, Select DS2 Loopback (R/W)
    • Table 284. M13_RDS2_EDGE_R[1�2], Rx DS2 Edge Registers [1�2](R/W)
    • Table 285. M13_DS2_OUT_IDLE_R, DS2 Output Idle (R/W)
    • Table 286. M13_DS2_OUT_AIS_R, DS2 Output Alarm Indication Signal (R/W)
    • Table 287. M13_TDS2_EDGE_R, Tx DS2 Edge (R/W)
    • Table 288. M13_RDL_CONTROL, RDL Control (R/W)
    • Table 289. M13_PM_CNT_ACT_R, Performance Counter (RO)
    • Table 290. M13_DS3_FERR_CNT_R[1�2], DS3 F-Bit Error Registers (RO)
    • Table 291. M13_DS3_FEBE_CNT_R[1�2], DS3 Far-End Block Error Registers (RO)
    • Table 292. M13_DS3_CPERR_CNT_R[1�2], DS3 C-Bit Parity Error Registers (RO)
    • Table 293. M13_DS3_PERR_CNT_R[1�2], DS3 P-Bit Error Registers (RO)
    • Table 294. M13_DS2_PERR_CNT[7�1]_R[1�2], P-Bit Error Counter Status Registers (RO)
    • Table 295. M13_DS2_FERR_CNT[7�1]_R, F-Bit Error Counter Status Registers (RO)
    • Table 296. M13_BPV_CNT_R[1�3], Bipolar Violation Counter Status Registers (RO)
    • Table 297. M13_EXZ_CNT_R[1�3], Bipolar Violation Counter Status Registers (RO)
    • Table 298. M13_TDL_BUFFER_R, Tx Data-Link Buffer Control (R/W)
    • Table 299. M13_TDL_0DATA_R[0�63], Tx Data for Path Maintenence Data-Link Buffer 0 Registers (64 B...
    • Table 300. M13_TDL_1DATA_R[0�63], Tx Data for Path Maintenence Data-Link Buffer 1 Registers (64 B...
    • M13 Register Map
    • Table 301. Register Address Map
• suprmapr_28ch_framr.pdf
  • 28-Channel Framer Block Functional Description
    • 28-Channel Framer Introduction
    • Figure 44. Switching Application of the Super Mapper
    • Figure 45. Super Mapper Switching Configuration
    • Figure 46. Super Mapper Switching Mode for Framer in DS0 Interface (Parallel or Serial) Configura...
    • Transport Applications
    • Figure 47. Transport Application of the Super Mapper
    • Figure 48. Super Mapper Transport Configuration
    • Figure 49. Super Mapper Transport (with Intrusive Performance Monitoring) Mode (the Optional Byte...
    • Framer-to-Line Interface Unit Physical Interface
    • DS1 Transparent Framing Format
    • Figure 50. DS1 Transparent Frame Structure
    • CEPT 2.048 Basic Frame Structure Transparent Framing Format
    • Figure 51. CEPT Transparent Frame Structure
    • Receive Framer Nonalignment Mode (DS1/E1)
    • Frame Alignment Criteria
    • Table 302. Frame Alignment Criteria
    • Receive and Transmit Signaling Processor
    • Receive Signaling Per-Link Feature Provisioning
    • Table 303. Receive Signaling Link Registers 0�31 Bit Description
    • Table 304. Receive Signaling Link Registers 0�31 G-Bit and F-Bit Description
    • Table 305. Receive Signaling Link Registers 0�31 DS1/CEPT/CMI Data
    • Table 306. Receive Signaling Link Registers 0�31 Expected Data
    • Optional Receive Signaling Features Provisioned For Each Link
    • Receive Signaling Global Feature Provisioning
    • Other Receive Signaling Global Features
    • Table 307. Signaling Receive Global Register 3, Bit Definition
    • Receive Signaling Interrupts
    • Figure 52. HG Alignment Algorithm
    • Transmit Signaling Per-Link Feature Provisioning
    • Table 308. Transmit Signaling Link Registers 0�31 Bit Description
    • Table 309. Transmit Signaling Link Registers 0�31 G-Bit and F-Bit Description
    • Table 310. Transmit Signaling Link Registers 0�31 DS1/CEPT/CMI Data
    • Table 311. Transmit Signaling Link Registers 0�31 Expected Data
    • Optional Transmit Signaling Features Provisioned For Each Link
    • Transmit Signaling Global Feature Provisioning
    • Other Transmit Signaling Global Features
    • Transmit Signaling Status Registers
    • Performance Monitoring Functional Integration Into Superframer
    • Table 312. Performance Monitor Functional Descriptions
    • Performance Report Message
    • Table 313. Performance Report Message Format
    • Table 314. Performance Report Message Field Definition
    • Performance Monitoring References/Standards
    • Facility Data Link
    • Table 315. Shared Rx Stack Format for SLC-96 Frames
    • Table 316. Shared Rx FDL Stack Format for DDS Frames
    • Table 317. Shared Rx Stack Format for CEPT Frames
    • Figure 53. Rx Data Link Block Diagram
    • Figure 54. Stack Available and Stack Ready Bit Formatting
    • Table 318. Shared Tx FDL Stack Format for SLC-96 Frames
    • Table 319. Shared Tx FDL Stack Format for DDS Frames
    • Table 320. Shared Tx Stack Format for CEPT Frame
    • Figure 55. Tx Data Link Block Diagram
    • HDLC Functional Description
    • HDLC Operation
    • Table 321. HDLC Frame Format
    • Figure 56. Receive HDLC Block Diagram
    • Figure 57. Transmit HDLC FIFO Block Diagram
    • Table 322. Performance Report Message Structure
    • Framer Phase Lock Loop (PLL)
    • Figure 58. Framer PLL
    • Table 323. Clock Mode Programming for PLL Mode Device Pins
    • Figure 59. Framer Block Transmit Path Timing Selection
    • System Interface
    • Figure 60. System Loopbacks
    • Figure 61. CHI Mode of the Transmit System Interface
    • Figure 62. Nominal Concentration Highway Interface Timing
    • Figure 63. CHIDTS Mode Concentration Highway Interface Timing
    • Figure 64. Associated Signaling Mode Concentration Highway Interface Timing
    • Table 324. Associated Signalling Mode CHI 2-Byte Time-Slot Format for DS1 Frames
    • Table 325. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels
    • Table 326. Associated Signaling Mode CHI 2-Byte Time-Slot format for CEPT
    • Table 327. Programming Values for FRM_TOFF[2:0] and FRM_ROFF[2:0] when FRM_CMS = 0
    • Table 328. Programming Values for FRM_TOFF[2:0] when FRM_CMS = 1
    • Table 329. Programming Values for FRM_ROFF[2:0] when FRM_CMS = 1
    • Figure 65. TCHIDATA and RCHIDATA to CHICK Relationship with FRM_CMS = 0 (CEX = 3 and CER = 4, Res...
    • Figure 66. CHI TCHIDATA and RCHIDATA to CHICK Relationship with FRM_CMS = 1 (CEX = 3 and CER = 6,...
    • Figure 67. Parallel Bus System Interface Mode of the Transmit System Interface
    • Table 330. Parallel System Bus Interface Time-Slot Arrangement for DS1
    • Table 331. Parallel System Bus Interface Time-Slot Arrangement for E1
    • Table 332. PSB System I/O Definition
    • Figure 68. Parallel Bus System Interface Turn-Around Timing
    • Serial Multiplex Interface
    • Figure 69. Signals (6-Pin Mode)
    • Figure 70. Signals (8-Pin Mode)
    • Figure 71. Network Serial Multiplexed Interface (Single Octet)
    • Table 333. Serial ID
    • Figure 72. Network Serial Multiplexed Interface (Multiple Octets)
    • Superframer Host Interface
    • Table 334. Current Number of Global and per Link/Channel Registers for Each Block
    • Superframer Register Addressing
    • Table 335. Framer Addressing Map for the Global and Per Link/Channel Registers of the Superframer
    • Framer Global Register Descriptions
    • Table 336. FRM_SFGR1, Superframer Global Register 1 (R/W)
    • Table 337. FRM_SFGR2, Superframer Global Register 2 (R/W)
    • Table 338. FRM_SFGR3, Superframer Global Register 3 (RO)
    • Table 339. FRM_SFGSR4, Superframer Global Register 4 (R/W)
    • Arbiter (Framer) Global Registers
    • Table 340. FRM_FGR1, Framer Global Register 1 (R/W)
    • Table 341. FRM_FGR2, Framer Global Register 2 (R/W)
    • Table 342. FRM_FGR3, Framer Global Register 3 (R/W)
    • Table 343. FRM_FGR4, Framer Global Register 4 (COR)
    • Table 344. FRM_FGR5, Framer Global Register 5 (COR)
    • Performance Monitor Global Registers
    • Table 345. FRM_PMGR1_B, Performance Monitor Global Register 1_B (R/W)
    • Table 346. FRM_PMGR1, Performance Monitor Global Register 1 (COR)
    • Table 347. FRM_PMGR2, Performance Monitor Global Register 2 (COR)
    • Table 348. FRM_PMGR3, Performance Monitor Global Register 3 (R/W)
    • Table 349. FRM_PMGR4, Performance Monitor Global Register 4 (R/W)
    • Table 350. FRM_PMGR5, Performance Monitor Global Register 5�PMGR5 (R/W)
    • Table 351. FRM_PMGR6, Performance Monitor Global Register 6 (R/W)
    • Table 352. FRM_PMGR7, Performance Monitor Global Register 7 (R/W)
    • Table 353. FRM_PMGR8, Performance Monitor Global Register 8 (R/W)
    • Table 354. FRM_PMGR9, Performance Monitor Global Register 9 (R/W)
    • Table 355. FRM_PMGR10, Performance Monitor Global Register 10 (R/W)
    • Table 356. FRM_PMGR11, Performance Monitor Global Register 11 (R/W)
    • Table 357. FRM_PMGR12, Performance Monitor Global Register 12 (R/W)
    • Table 358. FRM_PMGR13, Performance Monitor Global Register 13 (R/W)
    • Table 359. FRM_PMGR14, Performance Monitor Global Register 14 (R/W)
    • Table 360. FRM_PMGR15, Performance Monitor Global Register 15 (R/W)
    • Table 361. FRM_PMGR16, Performance Monitor Global Register 16 (R/W)
    • HDLC Global Configuration and Status Registers
    • Table 362. FRM_HGR1, Transmit HDLC Global Register 1 (R/W)
    • Table 363. FRM_HGR2, Transmit HDLC Global Register 2 (R/W)
    • Table 364. FRM_HGR3, Transmit HDLC Global Register 3 (R/W)
    • Table 365. FRM_HGR4, Transmit HDLC Global Register 4 (R/W)
    • Table 366. FRM_HGR5, Transmit HDLC Global Register 5 (R/W)
    • Table 367. FRM_HGR6, Transmit HDLC Global Register 6 (R/W)
    • Table 368. FRM_HGR7, Transmit HDLC Global Register 7 (R/W)
    • Table 369. FRM_HGR8, Transmit HDLC Global Register 8 (R/W)
    • Table 370. FRM_HGR9, Transmit HDLC Global Register 9 (R/W)
    • Table 371. FRM_HGR10, Transmit HDLC Global Register 10 (R/W)
    • Table 372. FRM_HGR11, Transmit HDLC Global Register 11 (R/W)
    • Table 373. FRM_HGR12, Transmit HDLC Global Register 12 (R/W)
    • Table 374. FRM_HGR13, Transmit HDLC Global Register 13 (R/W)
    • Table 375. FRM_HGR14, Transmit HDLC Global Register 14 (R/W)
    • Table 376. FRM_HGR15, Receive HDLC Global Register 15 (R/W)
    • Table 377. FRM_HGR16, Receive HDLC Global Register 16 (R/W)
    • Table 378. FRM_HGR17, Receive HDLC Global Register 17 (R/W)
    • Table 379. FRM_HGR18, Receive HDLC Global Register 18 (R/W)
    • Table 380. FRM_HGR19, Receive HDLC Global Register 19 (R/W)
    • Table 381. FRM_HGR20, Receive HDLC Global Register 20 (R/W)
    • System Interface Global Registers
    • Table 382. FRM_SYSGR1, System Interface Global Register 1 (R/W)
    • Table 383. FRM_SYSGR2, System Interface Global Register 2 (R/W)
    • Table 384. FRM_SYSGR3, System Interface Global Register 3 (R/W)
    • Table 385. FRM_SYSGR4, System Interface Global Register 4 (R/W)
    • Table 386. FRM_SYSGR5, System Interface Global Register 5 (R/W)
    • Table 387. FRM_SYSGR6, System Interface Global Register 6 (COR)
    • Table 388. FRM_SYSGR7, System Interface Global Register 7 (COR)
    • Table 389. FRM_SYSGR8, System Interface Global Register 8 (R/W)
    • Table 390. FRM_SYSGR9, System Interface Global Register 9 (R/W)
    • Table 391. FRM_SYSGR10�FRM_SYSGR14, System Interface Global Register 10�14 (R/W)
    • Table 392. FRM_SYSGR15, System Interface Global Register 15 (COR)
    • Table 393. FRM_SYSGR16, System Interface Global Register 16 (R/W)
    • Signaling Global Registers
    • Table 394. FRM_SGR1, Receive Signaling Global Register 1 (R/W)
    • Table 395. FRM_SGR2, Receive Signaling Global Register 2 (R/W)
    • Table 396. FRM_SGR3, Receive Signaling Global Register 3 (R/W)
    • Table 397. FRM_SGR4, Receive Signaling Global Register 4 (RO)
    • Table 398. FRM_SGR5, Receive Signaling Global Register 5 (RO)
    • Table 399. FRM_SGR6, Receive Signaling Global Register 6 (COR)
    • Table 400. FRM_SGR7, Receive Signaling Global Register 7 (R/W)
    • Table 401. FRM_SGR8, Transmit Signaling Global Register 8 (R/W)
    • Frame Formatter (Transmit Framer) Global Register
    • Table 402. FRM_FFGR1, Transmit Framer Global Register 1 (R/W)
    • Facility Data Link Global Registers
    • Table 403. FRM_FDLGR1, Receive Facility Data Link Global Register 1 (R/W)
    • Table 404. FRM_FDLGR2, Transmit Facility Data Link Global Register 2 (R/W)
    • Super Mapper Framer Per Link Configuration and Status Registers
    • Table 405. Receive Path Signaling Register Addressing Map
    • Table 406. Receive Path Signaling Registers Address Indexing
    • Table 407. FRM_RSLR0�FRM_RSLR31, Receive Signaling Link Registers 0�31 (R/W)
    • Table 408. FRM_RSLR32, Receive Signaling Link Register 32 (COR)
    • Table 409. FRM_RSLR33, Receive Signaling Link Register 33 (R/W)
    • Table 410. Transmit Path Signaling Register Addressing Map
    • Table 411. Transmit Path Signaling Registers Address Indexing
    • Table 412. FRM_TSLR0�FRM_TSLR31, Transmit Signaling Link Registers 0�31 (R/W)
    • Table 413. FRM_TSLR32, Transmit Signaling Link Register 32 (R/W)
    • Table 414. FRM_TSLR33, Transmit Signaling Link Register 33 (COR)
    • Performance Monitor Per Link Registers
    • Table 415. Performance Monitor Per Link Register Addressing Map
    • Table 416. Performance Monitor Per Link Register Address Indexing
    • Table 417. FRM_PMLR1, Performance Monitor Link Register 1 (R/W)
    • Table 418. FRM_PMLR2, Performance Monitor Link Register 2 (R/W)
    • Table 419. FRM_PMLR3, Performance Monitor Link Register 3 (R/W)
    • Table 420. FRM_PMLR4, Performance Monitor Link Register 4 (COR)
    • Table 421. FRM_PMLR5, Performance Monitor Link Register 5 (COR)
    • Table 422. FRM_PMLR6, Performance Monitor Link Register 6 (COR)
    • Table 423. FRM_PMLR7, Performance Monitor Link Register 7 (COR)
    • Table 424. FRM_PMLR8, Performance Monitor Link Register 8 (COR)
    • Table 425. FRM_PMLR9, Performance Monitor Link Register 9 (COR)
    • Table 426. FRM_PMLR10, Performance Monitor Link Register 10 (COR)
    • Table 427. FRM_PMLR11, Performance Monitor Link Register 11 (COR)
    • Table 428. FRM_PMLR12, Performance Monitor Link Register 12 (COR)
    • Table 429. FRM_PMLR13, Performance Monitor Link Register 13 (COR)
    • Table 430. FRM_PMLR14, Performance Monitor Link Register 14 (COR)
    • Table 431. FRM_PMLR15, Performance Monitor Link Register 15 (COR)
    • Table 432. FRM_PMLR16, Performance Monitor Link Register 16 (COR)
    • Table 433. FRM_PMLR17, Performance Monitor Link Register 17 (COR)
    • Table 434. FRM_PMLR18, Performance Monitor Link Register 18 (COR)
    • Table 435. FRM_PMLR19, Performance Monitor Link Register 19 (COR)
    • Table 436. FRM_PMLR20, Performance Monitor Link Register 20 (COR)
    • Receive Facility Data Link Configuration and Status Registers
    • Table 437. Receive Facility Data Link Register Addressing Map
    • Table 438. Receive Path Facility Data Link Registers Address Indexing
    • Table 439. FRM_RFDLLR1�FRM_RFDLLR5, Receive FDL Link Registers 1�5 (RO)
    • Table 440. FRM_RFDLLR6, Receive FDL Link Register 6 (R/W)
    • Table 441. FRM_RFDLLR7, Receive FDL Link Register 7 (RO)
    • Table 442. FRM_RFDLLR8, Receive FDL Link Register 8 (COR)
    • Table 443. FRM_RFDLLR9, Receive FDL Link Register 9 (R/W)
    • Transmit Facility Data Link Configuration and Status Registers
    • Table 444. Transmit Facility Data Link Register Addressing Map
    • Table 445. Transmit Path Facility Data Link Registers Address Indexing
    • Table 446. FRM_TFDLLR1�FRM_TFDLR5, Transmit FDL Link Registers 1�5 (COR)
    • Table 447. FRM_TFDLLR6, Transmit FDL Link Register 6 (R/W)
    • Table 448. FRM_TFDLLR7, Transmit FDL Link Register 7 (R/W)
    • Table 449. FRM_TFDLLR8, Transmit FDL Link Register 8 (RO/COW)
    • Table 450. FRM_TFDLLR9, Transmit FDL Link Register 9 (R/W)
    • System Interface, Arbiter, and Frame Formatter Mapping
    • Table 451. System Interface, Arbiter, and Frame Formatter Link Register Addressing Map
    • Table 452. System Interface, Arbiter, and Frame Formatter Link Register Address Indexing
    • System Interface Per Link Registers
    • Table 453. FRM_SYSLR1, System Interface Link Register 1 (R/W)
    • Table 454. FRM_SYSLR2, System Interface Link Register 2 (R/W)
    • Table 455. FRM_SYSLR3�FRM_SYSLR6, System Interface Link Registers 3�6 (R/W)
    • Arbiter Framer Per Link Registers
    • Table 456. FRM_ARLR1, Arbiter Link Register 1 (R/W)
    • Table 457. FRM_ARLR2, Arbiter Link Register 2 (R/W)
    • Table 458. FRM_ARLR3, Arbiter Link Register 3 (R/W)
    • Frame Formatter Per Link Registers
    • Table 459. FRM_FFLR1, Frame Formatter Link Register 1 (R/W)
    • Table 460. FRM_FFLR2, Frame Formatter Link Register 2 (R/W)
    • Line Decoder/Encoder Per Link Registers
    • Table 461. Line Decoder Per LInk Register Addressing Map
    • Table 462. Line Decoder Per Link Registers Address Indexing
    • Table 463. Line Encoder Per Link Register Addressing Map
    • Table 464. Line Encoder Per Link Registers Address Indexing
    • Line Encoder/Decoder Per Link Registers
    • Table 465. FRM_LDLR1, Line Decoder Link Register 1 (R/W)
    • Table 466. FRM_LDLR2, Line Encoder Link Register 2 (R/W)
    • HDLC Per Channel Configuration and Status Registers
    • Table 467. HDLC Per Channel Register Addressing Map
    • Table 468. FRM_HCR1, Transmit HDLC Channel Register 1 (R/W)
    • Table 469. FRM_HCR2, Transmit HDLC Channel Register 2 (R/W)
    • Table 470. FRM_HCR3, Transmit HDLC Channel Register 3 (R/W)
    • Table 471. FRM_HCR4, Transmit HDLC Channel Register 4 (RO)
    • Table 472. FRM_HCR5, Transmit HDLC Channel Register 5 (R/W)
    • Table 473. FRM_HCR6, Transmit HDLC Channel Register 6 (WO)
    • Table 474. FRM_HCR7, Transmit HDLC Channel Register 7 (R/W)
    • Table 475. FRM_HCR8, Receive HDLC Channel Register 8 (R/W)
    • Table 476. FRM_HCR9, Receive HDLC Channel Register 9 (R/W)
    • Table 477. FRM_HCR10, Receive HDLC Channel Register 10 (R/W)
    • Table 478. FRM_HCR11, Receive HDLC Channel Register 11 (RO)
    • Table 479. FRM_HCR12, Receive HDLC Channel Register 12 (R/W)
    • Table 480. FRM_HCR13, Receive HDLC Channel Register 13 (RO)
    • Table 481. FRM_HGR14, Receive HDLC Channel Register 14 (COR)
    • 28-Channel Framer Block Register Map
    • Table 482. Framer Register Map
• suprmapr_xc.pdf
  • Cross Connect (XC) Block Functional Description
    • Cross Connect Introduction
    • Cross Connect Features
    • Cross Connect Block Diagram
    • Figure 73. Cross Connect Block Diagram
    • Figure 74. Framer and Cross Connect
    • Table 483. Multi-Function System Interface Programmable I/O
    • Table 484. DS3 Interface Programmable I/O
    • Table 485. Transmit and Receive POAC Programmable I/O
    • Cross Connect Connectivity Overview
    • Table 486. Connectivity within the Cross Connect Block
    • DS1/E1 Cross Connect
    • Figure 75. DS1 Cross Connect Interface
    • Table 487. DS1/E1 Signal Connectivity Matrix
    • Table 488. Special XC_PDATA Source IDs for Source Block = 0
    • Table 489. Special XC_SYNC Source IDs for Source Block = 0
    • Table 490. Special XC_ALCO Source IDs for Source Block = 0
    • Notes on the DS1 Cross Connect
    • Figure 76. DS1E1 External I/O to M13
    • Figure 77. Framer Line Interface Cross Connect
    • Figure 78. Framer System Interface�Parallel System Bus (PSB)
    • Table 491. Configuration of the Control Group
    • Figure 79. Framer System Interface�Concentration Highway Interface (CHI)
    • DS2 Connectivity
    • Figure 80. DS2 Cross Connect Interface
    • Figure 81. M12 Mux DS2 Output Cross Connect
    • Table 492. XC_PDATA Source IDs for LINETXDATA routing with Source Block = 111
    • Table 493. XC_PDATA Source IDs for LINETXCLK routing with Source Block = 111
    • Figure 82. M12 Demux Input DS2 Cross Connect
    • Figure 83. M23 Demux DS2 Output Cross Connect
    • Figure 84. M23 Mux DS2 Input Cross Connect
    • DS3 Connectivity
    • Figure 85. DS3 Cross Connect
    • Table 494. DS3 Connectivity
    • Figure 86. DS3 Test-Pattern Cross Connect
    • Figure 87. DS3 Basic Cross Connect
    • Figure 88. NSMI Interface Cross Connect
    • Transmit and Receive Path Overhead Access Channel I/O Configuration
    • Figure 89. TPOAC and RPOAC Cross Connect
    • Cross Connect Register Descriptions
    • Table 495. XC_ID_R, XC Global Register 1 (RO)
    • Table 496. XC_CHI_MODE1_R, XC System Interface Global Register 1 (R/W)
    • Table 497. XC_CHI_MODE2_R, XC System Interface Global Register 2 (R/W)
    • Table 498. XC_PIND_SRC[1�15], XC1 External I/O TXDATA and TXCLK Source Configuration (R/W)
    • Table 499. XC_FRP_SRC[1�14], XC1 Framer Receive Path Data Source Configuration (R/W)
    • Table 500. XC_M13_SRC[1�14 ], XC1 M13 Data Source Configuration (R/W)
    • Table 501. XC_VT_SRC[ 1�14], XC1 VT Mapper Source Configuration (R/W)
    • Table 502. XC_DJA_SRC[1�14], XC1 Digital Jitter Attenuator Source Configuration (R/W)
    • Table 503. XC_FTP_SRC[1�14], XC1 Framer Transmit Path Data Source Configuration (R/W)
    • Table 504. XC_FRS_SRC[1�14], XC1 Framer Receive System Interface Source Configuration (R/W)
    • Table 505. XC_TPM_SRC[1�4], XC1 Test-Pattern Monitor Source Configuration (R/W)
    • Table 506. XC2_M12_SRC[1�7], XC2 M12 DS2 Clock and Data Source Configuration (R/W)
    • Table 507. XC2_M23_SRC[1�7], XC2 M23 DS2 Data Source Configuration (R/W)
    • Table 508. XC2_TPM_SRC, XC2 Test-Pattern Monitor Source Configuration (R/W)
    • Table 509. XC_MISC, XC Global Register 2 (R/W)
    • Table 510. XC3_TPM_SRC, XC3 Test-Pattern Monitor Source Configuration (R/W)
    • Table 511. XC3_MDS3_SRC, XC3 DS3 Source Configuration (R/W)
    • Table 512. XC_PINS_SRC[1�15], XC1 External I/O TXSYNC Source Configuration (R/W)
    • Table 513. XC_ALCO_SRC[1�15], XC1 External I/O RXCLK Clock Out Source Configuration (R/W)
    • Cross Connect Register Map
    • Table 514. Register Address Map
• suprmapr_dja.pdf
  • Digital Jitter Attenuation Controller Functional Description
    • Introduction
    • Features
    • Figure 90. DJA Block with I/O Connections to Other Blocks in the Device
    • Functional Block Diagram of the DJA Block
    • Figure 91. Basic Functional Flow of the DJA Block
    • Digital Jitter Attenuation Controller Operation
    • Table 515. PLL Bandwidth Control Parameters
    • Table 516. 1st Order Mode Duration Control
    • Digital Jitter Attenuation Controller Register Descriptions
    • Table 517. DJA_VERSION, DJA Version and Identification (RO)
    • Table 518. DJA_EVENT1�DJA_EVENT2, Loss of Clock and Overflow/Underflow Delta (COR/COW)
    • Table 519. DJA_MASK1�DJA_MASK2, Loss of Clock and Overflow/Underflow Masks (R/W)
    • Table 520. DJA_STATE1�DJA_STATE2, Loss of Clock and VT Pointer Adjustment Indicators (R/W)
    • Table 521. DJA_E1GAINH�DJA_E1GAINL, E1 Accumulator Gain Threshold (R/W)
    • Table 522. DJA_DS1GAINH�DJA_DS1GAINL, DS1 Accumulator Gain Threshold (R/W)
    • Table 523. DJA_E1SCALE, E1 Scale Factor (R/W)
    • Table 524. DJA_DS1SCALE, DS1 Scale Factor (R/W)
    • Table 525. DJA_E1PTRH�DJA_E1PTRL, E1 First Order Loop Counter (R/W)
    • Table 526. DJA_DS1PTRH�DJA_DS1PTRL, DS1 First Order Loop Counter (R/W)
    • Table 527. DJA_DS1SELH�DJA_DS1SELL, DS1 E1 Mode Select (R/W)
    • Table 528. DJA_CLK_CTL1�DJA_CLK_CTL4, Reference Clock Rate and Edge Transitions (R/W)
    • Digital Jitter Attenuation Controller Register Map
    • Table 529. DJA Register Map
• suprmapr_tpg_d.pdf
  • Test-Pattern Generation/Detection Functional Description
    • Test-Pattern Generator Introduction
    • Block Diagram
    • Figure 92. TPG Block Interface Block Diagram
    • Functional Descriptions
    • Table 530. TPG Framing Controls (TPG_FRAMEx = 1)
    • Table 531. TPG Test-Pattern Sequences
    • TPM Framing Acquisition and Synchronization
    • Table 532. TPM Interrupts
    • Microprocessor Interface
    • Test-Pattern Generation/Detection Register Descriptions
    • Table 533. TPG_ID, Status Register (RO)
    • Table 534. TPG_ISRC_OOFD, Delta Register (RO)
    • Table 535. TPG_ISRC_OOSD, Delta Register (RO)
    • Table 536. TPG_ISRC_BERE, Event Register (RO)
    • Table 537. TPG_ISRC_FERE, Event Register (RO)
    • Table 538. TPG_ISRC_BPVE, Event Register (RO)
    • Table 539. TPG_ISRC_AISD, Delta Register (RO)
    • Table 540. TPG_ISRC_CRCE, Event Register (RO)
    • Table 541. TPG_IMSK_OOFD, Register (R/W)
    • Table 542. TPG_IMSK_OOSD, Register (R/W)
    • Table 543. TPG_IMSK_BERE, Register (R/W)
    • Table 544. TPG_IMSK_FERE, Register (R/W)
    • Table 545. TPG_IMSK_BPV, Register (R/W)
    • Table 546. TPG_IMSK_AISD, Register (R/W)
    • Table 547. TPG_IMSK_CRCE, Register (R/W)
    • Table 548. TPG_VAL_OOF, Register (RO)
    • Table 549. TPG_VAL_OOS, Register (RO)
    • Table 550. TPG_VAL_AIS, Register (RO)
    • Table 551. TPG_VAL_FER, Register (RO)
    • Table 552. TPG_VAL_CRCE, Register (RO)
    • Table 553. TPG_BER_INSRT, Register (R/W)
    • Table 554. TPG_FER_INSRT, Register (R/W)
    • Table 555. TPG_CRCE_INSRT, Register (R/W)
    • Table 556. TPG_ESFDL_TX, Register (R/W)
    • Table 557. TPG_E1SA_TX12, Register (R/W)
    • Table 558. TPG_E1SA_TX34, Register (R/W)
    • Table 559. TPG_CONFIG0, Register (R/W)
    • Table 560. TPG_CONFIG2, Register (R/W)
    • Table 561. TPG_CONFIG4, Register (R/W)
    • Table 562. TPG_CONFIG5, Register (R/W)
    • Table 563. TPG_USER, Register (R/W)
    • Table 564. TPM_USER, Register (R/W)
    • Table 565. TPG_BERCNT0, Register (RO)
    • Table 566. TPG_BERCNT2, Register (RO)
    • Table 567. TPG_BERCNT4, Register (RO)
    • Table 568. TPG_BERCNT5, Register (RO)
    • Table 569. TPM_ESFDL_RX, Register (RO)
    • Table 570. TPM_E1SA_RX12, Register (RO)
    • Table 571. TPM_E1SA_RX34, Register (RO)
    • Test-Pattern Generation/Detection Register Map
    • Table 572. Test-Pattern Generation/Detection Register Map
• suprmapr_clkg_pwmgt_mtnc.pdf
  • Clocking and Power Management Philosophy
    • Figure 93. Clock And Power Shut Down Diagram
  • Maintenance Philosophy
    • Table 573. Maintenance Tasks Supported by the SMPR
• suprmapr_abm_elc_tim_ord.pdf
  • Electrical Characteristics
    • Absolute Maximum Ratings
    • Handling Precautions
    • Operating Conditions
    • Table 574. Recommended Operating Conditions.
    • Logic Interface Characteristics
    • Table 575. Logic Interface Characteristics
    • Figure 94. Single-Ended Input Specification
    • LVDS Interface Characteristics
    • Table 576. LVDS Interface Characteristics
  • Timing Characteristics
    • TMUX Block Timing
    • Table 577. High-Speed Input Clock Specifications*
    • Figure 95. Generic Clock Timing
    • Table 578. Output Clock Specifications
    • Table 579. Input Timing Specifications
    • Figure 96. Generic Interface Data Timing
    • Table 580. Output Timing Specifications
    • DS3 Timing
    • Table 581. DS3 Input Clock Specifications
    • Table 582. Input Timing Specifications
    • Table 583. Output Timing Specifications
    • M13 Timing
    • Table 584. M13 Clock Specifications
    • Table 585. Input Timing Specifications
    • Table 586. Output Timing Specifications
    • VT Mapper Timing
    • Table 587. VT Mapper Receive Path Overhead Detailed Timing
    • Figure 97. VT Mapper Transmit Path Overhead Detailed Timing
    • Figure 98. VT Mapper Receive Path Overhead Detailed Timing
    • Concentration Highway (CHI) Timing
    • Table 588. CHI Transmit Timing Characteristics
    • Figure 99. CHI Transmit I/O Timing
    • Table 589. CHI Receive Timing Characteristics
    • Figure 100. CHI Receive I/O Timing
    • Parallel System Bus Timing
    • Table 590. PSB Interface Transmit Timing Characteristics
    • Figure 101. Parallel System Bus Interface Transmit I/O Timing
    • Table 591. PSB Interface Receive Timing Characteristics
    • Figure 102. Parallel System Bus Interface Receive I/O Timing
    • NSMI Timing Mode 1 (6 pin)
    • Table 592. NSMI (Mode 1) Input Clock Specifications
    • Table 593. Input Timing Specifications
    • Table 594. Output Timing Specifications
    • SMI Timing Mode 2 (8 pin)
    • Table 595. SMI (Mode 2) Input Clock Specifications
    • Table 596. Input Timing Specifications
    • Table 597. Output Timing Specifications
    • Framer Only Mode Timing
    • Table 598. Framer Only Mode Clock Specifications
    • Table 599. Framer Mode Only Input Timing Specifications
    • Table 600. Framer Mode Only Output Timing Specifications
    • Framer�LIU Mode Timing
    • Table 601. Framer�LIU Mode Clock Specifications
    • Table 602. Framer�LIU Mode Input Timing Specifications
    • Table 603. Framer�LIU Mode Output Timing Specifications
    • Microprocessor Interface Timing
    • Figure 103. Microprocessor Interface Synchronous Write Cycle (MPMODE (Pin AD17) = 1)
    • Table 604. Microprocessor Interface Synchronous Write Cycle Specifications
    • Figure 104. Microprocessor Interface Synchronous Read Cycle (MPMODE (Pin AD17) = 1)
    • Table 605. Microprocessor Interface Synchronous Read Cycle Specifications
    • Figure 105. Microprocessor Interface Asynchronous Write Cycle Description (MPMODE (Pin AC18) = 0)
    • Table 606. Microprocessor Interface Asynchronous Write Cycle Specifications
    • Figure 106. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin AC18) = 0)
    • Table 607. Microprocessor Interface Asynchronous Read Cycle Specifications
    • General Purpose Interface Timing
    • Table 608. Input Timing Specifications
    • Table 609. Output Timing Specifications
  • Outline Diagram
    • 456-Pin PBGA
  • Ordering Information