Product Brief
May 2001
TTRN0112G
12.5 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
Features
I
Supports OC-192/STM-64 (standard and multiple
FEC rates) and 10GE data rates. Allows for two
separate frequency ranges of operation:
-- 9.95328 GHz through 10.70922 GHz
-- 12.0 GHz through 12.5 GHz
I
Supports clockless data transfer mode.
I
Supports forward directional clocking for parallel
transfer of input data with 311 MHz or 622 MHz
clocks.
I
Supports contradirectional clocking for parallel
transfer of input data using a 622 MHz output
clock.
I
Allows a 155.52 MHz or 622.08 MHz reference
clock using common PLL loop components.
I
Additional 12 Gbits/s CML serial data output for
system loop back.
I
Supports 12 GHz clock output for clocked laser
driver applications.
I
Single 3.3 V supply.
I
LVDS 622.08 Mbits/s signal I/Os.
I
CMOS I/O compatible with LVTTL signaling.
I
Power dissipation as low as 1.35 W.
I
Available in a 198-pin BGA package.
I
Jitter generation/transfer compliant with the follow-
ing:
-- Telcordia Technologies * GR-1377CORE
-- ITU-T G.825
-- ITU-T G.958
I
Fully compatible with the optical interface forum
specification OIF99.102.5.
Applications
I
SONET/SDH optical modules.
I
SONET/SDH line origination equipment.
* Telcordia Technologies is a registered trademark of Telecordia
Technologies, Inc..
I
SONET/SDH add/drop multiplexers.
I
SONET/SDH cross connects.
I
SONET/SDH test equipment.
I
Digital video transmission.
Description
The Agere Systems Inc. TTRN0112G device is
designed as a 16:1 multiplexer that accepts 16 differ-
ential LVDS data inputs and a divided-by-64 or
divided-by-16 reference clock and generates a CML
12.5 Gbits/s clock and data output. Both forward
directional and contradirectional clocking schemes
are supported for transferring data across the parallel
interface. When contraclocking is used, the
TTRN0112G provides one of four phases of a
divided-by-16 clock output back up stream to the
data chip. The device also supports a clockless par-
allel data transfer mode. The TTRN0112G can be
operated at either the frequency range of
9.95328 GHz through 10.70922 GHz or the range of
12.0 GHz through 12.5 GHz. The higher rate is pin
selectable.
Functional Overview
The TTRN0110G performs the clock synthesis and
16:1 data multiplexing operations required to support
10 Gbits/s
OC-192/STM-64 applications compliant
with Telcordia Technologies and ITU standards. Par-
allel 622 Mbits/s data is clocked into an input register.
Both forward directional and contra directional clock-
ing modes are supported as well as a clockless data
transfer mode. The data is then multiplexed into a
10 Gbits/s serial stream and output buffered for inter-
facing to a laser driver. A 10 GHz clock is synthe-
sized from a reference clock and is used to retime
the serial data. The 10 GHz clock is optionally avail-
able as an output.
The OC-192/STM-64 data rate of 9.95328 Gbits/s is typically
approximated as 10 Gbits/s in this document when referring to
the application rate. Similarly, the low-speed parallel interface
data rate of 622.08 Mbits/s is typically approximated as
622 Mbits/s. The exact frequencies are used only when neces-
sary for clarity.
2
Agere Systems Inc.
Product Brief
May 2001
12.5 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
TTRN0112G
Functional Overview
(continued)
FEC Rate Support
TTRN addition under functional overview will support the rates of 9.95328 GHz through the rate of 10.70922 GHz
(FECN = 1) and higher FEC rates of 12.0 GHz through 12.5 GHz (FECN = 0). The FECN pin selects between
VCO ranges of 9.95328 GHz through 10.70922 GHz and 12.0 GHz through 12.5 GHz. All frequency-based speci-
fications are to be multiplied by (rate/9.95328 GHz) when operating at higher frequency rates. All time-based
specifications, with the exception of electrical signal rise and fall times, are to be multiplied by (9.95328 GHz/rate).
At non-standard FEC rates, the reference clock would need to be applied at (rate/9.95328 GHz) 155.52 MHz or
(rate/9.95328 GHz) 622.08 MHz and the paralled data interface would operate at
(rate/9.95328 GHz) 622.08 MHz.
Block Diagram
Note: Diagram is representative of device functionality and conceptual signal flow. Internal implementation details may be different than shown.
0356 (F)
Figure 1. Functional Block Diagram of TTRN0112G
D0P
D0N
D1P
D1N
D15P
D15N
OVERFLOW
EXTCNTR
CLKMOD[1:0]
PICLKP
PICLKN
ENCK155N
CK155P
CK155N
CK622P
CK622N
PHADJ[1:0]
REFFREQ
REFCLKP
REFCLKN
LCKLOSSN
ACQUISITION
INDICATOR
MANUAL
PHASE
ADJUST
DIVIDE
BY 4
DECODE
TIMING GENERATION
INP
U
T
PHASE/
FREQ.
DETECTOR
CHARGE
PUMP
DIVIDE
BY 16
REGI
STE
R
DAT
A
BUFF
ER
16:
1
M
U
L
T
I
P
LE
XER
DATA
RETIME
TO DIGITAL LOGIC
RESETN
ENLBDN
LBDP
LBDN
D10GP
D10GN
INVDATN
ENCK10G
CK10GP
CK10GN
RREFCML
RREFVCO
RREFLVDS
TESTN
TSTCKP
FECN
0
1
LFP
LFN
VCO
TEST
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright 2001 Agere Systems Inc.
All Rights Reserved
Printed in U.S.A.
May 2001
PB01-126HSPL
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