Hardware Design Guide, Revision 1

November 2, 2005

TSI-8
8K x 8K Time-Slot Interchanger

1 Introduction

The last issue of this data sheet was May, 2002 (This docu-
ment was previously labeled Advance Information.) A
change history is included in

9 Change History on page 25

Red change bars have been installed on all text, figures,
and tables that were added or changed. All changes to the
text are highlighted in red. Changes within figures, and the
figure title itself, are highlighted in red, if feasible. Formatting
or grammatical changes have not been highlighted. Deleted
sections, paragraphs, figures, or tables will be specifically
mentioned.

If the reader displays this document in Acrobat Reader

clicking on any blue entry in the text will bring the reader to
that reference point.

This document describes the hardware interfaces to the
Agere Systems Inc. TSI-8 device. Information relevant to
the use of the device in a board design is covered. Ball de-
scriptions, dc electrical characteristics, timing diagrams, ac
timing parameters, packaging, and operating conditions are
included.

1.1 Related Documents

More information on the TSI-8 is contained in the following
documents:

TSI-8 Product Description

TSI-8 Register Description

TSI-8 Systems Design Guide

2 Description

2.1 Block Diagram and High-Level Interface Definition

Figure 2-1. Block Diagram and High-Level Interface Definition

TEST ACCESS

PORT

READ ADDRESS

COUNTER

CONNECTION

STORE

WRITE ADDRESS

COUNTER

DATA

STORE

MICROPROCESSOR

INTERFACE

TRANSMIT

CHI

TEST PATTERN

GENERATOR

TEST PATTERN

MONITOR

8K X 8K

SWITCH

FABRIC

CLOCK

GENERATOR

RECEIVE

CHI

TRANSLATION

TABLE LOOKUP

Table of Contents

Contents

Page

Contents

Page

Agere Systems Inc.

TSI-8

Hardware Design Guide, Revision 1

8K x 8K Time-Slot Interchanger

November 2, 2005

1 Introduction .............................................................. 1

1.1 Related Documents .......................................... 1

2 Description ............................................................... 1

2.1 Block Diagram and High-Level Interface

Definition .......................................................... 1

3 Ball Information ........................................................ 3

3.1 Ball Diagram ..................................................... 3
3.2 Package Ball Assignments ............................... 4
3.3 Ball Types ......................................................... 8
3.4 Ball Definitions .................................................. 8

4 Absolute Maximum Ratings ................................... 11

4.1 Handling Precautions ..................................... 11
4.2 ESD Tolerance ............................................... 11
4.3 Package Thermal Characteristics ................... 11
4.4 Recommended Operating Conditions ............ 12

5 dc Electrical Characteristics .................................. 13
6 Timing Diagrams and ac Characteristics ............... 14
7 Outline Diagrams ................................................... 24
8 Ordering Information .............................................. 25
9 Change History ...................................................... 25

Figures

Page

Figure 2-1. Block Diagram and High-Level Interface

Definition ................................................... 1

Figure 3-1. Package Diagram (Top View) ................... 3
Figure 6-1. CHICLK Timing Specifications ................ 14
Figure 6-2. MPUCLK Timing Specifications .............. 14
Figure 6-3. ac Timing Specification ........................... 15
Figure 6-4. CHI Interface Timing ............................... 15
Figure 6-5. Typical Receive CHI Timing with 16.384

Mbits/s Data and 16.384 MHz CHICLK... 16

Figure 6-6. Transmit CHI Timing with 16.384 Mbits/s

Data and 16.384 MHz CHICLK ............... 16

Figure 6-7. Typical Receive CHI Timing with 8.192

Mbits/s Data and 16.384 MHz CHICLK... 17

Figure 6-8. Transmit CHI Timing with 8.192 Mbits/s

Data and 16.384 MHz CHICLK ............... 17

Figure 6-9. Typical Receive CHI Timing with 4.096

Mbits/s Data and 16.384 MHz CHICLK... 18

Figure 6-10. Transmit CHI Timing with 4.096 Mbits/s

Data and 16.384 MHz CHICLK ............... 18

Figure 6-11. Typical Receive CHI Timing with 2.048

Mbits/s Data and 16.384 MHz CHICLK... 19

Figure 6-12. Transmit CHI Timing with 2.048 Mbits/s

Data and 16.384 MHz CHICLK ............... 19

Figure 6-13. Typical Receive CHI Timing with 8.192

Mbits/s Data and 8.192 MHz CHICLK.....20

Figure 6-14. Transmit CHI Timing with 8.192 Mbits/s

Data and 8.192 MHz CHICLK .................20

Figure 6-15. CHI 3-State Output Control ...................21
Figure 6-16. Microprocessor Port Timing--

Read Cycle.............................................22

Figure 6-17. Microprocessor Port Timing--

Write Cycle.............................................23

Tables

Page

Table 3-1. Package Ball Assignments in Signal Name

Order ...........................................................4

Table 3-2. Package Ball Assignments in Ball Number

Order (Top View) .........................................6

Table 3-3. Package Ball Assignments in Ball Number

Order (Bottom View) (continued).................7

Table 3-4. Ball Types ...................................................8
Table 3-5. Timing Port..................................................8
Table 3-6. Transmit and Receive Concentration

Highways.....................................................8

Table 3-7. Control Port.................................................9
Table 3-8. Initialization and Test Access......................9
Table 3-9. Power Balls...............................................10
Table 4-1. Absolute Maximum Ratings ...................... 11
Table 4-2. ESD Tolerance.......................................... 11
Table 4-3. Power Consumption ................................. 11
Table 4-4. Operating Conditions ................................12
Table 5-1. CMOS Inputs ............................................13
Table 5-2. CMOS Outputs .........................................13
Table 5-3. CMOS Bidirectionals (Excluding

TXD[31:00]) ...............................................13

Table 5-4. CMOS Bidirectionals (TXD[31:00]) ...........13
Table 6-1. CHICLK Timing Specifications ..................14
Table 6-2. MPUCLK Timing Specifications ................14
Table 6-3. CMOS Output ac Timing Specification * ...15
Table 6-4. CHI Interface Timing .................................15
Table 6-5. CHI 3-State Output Control.......................21
Table 6-6. Microprocessor Port Timing--

Read Cycle................................................22

Table 6-7. Microprocessor Port Timing--

Write Cycle23

Table 8-1. Ordering Information.................................25

TSI-8

Hardware Design Guide, Revision 1

8K x 8K Time-Slot Interchanger

November 2, 2005

4
4

Agere Systems Inc.

3.2 Package Ball Assignments

Table 3-1. Package Ball Assignments in Signal Name Order

Symbol

Ball Symbol

Ball

Symbol

Ball

Symbol

Ball

Symbol

Ball

ADDR00

A17

DATA13

P18

RXD11

TXD08

DD15

D13

ADDR01

A16

DATA14

P17

RXD12

TXD09

DD15

D14

ADDR02

A15

DATA15

P16

RXD13

TXD10

DD15

ADDR03

A14

H17

RXD14

TXD11

DD15

ADDR04

A13

FSYNC

T11

RXD15

TXD12

DD15

ADDR05

A12

HIZ

R17

RXD16

TXD13

DD15

ADDR06

A11

INT

H16

RXD17

V10

TXD14

DD15

ADDR07

A10

MPUCLK

K15

RXD18

U10

TXD15

DD15

ADDR08

PAR0

R18

RXD19

V11

TXD16

DD15

R11

ADDR09

PAR1

P15

RXD20

U11

TXD17

DD15

R12

ADDR10

R/W

J17

RXD21

V12

TXD18

DD33

ADDR11

RESET

H15

RXD22

U12

TXD19

DD33

C10

ADDR12

RSV1

F17

RXD23

V13

TXD20

DD33

C17

ADDR13

RSV2

F18

RXD24

U13

TXD21

DD33

ADDR14

RSV3

E15

RXD25

V14

TXD22

DD33

D10

ADDR15

RSV4

E16

RXD26

U14

TXD23

DD33

J16

RSV5

E17

RXD27

V15

TXD24

DD33

CHICLK

R16

RSV6

D17

RXD28

U15

TXD25

DD33

F15

CKSPD0

E18

RSV7

B18

RXD29

T15

TXD26

DD33

CKSPD1

D16

RSV8

C18

RXD30

V16

TXD27

DD33

J18

RSV9

D18

RXD31

U16

TXD28

DD33

K16

DATA00

K18

RSV10

T18

TCK

G17

TXD29

DD33

DATA01

K17

RSV11

V17

TDI

G16

TXD30

DD33

DATA02

L18

RXD00

TDO

G18

TXD31

DD33

DATA03

L17

RXD01

TMS

G15

DD15

DD33

DATA04

L16

RXD02

TRSTN

H18

DD15

DD33

DATA05

M18

RXD03

TXD00

DD15

DD33

T10

DATA06

M17

RXD04

TXD01

DD15

C12

DD33

T14

DATA07

M16

RXD05

TXD02

DD15

C13

DD33

T17

DATA08

M15

RXD06

TXD03

DD15

C14

DDPLL

R14

DATA09

N18

RXD07

TXD04

DD15

DATA10

N17

RXD08

TXD05

DD15

PRE

DATA11

N16

RXD09

TXD06

DD15

DATA12

N15

RXD10

TXD07

DD15

D12

A18

Hardware Design Guide, Revision 1

TSI-8

November 2, 2005

8K x 8K Time-Slot Interchanger

Agere Systems Inc.

Table 3-1. Package Ball Assignments in Signal Name Order (continued)

Symbol

Ball

Symbol

Ball

Symbol

Ball

Symbol Ball

C11

J10

C15

J11

C16

J15

R10

R15

D11

K10

T12

B10

D15

K11

T13

B11

T16

B12

B13

F16

U17

B14

L10

U18

B15

L11

B16

H10

L15

V18

B17

H11

SSPLL

R13

Agere Systems Inc.

TSI-8

Hardware Design Guide, Revision 1

8K x 8K Time-Slot Interchanger

November 2, 2005

Table 3-2. Package Ball Assignments in Ball Number Order

(Top View) (continued)

VSS ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR09 ADDR08 ADDR07 ADDR06 ADDR05 ADDR04 ADDR03 ADDR02 ADDR01 ADDR00

VSS

B TXD00

VSS

RSV7

C TXD02 TXD01

VSS

VDD15 VDD15 VDD15

VSS

VDD33 VDD33

VSS

VDD15 VDD15 VDD15

VSS

VDD33

RSV8

D TXD04 TXD03

VSS

VDD15 VDD15 VDD15

VSS

VDD33 VDD33

VSS

VDD15 VDD15 VDD15

VSS

CKSPD1

RSV6

RSV9

E TXD06 TXD05

VDD33

VSS

RSV3

RSV4

RSV5

CKSPD0

F TXD08 TXD07

VDD33

VSS

VDD33

VSS

RSV1

RSV2

G TXD11 TXD10

TXD09

VDD15

TMS

TDI

TCK

TDO

H TXD13 TXD12

VDD33 VDD15

VSS

RESET

INT

TRSTN

J TXD15 TXD14

VDD33

VSS

R/W

K TXD16 TXD17

VIO

VSS

MPUCLK VDD33

DATA01 DATA00

L TXD18 TXD19

VSS

VDD15

VSS

DATA04 DATA03 DATA02

M TXD20 TXD21

VSS

VDD15

DATA08

DATA07 DATA06 DATA05

N TXD22 TXD23

TXD24

VSS

DATA12

DATA11 DATA10 DATA09

P TXD25 TXD26

VDD33

VSS

PAR1

DATA15 DATA14 DATA13

R TXD27 TXD28

VDD33

VSS

VDD15 VDD15

VSS

VDD15 VDD15 VSSPLL VDDPLL

VSS

CHICLK

HIZ

PAR0

T TXD29 TXD30

VSS

VPRE

VDD33 VDD33 RXD09 RXD12 VDD33 VDD33 FSYNC

VSS

VDD33

RXD29

VSS

VDD33

RSV10

U TXD31

VSS

RXD01 RXD03 RXD05 RXD07 RXD10 RXD13 RXD15 RXD18 RXD20 RXD22 RXD24 RXD26

RXD28

RXD31

VSS

RXD00 RXD02 RXD04 RXD06 RXD08

RXD11

RXD14 RXD16 RXD17 RXD19 RXD21 RXD23 RXD25

RXD27

RXD30

RSV11

VSS

Hardware Design Guide, Revision 1

TSI-8

November 2, 2005

8K x 8K Time-Slot Interchanger

Agere Systems Inc.

Table 3-3. Package Ball Assignments in Ball Number Order

(Bottom View)

VSS

ADDR00 ADDR01 ADDR02 ADDR03 ADDR04 ADDR05 ADDR06 ADDR07 ADDR08 ADDR09 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 VSS

RSV7

VSS

TXD00

RSV8

VDD33

VSS

VDD15

VSS

VDD33 VDD33

VSS

VDD15 VDD15 VDD15

VSS

TXD01 TXD02

RSV9

RSV6

CKSPD1

VSS

VDD15

VSS

VDD33 VDD33

VSS

VDD15 VDD15 VDD15

VSS

TXD03 TXD04

E CKSPD0

RSV5

RSV4

RSV3

VSS

VDD33 TXD05 TXD06

RSV2

RSV1

VSS

VDD33

VSS

VDD33 TXD07 TXD08

TDO

TCK

TDI

TMS

VDD15 TXD09 TXD10 TXD11

TRSTN

INT

RESET

VSS

VDD15 VDD33 TXD12 TXD13

R/W

VSS

VDD33 TXD14 TXD15

K DATA00

DATA01

VDD33

MPUCLK

VSS

VIO

TXD17 TXD16

DATA02

DATA03

DATA04

VSS

VDD15

VSS

TXD19 TXD18

M DATA05

DATA06

DATA07

DATA08

VDD15

VSS

TXD21 TXD20

N DATA09

DATA10

DATA11

DATA12

VSS

TXD24 TXD23 TXD22

P DATA13

DATA14

DATA15

PAR1

VSS

VDD33 TXD26 TXD25

PAR0

HIZ

CHICLK

VSS

VDDPLL VSSPLL VDD15 VDD15

VSS

VDD15 VDD15

VSS

VDD33 TXD28 TXD27

RSV10

VDD33

VSS

RXD29

VDD33

VSS

FSYNC VDD33 VDD33 RXD12 RXD09 VDD33 VDD33

VPRE

VSS

TXD30 TXD29

VSS

RXD31

RXD28

RXD26

RXD24

RXD22 RXD20 RXD18 RXD15 RXD13 RXD10 RXD07 RXD05 RXD03 RXD01

VSS

TXD31

VSS

RSV11

RXD30

RXD27

RXD25

RXD23

RXD21 RXD19 RXD17 RXD16 RXD14 RXD11 RXD08 RXD06 RXD04 RXD02 RXD00

VSS

TSI-8

Hardware Design Guide, Revision 1

8K x 8K Time-Slot Interchanger

November 2, 2005

8
8

Agere Systems Inc.

3.3 Ball Types

This table describes each type of input, output, and I/O ball used on the TSI-8.

The dc switching and other electrical characteristics are specified later in this document.

3.4 Ball Definitions

This section describes the function of each of the device balls. The balls are listed by ball name. Package ball numbers are
listed in

Table 3-1

of this document. The static parameters (drive currents, switching thresholds, etc.) for each ball type (in-

put, output, etc.) are described in

Table 5-1

through

Table 5-4

Table 3-4. Ball Types

Type Label

Description

CMOS input, TTL switching thresholds.

I pd

CMOS input, TTL switching thresholds with internal pull-down resistor.

I pu

CMOS input, TTL switching thresholds with internal pull-up resistor.

CMOS output.

O od

Open drain output.

I/O

Bidirectional ball; CMOS input with TTL switching thresholds and CMOS output.

None

Analog inputs for external resistors, capacitors, voltage references, etc.

Power and ground.

Table 3-5. Timing Port

Ball Name Type

Name/Description

FSYNC

Frame Synchronization. This signal indicates the beginning of a 125 µs frame event (8 kHz). The
FSYNC ball can be programmed as active-low or active-high, but its polarity is the same for all concen-
tration highway interfaces (CHI). FSYNC can be sampled on either the positive or negative edge of
CHICLK. Time-slot numbers and bit offsets for each CHI are assigned relative to the detection of
FSYNC.

CHICLK

Clock. This is the master synchronous clock for the transmit and receive concentration highways. The
frequency can be 8.192 MHz or 16.384 MHz. It must be at least as fast as the highest CHI data rate.

CKSPD0

Clock Speed. Static control input that should be tied according to the frequency of CHICLK. If CHICLK
is connected to an 8.192 MHz source, CKSPD0 should be tied to V

. If CHICLK is connected to a

16.384 MHz source, CKSPD0 should be tied to V

DD33

CKSPD1

I pd Clock Speed. Reserved, leave disconnected. 20 k

pull-down resistor.

Table 3-6. Transmit and Receive Concentration Highways

Ball Name Type

Name/Description

RXD[31:00] I pd Receive Data [31:00]. Receive concentration highways. These are serial, synchronous data streams

which may be individually programmed to operate at 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s, or
16.384 Mbits/s. They carry 32, 64, 128, or 256 time slots (respectively) each occupying eight contiguous
bits. 20 k

pull-down resistor.

TXD[31:00] I/O Transmit Data [31:00]. Normally these are output concentration highway data streams with data rate

options identical to the RXD inputs. These balls can be configured to operate as bidirectional multiplex
ports such as H.110. Further information can be found in the system design guide. 20 k

resistor

connected to V

PRE

Hardware Design Guide, Revision 1

TSI-8

November 2, 2005

8K x 8K Time-Slot Interchanger

Agere Systems Inc.

Table 3-7. Control Port

Ball Name Type

Name/Description

MPUCLK

Processor Clock. This clock is used to sample address, data, and control signals from the
microprocessor. This clock must be within the range of 0 MHz--66 MHz. Required for operation.

Chip Select. Active-low chip select. This input is held low for the duration of any read or write access
to the TSI-8. Required for operation.

Address Strobe. Active-low address strobe that is one MPUCLK cycle wide at the start of a
microprocessor access cycle to the TSI-8. This is used to initiate a microprocessor access. Required
for operation.

R/W

Read/Write. Cycle selection. R/W is set high during a read cycle, or set low for a write cycle.
Required for operation.

ADDR[15:00] I pu Address [15:00]. ADDR[15] is the most significant bit and ADDR[00] is the least significant bit for

addressing all the internal registers during microprocessor access cycles. All addresses are
16-bit word addresses; hence, in a typical application ADDR[00] of the TSI-8 device would be
connected to address bit 1 of a byte addressable system address bus. Required for operation. 200
k

pull-up resistor.

Note: The TSI-8 is little-endian; the least significant byte is stored in the lowest address and the most

significant byte is stored in the highest address. Care must be exercised in connection to
microprocessors that use big-endian byte ordering.

DATA[15:00]

I/O Data [15:00]. Data bus for all transfers between the microprocessor and the internal registers. The

balls are inputs during write cycles and outputs during read cycles. DATA[15] is the most significant
bit, and DATA[00] is the least significant bit. Required for operation.

PAR[1:0]

I/O Control Port Parity [1:0]. Byte-wide parity bits for data. PAR[1] is the parity for DATA[15:8], and

PAR[0] is the parity for DATA[7:0]. The parity sense (even or odd) is application programmable via a
register bit in the TSI-8. Not required for operation.

Data Transfer Acknowledge. Active-low for one MPUCLK cycle. Indicates that data has been
written during write cycles or that data is valid during read cycles. High impedance when CS is a 1
and driven when CS is 0. Required for operation.

INT

O od Interrupt. This output is asserted low to indicate that an interrupt condition has occurred. This signal

remains active-low until the interrupt status register has been cleared or masked.

Table 3-8. Initialization and Test Access

Ball Name Type

Name/Description

RESET

I pu Reset. Global reset, active-low. Initializes all internal registers to their default state. The reset occurs

asynchronously, but RESET should be held low for at least two CHICLK periods. 20 k

pull-up resistor.

TCK

I pu Test Clock. This signal provides timing for the boundary scan and test access port (TAP) controller.

Should be static except during boundary-scan testing. 20 k

pull-up resistor.

TDI

I pu Test Data In. Data input for the boundary scan. Sampled on the rising edge of TCK. 20 k

pull-up

resistor.

TMS

I pu Test Mode Select (Active-Low). Controls boundary-scan test operations. TMS is sampled on the rising

edge of TCK. 20 k

pull-up resistor.

TRSTN

I pd Test Reset (Active-Low). This signal is an asynchronous reset for the TAP controller. 20 k

pull-down

resistor.

TDO

Test Data Out. Updated on the falling edge of TCK. The TDO output is high impedance except when
scanning out test data.

HIZ

I pu Output Enable. All output and bidrectional buffers will be high impedance when this input is low unless

boundary scan is enabled (TRSTN = 1). 20 k

pull-up resistor.

RSV[11:1]

-- Reserved [11:1]. These balls are used by Agere Systems during the manufacturing process. They must

be left unconnected.

TSI-8

Hardware Design Guide, Revision 1

8K x 8K Time-Slot Interchanger

November 2, 2005

Agere Systems Inc.

Table 3-9. Power Balls

Symbol Type

Name/Description

DD33

I/O Power. Power supply balls for the I/O pads (3.3 V ± 5%).

DD15

Core Power. Power supply balls for the core (1.5 V ± 5%).

Ground. Common ground balls for 3.3 V and 1.5 V supplies.

PRE

Precharge. Precharge voltage to support H.110 hot insertion on TXD[31:00]. If the device is used in an
H.110 hot insertion applications, the signal should be connected to backplane early voltage; otherwise
connect this signal to ground.

PCI Buffer Voltage Select. For an H.110 application using TXD[31:00] in a 5 V signaling environment,
connect this signal to 5 V. For an H.110 application using TXD[31:00] in a 3 V signaling environment,
connect this signal to V

DD33

. For all other applications, connect this signal to V

DD33

DDPLL

PLL Power. 1.5 V power supply for the internal phase-locked loop. Must include local 0.01 µF capacitor to
V

SSPLL

PLL Ground. Isolated ground for the internal phase-locked loop.

Hardware Design Guide, Revision 1

TSI-8

November 2, 2005

8K x 8K Time-Slot Interchanger

Agere Systems Inc.

4 Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress
ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the
operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect
device reliability.

4.1 Handling Precautions

Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be
taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere
employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to deter-
mine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit param-
eters used in each of the models, as defined by JEDEC's JESD22-A114 (HBM) and JESD22-C101 (CDM) standards.

4.2 ESD Tolerance

4.3 Package Thermal Characteristics

= 24.0 °C/W.

Table 4-1. Absolute Maximum Ratings

Parameter

Min

Max

Unit

Supply Voltage (V

DD33

)

0.5

4.2

Supply Voltage (V

DD15

)

0.5

1.8

Input Voltage:

TXD[31:00]
All Other Inputs

0.5
0.3

5.5

DD33

+ 0.3

Storage Temperature

125

°C

Junction Temperature

125

°C

Table 4-2. ESD Tolerance

Device

Voltage

Type

TSI-8

2,000 V

HBM (human-body model)

500 V

CDM (charged-device model)

Table 4-3. Power Consumption

Supply Voltage

Typ

*MPUCLK = 66 MHz, CHICLK = 16.384 MHz, TA = 25 °C, all CHIs active, all outputs loaded with 50 pF.

Max

DD33

100 mW at 3.3 V

150 mW at 3.47 V

DD15

275 mW at 1.5 V

325 mW at 1.6 V

Hardware Design Guide, Revision 1

TSI-8

November 2, 2005

8K x 8K Time-Slot Interchanger

Agere Systems Inc.

5 dc Electrical Characteristics

This section describes the static parameters associated with all the ball types used in the TSI-8 device.

* Excludes current due to pull-up or pull-down resistors.

Table 5-1. CMOS Inputs

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Input Leakage Current

< V

DD33

µA

High-Input Voltage

2.0

DD33

+ 0.3

Low-Input Voltage

0.3

0.8

Input Capacitance

2.5

Table 5-2. CMOS Outputs

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Output Voltage Low

= 10 mA

0.4

Output Voltage High

= 10 mA

2.4

Output Current Low

Output Current High

Output Capacitance

HIZ Output Leakage Current

µA

Table 5-3. CMOS Bidirectionals (Excluding TXD[31:00])

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Leakage Current

< V

DD33

µA

High-Input Voltage

2.0

DD33

+ 0.3

Low-Input Voltage

0.3

0.8

Biput Capacitance

5.0

Output Voltage Low

= 10 mA

0.4

Output Voltage High

= 10 mA

2.4

Table 5-4. CMOS Bidirectionals (TXD[31:00])

Parameter

Symbol

Conditions

Min

Max

Unit

Leakage Current

< V

DD33

µA

High-Input Voltage

= 5.0 V

= 3.3 V

2.0

0.5 V

DD33

5.5

DD33

+ 0.5

Low-Input Voltage

= 5.0 V

= 3.3 V

0.5
0.5

0.8

0.3 V

DD33

Biput Capacitance

Output Voltage Low

= 1.5 mA, V

= 3.3 V

= 6.0 mA, V

= 5.0 V

--
--

0.1 V

DD33

0.55

Output Voltage High

= 0.5 mA, V

= 3.3 V

= 2.0 mA, V

= 5.0 V

0.9 V

DD33

2.4

--
--

Positive-Going Threshold

1.2

2.0

Negative-Going Threshold

0.6

1.6

Hysteresis (V

)

HYS

0.4

TSI-8

Hardware Design Guide, Revision 1

8K x 8K Time-Slot Interchanger

November 2, 2005

Agere Systems Inc.

6 Timing Diagrams and ac Characteristics

Figure 6-1 and Figure 6-2 describe the timing specifications for the input clocks on the TSI-8.

Figure 6-1. CHICLK Timing Specifications

* V

to V

or V

to V

Figure 6-2. MPUCLK Timing Specifications

* V

to V

or V

to V

Table 6-1. CHICLK Timing Specifications

Parameter

Description

Min

Typ

Max

Unit

CHICLK Rise Time

CHICLK Width (8.192 MHz)*

48.84

73.24

CHICLK Width (16.384 MHz)*

24.42

36.62

CHICLK Fall Time

CHICLK Period (8.192 MHz)

122.07

CHICLK Period (16.384 MHz)

61.03

Table 6-2. MPUCLK Timing Specifications

Parameter

Description

Min

Typ

Max

Unit

MPUCLK Rise Time

MPUCLK Width*

6.06

MPUCLK Fall Time

MPUCLK Period

15.2

DD33

50%

VDD33

VIL

VIH

VIL

50%

Hardware Design Guide, Revision 1

TSI-8

November 2, 2005

8K x 8K Time-Slot Interchanger

Agere Systems Inc.

Figure 6-3 shows the ac timing specifications for the

CMOS outputs

on the device.

Figure 6-3. ac Timing Specification

* Test load = 50 pF (total).

Note: This figure assumes TSI-8 is programmed to sample FSYNC on rising edge of CHICLK.

Figure 6-4. CHI Interface Timing

* Applies if Driver_Enable_Control = 01. For Driver_Enable_Control = 11 refer to

Figure 6-15 CHI 3-State Output Control on page 21

Table 6-3. CMOS Output ac Timing Specification *

Parameter

Description

Min

Typ

Max

Unit

Rise Time (20%--80%)

1.5

Fall Time (80%--20%)

1.5

Table 6-4. CHI Interface Timing

Parameter

Description

Min

Max

Unit

FSYNC Setup Time to Active CHICLK Edge

FSYNC Hold Time from Active CHICLK Edge

RXD Setup to Active CHICLK Edge

RXD Hold Time from Active CHICLK Edge

TXD High Z to Data Valid

TXD Propagation Delay from Active CHICLK Edge

Transmit Data High Impedance*

20%

80 %

20 %

80 %

t10

TXD

CHICLK

RXD

FSYNC

TSI-8

Hardware Design Guide, Revision 1

8K x 8K Time-Slot Interchanger

November 2, 2005

Agere Systems Inc.

All timing specifications also apply under the following conditions:

If FS is active-low.

If the falling edge of CHICLK is specified as the active edge.

At all RXD and TXD rates (16.384 Mbits/s, 8.192 Mbits/s, 4.096 Mbits/s, or 2.048 Mbits/s) with a CHICLK frequency of
16.384 MHz or 8.192 MHz.

Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-5. Typical Receive CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK

Notes:
1/4 bit offset not valid with 16 Mbits/s data.
For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and sampled by the rising edge of the CHICLK.

Figure 6-6. Transmit CHI Timing with 16.384 Mbits/s Data and 16.384 MHz CHICLK

FSYNC

CHICLK

w/ 0 offset

data sampled

w/ ¼ bit offset

data sampled

w/ ½ bit offset

data sampled

w/ ¾ bit offset

data sampled

w/ bit offset = 1

data sampled

w/ 2¾ bit offset

data sampled

w/ bit offset = 7

data sampled

w/ TS offset = 1,

bit offset = 0

TS254 B6

TS254 B7

TS255 B0

TS0 B1

TS0 B0

TS255 B1

TS255 B2

TS255 B3

TS255 B4

TS0 B4

TS0 B5

TS254 B7

TS255 B0

TS255 B1

TS255 B2

TS255 B3

TS255 B4

TS255 B5

TS255 B6

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS255 B6

TS255 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

TS255 B6

TS255 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

TS255 B5

TS255 B3

TS255 B4

TS255 B5

TS255 B6

TS255 B7

TS255 B6

TS255 B7

TS255 B6

TS255 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS255 B6

TS255 B7

TS255 B5

TS255 B7

TS0 B 0

w/ TS offset = 13,

bit offset = 3¼

TS242 B3

TS242 B4

TS242 B5

TS243 B4

TS243 B5

TS242 B6

TS242 B7

TS243 B0

TS243 B1

TS255 B7

TS0 B0

TS243 B2

TS243 B3

TS0 B5

TS0 B6

TS0 B3

TS0 B4

TS0 B1

TS0 B2

TS0 B3

TS0 B7

TS1 B0

TS0 B1

TS0 B2

w/ TS offset = 255,

bit offset = 7¾

TS255 B6

TS0 B4

TS0 B0

TS255 B6

TS255 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

FSYNC

CHICLK

w/ 0 offset

w/ ½ bit offset

w/ bit offset = 1

w/ TS offset = 255,

bit offset = 7½

TS255 B6

TS255 B7

TS0 B0

w/ TS offset = 1,

bit offset = 0

TS0 B2

TS0 B3

TS0 B4

TS254 B5

TS254 B6

TS254 B7

TS255 B0

TS255 B4

TS255 B5

TS0 B3

TS0 B4

TS255 B1

TS255 B2

TS255 B3

TS0 B0

TS0 B1

TS255 B4

TS255 B5

TS255 B6

TS255 B7

TS0 B0

TS0 B3

TS0 B4

TS0 B5

TS0 B1

TS0 B2

TS0 B1

TS0 B2

TS255 B6

TS255 B7

TS255 B5

TS255 B6

TS255 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

Hardware Design Guide, Revision 1

TSI-8

November 2, 2005

8K x 8K Time-Slot Interchanger

Agere Systems Inc.

Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-7. Typical Receive CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK

Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-8. Transmit CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK

FSYNC

CHICLK

w/ 0 offset

data sampled

w/ ¼ bit offset

data sampled

w/ ½ bit offset

data sampled

w/ ¾ bit offset

data sampled

w/ bit offset = 1

data sampled

w/ 2¾ bit offset

data sampled

w/ bit offset = 7

data sampled

TS0 B2

TS0 B3

TS0 B4

w/ TS offset = 127,

bit offset = 7¾

TS 127 B7

TS0 B0

TS0 B1

TS127 B2

TS127 B3

TS127 B4

w/ TS offset = 13,

bit offset = 3¼

TS114 B4

TS114 B5

TS114 B6

TS114 B7

TS115 B0

TS115 B1

w/ TS offset = 1,

bit offset = 0

TS126 B7

TS127 B0

TS127 B1

TS127 B4

TS127 B5

TS 127 B4

TS127 B5

TS127 B0

TS127 B1

TS127 B2

TS127 B3

TS127 B6

TS127 B7

TS0 B2

TS0 B3

TS0 B2

TS0 B3

TS0 B0

TS0 B1

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS 127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B3

TS0 B4

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

FSYNC

CHICLK

w/ 0 offset

w/ ¼ bit offset

w/ ½ bit offset

w/ bit offset = 1

TS 127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B2

TS0 B3

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS 127 B5

TS127 B6

TS127 B7

TS0 B0

w/ TS offset = 1,

bit offset = 0

TS127 B7

TS0 B0

TS0 B1

w/ TS offset = 127,

bit offset = 7¾

TS 126 B6

TS126 B7

TS127 B0

TS127 B1

TS0 B2

TS0 B3

TS0 B1

TS0 B2

TS127 B2

TS127 B3

TS0 B3

TSI-8

Hardware Design Guide, Revision 1

8K x 8K Time-Slot Interchanger

November 2, 2005

Agere Systems Inc.

Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-9. Typical Receive CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK

Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-10. Transmit CHI Timing with 4.096 Mbits/s Data and 16.384 MHz CHICLK

FSYNC

CHICLK

w/ 0 offset

data sampled

w/ ¼ bit offset

data sampled

w/ ½ bit offset

data sampled

w/ ¾ bit offset

data sampled

w/ bit offset = 1

data sampled

w/ 2¾ bit offset

data sampled

w/ bit offset = 7

data sampled

TS50 B7

w/ TS offset = 63,

bit offset = 7¾

TS0 B0

TS0 B1

TS0 B2

w/ TS offset = 13,

bit offset = 3¼

TS50 B4

TS50 B5

TS50 B6

w/ TS offset = 1,

bit offset = 0

TS63 B0

TS63 B1

TS63 B2

TS63 B5

TS63 B6

TS63 B7

TS63 B1

TS63 B2

TS63 B3

TS63 B7

TS0 B0

TS0 B1

TS63 B7

TS0 B0

TS0 B1

TS63 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B0

TS0 B1

TS0 B2

TS63 B7

TS0 B0

TS0 B1

TS0 B2

FSYNC

CHICLK

w/ 0 offset

w/ ¼ bit offset

w/ ½ bit offset

w/ bit offset = 1

w/ TS offset = 63,

bit offset = 7¾

TS62 B7

TS63 B0

TS63 B1

w/ TS offset = 1,

bit offset = 0

TS63 B6

TS63 B7

TS0 B0

TS63 B7

TS0 B0

TS0 B1

TS0 B2

TS63 B6

TS63 B7

TS0 B0

TS0 B1

TS63 B7

TS0 B0

TS0 B1

TS63 B7

TS0 B0

TS0 B1

Hardware Design Guide, Revision 1

TSI-8

November 2, 2005

8K x 8K Time-Slot Interchanger

Agere Systems Inc.

Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-11. Typical Receive CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK

Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-12. Transmit CHI Timing with 2.048 Mbits/s Data and 16.384 MHz CHICLK

FSYNC

CHICLK

w/ 0 offset

data sampled

w/ ¼ bit offset

data sampled

w/ ½ bit offset

data sampled

w/ ¾ bit offset

data sampled

w/ bit offset = 1

data sampled

w/ 2¾ bit offset

data sampled

w/ bit offset = 7

data sampled

w/ TS offset = 31,

bit offset = 7¾

TS0 B0

TS0 B1

TS0

w/ TS offset = 1,

bit offset = 0

TS31 B0

TS31 B1

w/ TS offset = 13,

bit offset = 3¼

TS18 B5

TS18 B6

TS31 B5

TS31 B6

TS31

TS31 B1

TS31 B2

TS31 B7

TS0 B0

TS0

TS31 B7

TS0 B0

TS0 B1

TS0 B0

TS0 B1

TS31 B7

TS0 B0

TS0 B1

FSYNC

CHICLK

w/ 0 offset

w/ ¼ bit offset

w/ ½ bit offset

w/ bit offset = 1

TS30 B7

TS31 B0

TS31 B01

w/ TS offset = 1,

bit offset = 0

TS31 B7

TS0 B0

TS0 B1

w/ TS offset = 31,

bit offset = 7¾

TS31 B7

TS0 B0

TS31 B6

TS31 B7

TS0 B0

TS31 B7

TS0 B0

TS0 B1

TS31 B7

TS0 B0

TSI-8

Hardware Design Guide, Revision 1

8K x 8K Time-Slot Interchanger

November 2, 2005

Agere Systems Inc.

Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-13. Typical Receive CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK

Notes:
1/4 bit offset not valid with 8 MHz data and 8 MHz clock.
For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.

Figure 6-14. Transmit CHI Timing with 8.192 Mbits/s Data and 8.192 MHz CHICLK

FSYNC

CHICLK

w/ 0 offset

data sampled

w/ ¼ bit offset

data sampled

w/ ½ bit offset

data sampled

w/ ¾ bit offset

data sampled

w/ bit offset = 1

data sampled

w/ 2¾ bit offset

data sampled

w/ bit offset = 7

data sampled

TS0 B5

TS0 B6

TS0 B7

TS1 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

w/ TS offset = 127,

bit offset = 7¾

TS127 B6

TS127 B7

TS0 B0

TS115 B2

TS115 B3

TS115 B4

TS115 B5

TS114 B6

TS114 B7

TS115 B0

TS115 B1

w/ TS offset = 13,

bit offset = 3¼

TS114 B3

TS114 B4

TS114 B5

TS127 B5

TS127 B6

TS127 B7

TS0 B0

TS0 B 0

TS0 B1

w/ TS offset = 1,

bit offset = 0

TS126 B6

TS126 B7

TS127 B0

TS127 B1

TS127 B2

TS127 B3

TS127 B4

TS0 B3

TS126 B7

TS127 B0

TS127 B1

TS127 B2

TS127 B3

TS127 B4

TS127 B5

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS127 B3

TS127 B4

TS127 B5

TS127 B6

TS0 B5

TS127 B5

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS127 B5

TS127 B6

TS127 B7

TS0 B0

TS0 B2

TS0 B3

TS0 B4

TS0 B5

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

FSYNC

CHICLK

w/ 0 offset

w/ ½ bit offset

w/ bit offset = 1

TS127 B5

w/ TS offset = 127,

bit offset = 7½

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

TS0 B4

w/ TS offset = 1,

bit offset = 0

TS126 B5

TS126 B6

TS126 B7

TS127 B0

TS127 B1

TS127 B2

TS127 B3

TS127 B4

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS127 B4

TS127 B5

TS127 B6

TS127 B7

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS127 B5

TS127 B6

TS127 B7

TS0 B0

TS127 B5

TS127 B6

TS127 B7

TS0 B0

TS0 B1

TS0 B2

TS0 B3

TS0 B4

TS0 B5

Hardware Design Guide, Revision 1

TSI-8

November 2, 2005

8K x 8K Time-Slot Interchanger

Agere Systems Inc.

Figure 6-15. CHI 3-State Output Control

Table 6-5. CHI 3-State Output Control

Control in the table below refers to bits [6:4] in the Transmit_CHI_Global_Configuration register (0x0C84). This only applies
if bits 13 and 12 of the corresponding Transmit_CHI_Control register (0x0C00--0x0C3E) are set to 11. See the TSI-8 Reg-
ister Description document.

Parameter Control

Reference Point

* Like edge is the reference edge (rising or falling) as defined by the Transmit_Clock_Edge bit in the Transmit_CHI_Global_Configuration (0x0C84) regis-

ter. See the TSI-8 Register Description document for further details.

Min

Max

Unit

000

After Previous Like Edge in 16 MHz

001

After Previous Like Edge in 16 MHz

010

After Previous Like Edge in 16 MHz

011

After Previous Like Edge in 16 MHz

000

After Previous Opposite Edge in 8 MHz

001

After Previous Opposite Edge in 8 MHz

010

After Previous Opposite Edge in 8 MHz

011

After Previous Opposite Edge in 8 MHz

100

After Previous Like Edge (8 MHz mode only)

111

120

101

After Previous Like Edge (8 MHz mode only)

105

114

110

After Previous Like Edge (8 MHz mode only)

108

111

After Previous Like Edge (8 MHz mode only)

102

CHICLK

16.384 MHz

TXD

16.384 Mbits/s

CHICLK

8.192 MHz

TXD

8.192 Mbits/s

CHICLK

8.192 MHz

TXD

8.192 Mbits/s

Hardware Design Guide, Revision 1

TSI-8

November 2, 2005

8K x 8K Time-Slot Interchanger

Agere Systems Inc.

Figure 6-17. Microprocessor Port Timing--Write Cycle

Note: Posted writes follow the same timing shown in Figure 6-17 and Table 6-7. A posted write may return a DT prior to the

device completing the write cycle. This allows the microprocessor to continue operation while the TSI-8 completes the
write.

Table 6-7. Microprocessor Port Timing--Write Cycle

Parameter

Description

Min

Max

Unit

Address Setup

Address Hold

Chip Select Setup

Chip Select Hold

Address Strobe Setup

Address Strobe Hold

R/W Setup

R/W Hold

Data Setup

Data Hold

DT High-Impedance to Valid

DT Clock to Out

DT Valid to High-Impedance

MPUCLK

DATA[15:00]

PAR[1:0]

ADDR[15:00]

R/W

November 2, 2005

DS02-122SWCH-1 (Replaces DS02-122SWCH)

Hardware Design Guide, Revision 1

TSI-8

November 2, 2005

8K x 8K Time-Slot Interchanger

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Agere, Agere Systems, and the Agere logo are registered trademarks of Agere Systems Inc.

For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:

Home: http://www.agere.com Sales: http://www.agere.com/sales

E-MAIL:

docmaster@agere.com

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EUROPE:

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8 Ordering Information

9 Change History

page 1

, updated Figure 2-1.

page 15

deleted 2 sentences at the beginning of the page. (All timing parameters are referenced to V

IHmin

and V

max.

The reference signal polarity may be inverted for some timing parameters.)

page 15

, updated Figure 6-3, ac Timing Specification.

page 15

, updated Table 6-3. CMOS Output ac Timing Specification * .

page 15

under Table 6-4 eliminated the following sentence: All timing specifications are with respect to VIHmin and

VILmax as shown in Figure 5.

page 21

deleted footnote under Table 6-5 and clarified the remaining footnote.

page 22

deleted the footnote under Table 6-6

page 23

deleted the footnote under Table 6-7

On page 26, changed the part numbers.

Adobe Acrobat and Acrobat Reader are registered trademarks of Adobe Systems Incorporated.

Table 8-1. Ordering Information

Device

Part Number

Ball Count

Package

Comcode

TSI-8

TTSI008321BL-2-DB

240

PBGAM1

700046829

L-TTSI008321BL-2-DB

700078759*

* Pb-free/RoHS.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TTSI008321BL-2-DB

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TTSI008321BL-2-DB