1-120
Low Input Current Logic Gate
Optocouplers
Technical Data
HCPL-2200
HCPL-2219
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.
Features
2.5 kV/
s Minimum Common
Mode Rejection (CMR) at
V
CM
= 400 V (HCPL-2219)
Compatible with LSTTL,
TTL, and CMOS Logic
Wide V
CC
Range (4.5 to 20 V)
2.5 Mbd Guaranteed over
Temperature
Low Input Current (1.6 mA)
Three State Output (No
Pullup Resistor Required)
Guaranteed Performance
from 0
C to 85
C
Hysteresis
Safety Approval
UL Recognized -2500 V rms
for 1 minute
CSA Approved
VDE 0884 Approved with
V
IORM
= 630 V
peak
(HCPL-2219 Option 060
Only)
MIL-STD-1772 Version
Available (HCPL-5200/1)
Applications
Isolation of High Speed
Logic Systems
Computer-Peripheral
Interfaces
Microprocessor System
Interfaces
Functional Diagram
Ground Loop Elimination
Pulse Transformer
Replacement
Isolated Buss Driver
High Speed Line Receiver
Description
The HCPL-2200/2219 are
optically coupled logic gates that
combine a GaAsP LED and an
integrated high gain photo
detector. The detector has a three
state output stage and has a
detector threshold with hysteresis.
The three state output eliminates
the need for a pullup resistor and
allows for direct drive of data
busses. The hysteresis provides
differential mode noise immunity
and eliminates the potential for
output signal chatter.
A superior internal shield on the
HCPL-2219 guarantees common
mode transient immunity of
2.5 kV/
s at a common mode
voltage of 400 volts.
A 0.1
F bypass capacitor must be connected between pins 5 and 8.
7
1
2
3
4
5
6
8
NC
ANODE
CATHODE
NC
GND
VCC
VO
SHIELD
TRUTH TABLE
(POSITIVE LOGIC)
LED
ON
OFF
ON
OFF
ENABLE
H
H
L
L
VE
OUTPUT
Z
Z
H
L
5965-3596E
H
1-121
IF
SHIELD
VF
VCC
VO
GND
ICC
IO
+
2
3
8
5
VE
7
6
IE
The Electrical and Switching
Characteristics of the HCPL-
2200/2219 are guaranteed over
the temperature range of 0
C to
85
C and a V
CC
range of 4.5 volts
to 20 volts. Low I
F
and wide V
CC
range allow compatibility with
TTL, LSTTL, and CMOS logic and
result in lower power consump-
tion compared to other high
speed optocouplers. Logic signals
are transmitted with a typical
propagation delay of 160 nsec.
Selection Guide
Small-Outline
Widebody
Minimum CMR
8-Pin DIP (300 Mil)
SO-8
(400 Mil)
Hermetic
Input On-
Single
Dual
Single
Single
Single and Dual
dV/dt
V
CM
Current
Channel
Channel
Channel
Channel
Channel
(V/
s)
(V)
(mA)
Package
Package
Package
Package
Packages
1,000
50
1.6
HCPL-2200
[1]
HCPL-0201
HCNW2201
HCPL-2201
HCPL-2202
1.8
HCPL-2231
2,500
400
1.6
HCPL-2219
[1]
5,000
[2]
300
[2]
1.6
HCPL-2211
HCPL-0211
HCNW2211
HCPL-2212
1.8
HCPL-2232
1,000
50
2.0
HCPL-52XX
HCPL-62XX
Notes:
1. HCPL-2200/2219 devices include output enable/disable functionality.
2. Minimum CMR of 10 kV/
s with V
CM
= 1000 V can be achieved with input current, I
F
, of 5 mA.
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-2219#XXX
060 = VDE 0884 V
IORM
= 630 Vpeak Option*
300 = Gull Wing Surface Mount Option
500 = Tape and Reel Packaging Option
Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor for
information.
*For HCPL-2219 only.
Schematic
The HCPL-2200/2219 are useful
for isolating high speed logic
interfaces, buffering of input and
output lines, and implementing
isolated line receivers in high
noise environments.
1-122
1.080 0.320
(0.043 0.013)
2.54 0.25
(0.100 0.010)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
*MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
5 TYP.
0.254
+ 0.076
- 0.051
(0.010
+ 0.003)
- 0.002)
7.62 0.25
(0.300 0.010)
6.35 0.25
(0.250 0.010)
9.65 0.25
(0.380 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
HP XXXXZ
YYWW
DATE CODE
5
6
7
8
4
3
2
1
OPTION CODE*
UL
RECOGNITION
UR
TYPE NUMBER
Package Outline Drawings
8-Pin DIP Package
8-Pin DIP Package with Gull Wing Surface Mount Option 300
0.635 0.25
(0.025 0.010)
12 NOM.
9.65 0.25
(0.380 0.010)
0.635 0.130
(0.025 0.005)
7.62 0.25
(0.300 0.010)
5
6
7
8
4
3
2
1
9.65 0.25
(0.380 0.010)
6.350 0.25
(0.250 0.010)
1.016 (0.040)
1.194 (0.047)
1.194 (0.047)
1.778 (0.070)
9.398 (0.370)
9.906 (0.390)
4.826
(0.190)
TYP.
0.381 (0.015)
0.635 (0.025)
PAD LOCATION (FOR REFERENCE ONLY)
1.080 0.320
(0.043 0.013)
4.19
(0.165)
MAX.
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.254
+ 0.076
- 0.051
(0.010
+ 0.003)
- 0.002)
1-123
Note: Use of nonchlorine activated fluxes is highly recommended.
Maximum Solder Reflow Thermal Profile
240
T = 115C, 0.3C/SEC
0
T = 100C, 1.5C/SEC
T = 145C, 1C/SEC
TIME MINUTES
TEMPERATURE C
220
200
180
160
140
120
100
80
60
40
20
0
260
1
2
3
4
5
6
7
8
9
10
11
12
Regulatory Information
The HCPL-2200/2219 have been
approved by the following
organizations:
UL
Recognized under UL 1577,
Component Recognition
Program, File E55361.
CSA
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
VDE
Approved according to VDE
0884/06.92. (HCPL-2219 Option
060 Only)
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Min. External Air Gap
L(IO1)
7.1
mm
Measured from input terminals to output terminals,
(External Clearance)
shortest distance through air.
Min. External
L(IO2)
7.4
mm
Measured from input terminals to output terminals,
Tracking Path
shortest distance path along body.
(External Creepage)
Minimum Internal
0.08
mm
Through insulation distance, conductor to conductor,
Plastic Gap
usually the direct distance between the photoemitter
(Internal Clearance)
and photodetector inside the optocoupler cavity.
Tracking Resistance
CTI
200
V
DIN IEC 112/VDE 0303 Part 1
(Comparative
Tracking Index)
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
1-124
VDE 0884 Insulation Related Characteristics (HCPL-2219 OPTION 060 ONLY)
Description
Symbol
Characteristic
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage
300 V rms
I-IV
for rated mains voltage
450 V rms
I-III
Climatic Classification
55/85/21
Pollution Degree (DIN VDE 0110/1.89)
2
Maximum Working Insulation Voltage
V
IORM
630
V
peak
Input to Output Test Voltage, Method b*
V
IORM
x 1.875 = V
PR
, 100% Production Test with t
m
= 1 sec,
V
PR
1181
V
peak
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
V
IORM
x 1.5 = V
PR
, Type and sample test,
V
PR
945
V
peak
t
m
= 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, t
ini
= 10 sec)
V
IOTM
6000
V
peak
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 12, Thermal Derating curve.)
Case Temperature
T
S
175
C
Input Current
I
S,INPUT
230
mA
Output Power
P
S,OUTPUT
600
mW
Insulation Resistance at T
S
, V
IO
= 500 V
R
S
10
9
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, (VDE 0884), for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
1-125
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Power Supply Voltage
V
CC
4.5
20
V
Enable Voltage High
V
EH
2.0
20
V
Enable Voltage Low
V
EL
0
0.8
V
Forward Input Current
I
F(ON)
1.6*
5
mA
Forward Input Current
I
F(OFF)
0.1
mA
Operating Temperature
T
A
0
85
[1]
C
Fan Out
N
4
TTL Loads
*The initial switching threshold is 1.6 mA or less. It is recommended that 2.2 mA be
used to permit at least a 20% CTR degradation guardband.
Absolute Maximum Ratings
(No Derating Required up to 70
C)
Parameter
Symbol
Min.
Max.
Units
Note
Storage Temperature
T
S
-55
125
C
Operating Temperature
T
A
-40
85
C
1
Average Forward Input Current
I
F(AVG)
10
mA
Peak Transient Input Current
I
F(TRAN)
1.0
A
(
1
s Pulse Width, 300 pps)
Reverse Input Voltage
V
R
5
V
Average Output Current
I
O
25
mA
Supply Voltage
V
CC
0
20
V
Three State Enable Voltage
V
E
-0.5
20
V
Output Voltage
V
O
-0.5
20
V
Total Package Power Dissipation
P
T
210
mW
1
Lead Solder Temperature
260
C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile
See Package Outline Drawings section
1-126
Electrical Specifications
For 0
C
T
A
[1]
85
C, 4.5 V
V
CC
20 V, 1.6 mA
I
F(ON)
5 mA, 2.0 V
V
EH
20 V,
0.0 V
V
EL
0.8 V, 0 mA
I
F(OFF)
0.1 mA. All Typicals at T
A
= 25
C, V
CC
= 5 V, I
F(ON)
= 3 mA unless
otherwise specified. See Note 7.
Parameter
Sym.
Min.
Typ. Max. Units
Test Conditions
Fig.
Note
Logic Low
V
OL
0.5
V
I
OL
= 6.4 mA (4 TTL Loads)
1
Output Voltage
Logic High
V
OH
2.4
*
V
I
OH
= -2.6 mA
*V
OH
= V
CC
- 2.1 V
2
Output Voltage
Output Leakage
I
OHH
100
A
V
O
= 5.5 V
I
F
= 5 mA
Current (V
OUT
> V
CC
)
V
CC
= 4.5 V
Logic High Enable
V
EH
2.0
V
Voltage
Logic Low Enable
V
EL
0.8
V
Voltage
Logic High Enable
I
EH
20
A
V
EN
= 2.7 V
Current
Logic Low Enable
I
EL
-0.32
mA
V
EN
= 0.4 V
Current
Logic Low Supply
I
CCL
I
F
= 0 mA
Current
I
O
= Open
V
E
= Don't Care
Logic High Supply
I
CCH
I
F
= 5 mA
Current
I
O
= Open
V
E
= Don't Care
High Impedance
I
OZL
-20
A
V
O
= 0.4 V
V
EN
= 2 V,
I
F
= 5 mA
I
OZH
20
A
V
O
= 2.4 V
V
EN
= 2 V,
100
A
V
O
= 5.5 V
500
A
V
O
= 20 V
Logic Low Short
I
OSL
2
Circuit Output
Current
Logic High Short
I
OSH
I
F
= 5 mA,
2
Circuit Output
V
O
= GND
Current
Input Current
I
HYS
0.12
mA
V
CC
= 5 V
3
Hysteresis
Input Forward
V
F
1.5
1.7
V
T
A
= 25
C
I
F
= 5 mA
4
1.75
Input Reverse
BV
R
5
V
I
R
= 10
A
Breakdown Voltage
Input Diode
V
F
-1.7
mV/
C I
F
= 5 mA
Temperature
T
A
Coefficient
Input Capacitance
C
IN
60
pF
f = 1 MHz, V
F
= 0 V, Pins 2 and 3
mA
V
O
= V
CC
= 5.5 V I
F
= 0 mA
25
500
A
V
O
= 20 V
100
A
V
EN
= 5.5 V
250
A
V
EN
= 20 V
0.004
6.0
mA
V
CC
= 5.5 V
4.5
5.25
6.0
mA
V
CC
= 20 V
4.5
mA
V
CC
= 5.5 V
2.7
3.1
State Output
Current
mA
V
O
= V
CC
= 20 V
40
mA
V
CC
= 5.5 V
-10
mA
V
CC
= 20 V
-25
Voltage
7.5
mA
V
CC
= 20 V
I
F
= 5 mA
1-127
Switching Specifications (AC)
For 0
C
T
A
[1]
85
C, 4.5 V
V
CC
20 V, 1.6 mA
I
F(ON)
5 mA, 0.0 mA
I
F(OFF)
0.1 mA.
All Typicals at T
A
= 25
C, V
CC
= 5 V, I
F(ON)
= 3 mA unless otherwise specified.
Parameter
Sym.
Min.
Typ. Max. Units
Test Conditions
Fig.
Note
Propagation Delay Time to
t
PHL
210
ns
Without Peaking Capacitor
5, 6
4, 5
160
300
With Peaking Capacitor
Propagation Delay Time to
t
PLH
170
ns
Without Peaking Capacitor
5, 6
4, 5
115
300
With Peaking Capacitor
Output Enable Time to
t
PZH
25
ns
7, 9
Logic High
Output Enable Time to
t
PZL
28
ns
7, 8
Logic Low
Output Disable Time from
t
PHZ
105
ns
7, 9
Logic High
Output Disable Time from
t
PLZ
60
ns
7, 8
Logic Low
Output Rise Time (10-90%)
t
r
55
ns
5, 10
Output Fall Time (90-10%)
t
f
15
ns
5, 10
Parameter
Sym.
Device
Min.
Units
Test Conditions
Fig.
Note
Logic High
|CM
H
|
I
F
= 1.6 mA
11
6
Common Mode
V
CC
= 5 V
Transient
T
A
= 25
C
Immunity
Logic Low
|CM
L
|
V
F
= 0 V
11
6
Common Mode
V
CC
= 5 V
Transient
T
A
= 25
C
Immunity
Logic Low Output Level
Logic High Output Level
HCPL-2200
1,000
V/
s
|V
CM
| = 50 V
HCPL-2219
2,500
V/
s
|V
CM
| = 400 V
HCPL-2200
1,000
V/
s
|V
CM
| = 50 V
HCPL-2219
2,500
V/
s
|V
CM
| = 400 V
Package Characteristics
Parameter
Sym.
Min.
Typ.
Max. Units
Test Conditions
Fig.
Note
Input-Output Momentary
V
ISO
2500
V rms
RH
50%, t = 1 min.,
3, 8
Withstand Voltage*
T
A
= 25
C
Input-Output Resistance
R
I-O
10
12
V
I-O
= 500 VDC
3
Input-Output Capacitance
C
I-O
0.6
pF
f = 1 MHz, V
I-O
= 0 VDC
3
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level
safety specification or HP Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage," publication number 5963-2203E.
1-128
IF (ON)
50 % IF (ON)
0 mA
tPLH
tPHL
VOH
1.3 V
VOL
INPUT IF
OUTPUT
VO
Figure 2. Typical Logic High Output
Current vs. Temperature.
Figure 3. Output Voltage vs. Forward
Input Current.
Figure 4. Typical Input Diode Forward
Characteristic.
Figure 1. Typical Logic Low Output
Voltage vs. Temperature.
Notes:
1. Derate total package power dissipa-
tion, P
T
, linearly above 70
C free air
temperature at a rate of 4.5 mW/
C.
2. Duration of output short circuit time
should not exceed 10 ms.
3. Device considered a two-terminal
device: pins 1, 2, 3, and 4 shorted
together and pins 5, 6, 7, and 8
shorted together.
4. The t
PLH
propagation delay is
measured from the 50% point on the
leading edge of the input pulse to the
1.3 V point on the leading edge of the
output pulse. The t
PHL
propagation
delay is measured from the 50% point
on the trailing edge of the input pulse
to the 1.3 V point on the trailing edge
of the output pulse.
5. When the peaking capacitor is omitted,
propagation delay times may increase
by 100 ns.
6. CM
L
is the maximum rate of rise of the
common mode voltage that can be
sustained with the output voltage in the
logic low state (V
O
< 0.8 V). CM
H
is
the maximum rate of fall of the
common mode voltage that can be
I OH
HIGH LEVEL OUTPUT CURRENT mA
-60
-8
TA TEMPERATURE C
100
0
-20
-5
20
60
-40
0
40
80
-3
-1
-6
VCC = 4.5 V
IF = 5 mA
-7
-4
-2
VO = 2.7 V
VO = 2.4 V
I F
FORWARD CURRENT mA
1.1
0.001
VF FORWARD VOLTAGE V
1.0
1000
1.3
0.01
1.5
1.2
1.4
0.1
TA = 25 C
10
100
IF
+
VF
sustained with the output voltage in the
logic high state (V
O
> 2.0 V).
7. Use of a 0.1
F bypass capacitor
connected between pins 5 and 8 is
recommended.
8. In accordance with UL1577, each
optocoupler is proof tested by applying
an insulation test voltage
3000 V rms
for one second (leakage detection
current limit, I
I-O
5
A). This test is
performed before the 100% production
test for partial discharge (Method b)
shown in the VDE 0884 Insulation
Characteristics Table, if applicable.
Figure 5. Test Circuit for t
PLH
, t
PHL
, t
r
, and t
f
.
V
OL
LOW LEVEL OUTPUT VOLTAGE V
-60
0
TA TEMPERATURE C
100
1.0
-20
0.4
20
60
-40
0
40
80
0.6
0.8
0.2
VCC = 4.5 V
IF = 0 mA
VO = 6.4 mA
0.1
0.3
0.5
0.7
0.9
V
O
OUTPUT VOLTAGE V
0
0
IF INPUT CURRENT mA
2.0
5
2
1.0
0.5
3
1
4
IOL = 6.4 mA
IOH = -2.6 mA
1.5
VCC = 4.5 V
TA = 25 C
7
1
4
5
6
8
HCPL-2200
GND
VCC
5 V
619
INPUT
MONITORING
NODE
PULSE GEN.
tr = tf = 5 ns
f = 100 kHz
10 % DUTY
CYCLE
VO = 5 V
C2 =
15 pF
THE PROBE AND JIG CAPACITANCES
ARE INCLUDED IN C1 AND C2.
OUTPUT VO
MONITORING
NODE
VCC
R1
D1
D2
5 k
D3
D4
2
3
C1 =
120 pF
RI
IF (ON)
2.15 k
1.6 mA
1.10 k
3 mA
681
5 mA
ALL DIODES ARE 1N916 OR 1N3064.
IF
1-129
3.0 V
VOL
INPUT
VE
OUTPUT
VO
tPZL
tPLZ
1.3 V
0 V
VOH
1.5 V
OUTPUT
VO
S1 OPEN
S2 CLOSED
S1 CLOSED
S2 OPEN
tPZH
tPHZ
1.3 V
0 V
0.5 V
S1 AND
S2 CLOSED
0.5 V
S1 AND
S2 CLOSED
1.3 V
7
1
4
5
6
8
HCPL-2200
GND
VCC
+5 V
619
INPUT VC
MONITORING
NODE
PULSE
GENERATOR
ZO = 50
tr = tf = 5 ns
CL
CL= 15 pF INCLUDING PROBE
AND JIG CAPACITANCES.
VO
VCC
D1
D2
5 k
D3
D4
2
3
D1-4 ARE 1N916 OR 1N3064.
IF
S1
S2
Figure 10. Typical Rise, Fall Time vs.
Temperature.
Figure 8. Typical Logic Low Enable
Propagation Delay vs. Temperature.
Figure 9. Typical Logic High Enable
Propagation Delay vs. Temperature.
Figure 7. Test Circuit for t
PHZ
, t
PZH
, t
PLZ
, and t
PZL
.
Figure 6. Typical Propagation Delays
vs. Temperature.
T
p
ENABLE PROPAGATION DELAY ns
-60
0
TA TEMPERATURE C
100
100
-20
40
20
60
-40
0
40
80
60
80
20
tPLZ
CL = 15 pF
tPZL
VCC
20 V
4.5 V
20 V
4.5 V
t P
ENABLE PROPAGATION DELAY ns
-60
0
TA TEMPERATURE C
100
150
200
-20
50
20
60
-40
0
40
80
100
C
L
= 15 pF
20 V
VCC
t
PHZ
t
PZH
20 V
4.5 V
4.5 V
t P
PROPAGATION DELAY ns
-60
50
TA TEMPERATURE C
100
200
250
-20
100
20
60
-40
0
40
80
150
IF (mA)
5
3
1.6
1.6
3
5
t
PLH
t
PHL
V
CC
= 5 V
C1 (120 pF) PEAKING
CAPACITOR IS USED.
SEE FIGURE 5.
t r
,
t f
RISE, FALL TIME ns
-60
0
TA TEMPERATURE C
100
120
-20
40
20
60
-40
0
40
80
80
100
20
VCC = 5 V
C2 = 15 pF
tr
60
tf
1-130
1
8
2
7
3
6
4
5
HCPL-2200
DATA
INPUT
D1 (1N4150) REQUIRED FOR
ACTIVE PULL-UP DRIVER.
1.1 k
VCC1 (+5 V)
VCC
GND
D1
TTL OR
LSTTL
50 V
OUTPUT
VO
* SEE NOTE 6.
0 V
VOH
VOL
VO (MAX.)*
VO (MIN.)*
SWITCH AT A: IF = 1.6 mA
SWITCH AT B: IF = 0 mA
VCM
Figure 11. Test Circuit for Common Mode Transient Immunity and Typical
Waveforms.
Figure 13. Recommended LSTTL to LSTTL Circuit.
Figure 15. Recommended LED Drive Circuit.
Figure 12. Thermal Derating Curve,
Dependence of Safety Limiting Value
with Case Temperature per
VDE 0884.
Figure 14. LSTTL to CMOS Interface Circuit.
Figure 16. Series LED Drive with Open Collector Gate
(4.7 k
Resistor Shunts I
OH
from the LED).
*The 120 pF capacitor may be omitted in applications where 500 ns propagation delay is sufficient.
7
1
4
5
6
8
HCPL-2200
0.1 F
BYPASS
OUTPUT VO
MONITORING
NODE
VCC
RIN
2
3
VFF
A
B
+
VCM
PULSE GENERATOR
VCC
GND
OUTPUT POWER P
S
, INPUT CURRENT I
S
0
0
TS CASE TEMPERATURE C
200
50
400
125
25
75 100
150
600
800
200
100
300
500
700
PS (mW)
IS (mA)
HCPL-2219 OPTION 060 ONLY
175
120 pF
1
8
2
7
3
6
4
5
1
2
HCPL-2200
DATA
INPUT
TTL OR
LSTTL
VCC2
(+5 V)
UP TO 16
LSTTL
LOADS
OR 4 TTL
LOADS
1.1
k
VCC1
(+5 V)
DATA
OUTPUT
TOTEM
POLE
OUTPUT
GATE
VCC
GND
120 pF (OPTIONAL*)
1
8
2
7
3
6
4
5
HCPL-2200
DATA
INPUT
TTL OR
LSTTL
1.1
k
VCC (+5 V)
OPEN
COLLECTOR
GATE
VCC
GND
4.7 k
120 pF (OPTIONAL*)
1
8
2
7
3
6
4
5
1
2
HCPL-2200
DATA
INPUT
TTL OR
LSTTL
VCC2
(4.5 TO 20 V)
1.1
k
VCC1
(+5 V)
DATA
OUTPUT
TOTEM
POLE
OUTPUT
GATE
VCC
GND
CMOS
VCC2
5 V
10 V
15 V
20 V
RL
1.1 K
2.37 K
3.83 K
5.11 K
RL
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