Description
The Digital Interface IC, HCPL-
0872 converts the single-bit
data stream from the Isolated
Modulator (such as HCPL-
7860/786J/7560) into fifteen-
bit output words and provides
a serial output interface that is
compatible with SPI
, QSPI
,
and Microwire
protocols,
allowing direct connection to a
microcontroller. The Digital
Interface IC, HCPL-0872 is
available a 300-mil wide SO-16
Features
Interface between HCPL-7860/
786J/7560 and MCU/DSP
5 Conversion Modes for
Resolution/Speed Trade-Off
3 Pre-Trigger Modes
Offset Calibration
Fast 3 s Over-Range Detection
Adjustable Threshold Detection
Serial I/O (SPI
, QSPI
and
Microwire Compatible)
Offset Calibration
-40C to +85C Operating
Temperature Range
Applications
Motor Phase and Rail Current
Sensing
Data Acquisition Systems
Industrial Process Control
Inverter Current Sensing
General Purpose Current Sensing
and Monitoring
Agilent HCPL-0872
Digital Interface IC
Data Sheet
surface-mount package.
Features of the Digital
Interface IC include five
different conversion modes,
three different pre-trigger
modes, offset calibration, fast
over-range detection, and
adjustable threshold detection.
Programmable features are
configured via the Serial
Configuration port. A second
multiplexed input is available
to allow measurements with a
second isolated modulator
without additional hardware.
SPI and QSPI are trademarks of Motorola Corp.
Microwire is a trademark of National Semiconductor Inc.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation, which may be induced by ESD.
A 0.1 F bypass capacitor must be connected between pins V
DD
and Ground
HCPL-0872
MCU
or
DSP
1
2
3
4
5
8
6
7
14
13
12
16
15
9
11
10
CONFIG
INTER-
FACE
CON
VERSION
INTER-
FACE
CH1
CH2
THRES
HOLD
DETECT
& RESET
CCLK
CLAT
CDAT
MCLK1
MDAT1
MCLK2
MDAT2
GND
THR1
OVR1
RESET
SDAT
CS
V
DD
CHAN
SCLK
V
DD1
V
IN+
V
IN-
GND1
V
DD2
MCLK
MDAT
GND2
Input
Current
HCPL-7860
HCPL-786J
HCPL-7560
V
DD1
V
IN+
V
IN-
GND1
V
DD2
MCLK
MDAT
GND2
-
-
-
-
-
-
Input
Current
2
HCPL-0872 Digital Interface IC
Because the two inputs are
multiplexed, only one
conversion at a time can be
Pin Description, Digital Interface IC
Symbol
Description
CCLK
Clock input for the Serial Configuration Interface (SCI). Serial Configuration data is clocked in on the rising
edge of CCLK.
CLAT
Latch input for the Serial Configuration Interface (SCI). The last 8 data bits clocked in on CDAT by CCLK are
latched into the appropriate configuration register on the rising edge of CLAT.
CDAT
Data input for the Serial Configuration Interface (SCI). Serial configuration data is clocked in MSB first.
MCLK1
Channel 1 Isolated Modulator clock input. Input Data on MDAT1 is clocked in on the rising edge of MCLK1.
MDAT1
Channel 1 Isolated Modulator data input.
MCLK2
Channel 2 Isolated Modulator clock input. Input Data on MDAT2 is clocked in on the rising edge of MCLK2.
MDAT2
Channel 2 Isolated Modulator data input.
GND
Digital ground.
VDD
Supply voltage (4.5 V to 5.5 V).
CHAN
Channel select input. The input level on CHAN determines which channel of data is used during the next
conversion cycle. An input low selects channel 1, a high selects channel 2.
SCLK
Serial clock input. Serial data is clocked out of SDAT on the falling edge of SCLK.
SDAT
Serial data output. SDAT changes from high impedance to a logic low output at the start of a conversion
cycle. SDAT then goes high to indicate that data is ready to be clocked out. SDAT returns to a high-
impedance state after all data has been clocked out and CS has been brought high. SDAT goes high
immediately after RESET is released.
CS
Conversion start input. Conversion begins on the falling edge of CS. CS should remain low during the entire
conversion cycle and then be brought high to conclude the cycle.
THR1
Continuous, programmable-threshold detection for channel 1 input data. A high level output on THR1
indicates that the magnitude of the channel 1 input signal is beyond a user programmable threshold level
between 160 mV and 310 mV. This signal continuously monitors channel 1 independent of the channel
select (CHAN) signal.
OVR1
High speed continuous over-range detection for channel 1 input data. A high level output on OVR1
indicates that the magnitude of the channel 1 input is beyond full-scale. This signal continuously monitors
channel 1 independent of the CHAN signal.
RESET
Master reset input. A logic high input for at least 100 ns asynchronously resets all configuration registers
to their default values and zeroes the Offset Calibration registers.
5
6
12
11
MDAT1
MCLK2
CS
THR1
CON-
VERSION
INTER-
FACE
CONFIG.
INTER-
FACE
7
10
MDAT2
OVR1
8
9
GND
RESET
1
2
16
15
CCLK
CLAT
V
DD
CHAN
3
14
CDAT
SCLK
4
13
MCLK1
SDAT
CH1
CH2
THRES-
HOLD
DETECT
&
RESET
made and not all features are
available for the second
channel. The available features
for both channels are shown in
the table below
Feature
Channel 1
Channel 2
Conversion Mode
Offset Calibration
Pre-Trigger Mode
Over-Range Detection
Adjustable Threshold Detection
3
Package Outline Drawings
Standard 16-pin SO Package
Ordering Information
Specify part number followed by option number (if desired).
Example:
Option data sheets available. Contact Agilent sales representative or authorized distributor.
HCPL-0872-XXXX
No option = Standard DIP package, 47 units per tube.
500 = Tape and Reel Packaging Option, 1000 units per reel.
XXXE = Lead-Free Option
9
10.00-10.65
(0.394-0.419)
(TIP TO TIP)
2.386-2.586
(0.094-0.1018)
1.27 BSC
(0.050 BSC)
A 0872
YYWW
2.286
(0.090)
1.90
(0.075)
1.90
(0.075)
7.544 0.05
(0.297 0.002)
0.33 x 45
(0.013 x 45
)
PIN NO. 1 IDENTIFIER
1.27 (0.050) x 0.075 (0.003) DEPTH
SHINY SURFACE
1.27
(0.050)
10
11
12
13
14
15
16
8
7
6
5
4
3
2
1
10.21 0.10
(0.402 0.002)
0.33-0.51
(0.013-0.020)
0.01 (0.004)
0.10-0.30
(0.004-0.0118)
1.016 0.025
(0.040 0.001)
R 0.18 (R 0.007)
ALL CORNERS
AND EDGES
SEATING PLANE
TH
XX
TOP VIEW
BOTTOM VIEW
SIDE VIEW
END VIEW
A
1.016 REF.
(0.040)
0.40 - 1.27
(0.016 - 0.050)
0
- 8
7
DETAIL A
1.27 (0.050)
x 0.075 (0.003)
DEPTH
(2x) EJECTOR PIN
SHINY SURFACE
0.23-0.32
(0.0091-0.0125)
PARTING
LINE
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES
(UNLESS OTHERWISE SPECIFIED):
xx.xx = 0.010
xx.xxx = 0.002
1.27 (0.050)
4
Solder Reflow Temperature Profile
Lead Free IR Profile
0
TIME (SECONDS)
TEMPERATURE (C)
200
100
50
150
100
200
250
300
0
30
SEC.
50 SEC.
30
SEC.
160C
140C
150C
PEAK
TEMP.
245C
PEAK
TEMP.
240C
PEAK
TEMP.
230C
SOLDERING
TIME
200C
PREHEATING TIME
150C, 90 + 30 SEC.
2.5C 0.5C/SEC.
3C + 1C/-0.5C
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
PREHEATING RATE 3C + 1C/-0.5C/SEC.
REFLOW HEATING RATE 2.5C 0.5C/SEC.
217C
RAMP-DOWN
6C/SEC. MAX.
RAMP-UP
3C/SEC. MAX.
150 - 200 C
260 +0/-5C
t 25C to PEAK
60 to 150 SEC.
15 SEC.
TIME WITHIN 5C of ACTUAL
PEAK TEMPERATURE
tp
t
s
PREHEAT
60 to 180 SEC.
t
L
T
L
T
smax
T
smin
25
T
p
TIME (SECONDS)
TEMPERATURE (
C)
NOTES:
THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX.
T
smax
= 200C, T
smin
= 150C
5
Electrical Specifications (DC)
Unless otherwise noted, all Typical specifications are at T
A
= 25C and V
DD
= 5 V, and all Minimum and Maximum
specifications apply over the following ranges: T
A
= -40C to +85C and V
DD
= 4.5 to 5.5 V.
Absolute Maximum Ratings
Notes:
1. Agilent recommends the use of non-chlorinated solder fluxes.
Notes 1. Agilent Technologies recommends the use of non-chlorinated solder fluxes.
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Ambient Operating Temperature
T
A
-40
85
C
Supply Voltage
V
DD
4.5
5.5
V
Input Voltage
All Inputs
0
V
DD
V
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions Fig.
Supply Current
I
DD
3
5
mA
f
CLK
= 10 MHz
DC Input Current
I
IN
0.001
10
A
Input Logic Low Voltage
V
IL
0.8
V
Input Logic High Voltage
V
IH
3.6
V
Output Logic Low Voltage
V
OL
0.15
0.4
V
I
OUT
= 4 mA
Output Logic High Voltage
V
OH
4.3
5.0
V
I
OUT
= -400 A
Clock Frequency
(CCLK, MCLK and SCLK)
f
CLK
20
MHz
Clock Period (CCLK, MCLK and SCLK)
t
PER
50
ns
2, 3
Clock High Level Pulse Width
(CCLK, MCLK and SCLK)
t
PWH
20
ns
2, 3
Clock Low Level Pulse Width
(CCLK, MCLK and SCLK)
t
PWL
20
ns
2, 3
Setup Time from DAT to Rising Edge
of CLK (CDAT, CCLK, MDAT and MCLK)
t
SUCLK
10
ns
2
DAT Hold Time after Rising Edge
of CLK (CDAT, CCLK, MDAT and MCLK)
t
HDCLK
10
ns
2
Setup Time from Falling Edge
of CLAT to First Rising Edge of CCLK
t
SUCL1
20
ns
2
Setup Time from Last Rising
Edge of CCLK to Rising Edge of CLAT
t
SUCL2
20
ns
2
Delay Time from Falling
Edge of SCLK to SDAT
t
DSDAT
15
ns
3
Setup Time from Data
Ready to First Falling Edge of SCLK
t
SUS
200
ns
3
Setup Time from CHAN
to falling edge of CS
t
SUCHS
20
ns
Reset High Level Pulse Width
t
PWR
100
ns
Parameter
Symbol
Min.
Max.
Units
Note
Storage Temperature
T
S
-55
125
C
Operating Temperature
T
A
-40
85
C
Supply Voltage
V
DD
0
5.5
V
Input Voltage
All Inputs
-0.5
V
DD
+ 0.5
V
Output Voltage
All Outputs
-0.5
V
DD
+ 0.5
V
Lead Solder Temperature
260C for 10 sec., 1.6 mm below seating plane
1
Solder Reflow Temperature Profile
See Reflow Thermal Profile
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