1-197
H
0.5 Amp Output Current IGBT
Gate Drive Optocoupler
Technical Data
HCPL-3150
Features
0.5 A Minimum Peak Output
Current
15 kV/
s Minimum Common
Mode Rejection (CMR) at
V
CM
= 1500 V
1.0 V Maximum Low Level
Output Voltage (V
OL
)
Eliminates Need for
Negative Gate Drive
I
CC
= 5 mA Maximum Supply
Current
Under Voltage Lock-Out
Protection (UVLO) with
Hysteresis
Wide Operating V
CC
Range:
15 to 30 Volts
500 ns Maximum Switching
Speeds
Industrial Temperature
Range:
-40
C to 100
C
Safety and Regulatory
Approval:
UL Recognized
2500 Vrms for 1 min. per
UL1577
VDE 0884 Approved with
V
IORM
= 630 Vpeak
(Option 060 only)
CSA Approved
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
Applications
Isolated IGBT/MOSFET
Gate Drive
AC and Brushless DC Motor
Drives
Industrial Inverters
Switch Mode Power
Supplies (SMPS)
Description
The HCPL-3150 consists of a
GaAsP LED optically coupled to
an integrated circuit with a power
output stage. This optocoupler is
ideally suited for driving power
IGBTs and MOSFETs used in
motor control inverter applica-
tions. The high operating voltage
range of the output stage pro-
vides the drive voltages required
by gate controlled devices. The
voltage and current supplied by
this optocoupler makes it ideally
suited for directly driving IGBTs
with ratings up to 1200 V/50 A.
For IGBTs with higher ratings,
the HCPL-3120 can be used to
drive a discrete power stage
which drives the IGBT gate.
Truth Table
V
CC
- V
EE
V
CC
- V
EE
"Positive Going"
"Negative-Going"
LED
(i.e., Turn-On)
(i.e., Turn-Off)
V
O
OFF
0 - 30 V
0 - 30 V
LOW
ON
0 - 11 V
0 - 9.5 V
LOW
ON
11 - 13.5 V
9.5 - 12 V
TRANSITION
ON
13.5 - 30 V
12 - 30 V
HIGH
A 0.1
F bypass capacitor must be connected between pins 5 and 8.
Functional Diagram
1
3
SHIELD
2
4
8
6
7
5
N/C
CATHODE
ANODE
N/C
VCC
VO
VO
VEE
5965-4780E
1-198
Ordering Information
Specify Part Number followed by Option Number (if desired)
Example
HCPL-3150#XXX
No Option = Standard DIP package, 50 per tube.
060 = VDE 0884 V
IORM
= 630 Vpeak Option, 50 per tube.
300 = Gull Wing Surface Mount Option, 50 per tube.
500 = Tape and Reel Packaging Option, 1000 per reel.
Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor.
Package Outline Drawings
Standard DIP Package
Gull-Wing Surface-Mount Option 300
9.40 (0.370)
9.90 (0.390)
PIN ONE
1.78 (0.070) MAX.
1.19 (0.047) MAX.
HP 3150 Z
YYWW
DATE CODE
0.76 (0.030)
1.40 (0.055)
2.28 (0.090)
2.80 (0.110)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
6.10 (0.240)
6.60 (0.260)
0.20 (0.008)
0.33 (0.013)
5 TYP.
7.36 (0.290)
7.88 (0.310)
1
2
3
4
8
7
6
5
5
6
7
8
4
3
2
1
GND1
V
DD1
V
IN+
V
IN
GND2
V
DD2
V
OUT+
V
OUT
PIN DIAGRAM
PIN ONE
DIMENSIONS IN MILLIMETERS AND (INCHES).
* MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION 060.
OPTION NUMBERS 300 AND 500 NOT MARKED.
OPTION CODE*
0.635 0.25
(0.025 0.010)
12 NOM.
0.20 (0.008)
0.33 (0.013)
9.65 0.25
(0.380 0.010)
0.635 0.130
(0.025 0.005)
7.62 0.25
(0.300 0.010)
5
6
7
8
4
3
2
1
9.65 0.25
(0.380 0.010)
6.350 0.25
(0.250 0.010)
MOLDED
1.016 (0.040)
1.194 (0.047)
1.194 (0.047)
1.778 (0.070)
9.398 (0.370)
9.906 (0.390)
4.826
(0.190)
TYP.
0.381 (0.015)
0.635 (0.025)
PAD LOCATION (FOR REFERENCE ONLY)
1.080 0.320
(0.043 0.013)
4.19
(0.165)
MAX.
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.540
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES (UNLESS OTHERWISE SPECIFIED):
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
xx.xx = 0.01
xx.xxx = 0.005
HP 3150 Z
YYWW
1-199
VDE 0884 Insulation Characteristics (Option 060 Only)
Description
Symbol
Characteristic
Unit
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage
300 Vrms
I-IV
for rated mains voltage
600 Vrms
I-III
Climatic Classification
55/100/21
Pollution Degree (DIN VDE 0110/1.89)
2
Maximum Working Insulation Voltage
V
IORM
630
Vpeak
Input to Output Test Voltage, Method b*
V
IORM
x 1.875 = V
PR
, 100% Production Test with t
m
= 1 sec,
V
PR
1181
Vpeak
Partial discharge < 5 pC
Input to Output Test Voltage, Method a*
V
IORM
x 1.5 = V
PR
, Type and Sample Test, t
m
= 60 sec,
V
PR
945
Vpeak
Partial discharge < 5 pC
Highest Allowable Overvoltage*
V
IOTM
6000
Vpeak
(Transient Overvoltage t
ini
= 10 sec)
Safety-Limiting Values Maximum Values Allowed in the Event
of a Failure, Also See Figure 37, Thermal Derating Curve.
Case Temperature
T
S
175
C
Input Current
I
S, INPUT
230
mA
Output Power
P
S, OUTPUT
600
mW
Insulation Resistance at T
S
, V
IO
= 500 V
R
S
10
9
*Refer to the front of the optocoupler section of the current Catalog, under Product Safety Regulations section, (VDE 0884) for a
detailed description of Method a and Method b partial discharge test profiles.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
Regulatory Information
The HCPL-3150 has been
approved by the following
organizations:
UL
Recognized under UL 1577,
Component Recognition
Program, File E55361.
CSA
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
VDE (Option 060 only)
Approved under VDE 0884/06.92
with V
IORM
= 630 Vpeak.
Reflow Temperature Profile
240
T = 115C, 0.3C/SEC
0
T = 100C, 1.5C/SEC
T = 145C, 1C/SEC
TIME MINUTES
TEMPERATURE C
220
200
180
160
140
120
100
80
60
40
20
0
260
1
2
3
4
5
6
7
8
9
10
11
12
MAXIMUM SOLDER REFLOW THERMAL PROFILE
(NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)
1-200
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Power Supply Voltage
(V
CC
- V
EE
)
15
30
Volts
Input Current (ON)
I
F(ON)
7
16
mA
Input Voltage (OFF)
V
F(OFF)
-3.0
0.8
V
Operating Temperature
T
A
-40
100
C
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Minimum External Air Gap
L(101)
7.1
mm
Measured from input terminals to output
(External Clearance)
terminals, shortest distance through air.
Minimum External Tracking
L(102)
7.4
mm
Measured from input terminals to output
(External Creepage)
terminals, shortest distance path along body.
Minimum Internal Plastic Gap
0.08
mm
Through insulation distance conductor to
(Internal Clearance)
conductor.
Tracking Resistance
CTI
200
Volts
DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking Index)
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance wtih CECC 00802.
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Note
Storage Temperature
T
S
-55
125
C
Operating Temperature
T
A
-40
100
C
Average Input Current
I
F(AVG)
25
mA
1
Peak Transient Input Current
I
F(TRAN)
1.0
A
(<1
s pulse width, 300 pps)
Reverse Input Voltage
V
R
5
Volts
"High" Peak Output Current
I
OH(PEAK)
0.6
A
2
"Low" Peak Output Current
I
OL(PEAK)
0.6
A
2
Supply Voltage
(V
CC
- V
EE
)
0
35
Volts
Output Voltage
V
O(PEAK)
0
V
CC
Volts
Output Power Dissipation
P
O
250
mW
3
Total Power Dissipation
P
T
295
mW
4
Lead Solder Temperature
260
C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile
See Package Outline Drawings Section
1-201
Electrical Specifications (DC)
Over recommended operating conditions (T
A
= -40 to 100
C, I
F(ON)
= 7 to 16 mA, V
F(OFF)
= -3.0 to 0.8 V,
V
CC
= 15 to 30 V, V
EE
= Ground) unless otherwise specified.
Parameter
Symbol
Min.
Typ.*
Max. Units
Test Conditions
Fig.
Note
High Level
I
OH
0.1
0.4
A
V
O
= (V
CC
- 4 V)
2, 3,
5
0.5
V
O
= (V
CC
- 15 V)
2
Low Level
I
OL
0.1
0.6
A
V
O
= (V
EE
+ 2.5 V)
5, 6
5
0.5
V
O
= (V
EE
+ 15 V)
2
High Level Output
V
OH
(V
CC
- 4) (V
CC
- 3)
V
I
O
= -100 mA
1, 3
6, 7
Voltage
19
Low Level Output
V
OL
0.4
1.0
V
I
O
= 100 mA
4, 6
Voltage
20
High Level
I
CCH
2.5
5.0
mA
Output Open,
7, 8
Supply Current
I
F
= 7 to 16 mA
Low Level
I
CCL
2.7
5.0
mA
Output Open,
Supply Current
V
F
= -3.0 to +0.8 V
Threshold Input
I
FLH
2.2
5.0
mA
I
O
= 0 mA,
9, 15,
Current Low to High
V
O
> 5 V
21
Threshold Input
V
FHL
0.8
V
Voltage High to Low
Input Forward Voltage
V
F
1.2
1.5
1.8
V
I
F
= 10 mA
16
Temperature
V
F
/
T
A
-1.6
mV/
C
I
F
= 10 mA
Coefficient of
Forward Voltage
Input Reverse
BV
R
5
V
I
R
= 10
A
Breakdown Voltage
Input Capacitance
C
IN
60
pF
f = 1 MHz, V
F
= 0 V
UVLO Threshold
V
UVLO+
11.0
12.3
13.5
V
V
O
> 5 V,
22,
V
UVLO-
9.5
10.7
12.0
UVLO Hysteresis
UVLO
HYS
1.6
V
*All typical values at T
A
= 25
C and V
CC
- V
EE
= 30 V, unless otherwise noted.
Output Current
17
18
Output Current
I
F
= 10 mA
36
1-202
Switching Specifications (AC)
Over recommended operating conditions (T
A
= -40 to 100
C, I
F(ON)
= 7 to 16 mA, V
F(OFF)
= -3.0 to 0.8 V,
V
CC
= 15 to 30 V, V
EE
= Ground) unless otherwise specified.
Parameter
Symbol
Min.
Typ.*
Max.
Units
Test Conditions
Fig.
Note
Propagation Delay
t
PLH
0.10
0.30
0.50
s
Rg = 47
,
10, 11,
14
Time to High
Cg = 3 nF,
12, 13
Output Level
f = 10 kHz,
14, 23
Duty Cycle = 50%
Propagation Delay
t
PHL
0.10
0.27
0.50
s
Time to Low
Output Level
Pulse Width
PWD
0.3
s
15
Distortion
Propagation Delay
PDD
-0.35
0.35
s
34,35
10
Difference Between (t
PHL
- t
PLH
)
Any Two Parts
Rise Time
t
r
0.1
s
23
Fall Time
t
f
0.1
s
UVLO Turn On
t
UVLO ON
0.8
s
V
O
> 5 V,
22
Delay
I
F
= 10 mA
UVLO Turn Off
t
UVLO OFF
0.6
s
V
O
< 5 V,
Delay
I
F
= 10 mA
Output High Level
|CM
H
|
15
30
kV/
s
T
A
= 25
C,
24
11, 12
Common Mode
I
F
= 10 to 16 mA,
Transient
V
CM
= 1500 V,
Immunity
V
CC
= 30 V
Output Low Level
|CM
L
|
15
30
kV/
s
T
A
= 25
C,
11, 13
Common Mode
V
CM
= 1500 V,
Transient
V
F
= 0 V,
Immunity
V
CC
= 30 V
Package Characteristics
Parameter
Symbol
Min.
Typ.*
Max.
Units
Test Conditions
Fig.
Note
Input-Output
V
ISO
2500
Vrms
RH < 50%,
8, 9
Momentary
t = 1 min.,
Withstand Voltage**
T
A
= 25
C
Resistance
R
I-O
10
12
V
I-O
= 500 V
DC
9
(Input - Output)
Capacitance
C
I-O
0.6
pF
f = 1 MHz
(Input - Output)
LED-to-Case
LC
391
C/W
Thermocouple
28
Thermal Resistance
LED-to-Detector
LD
439
C/W
Thermal Resistance
Detector-to-Case
DC
119
C/W
Thermal Resistance
*All typical values at T
A
= 25
C and V
CC
- V
EE
= 30 V, unless otherwise noted.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or HP Application Note
1074 entitled "Optocoupler Input-Output Endurance Voltage."
located at center
underside of
package
1-203
Notes:
1. Derate linearly above 70
C free-air
temperature at a rate of 0.3 mA/
C.
2. Maximum pulse width = 10
s,
maximum duty cycle = 0.2%. This
value is intended to allow for
component tolerances for designs
with I
O
peak minimum = 0.5 A. See
Applications section for additional
details on limiting I
OH
peak.
3. Derate linearly above 70
C free-air
temperature at a rate of 4.8 mW/
C.
4. Derate linearly above 70
C free-air
temperature at a rate of 5.4 mW/
C.
The maximum LED junction tempera-
ture should not exceed 125
C.
5. Maximum pulse width = 50
s,
maximum duty cycle = 0.5%.
6. In this test V
OH
is measured with a dc
load current. When driving capacitive
loads V
OH
will approach V
CC
as I
OH
approaches zero amps.
7. Maximum pulse width = 1 ms,
maximum duty cycle = 20%.
8. In accordance with UL1577, each
optocoupler is proof tested by
applying an insulation test voltage
3000 Vrms for 1 second (leakage
detection current limit, I
I-O
5
A).
This test is performed before the
100% production test for partial
discharge (method b) shown in the
VDE 0884 Insulation Characteristics
Table, if applicable.
9. Device considered a two-terminal
device: pins 1, 2, 3, and 4 shorted
together and pins 5, 6, 7, and 8
shorted together.
10. The difference between t
PHL
and t
PLH
between any two HCPL-3150 parts
under the same test condition.
11. Pins 1 and 4 need to be connected to
LED common.
12. Common mode transient immunity in
the high state is the maximum
tolerable |dV
CM
/dt| of the common
mode pulse, V
CM
, to assure that the
output will remain in the high state
(i.e., V
O
> 15.0 V).
13. Common mode transient immunity in
a low state is the maximum tolerable
|dV
CM
/dt| of the common mode
pulse, V
CM
, to assure that the output
will remain in a low state (i.e.,
V
O
< 1.0 V).
14. This load condition approximates the
gate load of a 1200 V/25 A IGBT.
15. Pulse Width Distortion (PWD) is
defined as |t
PHL
-t
PLH
| for any given
device.
Figure 4. V
OL
vs. Temperature.
Figure 5. I
OL
vs. Temperature.
Figure 6. V
OL
vs. I
OL
.
I OL
OUTPUT LOW CURRENT A
-40
0
TA TEMPERATURE C
100
0.8
0.4
-20
1.0
0
20
40
0.2
60
80
VF(OFF) = -3.0 to 0.8 V
VOUT = 2.5 V
VCC = 15 to 30 V
VEE = 0 V
0.6
V
OL
OUTPUT LOW VOLTAGE V
-40
0
TA TEMPERATURE C
100
0.8
0.6
-20
1.0
0
20
40
0.2
60
80
VF(OFF) = -3.0 to 0.8 V
IOUT = 100 mA
VCC = 15 to 30 V
VEE = 0 V
0.4
V
OL
OUTPUT LOW VOLTAGE V
0
0
IOL OUTPUT LOW CURRENT A
1.0
4
0.2
5
0.4
0.6
1
0.8
VF(OFF) = -3.0 to 0.8 V
VCC = 15 to 30 V
VEE = 0 V
2
100 C
25 C
-40 C
3
Figure 1. V
OH
vs. Temperature.
Figure 2. I
OH
vs. Temperature.
Figure 3. V
OH
vs. I
OH
.
(V
OH
- V
CC
) HIGH OUTPUT VOLTAGE DROP V
-40
-4
TA TEMPERATURE C
100
-1
-2
-20
0
0
20
40
-3
60
80
IF = 7 to 16 mA
IOUT = -100 mA
VCC = 15 to 30 V
VEE = 0 V
I OH
OUTPUT HIGH CURRENT A
-40
0.25
TA TEMPERATURE C
100
0.45
0.40
-20
0.50
0
20
40
0.30
60
80
IF = 7 to 16 mA
VOUT = VCC - 4 V
VCC = 15 to 30 V
VEE = 0 V
0.35
(V
OH
- V
CC
) OUTPUT HIGH VOLTAGE DROP V
0
-6
IOH OUTPUT HIGH CURRENT A
1.0
-2
-3
0.2
-1
0.4
0.6
-5
0.8
IF = 7 to 16 mA
VCC = 15 to 30 V
VEE = 0 V
-4
100 C
25 C
-40 C
1-204
V
O
OUTPUT VOLTAGE V
0
0
IF FORWARD LED CURRENT mA
5
25
15
1
30
2
5
3
4
20
10
Figure 15. Transfer Characteristics.
Figure 14. Propagation Delay vs. Cg.
Figure 13. Propagation Delay vs. Rg.
I CC
SUPPLY CURRENT mA
-40
1.5
TA TEMPERATURE C
100
3.0
2.5
-20
3.5
0
20
40
2.0
60
80
VCC = 30 V
VEE = 0 V
IF = 10 mA for ICCH
IF = 0 mA for ICCL
ICCH
ICCL
I CC
SUPPLY CURRENT mA
15
1.5
VCC SUPPLY VOLTAGE V
30
3.0
2.5
3.5
20
2.0
25
IF = 10 mA for ICCH
IF = 0 mA for ICCL
TA = 25 C
VEE = 0 V
ICCH
ICCL
I FLH
LOW TO HIGH CURRENT THRESHOLD mA
-40
0
TA TEMPERATURE C
100
3
2
-20
4
0
20
40
1
60
80
5
VCC = 15 TO 30 V
VEE = 0 V
OUTPUT = OPEN
Figure 10. Propagation Delay vs. V
CC
.
Figure 11. Propagation Delay vs. I
F
.
Figure 12. Propagation Delay vs.
Temperature.
Figure 7. I
CC
vs. Temperature.
Figure 8. I
CC
vs. V
CC
.
Figure 9. I
FLH
vs. Temperature.
T
p
PROPAGATION DELAY ns
15
100
VCC SUPPLY VOLTAGE V
30
400
300
500
20
200
25
IF = 10 mA
TA = 25 C
Rg = 47
Cg = 3 nF
DUTY CYCLE = 50%
f = 10 kHz
TPLH
TPHL
T
p
PROPAGATION DELAY ns
6
100
IF FORWARD LED CURRENT mA
16
400
300
500
10
200
12
VCC = 30 V, VEE = 0 V
Rg = 47
, Cg = 3 nF
TA = 25 C
DUTY CYCLE = 50%
f = 10 kHz
TPLH
TPHL
14
8
T
p
PROPAGATION DELAY ns
-40
100
TA TEMPERATURE C
100
400
300
-20
500
0
20
40
200
60
80
TPLH
TPHL
IF(ON) = 10 mA
IF(OFF) = 0 mA
VCC = 30 V, VEE = 0 V
Rg = 47
, Cg = 3 nF
DUTY CYCLE = 50%
f = 10 kHz
T
p
PROPAGATION DELAY ns
0
100
Rg SERIES LOAD RESISTANCE
200
400
300
50
500
100
200
150
TPLH
TPHL
VCC = 30 V, VEE = 0 V
TA = 25 C
IF = 10 mA
Cg = 3 nF
DUTY CYCLE = 50%
f = 10 kHz
T
p
PROPAGATION DELAY ns
0
100
Cg LOAD CAPACITANCE nF
100
400
300
20
500
40
200
60
80
TPLH
TPHL
VCC = 30 V, VEE = 0 V
TA = 25 C
IF = 10 mA
Rg = 47
DUTY CYCLE = 50%
f = 10 kHz
1-205
Figure 16. Input Current vs. Forward
Voltage.
Figure 22. UVLO Test Circuit.
0.1 F
VCC = 15
to 30 V
1
3
IF = 7 to
16 mA
+
2
4
8
6
7
5
100 mA
VOH
0.1 F
VCC = 15
to 30 V
1
3
IF
+
2
4
8
6
7
5
VO > 5 V
Figure 17. I
OH
Test Circuit.
0.1 F
VCC = 15
to 30 V
1
3
IF = 7 to
16 mA
+
2
4
8
6
7
5
+
4 V
IOH
Figure 18. I
OL
Test Circuit.
Figure 19. V
OH
Test Circuit.
0.1 F
VCC = 15
to 30 V
1
3
+
2
4
8
6
7
5
2.5 V
IOL
+
0.1 F
VCC = 15
to 30 V
1
3
+
2
4
8
6
7
5
100 mA
VOL
Figure 20. V
OL
Test Circuit.
Figure 21. I
FLH
Test Circuit.
I F
FORWARD CURRENT mA
1.10
0.001
VF FORWARD VOLTAGE V
1.60
10
1.0
0.1
1.20
1000
1.30
1.40
1.50
TA = 25C
IF
VF
+
0.01
100
0.1 F
VCC
1
3
IF = 10 mA
+
2
4
8
6
7
5
VO > 5 V
1-206
Figure 25. Recommended LED Drive and Application Circuit.
Applications Information
Eliminating Negative IGBT
Gate Drive
To keep the IGBT firmly off, the
HCPL-3150 has a very low
maximum V
OL
specification of
1.0 V. The HCPL-3150 realizes
this very low V
OL
by using a
DMOS transistor with 4
(typical) on resistance in its pull
down circuit. When the
HCPL-3150 is in the low state,
the IGBT gate is shorted to the
emitter by Rg + 4
. Minimizing
Rg and the lead inductance from
the HCPL-3150 to the IGBT gate
and emitter (possibly by
mounting the HCPL-3150 on a
small PC board directly above the
IGBT) can eliminate the need for
negative IGBT gate drive in many
applications as shown in Figure
25. Care should be taken with
such a PC board design to avoid
routing the IGBT collector or
emitter traces close to the HCPL-
3150 input as this can result in
unwanted coupling of transient
signals into the HCPL-3150 and
degrade performance. (If the
IGBT drain must be routed near
the HCPL-3150 input, then the
LED should be reverse-biased
when in the off state, to prevent
the transient signals coupled
from the IGBT drain from turning
on the HCPL-3150.)
Figure 24. CMR Test Circuit and Waveforms.
0.1 F
VCC = 15
to 30 V
47
1
3
IF = 7 to 16 mA
VO
+
+
2
4
8
6
7
5
10 KHz
50% DUTY
CYCLE
500
3 nF
IF
VOUT
tPHL
tPLH
tf
tr
10%
50%
90%
Figure 23. t
PLH
, t
PHL
, t
r
, and t
f
Test Circuit and Waveforms.
0.1 F
VCC = 30 V
1
3
IF
VO
+
+
2
4
8
6
7
5
A
+
B
VCM = 1500 V
5 V
VCM
t
0 V
VO
SWITCH AT B: IF = 0 mA
VO
SWITCH AT A: IF = 10 mA
VOL
VOH
t
VCM
V
t
=
+ HVDC
3-PHASE
AC
- HVDC
0.1 F
VCC = 18 V
1
3
+
2
4
8
6
7
5
270
HCPL-3150
+5 V
CONTROL
INPUT
Rg
Q1
Q2
74XXX
OPEN
COLLECTOR
1-207
Figure 26. HCPL-3150 Typical Application Circuit with Negative IGBT Gate Drive.
Selecting the Gate Resistor
(Rg) to Minimize IGBT
Switching Losses.
Step 1: Calculate Rg Minimum
From the I
OL
Peak Specifica-
tion. The IGBT and Rg in Figure
26 can be analyzed as a simple
RC circuit with a voltage supplied
by the HCPL-3150.
(V
CC
V
EE
- V
OL
)
Rg
I
OLPEAK
(V
CC
V
EE
-
1.7 V)
=
I
OLPEAK
(
15 V + 5 V - 1.7 V)
=
0.6 A
= 30.5
The V
OL
value of 2 V in the pre-
vious equation is a conservative
value of V
OL
at the peak current
of 0.6 A (see Figure 6). At lower
Rg values the voltage supplied by
the HCPL-3150 is not an ideal
voltage step. This results in lower
peak currents (more margin)
than predicted by this analysis.
When negative gate drive is not
used V
EE
in the previous equation
is equal to zero volts.
Step 2: Check the HCPL-3150
Power Dissipation and
Increase Rg if Necessary. The
HCPL-3150 total power dissipa-
tion (P
T
) is equal to the sum of
the emitter power (P
E
) and the
output power (P
O
):
P
T
= P
E
+ P
O
P
E
= I
F
V
F
Duty Cycle
P
O
= P
O(BIAS)
+ P
O (SWITCHING)
= I
CC
(V
CC
- V
EE
)
+ E
SW
(R
G
, Q
G
)
f
For the circuit in Figure 26 with I
F
(worst case) = 16 mA, Rg =
30.5
, Max Duty Cycle = 80%,
Qg = 500 nC, f = 20 kHz and T
A
max = 90
C:
P
E
=
16 mA
1.8 V
0.8 = 23 mW
P
O
=
4.25 mA
20 V
+
4.0
J
20 kHz
=
85 mW + 80 mW
=
165 mW
>
154 mW (P
O(MAX)
@
90
C
=
250 mW
-
20C
4.8 mW/C)
P
O
Parameter
Description
I
CC
Supply Current
V
CC
Positive Supply Voltage
V
EE
Negative Supply Voltage
E
SW
(Rg,Qg)
Energy Dissipated in the HCPL-3150 for each
IGBT Switching Cycle (See Figure 27)
f
Switching Frequency
P
E
Parameter
Description
I
F
LED Current
V
F
LED On Voltage
Duty Cycle
Maximum LED
Duty Cycle
+ HVDC
3-PHASE
AC
- HVDC
0.1 F
VCC = 15 V
1
3
+
2
4
8
6
7
5
HCPL-3150
Rg
Q1
Q2
VEE = -5 V
+
270
+5 V
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
1-208
The value of 4.25 mA for I
CC
in
the previous equation was
obtained by derating the I
CC
max
of 5 mA (which occurs at -40
C)
to I
CC
max at 90
C (see Figure 7).
Since P
O
for this case is greater
than P
O(MAX)
, Rg must be
increased to reduce the HCPL-
3150 power dissipation.
P
O(SWITCHING MAX)
= P
O(MAX)
- P
O(BIAS)
= 154 mW - 85 mW
= 69 mW
P
O(SWITCHINGMAX)
E
SW(MAX)
=
f
69 mW
= = 3.45
J
20 kHz
For Qg = 500 nC, from Figure
27, a value of E
SW
= 3.45
J
gives a Rg = 41
.
Thermal Model
The steady state thermal model
for the HCPL-3150 is shown in
Figure 28. The thermal resistance
values given in this model can be
used to calculate the tempera-
tures at each node for a given
operating condition. As shown by
the model, all heat generated
flows through
CA
which raises
the case temperature T
C
accordingly. The value of
CA
depends on the conditions of the
board design and is, therefore,
determined by the designer. The
value of
CA
= 83
C/W was
obtained from thermal measure-
ments using a 2.5 x 2.5 inch PC
board, with small traces (no
ground plane), a single HCPL-
3150 soldered into the center of
the board and still air. The
absolute maximum power
dissipation derating specifications
assume a
CA
value of 83
C/W.
Inserting the values for
LC
and
DC
shown in Figure 28 gives:
T
JE
= P
E
(230
C/W +
CA
)
+ P
D
(49
C/W +
CA
) + T
A
T
JD
= P
E
(49
C/W +
CA
)
+ P
D
(104
C/W +
CA
) + T
A
For example, given P
E
= 45 mW,
P
O
= 250 mW, T
A
= 70
C and
CA
= 83
C/W:
shown in Figure 29. The HCPL-
3150 improves CMR performance
by using a detector IC with an
optically transparent Faraday
shield, which diverts the capaci-
tively coupled current away from
the sensitive IC circuitry. How
ever, this shield does not
eliminate the capacitive coupling
between the LED and optocoup-
ler pins 5-8 as shown in
Figure 30. This capacitive
coupling causes perturbations in
the LED current during common
mode transients and becomes the
major source of CMR failures for
a shielded optocoupler. The main
design objective of a high CMR
LED drive circuit becomes
keeping the LED in the proper
state (on or off) during common
mode transients. For example,
the recommended application
circuit (Figure 25), can achieve
15 kV/
s CMR while minimizing
component complexity.
Techniques to keep the LED in
the proper state are discussed in
the next two sections.
From the thermal mode in Figure
28 the LED and detector IC
junction temperatures can be
expressed as:
T
JE
= P
E
(
LC
||(
LD
+
DC
) +
CA
)
LC
DC
+ P
D
(
+
CA
)
+ T
A
LC
+
DC
+
LD
LC
DC
T
JD
=
P
E
(
+
CA
)
LC
+
DC
+
LD
+
P
D
(
DC
||(
LD
+
LC
) +
CA
) + T
A
T
JE
and T
JD
should be limited to
125
C based on the board layout
and part placement (
CA
) specific
to the application.
LED Drive Circuit
Considerations for Ultra
High CMR Performance
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive
coupling from the input side of
the optocoupler, through the
package, to the detector IC as
T
JE
= P
E
313
C/W + P
D
132
C/W + T
A
= 45 mW
313
C/W + 250 m
W
132
C/W + 70
C = 117
C
T
JD
= P
E
132
C/W + P
D
187
C/W + T
A
= 45 mW
132C/W + 250 m
W
187
C/W + 70
C = 123
C
Figure 27. Energy Dissipated in the
HCPL-3150 for Each IGBT Switching
Cycle.
Esw ENERGY PER SWITCHING CYCLE J
0
0
Rg GATE RESISTANCE
100
3
20
7
40
2
60
80
6
Qg = 100 nC
Qg = 250 nC
Qg = 500 nC
5
4
1
VCC = 19 V
VEE = -9 V
1-209
T
JE
= LED junction temperature
T
JD
= detector IC junction temperature
T
C
= case temperature measured at the center of the package bottom
LC
= LED-to-case thermal resistance
LD
= LED-to-detector thermal resistance
DC
= detector-to-case thermal resistance
CA
= case-to-ambient thermal resistance
CA
will depend on the board design and the placement of the part.
CMR with the LED On
(CMR
H
)
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. A minimum LED cur-
rent of 10 mA provides adequate
margin over the maximum I
FLH
of
5 mA to achieve 15 kV/
s CMR.
CMR with the LED Off
(CMR
L
)
A high CMR LED drive circuit
must keep the LED off
(V
F
V
F(OFF)
) during common
mode transients. For example,
during a -dV
CM
/dt transient in
Figure 31, the current flowing
through C
LEDP
also flows through
the R
SAT
and V
SAT
of the logic
gate. As long as the low state
voltage developed across the
logic gate is less than V
F(OFF)
, the
LED will remain off and no
common mode failure will occur.
The open collector drive circuit,
shown in Figure 32, cannot keep
the LED off during a +dV
CM
/dt
transient, since all the current
flowing through C
LEDN
must be
supplied by the LED, and it is not
recommended for applications
requiring ultra high CMR
L
performance. Figure 33 is an
alternative drive circuit which,
like the recommended application
circuit (Figure 25), does achieve
ultra high CMR performance by
shunting the LED in the off state.
Under Voltage Lockout
Feature
The HCPL-3150 contains an
under voltage lockout (UVLO)
feature that is designed to protect
the IGBT under fault conditions
which cause the HCPL-3150
supply voltage (equivalent to the
fully-charged IGBT gate voltage)
to drop below a level necessary to
keep the IGBT in a low resistance
state. When the HCPL-3150
output is in the high state and the
supply voltage drops below the
HCPL-3150 V
UVLO-
threshold
(9.5 <V
UVLO-
<12.0), the
optocoupler output will go into
the low state with a typical delay,
UVLO Turn Off Delay, of 0.6
s.
When the HCPL-3150 output is in
the low state and the supply
voltage rises above the HCPL-
3150 V
UVLO+
threshold
(11.0 < V
UVLO+
< 13.5), the
optocoupler will go into the high
state (assuming LED is "ON")
with a typical delay, UVLO TURN
On Delay, of 0.8
s.
IPM Dead Time and
Propagation Delay
Specifications
The HCPL-3150 includes a
Propagation Delay Difference
(PDD) specification intended to
help designers minimize "dead
time" in their power inverter
designs. Dead time is the time
period during which both the
high and low side power
transistors (Q1 and Q2 in Figure
25) are off. Any overlap in Q1
and Q2 conduction will result in
large currents flowing through
the power devices from the high-
to the low-voltage motor rails.
To minimize dead time in a given
design, the turn on of LED2
should be delayed (relative to the
Figure 28. Thermal Model.
LD = 439C/W
TJE
TJD
LC = 391C/W
DC = 119C/W
CA = 83C/W*
TC
TA
1-210
turn off of LED1) so that under
worst-case conditions, transistor
Q1 has just turned off when
transistor Q2 turns on, as shown
in Figure 34. The amount of delay
necessary to achieve this condi-
tions is equal to the maximum
value of the propagation delay
difference specification, PDD
MAX
,
which is specified to be 350 ns
over the operating temperature
range of -40
C to 100
C.
Delaying the LED signal by the
maximum propagation delay
difference ensures that the
minimum dead time is zero, but it
does not tell a designer what the
maximum dead time will be. The
maximum dead time is equivalent
to the difference between the
maximum and minimum propaga-
tion delay difference specifica-
tions as shown in Figure 35. The
maximum dead time for the
HCPL-3150 is 700 ns (= 350 ns -
(-350 ns)) over an operating
temperature range of -40
C to
100
C.
Note that the propagation delays
used to calculate PDD and dead
time are taken at equal tempera-
tures and test conditions since
the optocouplers under consider-
ation are typically mounted in
close proximity to each other and
are switching identical IGBTs.
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
C
LEDO1
C
LEDO2
Figure 29. Optocoupler Input to Output
Capacitance Model for Unshielded Optocouplers.
Figure 30. Optocoupler Input to Output
Capacitance Model for Shielded Optocouplers.
Figure 31. Equivalent Circuit for Figure 25 During
Common Mode Transient.
Figure 33. Recommended LED Drive
Circuit for Ultra-High CMR.
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Q1
I
LEDN
Figure 32. Not Recommended Open
Collector Drive Circuit.
Rg
1
3
VSAT
2
4
8
6
7
5
+
VCM
I
LEDP
C
LEDP
C
LEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING dV
CM
/dt.
+5 V
+
VCC = 18 V
0.1
F
+
1-211
tPHL MAX
tPLH MIN
PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
VOUT1
ILED2
VOUT2
ILED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
Figure 34. Minimum LED Skew for Zero Dead Time.
Figure 35. Waveforms for Dead Time.
Figure 36.Under Voltage Lock Out.
V
O
OUTPUT VOLTAGE V
0
0
(VCC - VEE ) SUPPLY VOLTAGE V
10
5
14
10
15
2
20
6
8
4
12
(12.3, 10.8)
(10.7, 9.2)
(10.7, 0.1)
(12.3, 0.1)
Figure 37. Thermal Derating Curve,
Dependence of Safety Limiting Value
with Case Temperature per
VDE 0884.
OUTPUT POWER P
S
, INPUT CURRENT I
S
0
0
TS CASE TEMPERATURE C
200
600
400
25
800
50
75 100
200
150 175
PS (mW)
IS (mA)
125
100
300
500
700
tPLH
MIN
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN)
= (tPHL MAX - tPLH MIN) (tPHL MIN - tPLH MAX)
= PDD* MAX PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
VOUT1
ILED2
VOUT2
ILED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
tPHL MIN
tPHL MAX
tPLH MAX
= PDD* MAX
(tPHL-tPLH) MAX
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