0.4 Amp Output Current
IGBT Gate Drive Optocoupler

Technical Data

HCPL-J314

Features

· 0.4 A Minimum Peak

Output Current

· High Speed Response:

0.7

s Max. Propagation

Delay over Temp. Range

· Ultra High CMR: Min.

10 kV/

s at V

= 1.5 kV

· Bootstrappable Supply

Current: Max. 3 mA

· Wide Operating Temp.

Range: -40

C to 100

· Wide V

Operating Range:

10 V to 30 V over Temp.
Range

· Available in DIP8 (Single)

and SO16 (Dual) Package

· Safety Approvals: UL

Recognized, 3750 V

rms

for

1 Minute. CSA Approval
IEC/EN/DIN EN 60747-5-2
Approval. VIORM=891 V

peak

Applications

· Isolated IGBT/Power

MOSFET Gate Drive

· AC and Brushless DC Motor

Drives

· Inverters for Appliances

· Industrial Inverters

· Switch Mode Power

Supplies (SMPS)

· Uninterruptable Power

Supplies (UPS)

Description

The HCPL-J314 family of devices
consists of an AlGaAs LED
optically coupled to an integrated
circuit with a power output stage.
These optocouplers are ideally
suited for driving power IGBTs
and MOSFETs used in motor
control inverter applications. The
high operating voltage range of
the output stage provides the
drive voltages required by gate
controlled devices. The voltage
and current supplied by this
optocoupler makes it ideally
suited for directly driving small
or medium power IGBTs. For
IGBTs with higher ratings the
HCPL-3150(0.5A) or HCPL-3120
(2.0A) optocouplers can be used.

Functional Diagram

A 0.1

µF bypass capacitor must be connected between pins V

and V

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent
damage and/or degradation which may be induced by ESD.

Truth Table

LED

OFF

LOW

HIGH

SHIELD

N/C

CATHODE

ANODE

N/C

VCC

VEE

HCPL-J314

HCPL-J314 Package Outline Drawings

Standard DIP Package

Gull Wing Surface Mount Option 300

1.080 ± 0.320

(0.043 ± 0.013)

2.54 ± 0.25

(0.100 ± 0.010)

0.51 (0.020) MIN.

0.65 (0.025) MAX.

4.70 (0.185) MAX.

2.92 (0.115) MIN.

5° TYP.

0.254

+ 0.076

- 0.051

(0.010

+ 0.003)

- 0.002)

7.62 ± 0.25

(0.300 ± 0.010)

6.35 ± 0.25

(0.250 ± 0.010)

9.80 ± 0.25

(0.386 ± 0.010)

1.78 (0.070) MAX.

1.19 (0.047) MAX.

HCPL-J314

YYWW

DATE CODE

DIMENSIONS IN MILLIMETERS AND (INCHES).

NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.

3.56 ± 0.13

(0.140 ± 0.005)

0.635 ± 0.25

(0.025 ± 0.010)

12° NOM.

9.65 ± 0.25

(0.380 ± 0.010)

0.51 ± 0.130

(0.020 ± 0.005)

7.62 ± 0.25

(0.300 ± 0.010)

9.80 ± 0.25

(0.386 ± 0.010)

6.350 ± 0.25

(0.250 ± 0.010)

1.02 (0.040)

1.27 (0.050)

10.9 (0.430)

2.0 (0.080)

LAND PATTERN RECOMMENDATION

1.080 ± 0.320

(0.043 ± 0.013)

3.56 ± 0.13

(0.140 ± 0.005)

1.780

(0.070)

MAX.

1.19

(0.047)

MAX.

2.540

(0.100)

BSC

0.255 (0.075)
0.010 (0.003)

NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.

DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01

xx.xxx = 0.005

LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)

HCPL-J314

YYWW

MOLDED

Solder Reflow Temperature Profile

TIME (SECONDS)

TEMPERATURE (

°
C)

200

100

150

100

200

250

300

SEC.

50 SEC.

SEC.

160°C

140°C

150°C

PEAK

TEMP.

245°C

PEAK
TEMP.
240°C

PEAK

TEMP.

230°C

SOLDERING

TIME

200°C

PREHEATING TIME

150°C, 90 + 30 SEC.

2.5°C ± 0.5°C/SEC.

3°C + 1°C/0.5°C

TIGHT
TYPICAL
LOOSE

ROOM

TEMPERATURE

PREHEATING RATE 3°C + 1°C/0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.

Recommended Pb-Free IR Profile

Regulatory Information

The HCPL-J314 has been
approved by the following
organizations:

IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01

UL
Approval under UL 1577,
component recognition program
up to V

ISO

= 3750 V

rms

. File

E55361.

CSA
Approved under CSA Component
Acceptance Notice #5, File CA
88324.

217 °C

RAMP-DOWN
6 °C/SEC. MAX.

RAMP-UP

3 °C/SEC. MAX.

150 - 200 °C

260 +0/-5 °C

t 25 °C to PEAK

60 to 150 SEC.

20-40 SEC.

TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE

PREHEAT

60 to 180 SEC.

Tsmax

Tsmin

TIME

TEMPERA

TURE

NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C

OUTPUT POWER

, INPUT CURRENT

TS CASE TEMPERATURE °C

200

600

400

800

75 100

200

150 175

PS (mW)

125

100

300

500

700

IS (mA)

IEC/EN/DIN EN 60747-5-2 Insulation Characteristics

Description

Symbol

Characteristic

Unit

Installation classification per DIN VDE 0110/1.89, Table 1

for rated mains voltage

150 V

rms

I - IV

for rated mains voltage

300 V

rms

I - III

for rated mains voltage

600 V

rms

I-II

Climatic Classification

55/100/21

Pollution Degree (DIN VDE 0110/1.89)

Maximum Working Insulation Voltage

IORM

891

peak

Input to Output Test Voltage, Method b*

IORM

x 1.875=V

, 100% Production Test with

1670

peak

=1 sec, Partial discharge < 5 pC

Input to Output Test Voltage, Method a*

IORM

x 1.5=V

, Type and Sample Test, t

=60 sec,

1336

peak

Partial discharge < 5 pC

Highest Allowable Overvoltage

IOTM

6000

peak

(Transient Overvoltage t

ini

= 10 sec)

Safety-limiting values - maximum values allowed in the
event of a failure.

Case Temperature

175

°C

Input Current**

S,INPUT

400

Output Power**

S, OUTPUT

1200

Insulation Resistance at T

, V

= 500 V

>10

* Refer to the optocoupler section of the Isolation and Control Components Designer's Catalog, under Product Safety Regulations

section, IEC/EN/DIN EN 60747-5-2 for a detailed description of Method a and Method b partial discharge test profiles.

** Refer to the following figure for dependence of P

and I

on ambient temperature.

Insulation and Safety Related Specifications

Parameter

Symbol HCPL-J314

Units

Conditions

Minimum External Air Gap

L(101) 7.4 mm

Measured from input terminals

(Clearance)

to output terminals, shortest
distance through air.

Minimum External Tracking

L(102) 8.0

Measured from input terminals

(Creepage)

to output terminals, shortest
distance path along body.

Minimum Internal Plastic Gap

0.5 mm

Through insulation distance

(Internal Clearance)

conductor to conductor, usually
the straight line distance
thickness between the emitter
and detector.

Tracking Resistance

CTI >175 V

DIN IEC 112/VDE 0303 Part 1

(Comparative Tracking Index)

Isolation Group

IIIa Material Group (DIN VDE

0110, 1/89, Table 1)

Absolute Maximum Ratings

Parameter

Symbol

Min.

Max.

Units

Note

Storage Temperature

-55

125

°C

Operating Temperature

-40

100

°C

Average Input Current

F(AVG)

Peak Transient Input Current (<1

µs pulse

F(TRAN)

1.0

width, 300pps)

Reverse Input Voltage

"High" Peak Output Current

OH(PEAK)

0.6

"Low" Peak Output Current

OL(PEAK)

0.6

Supply Voltage

-V

-0.5

Output Voltage

O(PEAK)

-0.5

Output Power Dissipation

260

Input Power Dissipation

105

Lead Solder Temperature

260

°C for 10 sec., 1.6 mm below seating plane

Solder Reflow Temperature Profile

See Package Outline Drawings section

Electrical Specifications (DC)

Over recommended operating conditions unless otherwise specified.

Test

Parameter

Symbol

Min.

Typ.

Max.

Units

Conditions

Fig.

Note

High Level Output Current

0.2

Vo = V

- 4

0.4

0.5

Vo = V

-10

Low Level Output Current

0.2

0.4

Vo = V

+2.5

0.4

0.5

Vo = V

+10

High Level Output Voltage

-4

-1.8

Io = -100 mA

6,7

Low Level Output Voltage

0.4

Io = 100 mA

High Level Supply Current

CCH

0.7

Io = 0 mA

7,8

Low Level Supply Current

CCL

1.2

Io = 0 mA

Threshold Input Current

FLH

Io = 0 mA,

9,15

Low to High

Vo>5 V

Threshold Input Voltage

FHL

0.8

High to Low

Input Forward Voltage

1.2

1.5

1.8

= 10 mA

Temperature Coefficient of

-1.6

mV/

°C

Input Forward Voltage

Input Reverse Breakdown

= 10

µA

Voltage

Input Capacitance

f = 1 MHz,
V

= 0 V

Recommended Operating Conditions

Parameter

Symbol

Min.

Max.

Units

Note

Power Supply

-V

Input Current (ON)

F(ON)

Input Voltage (OFF)

F(OFF)

-3.0

0.8

Operating Temperature

- 40

100

°C

Switching Specifications (AC)

Over recommended operating conditions unless otherwise specified.

Test

Parameter

Symbol

Min.

Typ.

Max.

Units

Conditions

Fig.

Note

Propagation Delay Time to

PLH

0.1

0.2

0.7

µs

Rg = 47

10,11,

High Output Level

Cg = 3 nF,

12,13,

Propagation Delay Time to

PHL

0.1

0.3

0.7

µs

f = 10 kHz,

14,17

Low Output Level

Duty Cycle =

Propagation Delay

PDD

-0.5

0.5

µs

50%,

Difference Between Any

F =

8 mA,

Two Parts or Channels

= 30 V

Rise Time

Fall Time

Output High Level Common

|CM

kV/

µs

= 25

°C,

Mode Transient Immunity

= 1.5 kV

Output Low Level Common

|CM

kV/

µs

Mode Transient Immunity

Package Characteristics

For each channel unless otherwise specified.

Test

Parameter

Symbol

Min.

Typ.

Max.

Units

Conditions

Fig.

Note

Input-Output Momentary

ISO

3750

rms

=25

°C,

8,9

Withstand Voltage

RH<50% for

Output-Output Momentary

O-O

1500

rms

1 min.

Withstand Voltage

Input-Output Resistance

I-O

=500 V

Input-Output Capacitance

I-O

1.2

Freq=1 MHz

Notes:

1. Derate linearly above 70

°C free air temperature at a rate of 0.3 mA/°C.

2. Maximum pulse width = 10

µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs

with I

peak minimum = 0.4 A. See Application section for additional details on limiting I

peak.

3. Derate linearly above 85

°C, free air temperature at the rate of 4.0 mW/°C.

4. Input power dissipation does not require derating.
5. Maximum pulse width = 50

µs, maximum duty cycle = 0.5%.

6. In this test, V

is measured with a DC load current. When driving capacitive load V

will approach V

as I

approaches zero

amps.

7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
8. In accordance with UL 1577, each HCPL-J314 optocoupler is proof tested by applying an insulation test voltage

5000 V

rms

for

1 second (leakage detection current limit I

I-O

5 µA). This test is performed before 100% production test for partial discharge

(method B) shown in the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable.

9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.

10. PDD is the difference between t

PHL

and t

PLH

between any two parts or channels under the same test conditions.

11. Common mode transient immunity in the high state is the maximum tolerable |dVcm/dt| of the common mode pulse V

assure that the output will remain in the high state (i.e. Vo > 6.0 V).

12. Common mode transient immunity in a low state is the maximum tolerable |dV

/dt| of the common mode pulse, V

, to assure

that the output will remain in a low state (i.e. Vo < 1.0 V).

13. This load condition approximates the gate load of a 1200 V/25 A IGBT.
14. For each channel. The power supply current increases when operating frequency and Qg of the driven IGBT increases.
15. Device considered a two terminal device: Channel one output side pins shorted together, and channel two output side pins shorted

together.

Figure 1. V

vs. Temperature.

Figure 2. I

vs. Temperature.

Figure 3. V

vs. I

Figure 4. V

vs. Temperature.

Figure 5. I

vs. Temperature.

Figure 6. V

vs. I

Figure 7. I

vs. Temperature.

Figure 8. I

vs. V

Figure 9. I

FLH

vs. Temperature.

-V

)

HIGH OUTPUT VOLTAGE DROP

-50

-2.5

TA TEMPERATURE °C

125

-25

100

-2.0

-1.5

-1.0

-0.5

I OH

OUTPUT HIGH CURRENT

-50

0.30

TA TEMPERATURE °C

125

-25

0.40

100

0.32

0.34

0.36

0.38

-6

IOH OUTPUT HIGH CURRENT A

0.6

0.2

0.4

-5

-4

-3

-1

-V

)

OUTPUT HIGH VOLTAGE DROP

-2

VOH

OUTPUT LOW VOLTAGE

-50

0.39

TA TEMPERATURE °C

125

-25

0.44

100

0.40

0.41

0.42

0.43

I OL

OUTPUT LOW CURRENT

-50

0.440

TA TEMPERATURE °C

125

-25

0.470

100

0.450

0.455

0.460

0.465

0.445

I CC

SUPPLY CURRENT

-50

TA TEMPERATURE °C

125

-25

1.4

100

0.4

0.6

0.8

1.2

0.2

1.0

ICCL
ICCH

I CC

SUPPLY CURRENT

VCC SUPPLY VOLTAGE V

1.2

0.4

0.8

0.2

0.6

1.0

ICCL
ICCH

I FLH

LOW TO HIGH CURRENT THRESHOLD

-50

1.5

TA TEMPERATURE °C

125

-25

3.5

100

2.0

2.5

3.0

OUTPUT LOW VOLTAGE

IOL OUTPUT LOW CURRENT mA

700

100

400 500

200 300

600

Figure 10. Propagation Delay vs. V

Figure 11. Propagation Delay vs. I

Figure 12. Propagation Delay vs.
Temperature.

Figure 13. Propagation Delay vs. Rg.

Figure 14. Propagation Delay vs. Cg.

Figure 15. Transfer Characteristics.

Figure 16. Input Current vs. Forward Voltage.

PROPAGATION DELAY

IF FORWARD LED CURRENT mA

400

100

200

300

-50

TA TEMPERATURE °C

125

-25

500

100

200

300

400

PROPAGATION DELAY

TPLH
TPHL

PROPAGATION DELAY

200

Rg SERIES LOAD RESISTANCE 

200

400

150

100

250

300

350

TPLH
TPHL

I F

FORWARD CURRENT

1.2

VF FORWARD VOLTAGE V

1.8

1.4

1.6

PROPAGATION DELAY

Cg LOAD CAPACITANCE nF

100

400

100

200

300

TPLH
TPHL

PROPAGATION DELAY

VCC SUPPLY VOLTAGE V

400

100

200

300

TPLH
TPHL

OUTPUT VOLTAGE

-5

IF FORWARD LED CURRENT mA

Applications Information

Eliminating Negative IGBT
Gate Drive
To keep the IGBT firmly off,
the HCPL-J314 has a very low
maximum V

specification of

1.0 V. Minimizing Rg and
the lead inductance from the
HCPL-J314 to the IGBT gate and
emitter (possibly by mounting the
HCPL-J314 on a small PC board
directly above the IGBT) can

eliminate the need for negative
IGBT gate drive in many
applications as shown in
Figure 19. Care should be taken
with such a PC board design to
avoid routing the IGBT collector
or emitter traces close to the
HCPL-J314 input as this can
result in unwanted coupling of
transient signals into the input of
HCPL-J314 and degrade
performance. (If the IGBT

drain must be routed near the
HCPL-J314 input, then the LED
should be reverse biased when in
the off state, to prevent the
transient signals coupled from
the IGBT drain from turning on
the HCPL-J314.)

Figure 19. Recommended LED Drive and Application Circuit for HCPL-J314.

+ HVDC

3-PHASE

- HVDC

0.1 µF

VCC = 15 V

HCPL-J314

270

+5 V

CONTROL

INPUT

74XXX

OPEN

COLLECTOR

Selecting the Gate Resistor (Rg)
Step 1: Calculate R

minimum from the I

peak specification. The

IGBT and Rg in Figure 19 can be analyzed as a simple RC circuit with a
voltage supplied by the HCPL-J314.

The V

value of 5 V in the previous equation is the V

at the peak

current of 0.6A. (See Figure 6).

Step 2: Check the HCPL-J314 power dissipation and increase Rg if
necessary. The HCPL-J314 total power dissipation (P

) is equal to the

sum of the emitter power (P

) and the output power (P

= P

+ P

= I

· V

· Duty Cycle

= P

O(BIAS)

+ P

O(SWITCHING)

= I

+ E

(Rg,Qg)

· f

= (I

CCBIAS

+ K

ICC

Qg · f) · V

+ E

(Rg,Qg)

where K

ICC

Qg · f is the increase in I

due to switching and K

ICC

is a

constant of 0.001 mA/(nC*kHz). For the circuit in Figure 19 with I

(worst case) = 10 mA, Rg = 32

, Max Duty Cycle = 80%,

Qg = 100 nC, f = 20 kHz and T

AMAX

= 85

°C:

= 10 mA

· 1.8 V · 0.8 = 14 mW

= (3 mA + (0.001 mA/(nC

· kHz)) · 20 kHz · 100 nC) · 24 V +

0.4

µJ · 20 kHz = 80 mW

< 260 mW (P

O(MAX)

@ 85

°C)

The value of 3 mA for I

in the previous equation is the max. I

over

entire operating temperature range.

Since P

for this case is less than P

O(MAX)

, Rg = 32

is alright for the

power dissipation.

24 V 5 V

0.6A

= 32

Figure 20. Energy Dissipated in the
HCPL-J314 and for Each IGBT
Switching Cycle.

LED Drive Circuit
Considerations for Ultra
High CMR Performance

Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive
coupling from the input side of
the optocoupler, through the
package, to the detector IC
as shown in Figure 21. The
HCPL-J314 improves CMR
performance by using a detector
IC with an optically transparent
Faraday shield, which diverts the
capacitively coupled current away
from the sensitive IC circuitry.
However, this shield does not
eliminate the capacitive coupling
between the LED and opto-
coupler pins 5-8 as shown in
Figure 22. This capacitive
coupling causes perturbations in
the LED current during common
mode transients and becomes the
major source of CMR failures for
a shielded optocoupler. The main
design objective of a high CMR
LED drive circuit becomes
keeping the LED in the proper
state (on or off ) during common
mode transients. For example,
the recommended application
circuit (Figure 19), can achieve
10 kV/

µs CMR while minimizing

component complexity.

Techniques to keep the LED in
the proper state are discussed in
the next two sections.

 V

OLPEAK

Esw

ENERGY PER SWITCHING CYCLE

µJ

Rg GATE RESISTANCE 

100

1.5

4.0

1.0

3.5

Qg = 50 nC

Qg = 100 nC

Qg = 200 nC

Qg = 400 nC

3.0

2.0

0.5

2.5

Figure 21. Optocoupler Input to Output
Capacitance Model for Unshielded Optocouplers.

Figure 22. Optocoupler Input to Output
Capacitance Model for Shielded Optocouplers.

Figure 23. Equivalent Circuit for Figure 17 During Common
Mode Transient.

Figure 24. Not Recommended Open Collector
Drive Circuit.

Figure 25. Recommended LED Drive Circuit for Ultra-High
CMR IPM Dead Time and Propagation Delay Specifications.

LEDP

LEDN

LEDP

LEDN

SHIELD

LEDO1

LEDO2

VSAT

VCM

LEDP

LEDN

SHIELD

* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING dV

/dt.

+5 V

VCC = 18 V

· · ·

0.1
µF

LEDP

LEDN

SHIELD

+5 V

LEDN

LEDP

LEDN

SHIELD

+5 V

CMR with the LED On
(CMR

)

A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. A minimum LED
current of 8 mA provides
adequate margin over the
maximum I

FLH

of 5 mA to

achieve 10 kV/

µs CMR.

CMR with the LED Off
(CMR

)

A high CMR LED drive
circuit must keep the LED off
(V

F(OFF)

) during common

mode transients. For example,
during a -dV

/dt transient in

Figure 23, the current flowing
through C

LEDP

also flows

through the R

SAT

and V

SAT

of the

logic gate. As long as the low
state voltage developed across
the logic gate is less than V

F(OFF)

the LED will remain off and no
common mode failure will occur.

The open collector drive circuit,
shown in Figure 24, can not keep
the LED off during a +dV

/dt

transient, since all the current
flowing through C

LEDN

must be

supplied by the LED, and it is
not recommended for
applications requiring ultra high
CMR

performance. The

alternative drive circuit which
like the recommended
application circuit (Figure 19),
does achieve ultra high CMR
performance by shunting the
LED in the off state.

IPM Dead Time and
Propagation Delay
Specifications
The HCPL-J314 includes a
Propagation Delay Difference
(PDD) specification intended to
help designers minimize "dead
time" in their power inverter
designs. Dead time is the time
high and low side power
transistors are off. Any overlap
in Ql and Q2 conduction will
result in large currents flowing
through the power devices from
the high-voltage to the low-
voltage motor rails. To minimize
dead time in a given design, the
turn on of LED2 should be
delayed (relative to the turn off
of LED1) so that under worst-
case conditions, transistor Q1
has just turned off when
transistor Q2 turns on, as shown
in Figure 26. The amount of

delay necessary to achieve this
condition is equal to the
maximum value of the
propagation delay difference
specification, PDD max, which is
specified to be 500 ns over the
operating temperature range of
-40

° to 100°C.

Delaying the LED signal by the
maximum propagation delay
difference ensures that the
minimum dead time is zero, but it
does not tell a designer what the
maximum dead time will be. The
maximum dead time is equivalent
to the difference between the
maximum and minimum
propagation delay difference
specification as shown in
Figure 27. The maximum dead
time for the HCPL-J314 is 1

µs

(= 0.5

µs - (-0.5 µs)) over the

operating temperature range of
-40

°C to 100°C.

Note that the propagation delays
used to calculate PDD and dead
time are taken at equal
temperatures and test conditions
since the optocouplers under
consideration are typically
mounted in close proximity to
each other and are switching
identical IGBTs.

Figure 26. Minimum LED Skew for Zero Dead Time.

Figure 27. Waveforms for Dead Time.

tPLH

MIN

MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN)
= (tPHL MAX - tPLH MIN) (tPHL MIN - tPLH MAX)
= PDD* MAX PDD* MIN

*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.

VOUT1

ILED2

VOUT2

ILED1

Q1 ON

Q2 OFF

Q1 OFF

Q2 ON

tPHL MIN

tPHL MAX

tPLH MAX

PDD* MAX

(tPHL-tPLH) MAX

tPHL MAX

tPLH MIN

PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN

*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.

VOUT1

ILED2

VOUT2

ILED1

Q1 ON

Q2 OFF

Q1 OFF

Q2 ON

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HCPL-J314

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HCPL-J314