2-178
H
Quadrature Decoder/Counter
Interface ICs
Technical Data
HCTL-2000
HCTL-2016
HCTL-2020
Features
Interfaces Encoder to
Microprocessor
14 MHz Clock Operation
Full 4X Decode
High Noise Immunity:
Schmitt Trigger Inputs Digital
Noise Filter
12 or 16-Bit Binary Up/
Down Counter
Latched Outputs
8-Bit Tristate Interface
8, 12, or 16-Bit Operating
Modes
Quadrature Decoder Output
Signals, Up/Down and Count
Cascade Output Signals, Up/
Down and Count
Substantially Reduced
System Software
ESD WARNING: Standard CMOS handling precautions should be observed with the HCTL-20XX family
ICs.
Devices
Part Number
Description
Package Drawing
HCTL-2000
12-bit counter. 14 MHz clock operation.
A
HCTL-2016
All features of the HCTL-2000. 16-bit counter.
A
HCTL-2020
All features of the HCTL-2016. Quadrature decoder output
B
signals. Cascade output signals.
Description
The HCTL-2000, 2016, 2020 are
CMOS ICs that perform the
quadrature decoder, counter, and
bus interface function. The
HCTL-20XX family is designed to
improve system performance
Applications
Interface Quadrature
Incremental Encoders to
Microprocessors
Interface Digital Potentiom-
eters to Digital Data Input
Buses
5965-5894E
2-179
MOTION SENSING
AND CONTROL
in digital closed loop motion
control systems and digital data
input systems. It does this by
shifting time intensive quadrature
decoder functions to a cost
effective hardware solution. The
entire HCTL-20XX family con-
sists of a 4x quadrature decoder,
a binary up/down state counter,
and an 8-bit bus interface. The
use of Schmitt-triggered CMOS
inputs and input noise filters
allows reliable operation in noisy
environments. The HCTL-2000
contains a 12-bit counter. The
HCTL-2016 and 2020 contain a
16-bit counter. The HCTL-2020
also contains quadrature decoder
output signals and cascade
signals for use with many
standard counter ICs. The HCTL-
20XX family provides LSTTL
compatible tri-state output
buffers. Operation is specified for
a temperature range from -40 to
+85
C at clock frequencies up to
14 MHz.
Package Dimensions
Operating Characteristics
Table 1. Absolute Maximum Ratings
(All voltages below are referenced to V
SS
)
Parameter
Symbol
Limits
Units
DC Supply Voltage
V
DD
-0.3 to +5.5
V
Input Voltage
V
IN
-0.3 to V
DD
+0.3
V
Storage Temperature
T
S
-40 to +125
C
Operating Temperature
T
A
[1]
-40 to +85
C
Table 2. Recommended Operating Conditions
Parameter
Symbol
Limits
Units
DC Supply Voltage
V
DD
+4.5 to +5.5
V
Ambient Temperature
T
A
[1]
-40 to +85
C
19.05
0.25
(0.750
0.010)
15
1.52
0.13
(0.060
0.005)
25.91
0.25
(1.02
0.010)
9.40 (0.370)
15
2-180
Table 3. DC Characteristics V
DD
= 5 V
5%; T
A
= -40 to 85
C
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
V
IL
[2]
Low-Level Input Voltage
1.5
V
V
IH
[2]
High-Level Input Voltage
3.5
V
V
T+
Schmitt-Trigger Positive-
3.5
4.0
V
Going Threshold
V
T-
Schmitt-Trigger Negative-
1.0
1.5
V
Going Threshold
V
H
Schmitt-Trigger Hysteresis
1.0
2.0
V
I
IN
Input Current
V
IN
= V
SS
or V
DD
-10
1
+10
A
V
OH
[2]
High-Level Output
I
OH
-1.6 mA
2.4
4.5
V
Voltage
V
OL
[2]
Low-Level Output
I
OL
= +4.8 mA
0.2
0.4
V
Voltage
I
OZ
High-Z Output Leakage
V
O
= V
SS
or V
DD
-10
1
+10
A
Current
I
DD
Quiescent Supply Current
V
IN
= V
SS
or V
DD
, V
O
= HiZ
1
5
A
C
IN
Input Capacitance
Any Input
[3]
5
pF
C
OUT
Output Capacitance
Any Output
[3]
6
pF
Notes:
1. Free air.
2. In general, for any V
DD
between the allowable limits (+4.5 V to +5.5 V), V
IL
= 0.3 V
DD
and V
IH
= 0.7 V
DD
; typical values are
V
OH
= V
DD
- 0.5 V @ I
OH
= -40
A and V
OL
= V
SS
+ 0.2 V @ I
OL
= 1.6 mA.
3. Including package capacitance.
Figure 2. Waveform for Positive Clock Related Delays.
Figure 1. Reset Waveform.
2-181
MOTION SENSING
AND CONTROL
Functional Pin Description
Table 4. Functional Pin Descriptions
Pin
Pin
Symbol
2000/2016 2020
Description
V
DD
16
20
Power Supply
V
SS
8
10
Ground
CLK
2
2
CLK is a Schmitt-trigger input for the external clock signal.
CHA
7
9
CHA and CHB are Schmitt-trigger inputs which accept the outputs
CHB
6
8
from a quadrature encoded source, such as incremental optical shaft
encoder. Two channels, A and B, nominally 90 degrees out of phase,
are required.
RST
5
7
This active low Schmitt-trigger input clears the internal position
counter and the position latch. It also resets the inhibit logic. RST is
asynchronous with respect to any other input signals.
OE
4
4
This CMOS active low input enables the tri-state output buffers. The
OE and SEL inputs are sampled by the internal inhibit logic on the
falling edge of the clock to control the loading of the internal position
data latch.
SEL
3
3
This CMOS input directly controls which data byte from the position
latch is enabled into the 8-bit tri-state output buffer. As in OE above,
SEL also controls the internal inhibit logic.
SEL
BYTE SELECTED
0
High
1
Low
CNT
DCDR
16
A pulse is presented on this LSTTL-compatible output when the
quadrature decoder has detected a state transition.
U/D
5
This LSTTL-compatible output allows the user to determine whether
the IC is counting up or down and is intended to be used with the
CNT
DCDR
and CNT
CAS
outputs. The proper signal U (high level) or D
(low level) will be present before the rising edge of the CNT
DCDR
and
CNT
CAS
outputs.
CNT
CAS
15
A pulse is presented on this LSTTL-compatible output when the
HCTL-2020 internal counter overflows or underflows. The rising edge
on this waveform may be used to trigger an external counter.
D0
1
1
D1
15
19
D2
14
18
D3
13
17
D4
12
14
D5
11
13
D6
10
12
D7
9
11
NC
6
Not connected - this pin should be left floating.
These LSTTL-compatible tri-state outputs form an 8-bit output port
through which the contents of the 12/16-bit position latch may be read in
2 sequential bytes. The high byte, containing bits 8-15, is read first (on the
HCTL-2000, the most significant 4 bits of this byte are set to 0 internally).
The lower byte, bits 0-7, is read second.
2-182
Switching Characteristics
Table 5. Switching Characteristics Min/Max specifications at V
DD
= 5.0
5%, T
A
= -40 to + 85
C.
Symbol Description
Min.
Max.
Units
1
t
CLK
Clock period
70
ns
2
t
CHH
Pulse width, clock high
28
ns
3
t
CD
[1]
Delay time, rising edge of clock to valid, updated count
65
ns
information on D0-7
4
t
ODE
Delay time, OE fall to valid data
65
ns
5
t
ODZ
Delay time, OE rise to Hi-Z state on D0-7
40
ns
6
t
SDV
Delay time, SEL valid to stable, selected data byte
65
ns
(delay to High Byte = delay to Low Byte)
7
t
CLH
Pulse width, clock low
28
ns
8
t
SS
[2]
Setup time, SEL before clock fall
20
ns
9
t
OS
[2]
Setup time, OE before clock fall
20
ns
10
t
SH
[2]
Hold time, SEL after clock fall
0
ns
11
t
OH
[2]
Hold time, OE after clock fall
0
ns
12
t
RST
Pulse width, RST low
28
ns
13
t
DCD
Hold time, last position count stable on D0-7 after clock rise
10
ns
14
t
DSD
Hold time, last data byte stable after next SEL state change
5
ns
15
t
DOD
Hold time, data byte stable after OE rise
5
ns
16
t
UDD
Delay time, U/D valid after clock rise
45
ns
17
t
CHD
Delay time, CNT
DCDR
or CNT
CAS
high after clock rise
45
ns
18
t
CLD
Delay time, CNT
DCDR
or CNT
CAS
low after clock fall
45
ns
19
t
UDH
Hold time, U/D stable after clock rise
10
ns
20
t
UDCS
Setup time, U/D valid before CNT
DCDR
or CNT
CAS
rise
t
CLK
-45
ns
21
t
UDCH
Hold time, U/D stable after CNT
DCDR
or CNT
CAS
rise
t
CLK
-45
ns
Notes:
1. t
CD
specification and waveform assume latch not inhibited.
2. t
SS
, t
OS
, t
SH
, t
OH
only pertain to proper operation of the inhibit logic. In other cases, such as 8 bit read operations, these setup
and hold times do not need to be observed.
Figure 3. Tri-State Output Timing.
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