Agilent HDMP-1687
Four Channel SerDes Circuit
for Gigabit Ethernet and
Fibre Channel
Data Sheet
Functional Description
The HDMP-1687 is a four channel
SERDES device. HDMP-1687 is in a
208-ball TBGA package with four
1.0625/1.25 Gbps serial I/O. This
integrated circuit provides a low-
cost, low-power, small-form-factor
physical-layer solution for multi-link
Gigabit Ethernet/Fibre Channel
interfaces. This IC may be used to
directly drive copper cables, or it
may be used to interface with opti-
cal transceivers. Each IC contains
transmit and receive channel cir-
cuitry for all four channels.
The transmitter section accepts
10-bit-wide parallel TTL data on
each channel and serializes it into
a high-speed serial stream. The
parallel data is expected to be
8B/10B encoded (or equivalent).
Four banks of parallel data are
latched into the input registers of
the transmitter sections on the ris-
ing edge of RFCT.
Receive data are latched out with
separate clock pins for each chan-
nel. These pins may be single
106.25/125 MHz TTL clock outputs
RC [0:3] [1] or dual 53.125/62.5
MHz TTL pairs RC [0:3] [0:1] to
serve legacy applications where
single SerDes devices were used
before. The receive clock mode
select (RCM0) pin is used to de-
fine the designer's choice.
RCM0 Receive Clock Mode
0
half speed dual clocks
1
full speed single clocks
The SYNC pin enables bytesync
detection on all four channels.
When a comma character is
detected on any channel, its corre-
sponding SYN [0:3] pin goes high.
A single LOOP pin is provided for
all channels to enable the local
loopback function.
HDMP-1687 Block Diagram
The following is a description of
the blocks in each channel. Ex-
cept for the transmit PLL section,
circuits for the channels are inde-
pendent. Figure 1 shows how this
IC may be connected to a protocol
device that controls four channels.
Each channel of the four channel
SERDES (Figure 2) was designed
to transmit and receive 10-bit-
wide characters over dedicated
differential high-speed lines. The
parallel data applied to the trans-
mitter is expected to be encoded
per the 8B/10B encoding scheme,
with special reserve characters for
link management purposes. Other
encoding schemes will also work
as long as they provide dc balance
and sufficient transition density.
In order to accomplish this task,
the SERDES circuitry incorporates
the following:
Features
Four ANSI x3.230- 1994 Fibre Chan-
nel (FC-O) or IEEE 802.3z Gigabit
Ethernet compatible SerDes in
a single package
Supports serial data rates of 1062.5
MBd (Fibre Channel) & 1250 MBd
(Gigabit Ethernet)
Based on X3T11 Fibre Channel
"10 bit specification"
Uses reference clock (RFCT) for Tx
data latching
Half or full speed Rx clocks
5-Volt tolerant TTL I/Os
Low power consumption
208 ball, 23 mm TBGA package
Single +3.3 V power supply
1.5 kV ESD protection on all pins
Equalizers on inputs
Copper drive capability
Buffered line logic outputs
Applications
1250 MBd Gigabit Ethernet high
density ports
1062.5 MBd Fibre Channel interface
Mass storage system I/O channel
Work station/server I/O channel
FC interface for disk drives and
arrays
Serial backplanes
Clusters
2
TTL parallel I/Os
High-speed phase locked loops
Parallel-to-serial converter
High-speed serial clock and
data recovery circuitry
Comma character recognition
circuitry for 8B/10B
Character alignment circuitry
Serial-to-parallel converter
PARALLEL INPUT LATCH
The transmitter accepts 10-bit
wide single-ended TTL parallel
data at inputs TX [0:3] [0:9]. The
RFCT pin is used as transmit byte
clock. The TX [0:3] [0:9] and
RFCT signals must be properly
aligned, as shown in Figure 3.
RFCT is also used as a clean fre-
quency reference for the receiver
PLLs.
TX PLL/CLOCK GENERATOR
The transmitter Phase Locked
Loop and Clock Generator (TX
PLL/CLOCK GENERATOR) block
generates all internal clocks
needed by the transmitter section
to perform its functions. These
clocks are based on the supplied
reference clock (RFCT). RFCT is
used as the frequency reference
clock for the PLL as well as for
the incoming data latches. The
RFCT clock is multiplied by 10 to
generate the serial rate clock
necessary for clocking the high
speed serial outputs.
FRAME MUX
The FRAME MUX accepts the
10-bit wide parallel data from the
INPUT LATCH. Using internally
generated high speed clocks, this
parallel data is multiplexed into
serial data streams. The data bits
are transmitted sequentially, from
TX [0:3] [0] to TX [0:3] [9].
SERIAL OUTPUT SELECT
The OUTPUT SELECT block
provides for an optional internal
loopback of the high speed serial
signal for testing purposes.
In normal operation, LOOP is set
low and the serial data stream is
placed at SO [0:3]
. When
wrap-mode is activated by setting
LOOP high, the SO [0:3]
pins
are held static at logic 1 and the
serial output signal is internally
wrapped to the INPUT SELECT
block of the receiver section.
SERIAL INPUT SELECT
The INPUT SELECT block deter-
mines whether the signal at
SI [0:3]
or the internal loop-
back serial signal is used. In
normal operation, LOOP is set
low and the serial data is ac-
cepted at SI [0:3]
. When LOOP
is set high, the outgoing high
speed serial signal is internally
looped-back from the transmitter
section to the receiver section.
This feature allows parallel
loopback testing, exclusive of the
transmission medium.
RX PLL/CLOCK RECOVERY
The RX PLL/CLOCK RECOVERY
block is responsible for frequency
and phase locking onto the in-
coming serial data stream and
recovering the bit and byte
clocks. The Rx PLL continually
frequency locks onto the refer-
ence clock, and then phase locks
onto the selected input data
stream. The frequency lock part
of the PLL is shared among all
channels. Phase locking is per-
formed separately on each chan-
nel. An internal signal detection
circuit monitors the presence of
the input, and invokes the phase
detection once the minimum
differential input signal level is
supplied (AC Electrical Specifica-
tions). Once bit locked, the re-
ceiver generates the high speed
sampling clock at serial data
rates for the input sampler.
SERIAL INPUT SAMPLER
The INPUT SAMPLER converts
the serial input signal into a high
speed serial bit stream. In order
to accomplish this, it uses the
high speed serial clock recovered
from the RX PLL/CLOCK RECOV-
ERY block. This serial bit stream
is sent to the FRAME DEMUX
AND BYTE SYNC block.
FRAME DEMUX, BYTE SYNC
The FRAME DEMUX, BYTE
SYNC block is responsible for
restoring the 10-bit parallel data
from the high speed serial bit
stream. This block is also re-
sponsible for recognizing the
comma character (K28.5+) of
positive disparity (0011111xxx).
When recognized, the FRAME
DEMUX, CHAR SYNC block
works with the RX PLL/CLOCK
RECOVERY block to properly
select the parallel data edge out
of the bit stream so that the
comma character starts at bit
RX [0:3] [0]. When a comma
character is detected and realign-
ment of the receiver byte clock
RC [0:3] [0:1] is necessary, this
clock is stretched, not slivered, to
the next possible correct align-
ment position. This clock will be
fully aligned by the start of the
second 4-byte ordered set. The
second comma character received
will be aligned with the rising
edge of RC [0:3] [1] and will
follow it with a delay. This delay
guarantees hold time at the re-
ceiving ICs input latches. Comma
characters of positive disparity
must not be transmitted in con-
secutive bytes to allow the re-
ceiver byte clocks to maintain
their proper recovered frequen-
cies.
PARALLEL OUTPUT DRIVERS
The OUTPUT DRIVERS present
the 10-bit parallel recovered data
byte properly aligned to the
receive byte clocks RC [0:3]
[0:1] as shown in Figure 5.
These output data buffers provide
single ended TTL compatible
signals.
3
Figure 1. Typical application using HDMP-1687.
Figure 2. Block diagram of HDMP-1687.
SO0
SI0
SO1
SI1
SI2
SO2
SI3
SO3
4-CHANNEL MAC
RC0
RX0
RFCT
RC1
RX1
RC2
RX2
RC3
RX3
HDMP-1687
TX1
TX0
TX3
TX2
SO [0:3]
TX PLL
CLOCK
GENERATOR
CAP0
LOOP
RFCT
RC[0:3][1]
OUTPUT
DRIVER
INPUT
LATCH
RX [0:3][0:9]
TX[0:3][0:9]
OUTPUT
SELECT
FRAME
MUX
RX PLL
CLOCK
RECOVERY
INPUT
SELECT
FRAME
DEMUX
AND
BYTE SYNC
INPUT
SAMPLER
RC[0:3][0]
CAP1
RX CLOCKS
TX CLOCKS
SYNC
SYN [0:3]
LOOPBACK
SI [0:3]
4
Timing Characteristics for Gigabit Ethernet Transmitter Section
T
= 0
C Ambient to +85
C Case, V
CC
= 3.15 V to 3.45 V
Symbol
Parameter
Units Min.
Typ.
Max.
T
txsetup
Tx Input Setup Time
ns
1.5
T
txhold
Tx Input Hold Time
ns
0.5
t_txlat
[1]
Transmitter Latency
ns
2.3
bits
2.8
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of
the transmit byte clock, RFCT) and the transmission of the first serial bit of that parallel word (defined by the edge of the first bit transmitted).
Figure 3. Transmitter section timing.
Figure 4. Transmitter latency.
TX BYTE C
TX BYTE B
TX [0:3] [0:9]
TX BYTE A
SO [0:3]
TX BYTE B
t_txlat
S5
S6
S7
S8
S9
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S0
S1
S2
S3
S4
S5
RFCT
S6
DATA
DATA
TX [0:3] [0:9]
t
txsetup
t
txhold
RFCT
DATA
DATA
DATA
1.4 V
2.0 V
0.8 V
Timing Characteristics for Fibre Channel Transmitter Section
T
= 0
C Ambient to +85
C Case, V
CC
= 3.15 V to 3.45 V
Symbol
Parameter
Units Min.
Typ.
Max.
T
txsetup
Tx Input Setup Time
ns
2.0
T
txhold
Tx Input Hold Time
ns
1.5
t_txlat
[1]
Transmitter Latency
ns
3.8
bits
4.0
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of
the transmit byte clock, RFCT) and the transmission of the first serial bit of that parallel word (defined by the edge of the first bit transmitted).
5
Figure 5a. Receiver section timing (dual receive clocks).
Timing Characteristics for Gigabit Ethernet Receiver Section
T
= 0
C Ambient to +85
C Case, V
CC
= 3.15 V to 3.45 V
Symbol
Parameter
Units Min.
Typ.
Max.
f_lock
Frequency Lock at Powerup
s
500
b_sync
[1,2]
Bit Sync Time
bits
2500
t
rxsetup
RX [0:3][0:9] Output Setup Time (Data Valid Before Clock)
ns
2.5
t
rxhold
RX [0:3][0:9] Output Hold Time (Data Valid After Clock)
ns
2.0
T
duty
RC [0:3][0] and RC [0:3][1] Duty Cycle
%
40
60
t
A-B
Rising Edge Time Difference between RBC0 and RBC1 (Half Rate) ns
7.5
8.5
t_rxlat
[3]
Receiver Latency
ns
20.7
bits
26.0
Notes:
1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2. Tested using C
PLL
= 0.1
F.
3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the
edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC[0:1]).
DATA
DATA
RX [0:3] [0:9]
t
rxsetup
t
rxhold
RC [0:3] [1]
DATA
DATA
1.4 V
2.0 V
0.8 V
SYNC
RC [0:3] [0]
t
A-B
2.0 V
0.8 V
1.4 V
K28.5+
Timing Characteristics for Fibre Channel Receiver Section
T
= 0
C Ambient to +85
C Case, V
CC
= 3.15 V to 3.45 V
Symbol
Parameter
Units Min.
Typ.
Max.
f_lock
Frequency Lock at Powerup
s
500
b_sync
[1,2]
Bit Sync Time
bits
2500
t
rxsetup
RX [0:3][0:9] Output Setup Time (Data Valid Before Clock)
ns
3.0
t
rxhold
RX [0:3][0:9] Output Hold Time (Data Valid After Clock)
ns
1.5
T
duty
RC [0:3][0] and RC [0:3][1] Duty Cycle
%
40
60
t
A-B
Rising Edge Time Difference between RBC0 and RBC1 (Half Rate) ns
8.9
9.9
t_rxlat
[3]
Receiver Latency
ns
22.4
bits
28.0
Notes:
1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3.
2. Tested using C
PLL
= 0.1
F.
3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the
edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC[0:1]).
PDF 
ZIP