Document Outline

• Table of Contents
• Figures
• Tables
• 1.0 Introduction
  • 1.1 Conventions, Notations and Definitions
  • 1.2 Features
  • 1.3 Applications
  • 1.4 Functional Description
    • 1.4.1 Port A and Port B Interfaces
    • 1.4.2 FIFO Operation
    • 1.4.3 Data Expansion During Compression
      • Figure 1 : Functional Block Diagram
• 2.0 Compression Operation
  • 2.1 Compression Pass Through
  • 2.2 Compression
• 3.0 Decompression Operation
  • 3.1 Decompression Pass Through
  • 3.2 Decompression
  • 3.3 Decompression Output Disabled Mode
• 4.0 Microprocessor Interface and Register Access
  • 4.1 Microprocessor Interface
    • 4.1.1 Interrupts
      • Table 1 : Microprocessor Interface Control Signals
    • 4.1.2 Resets
  • 4.2 Register Access
  • 4.3 Pausing
• 5.0 Port A and Port B Configuration
  • Table 2 : Port A Interface Signals
  • Table 3 : Port B Interface Signals
• 6.0 Register Description
  • 6.1 Status 0 (STAT0)
  • 6.2 Port A Configuration 0 (ACNF0)
  • 6.3 Port A Configuration 1 (ACNF1)
  • 6.4 Port B Configuration 0 (BCNF0)
  • 6.5 Port B Configuration 1 (BCNF1)
  • 6.6 Identification (ID)
  • 6.7 Port A Polarity (APOL)
  • 6.8 Port B Polarity (BPOL)
  • 6.9 Port A Transfer Count (ATC0, ATC1, ATC2, ATC3)
  • 6.10 Port B Transfer Count (BTC0, BTC1, BTC2, BTC3)
  • 6.11 Error Status (ERRS)
  • 6.12 Interrupt Status (INTS)
  • 6.13 Command (CMND)
  • 6.14 Transfer Size (TS0, TS1, TS2, TS3)
  • 6.15 Data Disabled Count (DDC0, DDC1, DDC2, DDC3)
  • 6.16 error mask (EMSK)
  • 6.17 Interrupt Mask (IMSK)
• 7.0 Signal Descriptions
  • 7.1 Microprocessor Interface
  • 7.2 Port A Interface
  • 7.3 Port B Interface
• 8.0 Pinout
  • Figure 2 : Pinout
• 9.0 Electrical Specifications
  • 9.1 Absolute Maximum Ratings
  • 9.2 Recommended Operating Conditions
  • 9.3 DC Specifications
• 10.0 Timing Specifications
  • Figure 3 : Clock Timing
  • Table 4 : Clock Timing
  • Figure 4 : Reset Timing
  • Table 5 : Reset Timing
  • Figure 5 : Almost Full/Almost Empty Timing
  • Table 6 : Almost Full/Almost Empty Timing
  • Figure 6 : Processor Read Timing, MMODE = 1
  • Table 7 : Processor Read Timing, MMODE = 1
  • Figure 7 : Processor Write Timing, MMODE = 1
  • Table 8 : Processor Write Timing, MMODE = 1
  • Figure 8 : Processor Read Timing, MMODE = 0
  • Table 9 : Processor Read Timing, MMODE = 0
  • Figure 9 : Processor Write Timing, MMODE = 0
  • Table 10 : Processor Write Timing, MMODE = 0
  • Figure 10 : Port A/B Timing, Four Edge, Master Mode
  • Table 11 : Port A/B Timing, Four Edge, Master Mode
  • Figure 11 : Port A/B Timing, Four Edge, Slave Mode
  • Table 12 : Port A/B Timing, Four Edge, Slave Mode
  • Figure 12 : Port A/B Timing, Burst, Master Mode
  • Table 13 : Port A/B Timing, Burst, Master Mode
  • Figure 13 : Port A/B Timing, Burst, Slave Mode
  • Table 14 : Port A/B Timing, Burst, Slave Mode
  • Figure 14 : Peripheral Access Read Timing, MMODE = 1
  • Table 15 : Peripheral Access Read Timing, MMODE = 1
  • Figure 15 : Peripheral Access Write Timing, MMODE = 1
  • Table 16 : Peripheral Access Write Timing, MMODE = 1
  • Figure 16 : Peripheral Access Read Timing, MMODE = 0
  • Table 17 : Peripheral Access Read Timing, MMODE = 0
  • Figure 17 : Peripheral Access Write Timing, MMODE = 0
  • Table 18 : Peripheral Access Write Timing, MMODE = 0
• 11.0 Packaging
  • Figure 18 : AHA3520 PQFP Package Specifications
  • Table 19 : PQFP (Plastic Quad Flat Pack) 14 mm � 20 mm Package Dimensions
• 12.0 Ordering Information
  • 12.1 Available Parts
  • 12.2 Part Numbering
• 13.0 AHA Related Technical Publications