The AHA LDPC core technology is covered under multiple patents pending.
Specifications and availability are subject to change. Contact AHA for the latest
information.
comtech aha corporation
comtech aha corporation
PRODUCT BRIEF
AHA4701
30 Mbps LDPC
Low Density Parity Check Code Encoder/Decoder Core
INTRODUCTION
Comtech AHA (AHA) has developed a
configurable and compact Low Density Parity
Check Code (LDPC) core for use in a variety of
Forward Error Correction (FEC) applications. The
core supports numerous codes, modulation schemes
and data rates, which can be changed "on-the-fly" to
accommodate changing channel conditions. AHA's
IP provides an economical solution by obtaining
greater coding gain and placing communications
links closer to the Shannon Limit for Bit-Error-Rate
(BER) performance. AHA delivers this core as an
Altera Stratix 30 "SOF" file, "POF" file or Stratix
netlist.
AHA has a long history of providing leading
edge FEC solutions in silicon for a broad spectrum
of communications links. AHA's "firsts" include a
single chip Reed-Solomon IC release with the
AHA4011 in 1989 and a Turbo Product Code IC
introduction of the AHA4501 in 1998. Since
introducing RS and TPC FEC technology to the
communications markets, AHA has continued the
development of their TPC product line to include
the latest AHA4541, with 16K max block size and a
throughput of 311 Mbps.
LDPC PERFORMANCE
LDPC codes have demonstrated superior bit-
error-rate (BER) performance over many FEC
solutions. LDPC codes, combined with high
iteration performance, provide a BER that is closer
to the Shannon Limit than other available
technologies.
FEATURES
Altera Stratix FPGA Core
Compact, area efficient, low power
Supports "code-change-on-the-fly" allowing
adaptation to changing channel conditions
Exact code rate matching is possible
Field re-programmability that supports multiple
code rates and block sizes
Fully synchronous design style
Configurable design allows trade-offs between
error rate performance and data rate
Data rates up to 30 Mbps supported for 3/4 rate
code
Block sizes up to 30 Kbits
Input quantization up to 6 bits
Internal buffering allows flexible data interface
Programmable up to 256 iterations per block
Additional custom codes available upon request
Concatenated code includes a BCH outer code
Available as ASIC core upon request
Table 1: Partial Code List & Performance
Code Rate
Block Size
Max Data Rate
Es/No@ BER = 10
-7
1/2
16K
20 Mbps
1.39
2/3
16K
25 Mbps
3.29
3/4
16K
30 Mbps
4.32
1/2
30K
20 Mbps
1.2
2/3
30K
25 Mbps
3.15
3/4
30K
30 Mbps
4.21
PB4701_0405
2005 Comtech AHA Corp.
comtech aha corporation
comtech aha corporation
1126 Alturas Drive
fax: 208.892.5601
tel: 208.892.5600
e-mail: sales@aha.com
www.aha.com
Moscow, ID 83843-8331
A subsidiary of Comtech Telecommunications Corporation
Figure 1:
LDPC Core (block diagram)
FUNCTIONAL DESCRIPTION
The LDPC core operates as a flow-through
device in a data path architecture. The input and
output data flow is controlled with synchronous
handshaking for each transfer. Internal buffering
provides flexibility in the input and output data
transfer rates. Data transfers can either be a
continuous stream or intermittent bursts or a
combination of the two.
The core's performance and code can be
changed as needed by the system "on-the-fly"
without interruption to the data stream.
DELIVERABLES
Altera Stratix 30 SOF/POF files or Altera Stratix
netlist
Complete documentation
Test bench/Test vectors
ORDERING INFORMATION
ABOUT AHA
Comtech AHA Corporation (AHA) develops
and markets superior integrated circuits, boards,
and intellectual property core technology for
communications systems architects worldwide.
AHA has been setting the standard in Forward
Error Correction and Lossless Data Compression
technology for many years and provides flexible,
cost-effective solutions for today's growing
bandwidth and reliability challenges. Comtech
AHA Corporation is a wholly owned subsidiary of
Comtech Telecommuncations Corp. (NASDAQ:
CMTL). For more information, visit www.aha.com.
Encode
Output
Decode
Output
Decode
Input
LDPC
LDPC
UDATA
URDY
UACPT
CLK
CSN
WRN
RDN
A[6:0]
D[7:0]
DSTART
DDATA
DRDY
DACPT
ESTART
EDATA
ERDY
EACPT
CDATA_I[5:0]
CSTART
CRDY
CDATA_Q[5:0]
CACPT
RESET
Control
Port
ENCODER
Encode
Input
BCH
DECODER
ENCODER
DECODER
BCH
PART NUMBER
DESCRIPTION
AHA4701
30 Mbps LDPC Core
PDF 
ZIP