ASAHI KASEI
[AK4112A]
MS0020-E-00
2000/3
- 1 -
GENERAL DESCRIPTION
The AK4112A is a digital audio receiver (DIR) compatible with 96kHz, 24bits. The channel status
decoding supports both consumer and professional modes. The AK4112A can automatically detect a
Non-PCM bit stream. When combined with an AK4527 multi channel codec, the two chips provide a
system solution for AC-3 applications. The dedicated pins or a serial uP I/F can control the mode setting.
The small package, 28pin VSOP saves the board space.
*AC-3 is a trademark of Dolby Laboratories.
FEATURES
o
Supports AES/EBU, IEC958, S/PDIF, EIAJ CP1201
o
Low jitter Analog PLL
o
PLL Lock Range : 22k~108kHz
o
Clock Source: PLL or X'tal
o
4 channel Receivers input and 1 through transmission output
o
Auxiliary digital input
o
De-emphasis for 32kHz, 44.1kHz, 48kHz and 96kHz
o
Dedicated Detect Pins
Non-PCM Bit Stream Detect Pin
Validity Flag Detect Pin
96kHz Sampling Detect Pin
Unlock & Parity Error Detect Pin
o
Supports up to 24bit Audio Data Format
o
Audio I/F: Master or Slave Mode
o
32bits Channel Status Buffer
o
Burst Preamble bit Pc, Pd Buffer for Non-PCM bit stream
o
Serial P I/F
o
Two Master Clock Outputs:128fs/256fs/512fs
o
Operating Voltage: 2.7 to 3.6V with 5V tolerance
o
Small Package: 28pin VSOP
o
Ta: -40~85
C
High Feature 96kHz 24bit DIR
AK4112A
ASAHI KASEI
[AK4112A]
MS0020-E-00
2000/3
- 2 -
n
n
n
n
Compatibility with AK4110
AK4110
AK4112A
Ambient Temperature
-20 ~ 85
C
-40 ~ 85
C
AVDD, DVDD
3.0 ~ 3.6V
2.7 ~ 3.6V
fs
32kHz ~ 96kHz
22kHz ~ 108kHz
Crystal resonator (max)
12.288MHz
24.576MHz
Clock Operation Mode 3
X
O
Parallel Control Mode
X
O
TX output
X
O
512fs output
X
O
384fs output
O
X
Burst Preamble Pc, Pd buffers
X
O
(0DH ~ 10H)
FS96 output select in X'tal Mode
X
O
(11H D0; XFS96)
ERF hold time
fixed (1028/fs)
selectable (512, 1024, 2048, 4096/fs)
(11H D2, D1; ERH1, ERH0)
Input data format of DAUX
Mode5 and 7
not available
I
2
S
Pin #7
R
PDN
Pin #8
DAUX
R
Pin #22
PDN
DAUX
Resistor on R pin
9.1k
W
18k
W
Capacitor on R pin
No need
No need (
100pF)
O: Available, X: Not available
ASAHI KASEI
[AK4112A]
MS0020-E-00
2000/3
- 5 -
PIN/FUNCTION
No.
Pin Name
I/O
Function
1
DVDD
-
Digital Power Supply Pin, 3.3V
2
DVSS
-
Digital Ground Pin
3
TVDD
-
Input Buffer Power Supply Pin, 3.3V or 5V
V
O
Validity Flag Output Pin in Parallel Mode
4
TX
O
Transmit channel (through data) Output Pin in Serial Mode
5
XTI
I
X'tal Input Pin
6
XTO
O
X'tal Output Pin
7
PDN
I
Power-Down Mode Pin
When "L", the AK4112A is powered-down and reset.
8
R
-
External Resistor Pin
18k
W +/-1% resistor to AVSS externally.
9
AVDD
-
Analog Power Supply Pin
10
AVSS
-
Analog Ground Pin
11
RX1
I
Receiver Channel 1
This channel is selected in Parallel Mode or default of Serial Mode.
DIF0
I
Audio Data Interface Format 0 Pin in Parallel Mode
12
RX2
I
Receiver Channel 2 in Serial Mode
DIF1
I
Audio Data Interface Format 1 Pin in Parallel Mode
13
RX3
I
Receiver Channel 3 in Serial Mode
DIF2
I
Audio Data Interface Format 2 Pin in Parallel Mode
14
RX4
I
Receiver Channel 4 in Serial Mode
15
AUTO
O
Non-PCM Detect Pin
"L": No detect, "H" : Detect
16
P/S
I
Parallel/Serial Select Pin
"L": Serial Mode, "H": Parallel Mode
17
FS96
O
96kHz Sampling Detect Pin
(RX Mode) "H" : fs=88.2kHz or more, "L" fs=54kHz or less.
(X'tal Mode) "H" : XFS96=1, "L" : XFS96=0.
18
ERF
O
Unlock & Parity Error Output Pin
"L": No Error, "H": Error
19
LRCK
I/O
Output Channel Clock Pin
20
SDTO
O
Audio Serial Data Output Pin
21
BICK
I/O
Audio Serial Data Clock Pin
22
DAUX
I
Auxiliary Audio Data Input Pin
23
MCK02
O
Master Clock #2 Output Pin
24
MCK01
O
Master Clock #1 Output Pin
OCKS0
I
Output Clock Select 0 Pin in Parallel Mode
25
CSN
I
Chip Select Pin in Serial Mode
OCKS1
I
Output Clock Select 1 Pin in Parallel Mode
26
CCLK
I
Control Data Clock Pin in Serial Mode
CM1
I
Master Clock Operation Mode Pin0 in Parallel Mode
27
CDTI
I
Control Data Input Pin in Serial Mode
CM0
I
Master Clock Operation Mode Pin1 in Parallel Mode
28
CDTO
O
Control Data Output Pin in Serial Mode
Note 1: All input pins except internal pull-down pins should not be left floating.
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