ASAHI KASEI
[AK4114]
MS0098-E-04
2004/03
- 1 -
GENERAL DESCRIPTION
The AK4114 is a digital audio transceiver supporting 192kHz, 24bits. The channel status decoder
supports both consumer and professional modes. The AK4114 can automatically detect a Non-PCM bit
stream. When combined with the multi channel codec (AK4527B or AK4529), the two chips provide a
system solution for AC-3 applications. The dedicated pins or a serial P I/F can control the mode setting.
The small package, 48pin LQFP saves the system space.
*AC-3 is a trademark of Dolby Laboratories.
FEATURES
AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible
Low jitter Analog PLL
PLL Lock Range : 32kHz to 192kHz
Clock Source: PLL or X'tal
8-channel Receiver input
2-channel Transmission output (Through output or DIT)
Auxiliary digital input
De-emphasis for 32kHz, 44.1kHz, 48kHz and 96kHz
Detection Functions
Non-PCM Bit Stream Detection
DTS-CD Bit Stream Detection
Sampling Frequency Detection
(32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz)
Unlock & Parity Error Detection
Validity Flag Detection
Up to 24bit Audio Data Format
Audio I/F: Master or Slave Mode
40-bit Channel Status Buffer
Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream
Q-subcode Buffer for CD bit stream
Serial P I/F
Two Master Clock Outputs: 64fs/128fs/256fs/512fs
Operating Voltage: 2.7 to 3.6V with 5V tolerance
Small Package: 48pin LQFP
Ta: -10 to 70
C
AK4114
High Feature 192kHz 24bit Digital Audio Interface Transceiver
ASAHI KASEI
[AK4114]
MS0098-E-04
2004/03
- 2 -
Input
Selector
Clock
Recovery
Clock
Generator
DAIF
Decoder
AC-3/MPEG
Detect
DEM
P I/F
Audio
I/F
X'tal
Oscillator
PDN
INT0
P/S="L"
LRCK
BICK
SDTO
DAUX
MCKO2
XTO
XTI
R
AVDD
AVSS
CDTI
CDTO
CCLK
CSN
DVDD
DVSS
TVDD
MCKO1
IIC
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
DIT
TX0
Error &
Detect
STATUS
INT1
Q-subcode
buffer
TX1
B,C,U,VOUT
8 to 3
VIN
Serial Control Mode
Input
Selector
Clock
Recovery
Clock
Generator
DAIF
Decoder
AC-3/MPEG
Detect
DEM
Audio
I/F
X'tal
Oscillator
PDN
INT0
P/S="H"
LRCK
BICK
SDTO
DAUX
XTO
XTI
R
AVDD
AVSS
CM1
CM0
OCKS1
OCKS0
DVDD
DVSS
TVDD
IPS1
RX0
RX1
RX2
RX3
IPS0
DIF0
DIF1
DIF2
DIT
TX0
Error &
Detect
STATUS
INT1
TX1
B,C,U,VOUT
4 to 2
VIN
MCKO2
MCKO1
Parallel Control Mode
ASAHI KASEI
[AK4114]
MS0098-E-04
2004/03
- 3 -
Ordering Guide
AK4114VQ -10 ~ +70
C
48pin
LQFP
(0.5mm
pitch)
Pin Layout
IPS0/RX4
RX
3
1
AVSS
48
2
DIF0/RX5
3
TEST2
4
DIF1/RX6
5
AVSS
6
DIF2/RX7
7
IPS1/IIC
8
P/SN
9
XTL0
10
XTL1
A
VSS
47
RX
2
46
45
44
A
VSS
43
RX
0
42
A
VSS
41
VC
O
M
40
R
39
AV
D
D
38
TV
D
D
1
3
NC
14
TX
0
15
TX
1
16
BO
U
T
17
18
UO
U
T
19
VO
U
T
20
DV
DD
21
DV
S
S
22
MC
KO
1
23
36
35
34
33
32
31
30
29
28
27
26
INT0
OCKS0/CSN/CAD0
OCKS1/CCLK/SCL
CM1/CDTI/SDA
CM0/CDTO/CAD1
PDN
XTI
XTO
DAUX
MCKO2
BICK
AK4114VQ
Top View
CO
U
T
TE
S
T
1
RX
1
IN
T
1
37
LRC
K
24
11
VIN
12
25
SDTO
ASAHI KASEI
[AK4114]
MS0098-E-04
2004/03
- 4 -
PIN/FUNCTION
No. Pin
Name
I/O
Function
IPS0
I
Input Channel Select 0 Pin in Parallel Mode
1
RX4
I
Receiver Channel 4 Pin in Serial Mode (Internal biased pin)
2 NC(AVSS)
I
No Connect
No internal bonding. This pin should be connected to AVSS.
DIF0
I
Audio Data Interface Format 0 Pin in Parallel Mode
3
RX5
I
Receiver Channel 5 Pin in Serial Mode (Internal biased pin)
4 TEST2
I
TEST 2 pin
This pin should be connect to AVSS.
DIF1
I
Audio Data Interface Format 1 Pin in Parallel Mode
5
RX6
I
Receiver Channel 6 Pin in Serial Mode (Internal biased pin)
6 NC(AVSS)
I
No Connect
No internal bonding. This pin should be connected to AVSS.
DIF2
I
Audio Data Interface Format 2 Pin in Parallel Mode
7
RX7
I
Receiver Channel 7 Pin in Serial Mode (Internal biased pin)
IPS1
I
Input Channel Select 1 Pin in Parallel Mode
8
IIC I
IIC Select Pin in Serial Mode.
"L": 4-wire Serial, "H": IIC
9 P/SN
I
Parallel/Serial Select Pin
"L": Serial Mode, "H": Parallel Mode
10
XTL0
I
X'tal Frequency Select 0 Pin
11
XTL1
I
X'tal Frequency Select 1 Pin
12
VIN
I
V-bit Input Pin for Transmitter Output
13
TVDD
I
Input Buffer Power Supply Pin, 3.3V or 5V
14 NC
I
No Connect
No internal bonding. This pin should be open or connected to DVSS.
15
TX0
O
Transmit Channel (Through Data) Output 0 Pin
16 TX1
O
When TX bit = "0", Transmit Channel (Through Data) Output 1 Pin.
When TX bit = "1", Transmit Channel (DAUX Data) Output Pin (Default).
17 BOUT
O
Block-Start Output Pin for Receiver Input
"H" during first 40 flames.
18
COUT
O
C-bit Output Pin for Receiver Input
19
UOUT
O
U-bit Output Pin for Receiver Input
20
VOUT
O
V-bit Output Pin for Receiver Input
21
DVDD
I
Digital Power Supply Pin, 3.3V
22
DVSS
I
Digital Ground Pin
23
MCKO1
O
Master Clock Output 1 Pin
24 LRCK
I/O Channel
Clock
Pin
25
SDTO
O
Audio Serial Data Output Pin
26
BICK
I/O
Audio Serial Data Clock Pin
27
MCKO2
O
Master Clock Output 2 Pin
28
DAUX
I
Auxiliary Audio Data Input Pin
29
XTO
O
X'tal Output Pin
30 XTI
I X'tal
Input
Pin
ASAHI KASEI
[AK4114]
MS0098-E-04
2004/03
- 5 -
PIN/FUNCTION (Continued)
No. Pin
Name
I/O
Function
31 PDN
I
Power-Down Mode Pin
When "L", the AK4114 is powered-down and reset.
CM0
I
Master Clock Operation Mode 0 Pin in Parallel Mode
CDTO
O
Control Data Output Pin in Serial Mode, IIC= "L".
32
CAD1
I
Chip Address 1 Pin in Serial Mode, IIC= "H".
CM1
I
Master Clock Operation Mode 1 Pin in Parallel Mode
CDTI
I
Control Data Input Pin in Serial Mode, IIC= "L".
33
SDA
I/O
Control Data Pin in Serial Mode, IIC= "H".
OCKS1
I
Output Clock Select 1 Pin in Parallel Mode
CCLK
I
Control Data Clock Pin in Serial Mode, IIC= "L"
34
SCL
I
Control Data Clock Pin in Serial Mode, IIC= "H"
OCKS0
I
Output Clock Select 0 Pin in Parallel Mode
CSN
I
Chip Select Pin in Serial Mode, IIC="L".
35
CAD0
I
Chip Address 0 Pin in Serial Mode, IIC= "H".
36
INT0
O
Interrupt 0 Pin
37
INT1
O
Interrupt 1 Pin
38
AVDD
I
Analog Power Supply Pin, 3.3V
39 R
-
External Resistor Pin
18k
+/-1% resistor should be connected to AVSS externally.
40 VCOM
-
Common Voltage Output Pin
0.47F capacitor should be connected to AVSS externally.
41
AVSS
I
Analog Ground Pin
42 RX0
I
Receiver Channel 0 Pin (Internal biased pin)
This channel is default in serial mode.
43 NC(AVSS)
I
No Connect
No internal bonding. This pin should be connected to AVSS.
44
RX1
I
Receiver Channel 1 Pin (Internal biased pin)
45 TEST1
I
TEST 1 pin.
This pin should be connected to AVSS.
46
RX2
I
Receiver Channel 2 Pin (Internal biased pin)
47 NC(AVSS)
I
No Connect
No internal bonding. This pin should be connected to AVSS.
48
RX3
I
Receiver Channel 3 Pin (Internal biased pin)
Note 1. All input pins except internal biased pins should not be left floating.
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