ASAHI KASEI
[AK4351]
M0022-E-04
1999/12
- 1 -
GENERAL DESCRIPTION
The AK4351 is a high cost performance 18bit stereo DAC for low-end digital audio systems. The
modulator in the AK4351 uses the new developed Advanced Multi Bit architecture with wide dynamic
range. The analog outputs are filtered in the analog domain by a combination of SCF and CTF.
Therefore, any external filters are not required. The SCF techniques also improve the loss of accuracy
from clock jitter. Therefore, the AK4351 is suitable for the system like STB including PLL circuit. The
AK4351 is available in very small 16pin TSSOP package, which reduces system space.
FEATURES
Sampling Rate Ranging from 8kHz to 50kHz
128 times Oversampling
Perfect filtering
18bit 8 times FIR Interpolator with 57dB attenuation
2nd order LPF
Total Response:
0.2dB at 20kHz
On chip Buffer with Single End Output
Digital de-emphasis for 44.1kHz sampling
I/F format: MSB justified, 16/18bit LSB justified or I
2
S
Master clock: 256fs or 384fs
TTL Level Digital Interface
THD+N: -88dB
D-Range: 96dB
High Tolerance to Clock Jitter
Power supply: 4.5 to 5.5V
Very Small Package: 16pin TSSOP (6.4mm x 5.0mm)
DS
Modulator
CKS
LRCK
AOUTL
PD
8X
Interpolator
Clock Divider
LPF
BICK
SDATA
Serial Input
Interface
MCLK
VDD
VSS
VCOM
DEM
TST
DS
Modulator
AOUTR
8X
Interpolator
LPF
VREF
De-emphasis
Control
DIF1
DIF0
18Bit Advanced Multi Bit
DS
2ch DAC
AK4351
ASAHI KASEI
[AK4351]
M0022-E-04
1999/12
- 2 -
n
Ordering Guide
AK4351VT
-40
~ +85C
16pin TSSOP (0.65mm pitch)
AKD4351
Evaluation Board for AK4351
n
Pin Layout
1
DIF1
LRCK
SDATA
BICK
MCLK
DEM
CKS
Top
View
2
3
4
5
6
7
8
DIF0
VSS
VREF
VDD
VCOM
AOUTL
AOUTR
TST
16
15
14
13
12
11
10
9
PD
PIN/FUNCTION
No.
Pin Name
I/O
Function
1
DIF1
I
Digital Input Format Pin (Internal Pull-down pin)
2
LRCK
I
L/R Clock Pin
3
BICK
I
Audio Serial Data Clock Pin
4
SDATA
I
Audio Serial Data Input Pin
5
PD
I
Power-Down Mode Pin
When at "L", the AK4351 is in power-down mode and is held in reset.
The AK4351 should always be reset upon power-up.
6
MCLK
I
Master Clock Input Pin
An external TTL clock should be input on this pin.
7
DEM
I
De-emphasis Enable Pin
When at "H", de-emphasis of fs=44.1kHz is enabled.
8
CKS
I
Master Clock Select Pin (Internal Pull-down pin)
"L": MCLK=256fs, "H": MCLK=384fs
9
TST
O
Test Pin
Must be left floating.
10
AOUTR
O
Rch Analog Output Pin
11
AOUTL
O
Lch Analog Output Pin
12
VCOM
O
Common Voltage Pin, VDD/2
Normally connected to VSS with a 0.1F ceramic capacitor in parallel with
a 10F electrolytic cap.
13
VREF
I
Voltage Reference Input Pin
The differential Voltage between this pin and VSS set the analog output range.
Normally connected to VDD.
14
VDD
-
Power Supply Pin
15
VSS
-
Ground Pin
16
DIF0
I
Digital Input Format Pin (Internal Pull-down pin)
Note: All input pins except pull-down pins should not be left floating.
ASAHI KASEI
[AK4351]
M0022-E-04
1999/12
- 3 -
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter
Symbol
min
max
Units
Power Supply
VDD
-0.3
6.0
V
Input Current, Any Pin Except Supplies
IIN
-
10
mA
Input Voltage
VIND
-0.3
VDD+0.3
V
Ambient Operating Temperature
Ta
-40
85
C
Storage Temperature
Tstg
-65
150
C
Note:1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Symbol
min
typ
max
Units
Power Supply
VDD
4.5
5.0
5.5
V
Voltage Reference (Note 2)
VREF
3.0
-
VDD
V
Note:2. Analog output voltage scales with the voltage of VREF.
AOUT (typ.@0dB)=3.45Vpp*VREF/5.
*AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
ASAHI KASEI
[AK4351]
M0022-E-04
1999/12
- 4 -
ANALOG CHARACTERISTICS
(Ta=25
C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 18bit Input Data;
Measurement frequency=10Hz
~ 20kHz; R
L
5kW; unless otherwise specified)
Parameter
min
typ
max
Units
Resolution
18
Bits
Dynamic Characteristics (Note 3)
THD+N (0dB Output)
-88
-80
dB
Dynamic Range (-60dB Output, A-weight)
90
96
dB
S/N (A-weight)
90
96
dB
Interchannel Isolation (1kHz)
96
100
dB
Interchannel Gain Mismatch
0.2
0.5
dB
DC Accuracy
Gain Drift
100
-
ppm/
C
Output Voltage (Note 4)
3.20
3.45
3.70
Vpp
Load Resistance
5
k
W
Output Current
400
A
Power Supplies
Power Supply Current
Normal Operation ( PD ="H")
VDD
Power-Down Mode ( PD ="L")
VDD (Note 5)
14
10
20
50
mA
A
Power Dissipation (VDD)
Normal Operation
Power-Down Mode (Note 5)
70
50
100
250
mW
W
Power Supply Rejection (Note 6)
40
dB
Note: 3. Measured by AD725C (SHIBASOKU). Averaging mode. Refer to the evaluation board manual.
4.
Full-scale voltage (0dB). Output voltage scales with the voltage of VREF.
AOUT (typ.@0dB)=3.45Vpp*VREF/5.
5. Power Dissipation in the power-down mode is applied with no external clocks
(MCLK, BICK and LRCK held "VDD" or "VSS").
6. PSR is applied to VDD with 1kHz, 100mVpp. VREF pin is held +5V.
ASAHI KASEI
[AK4351]
M0022-E-04
1999/12
- 5 -
FILTER CHARACTERISTICS
(Ta=25
C; VDD=4.5 ~ 5.5V; fs=44.1kHz; DEM="L")
Parameter
Symbol
min
typ
max
Units
Digital filter
Passband
0.05dB (Note 7)
-6.0dB
PB
0
-
22.05
20.0
-
kHz
kHz
Stopband (Note 7)
SB
24.1
kHz
Passband Ripple
PR
0.02
dB
Stopband Attenuation
SA
54
dB
Group Delay (Note 8)
GD
-
19.1
-
1/fs
Digital Filter + LPF
Frequency Response 0
~ 20.0kHz
-
0.2
-
dB
Note: 7. The passband and stopband frequencies scale with fs.
For example, PB=0.4535*fs (@
0.05dB), SB=0.546*fs.
8. The calculating delay time which occurred by digital filtering. This time is from setting the 16/18bit data of both
channels to input register to the output of analog signal.
DIGITAL CHARACTERISTICS
(Ta=25
C; VDD=4.5 ~ 5.5V)
Parameter
Symbol
min
typ
max
Units
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
2.2
-
-
-
-
0.8
V
V
High-Level Output Voltage (Iout=-80A)
Low-Level Output Voltage (Iout=80A)
VOH
VOL
VDD-0.4
-
-
-
0.4
V
V
Input Leakage Current (Note 9)
Iin
-
-
10
A
Note: 9. DIF0, DIF1 and CKS pins have internal pull-down devices, normally 100k
W.
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