ASAHI KASEI
[AK4620A]
MS0368-E-00
2004/12
- 1 -
GENERAL DESCRIPTION
The AK4620A is a high performance 24-bit CODEC that supports up to 192kHz record and playback. The
on-board analog-to-digital converter has a high dynamic range due to AKM's Enhanced Dual-Bit
architecture. The DAC utilizes AKM's Advanced Multi-Bit architecture that achieves low out-of-band noise
and high jitter tolerance through the use of Switched Capacitor Filter (SCF) technology. The AK4620A has
an input Programmable Gain Amplifier and is ideal for Pro Audio sound cards, Digital Audio Workstations,
DVD-R, hard disk, CD-R recording/playback systems, and musical instrument recording.
FEATURES
24-bit 2-channel ADC
- Selectable Single-ended or Differential Input
- High Performance Linear Phase Digital Anti-Alias Filter
Passband: 0 ~ 20.25kHz (@fs=44.1kHz)
Ripple: 0.005dB
Stopband Attenuation: 100dB
- S/(N+D): 92dB (single-ended)
100dB (differential)
- S/N: 110dB (single-ended)
113dB (differential)
- Digital High-pass Filter for Offset Cancellation
- Input PGA: 0dB to +18dB, 0.5dB/step (for single-ended input)
- Input Digital Attenuator: 0dB to 63dB, 0.5dB/step
- Overflow Flag
- Audio Interface Format: MSB justified or I
2
S
24-bit 2-channel DAC
- 24-bit 8 times Oversampling Linear Phase Digital Filter
Ripple: 0.005dB
Stopband Attenuation: 75dB
- Switched-cap Low Pass Filter
- Differential Outputs
- S/(N+D): 100dB
- S/N: 115dB
- De-emphasis for 32kHz, 44.1kHz, 48kHz Sampling
- Output Digital Attenuator: Linear 255 steps
- Soft Mute
- Zero Detection Function
- Audio interface format: MSB justified, LSB justified, I
2
S, or DSD
High Jitter Tolerance
Sampling Rate: Up to 216kHz
P Interface: 3-wire Serial Interface
Master Clock
- 128fs/192fs/256fs/384fs/512fs/768fs/1024fs
Power Supply: 5V 5%(Analog), 3V~3.6V with 5V tolerant I/O(Digital)
Small 30-pin VSOP package
Ta: -10 to 70
C
24-Bit 192kHz Audio CODEC with IPGA
AK4620A
ASAHI KASEI
[AK4620A]
MS0368-E-00
2004/12
- 2 -
Block Diagram
AINL+
VCOM
AOUTL+
AOUTL-
AOUTR-
AOUTR+
CSN/
DIF
CCLK/
CKS1
CDTI/
CKS0
SDTI
SDTO
BICK
LRCK
DGND
VT
VD
ADC
DAC
HPF
DATT
SMUTE
Audio I/F
Controller
Control Register I/F
PDN
MCLK
OVFL/DZFL
VREF
VA
AGND
OVFR/DZFR
AINL-/NC
AINR+
AINR-/NC
ADMODE
DFS0
DEM0
P/S
DATT
OVF
Figure 1. Block Diagram
Compatibility with AK4528 / AK4524
Function AK4524
AK4528 AK4620A
Max fs
96kHz
108kHz
216kHz
ADC
Inputs
Single-ended Differential Single-ended Differential
Input analog PGA
0dB ~ +18dB
0.5dB/step
-
0 ~ +18dB
0.5dB/step
-
Input digital ATT
Mute, -72dB ~ 0dB
Pseudo-log step
Mute, -72dB ~ 0dB
Pseudo-log step
Mute,-63.5dB ~ 0dB
0.5dB/step
Mute,-63.5dB ~ 0dB
0.5dB/step
ADC S/(N+D)
90dB
94dB
92dB
100dB
ADC
DR,
S/N
100dB 108dB 110dB 113dB
ADC Digital Filter SA 75dB
75dB
100dB
ADC Overflow detection
-
-
X
DAC S/(N+D)
94dB
94dB
100dB
DAC DR, S/N
110dB
110dB
115dB
Output digital Attenuator
Mute, -72dB ~ 0dB
Pseudo-log step
Mute, -72dB ~ 0dB
Pseudo-log step
Mute, -48dB ~ 0dB
Linear 256 steps
Mute, -48dB ~ 0dB
Linear 256 steps
DAC DSD mode
-
-
X
DAC Zero-data detection
-
-
X
X'tal Oscillating Circuit
X
-
-
Master Mode
X
-
-
Parallel Mode
-
X
X
X: Available, -: NOT available
ASAHI KASEI
[AK4620A]
MS0368-E-00
2004/12
- 3 -
Ordering Guide
AK4620AVF
-10
+70C 30pin
VSOP
(0.65mm
pitch)
AKD4620A Evaluation
Board
Pin Layout
6
5
4
3
2
1
VCOM
AINR+
AINL+
AINR-/NC
AINL-/NC
VREF
AGND 7
VA
8
Top
View
10
9
P/S
MCLK
LRCK/DSDR
11
BICK/DCLK 12
13
14
SDTO
SDTI/DSDL
AOUTR+
AOUTR-
AOUTL+
AOUTL-
DGND
VD
VT
ADMODE
DEM0
PDN
DFS0
CSN/DIF
25
26
27
28
29
30
24
23
21
22
20
19
18
17
CCLK/CKS1
CDTI/CKS0
15
OVFR/DZFR
16
OVFL/DZFL
ASAHI KASEI
[AK4620A]
MS0368-E-00
2004/12
- 4 -
PIN/FUNCTION
No. Pin
Name I/O Function
1 VCOM
O
Common Voltage Output Pin, VA/2
Bias voltage of ADC inputs and DAC outputs.
2
AINR+
I
Rch Positive Input Pin
I
Rch Negative Input Pin (when ADMODE pin="H")
3 AINR-
I
No Connect pin (when ADMODE pin="L")
No internal bonding. This pin should be open.
4
AINL+
I
Lch Positive Input Pin
I
Lch Negative Input Pin (when ADMODE pin="H")
5 AINL-
I
No Connect pin (when ADMODE pin="L")
No internal bonding. This pin should be open.
6 VREF
I
Voltage Reference Input Pin, VA
Used as a voltage reference by ADC & DAC. VREF is connected externally to filtered
VA.
7
AGND
-
Analog Ground Pin
8
VA
-
Analog Power Supply Pin, 4.75
5.25V
9 P/S
I
Parallel/Serial Mode Select Pin
"L": Serial Mode, "H": Parallel Mode
Do not change this pin during PDN pin = "H".
10 MCLK
I
Master Clock Input Pin
LRCK
I
Input/Output Channel Clock Pin (in Parallel mode or when D/P bit="0" in Serial Mode)
11
DSDR
I
DSD Rch Data Input Pin (when D/P bit="1" in Serial Mode)
BICK
I
Audio Serial Data Clock Pin (in Parallel mode or when D/P bit="0" in Serial Mode)
12
DCLK
I
DSD Clock Pin (when D/P bit="1" in Serial Mode)
13 SDTO
O
Audio Serial Data Output Pin
SDTI
I
Audio Serial Data Input Pin (in Parallel mode or when D/P bit="0" in Serial Mode)
14
DSDL
I
DSD Lch Data Input Pin (when D/P bit="1" in Serial Mode)
OVFR
O
Rch Over Flow Flag Pin (in Parallel mode or when ZOS bit="0" in Serial Mode)
15
DZFR
O
Rch Zero Detection Flag Pin (when ZOS bit="1" in Serial Mode)
OVFL
O
Lch Over Flow Flag Pin (in Parallel mode or when ZOS bit="0" in Serial Mode)
16
DZFL
O
Lch Zero Detection Flag Pin (when ZOS bit="1" in Serial Mode)
CDTI
I
Control Data Input Pin (in Serial Mode)
17
CKS0
I
Master Clock Select Pin (in Parallel Mode)
CCLK
I
Control Data Clock Pin (in Serial Mode)
18
CKS1
I
Master Clock Select Pin (in Parallel Mode)
CSN
I
Chip Select Pin in Serial Mode (in Serial Mode)
19
DIF I
Digital Audio Interface Select Pin (in Parallel Mode)
"L": 24bit MSB justified, "H": I
2
S compatible
20 DFS0
I
Double Speed Sampling Mode Pin
21 PDN
I
Power-Down Mode Pin
"L": Power down reset and initialize the control register, "H": Power up
22 DEM0
I
De-emphasis Control Pin
23 ADMODE I
Analog Input Mode Select Pin
"L": Single-ended Input & IPGA Enable
"H": Differential Input & IPGA Bypass
ASAHI KASEI
[AK4620A]
MS0368-E-00
2004/12
- 5 -
PIN/FUNCTION (Continued)
24 VT
-
Input Buffer Tolerant Pin, 3.0
5.25V
25 VD
-
Digital Power Supply Pin, 3.0
3.6V
26 DGND
-
Digital Ground Pin
27 AOUTL-
O
Lch Negative Analog Output Pin
28 AOUTL+
O
Lch Positive Analog Output Pin
29 AOUTR-
O
Rch Negative Analog Output Pin
30 AOUTR+
O
Rch Positive Analog Output Pin
Note. Do not allow digital input pins (P/S, MCLK, LRCK/DSDR, BICK/DCLK, SDTI/DSDL, CDTI/CKS0,
CCLK/CKS1, CSN/DIF, DFS0, PDN, DEM0 and ADMODE pins) to float.
Handling of Unused Pin
The unused I/O pin should be processed appropriately as below.
Classification Pin
Name
Setting
AINL+, AINL-/NC, AINR+, AINR+NC
These pins should be open when ADMODE pin = "L".
AINL+, AINL-/NC
AINL+ pin is connected to AINL-/NC pin when
ADMODE pin = "H".
Analog Input
AINR+, AINR-/NC
AINR+ pin is connected to AINR-/NC pin when
ADMODE pin = "H".
Analog Output
AOUTL+, AOUTL-, AOUTR+,
AOUTR-
These pins should be open.
Digital Input
DEM0
This pin should be connected to DVSS.
Digital Output
OVFL/DZFL, OVFR/DZFR
These pins should be open.
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