ASAHI KASEI
[AK6512CA]
DAP03E-00
2005/03
- 1 -
AK6512CA
SPI bus 64Kbit Serial CMOS EEPROM
Features
Advanced CMOS EEPROM Technology
Single Voltage Supply: 1.8V to 5.5V
64Kbits; 8192 x 8 organization
SPI Serial Interface Compatible
High Speed Operation (f
MAX
=10MHz: VCC=4.5V to 5.5V)
Low Power Consumption
0.8
A Max. (Standby mode)
High Reliability
Endurance:
1000K E/W cycles / Address
Data Retention: 10 Years
Special Features
32 byte Page Write Mode
Block Write Protection (Protect 1/4,1/2 or Entire Array)
Automatic write cycle time-out with auto-ERASE
Software and Hardware controlled Write Protection
Self timed Programming Cycle: 5msec. Max.
Ideal for Low Density Data Storage
Low cost, space saving, 8-pin SSOP/SONW package
Block Diagram
64Kbit
8192
8
DATA
REGISTER
INSTRUCTION
DECODE,
CONTROL
AND
CLOCK
GENERATION
INSTRUCTION
REGISTER
EEPROM
SI
CS
SCK
HOLD
ADD.
BUFFERS
VREF
VPP
GENERATOR
VPP SW
DECODER
R/W AMPS
AND
AUTO ERASE
SO
STATUS REGISTER
WP
ASAHI KASEI
[AK6512CA]
DAP03E-00
2005/03
- 2 -
General Description
The AK6512CA is a 65536-bit, serial, read/write, non-volatile memory device fabricated using an
advanced CMOS EEPROM technology. The AK6512CA has 65536-bits of memory organized as
8192 registers of 8 bits each. The AK6512CA can operate all function under wide operating
voltage range: 1.8V to 5.5V. The charge up circuit for high voltage generation needed for write
operations is integrated.
The AK6512CA serial interface is compatible to a SPI bus. The AK6512CA has 6 instructions:
READ, WRITE, WREN (write enable), WRDI (write disable), RDSR (read status register), and
WRSR (write status register).
Each instruction is organized by an op-code (8bits), address (16bits), and data (8bits). When input
level of CS pin changed from high level to low level, AK6512CA can receive instructions.
Pin Configurations
Pin name
Functions
CS Chip
Select
input
SCK
Serial Clock input
SI
Serial Data input
SO
Serial Data output
WP
Write Protect input
HOLD Hold
input
VCC Power
Supply
GND Ground
Type of Products
Model
Memory size
Temp. Range
VCC
Package
AK6512CAM 64K
bits -40C to +85C
1.8V to 5.5V
8pin Plastic SSOP
AK6512CAL 64K
bits -40C to +85C
1.8V to 5.5V
8pin Plastic SONW
8
7
6
5
CS
SO
WP
GND
VCC
SI
1
2
3
4
SCK
AK6512CAM
8pin SSOP
HOLD
AK6512CAL
8pin SONW
CS
SO
WP
GND
VCC
HOLD
SI
1
2
3
4
8
7
6
5
SCK
ASAHI KASEI
[AK6512CA]
DAP03E-00
2005/03
- 3 -
Data Transfer
An IC that outputs the clock is called "MASTER", an IC that receives the clock is called "SLAVE".
The AK6512CA operates as a SLAVE. Data is written to the SI pin and read from SO pin. The
MSB is transmitted first.
After CS pin changes high level to low level, AK6512CA receives the first data bit on the SI pin
synchronously with the rising edge of the input pulse of serial clock. While CS pin is high level, the
data input to the SI pin is don't care and SO pin indicates Hi-Z.
All the functions are organized 8 bits of op-code, address, and data. If there is an invalid op-code,
the AK6512CA ignores the address and data information and SO pin indicates Hi-Z. In order to
input new op-code, CS pin should be toggled.
Hold
AK6512CA has a HOLD pin that can hold the data transfer. When HOLD changes high to low
while SCK is low, the data transfer stops. After the HOLD pin changes low to high while SCK is low,
the data transfer starts again. While the data transfer is paused, AK6512CA ignores the clock on
the SCK line.
Write Protect
AK6512CA has status registers. When the WPEN bit in the status registers is "1", Write Protect
function is enabled. When WPEN bit is "1" and WP pin is low level, the status register is protected
from write function. When WP pin becomes low level while the WRITE to the status register
instruction is written, the AK6512CA doesn't accept the instruction. When the WP pin changes low
level while the internal programming, the programming function continues.
When the WPEN bit is "0", WP pin function is disabled. Even if WP pin is fixed to low level, the
WRITE function to the status register can be done. When the WP pin is high level, AK6512CA can
accept all of READ and WRITE functions.
ASAHI KASEI
[AK6512CA]
DAP03E-00
2005/03
- 4 -
Pin Description
CS
(Chip Select Input)
When CS changes high level to low level, the AK6512CA can receive the instructions.
CS should be kept low level while receiving op-code, address and data, and while outputting
data.
When CS is high level, SO indicate Hi-Z.
SCK
(Serial Clock Input)
The SCK clock pin is the synchronous clock input for input/output data.
SI
(Serial Data Input)
The op-code, address, and data are written to the SI pin.
SO
(Serial Data Output)
The SO pin outputs the data from memory array and status register.
WP
(Write Protect Input)
The WP pin controls the write function to the status register.
When the WPEN bit in the status register is "0", the function of WP pin becomes disable.
Then the status register can be programmable when the WEN bit in the status register is "1".
And it does not depend on the status of WP pin.
When the WPEN bit is "1", the function of WP is enabled. Then the status register can not
be programmable when the WEN bit is "1" and the status of WP pin is low.
When the WPEN bit is "1", WP pin is high and WEN bit is "1", AK6512CA can accept the
WRITE instruction to the status registers.
During the instruction input, WP pin should keep high or low level.
HOLD
(Hold Input)
The HOLD pin can hold the data transfer. When the HOLD pin changes high to low while the
SCK is low, the data transfer is held. And the transfer starts when the HOLD pin changes
low to high while the SCK is low. While the holding the data transfer, AK6512CA ignores the
clock signal on SCK pin.
ASAHI KASEI
[AK6512CA]
DAP03E-00
2005/03
- 5 -
Function Description
AK6512CA has six instructions. The instruction can be input after the CS pin changes high to low.
All the instructions are MSB first.
Instruction
Op-code
Address Data
Description
READ
0000 X011
X X X A12-A8
A7-A0
D7-D0 (out)
Read from Memory Array
WRITE
0000 X010
X X X A12-A8
A7-A0
D7-D0 (in)
Write to Memory Array
WREN
0000 X110
------ ------
Write
Enable
WRDI
0000 X100
------ ------
Write
Disable
RDSR
0000 X101
Bit7-Bit0 (out)
------
------
Read Status Register
WRSR
0000 X001
Bit7-Bit0 (in)
------
------
Write Status Register
X: don't care
Table 1. Instruction set for AK6512CA
WREN (WRITE ENABLE) / WRDI (WRITE DISABLE)
The WRITE function can be accepted only in the status of Write Enable. After VCC is applied,
AK6512CA is in the status of Write Disable. After the function of WRDI, AK6512CA cannot accept
any programming function.
WREN
WRDI
0
1
2
3
4
5
6
7
1
X
0
0
0
0
0
0
Hi-Z
CS
SCK
SI
SO
X = don't care
0
1
2
3
4
5
6
7
1
X
0
0
0
0
1
0
Hi-Z
CS
SCK
SI
SO
X = don't care
ASAHI KASEI
[AK6512CA]
DAP03E-00
2005/03
- 6 -
RDSR (READ STATUS REGISTER)
The RDSR function is used to read the data in the STATUS register. The STATUS register has
RDY bit, WEN bit, BP0/BP1 bit and WPEN bit. RDSR function can be used to read READY/BUSY
status bit, WRITE ENABLE/DISABLE bit, and BLOCK PROTECT bit.
These bits can be set by WRSR function.
RDSR
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
WPEN X
X
X BP1 BP0 WEN RDY
Register Definition
WPEN
WP pin set bit (programmable)
See Table 3.
BP0 / BP1
Block Protect bit for EEPROM memory array (programmable)
See Table 4.
WEN
WRITE ENABLE / DISABLE bit (READ only)
This is set by WREN/WRDI function.
WEN=0 : WRITE DISABLE
WEN=1 : WRITE ENABLE
RDY
READY/BUSY status bit (READ only)
RDY=0 : READY
RDY=1 : BUSY
Table 2. Status Register Configuration
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
X
0
0
0
0
0
1
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7
Hi-Z
CS
SCK
SI
SO
X = don't care
ASAHI KASEI
[AK6512CA]
DAP03E-00
2005/03
- 7 -
WRSR (WRITE STATUS REGISTER)
The WRSR instruction can set the Write Protect Block size of the memory array.
AK6512CA has 4 Blocks of memory arrays. Write Protect Block size can be selected from 1/4, 1/2
and whole memory array. The block, which is set by Write Protect, is Read only.
BP0 bit, BP1 bit, and WPEN bit are programmable with EEPROM memory cell bits. The
characteristics of those bits (WREN, tE/W, RDSR) are same as the EEPROM memory array.
WP pin function can be set by WPEN (WRITE PROTECT ENABLE) bit which is defined by WRSR
function. When WP pin is low level and WPEN bit is "1", the WRITE function to Status register,
which has WPEN bit and BP0/BP1 bit, and to Write Disable Block is not performed. Then WRITE
function is performed only to the Write enable block.
When WP pin is "1" or WPEN bit is "0", then the function of WP pin is disabled and WRITE function
to the Status Register is performed.
WREN function should be done before WRSR function. And after the Programming function,
AK6512CA becomes Write Disable status automatically.
WRSR
WPEN
Bit
WP
Pin
WEN
Bit
Write Protected
Block
Not Protected
Block
Status Register
0
X
0
WRITE Disable WRITE Disable WRITE Disable
0
X
1
WRITE Disable
WRITE Enable
WRITE Enable
1
Low
0
WRITE Disable WRITE Disable WRITE Disable
1
Low
1
WRITE Disable
WRITE Enable
WRITE Disable
X
High
0
WRITE Disable WRITE Disable WRITE Disable
X
High
1
WRITE Disable
WRITE Enable
WRITE Enable
Table 3. WPEN function
Status Register bits
BP1 BP0
Write Protected
Block
0 0
none
0 1
1800h
-
1FFFh
1 0
1000h
-
1FFFh
1 1
0000h
-
1FFFh
Table 4. Write Protected Block Size
Hi-Z
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
1
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Bit0
CS
SCK
SI
SO
X = don't care
X
ASAHI KASEI
[AK6512CA]
DAP03E-00
2005/03
- 8 -
WRITE (WRITE SEQUENCE)
WRITE instruction can start the WRITE function to the memory cell array.
After CS pin changes high to low, op-code, address and data are input from SI pin. After the
instruction input, the internal programming cycle starts when CS pin changes low to high. After the
instructions are inputted, CS pin should change low to high after the last data bit (D0) inputs and
before next SCK clock rises. Write function can start only at this timing.
AK6512CA can indicate the BUSY status by using RDSR instruction and READ the RDY bit (Bit0) in
the status register. RDY is "1" indicates AK6512CA is in the programming cycle, and RDY is "0"
indicates AK6512CA is in the READY status. AK6512CA outputs the "FF" when RDSR instruction
executes during the programming cycle. Only RDSR instruction can be accepted during
programming cycle.
AK6512CA has Page Write mode, which can write the data within 32 bytes with one programming
cycle. The input data sent to the shift register within 32 bytes. If the number of bytes exceeded
32, the address counter rolls over to the first address of the page.
Internal programming cycle starts after CS pin changes low to high.
After WRITE instruction, AK6512CA changes to Write Disable status automatically. AK6512CA
needs WREN instruction before every WRITE instruction. When WRITE instruction is done while
AK6512CA is in Write Disable status, WRITE instructions are ignored and AK6512CA becomes
standby status after CS changes to high. AK6512CA can accept the next instruction after CS
becomes low.
WRITE instruction cannot write the data into the address of the protected block.
WRITE
Hi-Z
32
33
34
35
36
37
38
39
40
0
1
2
3
4
5
6
7
8
9
10
11
12
13
23
22
0
0
0
0
0
1
0
A0
A1
A10
Hi-Z
CS
SCK
SI
SO
A11
24
25
30
31
D0
D1
D6
D7
Data(n)
CS
SCK
SI
SO
X = don't care
Data(n+1)
D0
D1
D6
D7
D4
D5
D3 D2
D7
Data(n+31)
D0
D0
D1
D6
D7
D4
D5
D3 D2
A12
X
X
X
X
ASAHI KASEI
[AK6512CA]
DAP03E-00
2005/03
- 9 -
READ (READ SEQUENCE)
After CS changes high to low, the op-code and address are sent on SI pin and the data (D7-D0)
read from SO pin.
After 1 byte of data output, internal address register is incremented, and the next byte of data is
outputted. After READ the data in the highest address, the address register rolls over to the lowest
address. After the last bit of the address shift into the register, the input data on SI pin is ignored.
READ
0
1
2
3
4
5
6
7
8
9
10
11
12
13
23
22
0
0
0
0
0
1
1
A0
A1
A10
Hi-Z
CS
SCK
SI
SO
A11
24
25
29
30
D0
D1
D2
D6
X = don't care
D7
A12
X
X
X
X
ASAHI KASEI
[AK6512CA]
DAP03E-00
2005/03
- 10 -
Absolute Maximum Ratings
Parameter Symbol
Min
Max
Unit
Power Supply
VCC
-0.6
+6.5
V
All Input Voltages
with Respect to Ground
VIO
-0.6
VCC+0.6
V
Ambient Storage Temperature
Tst
-65
+150
C
Stress above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of the specification is not implied. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
Recommended Operating Condition
Parameter Symbol
Min
Max
Unit
Power Supply
VCC
1.8
5.5
V
Ambient Operating Temperature
Ta
-40
+85
C
ASAHI KASEI
[AK6512CA]
DAP03E-00
2005/03
- 11 -
Electrical Characteristics
(1) D.C. ELECTRICAL CHARACTERISTICS
(1.8V
VCC
5.5V, -40C
Ta
85C, unless otherwise specified)
Parameter Symbol
Condition
Min. Max.
Unit
ICC1 VCC=5.5V,fSCK=10.0MHz, *1
2.5
mA
Current Dissipation
(WRITE)
ICC2 VCC=2.5V,fSCK=5.0MHz, *1
2.0
mA
ICC3
VCC=1.8V,fSCK=2.0MHz,
*1
1.5
mA
ICC4 VCC=5.5V,fSCK=10.0MHz, *1
2.0
mA
Current Dissipation
(READ)
ICC5 VCC=2.5V,fSCK=5.0MHz, *1
0.4
mA
ICC6
VCC=1.8V,fSCK=2.0MHz,
*1
0.2
mA
Current Dissipation
(Standby)
ICCS
VCC=5.5V *2
0.8
A
VIH1 2.5V
VCC
5.5V 0.7
VCC VCC+0.5 V
Input High Voltage
VIH2 1.8V
VCC
<
2.5V 0.8
VCC VCC+0.5 V
VIL1
2.5V
VCC
5.5V
-0.3
0.3
VCC
V
Input Low Voltage
VIL2
1.8V
VCC
<
2.5V
-0.3
0.2
VCC
V
Output High Voltage
VOH1
4.5V
VCC
5.5V
IOH=-2mA
VCC-0.5
V
VOH2
2.5V
VCC
<
4.5V
IOH=-0.4mA
VCC-0.2
V
VOH3
1.8V
VCC
<
2.5V
IOH=-0.1mA
VCC-0.2
V
Output Low Voltage
VOL1
4.5V
VCC
5.5V
IOL=3.0mA
0.4
V
VOL2
2.5V
VCC
<
4.5V
IOL=1.6mA
0.4
V
VOL3
2.5V
VCC
<
4.5V
IOL=1.0mA
0.2
V
VOL4
1.8V
VCC
<
2.5V
IOL=1.0mA
0.2
V
ILI
VCC=5.5V, VIN=VCC/GND
1.0
A
Input Leakage
CS, SCK, DI pins
WP, HOLD pins
Output Leakage
SO pin
ILO
VCC=5.5V,
VOUT=VCC/GND
1.0
A
*1: VIN=VIH/VIL, SO=open
*2: CS=VCC, VIN=VCC/GND, WP,HOLD=VCC, SO=open
(2) CAPACITANCE
(Ta=25C, fSCK=1MHz, VCC=5.0V)
Parameter Symbol
Condition
Min. Max.
Unit
Output Capacitance
SO pin
CO
VO=0V
8.0
pF
Input Capacitance
CS, SCK, SI pins
CIN
VIN=0V
6.0
pF
Note: These parameters are not 100% tested. These are the sample value.
ASAHI KASEI
[AK6512CA]
DAP03E-00
2005/03
- 12 -
(3) A.C. ELECTRICAL CHARACTERISTICS 1
(1.8V
VCC
5.5V, -40C
Ta
85C, unless otherwise specified)
Parameter Symbol
Condition
Min.
Max.
Unit
fSCK1
4.5V
VCC
5.5V
10.0 MHz
SCK Frequency
fSCK2
2.5V
VCC
<
4.5V
5.0 MHz
fSCK3
1.8V
VCC
<
2.5V
2.0 MHz
tSKSH1
4.5V
VCC
5.5V
20
ns
SCK Setup Time
tSKSH2
2.5V
VCC
<
4.5V
50
ns
tSKSH3
1.8V
VCC
<
2.5V
50
ns
tCSS1
4.5V
VCC
5.5V
40
ns
CS Setup Time
tCSS2
2.5V
VCC
<
4.5V
80
ns
tCSS3
1.8V
VCC
<
2.5V
200
ns
tSKW1 4.5V
VCC
5.5V
40
ns
SCK Pulse Width
tSKW2 2.5V
VCC
<
4.5V
80
ns
tSKW3
1.8V
VCC
<
2.5V
200
ns
SCK Rise Time
*3 tRC
2
s
SCK Fall Time
*3 tFC
2
s
tDIS1
4.5V
VCC
5.5V
15
ns
Data Setup Time
tDIS2
2.5V
VCC
<
4.5V
20
ns
tDIS3
1.8V
VCC
<
2.5V
50
ns
tDIH1
4.5V
VCC
5.5V
15
ns
Data Hold Time
tDIH2
2.5V
VCC
<
4.5V
30
ns
tDIH3
1.8V
VCC
<
2.5V
60
ns
Data Rise Time
*3 tRD
2
s
Data Fall Time
*3 tFD
2
s
tPD1
4.5V
VCC
5.5V
25 ns
SO pin Output Delay
tPD2
2.5V
VCC
<
4.5V
60 ns
tPD3
1.8V
VCC
<
2.5V
100 ns
tOZ1
4.5V
VCC
5.5V
40 ns
SO pin Hi-Z Time
tOZ2
2.5V
VCC
<
4.5V
100 ns
tOZ3
1.8V
VCC
<
2.5V
200 ns
SO pin Output Hold Time
tOHD
0
ns
tCSH1
4.5V
VCC
5.5V
40
ns
CS Hold Time
tCSH2
2.5V
VCC
<
4.5V
80
ns
tCSH3
1.8V
VCC
<
2.5V
200
ns
tSKH1
4.5V
VCC
5.5V
20
ns
SCK Hold Time
tSKH2
2.5V
VCC
<
4.5V
50
ns
tSKH3
1.8V
VCC
<
2.5V
50
ns
tCS1
4.5V
VCC
5.5V
40
ns
CS High Time
tCS2
2.5V
VCC
<
4.5V
100
ns
tCS3
1.8V
VCC
<
2.5V
200
ns
*3: These parameters are not 100% tested. These are the sample value.
ASAHI KASEI
[AK6512CA]
DAP03E-00
2005/03
- 13 -
(4) A.C. ELECTRICAL CHARACTERISTICS 2
(1.8V
VCC
5.5V, -40C
Ta
85C, unless otherwise specified)
Parameter Symbol
Condition
Min.
Max.
Unit
tHFS1
4.5V
VCC
5.5V
15
ns
HOLD Setup Time 1
tHFS2
2.5V
VCC
<
4.5V
30
ns
tHFS3
1.8V
VCC
<
2.5V
90
ns
tHFH1
4.5V
VCC
5.5V
15
ns
HOLD Hold Time 1
tHFH2
2.5V
VCC
<
4.5V
30
ns
tHFH3
1.8V
VCC
<
2.5V
90
ns
tHRS1
4.5V
VCC
5.5V
15
ns
HOLD Setup Time 2
tHRS2
2.5V
VCC
<
4.5V
30
ns
tHRS3
1.8V
VCC
<
2.5V
90
ns
tHRH1
4.5V
VCC
5.5V
15
ns
HOLD Hold Time 2
tHRH2
2.5V
VCC
<
4.5V
30
ns
tHRH3
1.8V
VCC
<
2.5V
90
ns
tHOZ1
4.5V
VCC
5.5V
25
ns
HOLD Low to Output Hi-Z
tHOZ2
2.5V
VCC
<
4.5V
100
ns
tHOZ3
1.8V
VCC
<
2.5V
150
ns
tHPD1
4.5V
VCC
5.5V
25
ns
HOLD High to Output Low-Z
tHPD2
2.5V
VCC
<
4.5V
50
ns
tHPD3
1.8V
VCC
<
2.5V
100
ns
Selftimed Programming Time tWR
5 ms
Endurance
*4
5.5V, 25
C, Page Write 1,000,000
E/W
cycles /
Address
*4: These parameters are not 100% tested. These are the sample value.
AC Measurement Condition
Load Capacitance
CL=100pF
ASAHI KASEI
[AK6512CA]
DAP03E-00
2005/03
- 14 -
Synchronous Data Timing
Instruction Input
Data Output (READ)
CS
tCS
tCSS
tSKSH
tDIS tDIH
0
0
0
Hi-Z
SI
SO
tRC
tFC
SCK
tSKW
tSKW
tFD
tRD
tSKW
tSKW
tDIS tDIH
A0
Hi-Z
D7
D6
"L"
"H"
tPD
tPD
SCK
CS
SI
SO
A1
tOHD
ASAHI KASEI
[AK6512CA]
DAP03E-00
2005/03
- 15 -
Data Output (READ)
Data Input (WRITE)
D0
tOZ
D1
SCK
CS
SI
SO
tCS
tCSS
tSKSH
tPD
tOHD
Hi-Z
0
tSKH
tCSH
Hi-Z
D2
D1
D0
tCSH
SCK
CS
SI
SO
tSKH
ASAHI KASEI
[AK6512CA]
DAP03E-00
2005/03
- 16 -
Hold
tHFS
tHOZ
n+1
Hi-Z
"L"
"H"
SCK
CS
SI
SO
HOLD
tHFH
D
n+1
D
n
tHRS
tHRH
n
tDIS
tHPD
D
n
n-1
D
n-1
IMPORTANT NOTICE
These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
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