ASAHI KASEI
[AK8850]
AK8850
NTSC Digital Video Decoder
General Description
The AK8850 decodes NTSC composite video, S-Video and Component Video signals (525/625) into digital
formats. Digital output conforms to ITU-R BT.601 and ITU-R BT.656* YCrCb specifications. The AK8850 outputs
a control signal to generate clocks synchronized with either Horizontal Sync or Vertical Sync signals. Its clock rate
is 27 MHz.
An encoded VBID Closed Caption signal can be extracted from the video signal and sent to an external pin on the
AK8850.
Features
NTSC-M Composite signal and S-Video signal decoder
Component Video decoder for 525 / 625 systems ( Betacam,MII,EBU N10 )
On-chip triple 10-Bit ADCs ( 27 MHz operation )
On-chip Programmable Gain Amp ( PGA ), ranging from 0 dB to 12 dB in 0.1 dB / steps
Input-synchronized clock is generated by an external VCXO
Sub-Carrier generation by Digital Synthesizer ( DFS )
Auto Color Control ( ACC )
Auto Gain Control ( AGC )
Adaptive 3-line Y-C separation
ITU-R BT.656 format output ( 4:2:2 8-Bit parallel output with EAV / SAV )
NTSC Closed Caption signal decoding function
VBID Program condition decoding function
WSS Program condition decoding function
Video Aspect Signal decoding function on Line 16 and Line 279
Sleep function
6channel Analog inputs
I2C Control
3.3 V CMOS
100-Pin LQFP package
note: * ITU-R BT.656 spec may not be satisfied, as it is dependent upon input signal quality.
Rev.0 1
2002/01
ASAHI KASEI
[AK8850]
Analog Multiplexer
Clamp
PGA
Sync Separator
VREF
Decimation
Filter
Sync-Separatio
n
&
AGC Info.
&
Closed Caption
VBID
Extraction
Timing
Contorller
&
VCO Controller
&
Registers
CLOCK
Module
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
FBCAP1
FBCAP2
FBCAP3
LLPFC
LLPF
Y/C
Separation
(2D-3Line
or
1D-BPF)
Luma-
Processing
&
Image Ctrl
(Brightness,
Contrast etc.)
Chroma-
Processing
&
ACC
&
Image Ctrl
(HUE,Saturation)
DFS
(Chroma
PLL)
D[7:0]
10-bit
ADC
HALFCLKOUT
DVALID/VLOCK
VSYNC
HSYNC
FIELD
FRAME0
FRAME1/CSYNC
EXTCLP
IRefR1
10-bit
ADC
10-bit
ADC
Composite
Y
C /U
V
Y
V
U
V
CLK27MOUT
Microprocessor I/F
NSIG
NSTD
U
Phase Error
27MHz
13.5MHz
SYNC1
SYNC2
SYNC3
CLPCAP1
CLPCAP2
CLKINV
Output Processing
(Level Shifter
&
Rec.656 formatter
etc.)
with Buffer
FLPF
FLPFC
CLK
IVCXO
1. Functional Block Diagram
C
Rev.0
2
2002/01
site Video signal i put )
1-1. Signal Path ( Compo
n
AVDD
AVSS
VRN
VRP VCOM
SELA
SDA
SCL /RESET
IRefR2
VREF
DVSS
DVDD
PD
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