ASAHI KASEI
[AKD4122]
<KM071100>
2003/06
- 1 -
GENERAL DESCRIPTION
The AKD4122 is an evaluation board for the digital sample rate converter, the AK4122 with built-in
digital audio interface receiver (DIR). The AKD4122 has the digital audio interface and can achieve the
interface with digital audio system via opt-connector.
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Ordering guide
AKD4122 --- Evaluation board for AK4122
(Cable for connecting with printer port of IBM-AT compatible PC and control
software are packed with this. This control software does not operate on Windows
NT.)
FUNCTION
DIR/DIT with optical input/output
10pin Header for AKM AD/DA evaluation board
BNC connector for an external clock input
10pin Header for serial control mode
Opt In
AK4114
10pin
Header
DSP
Data
AVDD, DVDD
BICK In
AGND, DGND
Digital In
Opt In
10pin
Header
DSP
Data
Clock
Divider
MCLK In
Opt In
AK4114
Opt Out
Opt Out
AK4114
10pin
Header
DSP
Data
MCLK In
Clock
Divider
10pin
Header
Control
Data
AK4122
Figure 1. AKD4122 Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
Evaluation board Rev.A for AK4122
AKD4122
ASAHI KASEI
[AKD4122]
<KM071100>
2003/06
- 2 -
1. Evaluation Board Manual
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Operation sequence
1) Set up the power supply lines.
[AVDD] (red) = 3.0
3.6V (typ. 3.3V, AVDD pin)
[DVDD] (red) = 3.0
3.6V (typ. 3.3V, DVDD pin)
[+5V] (orange) = +5V (for regulator)
[VCC] (blue) = 3.0
3.6V (typ. 3.3V, for digital logic)
[AGND] (black) = 0V
[DGND] (black) = 0V
Each supply line should be distributed from the power supply unit.
2) Set up the evaluation mode, jumper pins. (See the followings.)
3) Power on.
The AK4122 should be reset once bringing SW6 (PDN) "L" upon power-up.
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Evaluation mode
I/O ports and jumper pins on the board should be set according to the following explanation in order to evaluate each
pass of the AK4122. The block diagram is shown in Figure 2.
RX2
RX2
PDN
RX1
RX1
IPS1-0
Serial
Audio
I/F
LRCK1
SDTI
LRCK1
SDTI
BICK1
BICK1
Serial
Audio
I/F
LRCK2
SDTIO
LRCK2
SDTIO
BICK2
BICK2
MCLK2
LRCK
BICK
SDTO
LRCK
BICK
SDTO
OMCLK
SMUTE
Control Register
CDTO CDTI CCLK CSN
AVDD AVSS
DVDD DVSS
M/S2
M/S3
SRC
PLL
Serial
Audio
I/F
De-em
Filter
PORT1
PORT2
PORT3
RX3
RX3
RX4
RX4
DIR
TX
TX
ISEL1-0
OSEL
BYPS
INT0 INT1
R
FILT
INT2
OPS1-0
MCKO
MCKE
Figure 2. AK4122 Block Diagram
ASAHI KASEI
[AKD4122]
<KM071100>
2003/06
- 3 -
(1) AK4122 PORT1
SRC
AK4122 PORT3
Refer to page 5 for input port setting, and page 15
18 for output port setting.
PORT4
DIR1
U12
AK4114
PORT5
DSP1
J4
EXT1
BICK1
LRCK1
SDTI
BICK
LRCK
SDTO
PORT9
DSP3
OMCLK
PORT10
DIT3
U14
AK4114
J3
EXT3
Divider
AK4122
Figure 3. AK4122 PORT1
SRC
AK4122 PORT3
(2) AK4122 PORT2
SRC
AK4122 PORT3
Refer to page 6
9 for input port setting, and page 15
18 for output port setting.
PORT6
DIR2
U13
AK4114
PORT7
DSP2
J2
EXT2
BICK2
LRCK2
SDTIO
BICK
LRCK
SDTO
PORT9
DSP3
OMCLK
PORT10
DIT3
U14
AK4114
J3
EXT3
Divider
AK4122
MCLK2
Divider
Figure 4. AK4122 PORT2
SRC
AK4122 PORT3
(3) AK4122 DIR
SRC
AK4122 PORT3
Refer to page 10 for input port setting, and page 15
18 for output port setting.
PORT3
DIR
RX1
RX2
RX3
BICK
LRCK
SDTO
PORT9
DSP3
OMCLK
PORT10
DIT3
U14
AK4114
J3
EXT3
Divider
AK4122
RX4
J1
RX
Figure 5. AK4122 DIR
SRC
AK4122 PORT3
ASAHI KASEI
[AKD4122]
<KM071100>
2003/06
- 4 -
(4) AK4122 PORT1
SRC
AK4122PORT2
Refer to page 5 for input port setting, and page 11
14 for output port setting.
PORT4
DIR1
U12
AK4114
PORT5
DSP1
J4
EXT1
BICK1
LRCK1
SDTI
BICK2
LRCK2
SDTIO
PORT7
DSP2
MCLK2
PORT8
DIT2
U13
AK4114
J2
EXT2
Divider
AK4122
Figure 6. AK4122 PORT1
SRC
AK4122 PORT2
(5) AK4122 DIR
SRC
AK4122 PORT2
Refer to page 10 for input port setting, and page 11
14 for output port setting.
PORT3
DIR
RX1
RX2
RX3
BICK2
LRCK2
SDTIO
PORT7
DSP2
MCLK2
PORT8
DIT2
U13
AK4114
J2
EXT2
Divider
AK4122
RX4
J1
RX
Figure 7. AK4122 DIR
SRC
KA4122 PORT2
(6) Bypass Mode
Refer to page 5
10 for input port setting, and output port setting should be master mode. The bypass mode of the
AK4122 is set by the register.
In bypass mode, the DIT function of the AK4114 can not be used as the output port. 10pin PORT should be used
instead.
Input BICK, LRCK, and DATA are output from the output port side in the bypass mode.
ASAHI KASEI
[AKD4122]
<KM071100>
2003/06
- 5 -
(1) Setting for Input port (AK4122 PORT1)
(1-1) Slave Mode
1. When using DIR function of AK4114 (U12)
When using PORT4 (DIR1), nothing should be connected to J4 (EXT1) and PORT5 (DSP1). JP12 (EXT1)
should be short.
JP12
EXT1
JP13
SDTO
JP11
BICK1
EXT
DIR
JP14
LRCK1
SW2 setting (See Table 1, 2)
Upper-side is "H" and lower-side is "L".
SW2 No.
Name
ON ("H")
OFF ("L")
1
OCKS
Fixed to "L"
2
DIF0
3
DIF1
4
DIF2
AK4114 Audio Format Setting
Refer to Table 2
Table 1. SW2 setting
AK4114
AK4122
Mode
Audio I/F Format
DIF2
DIF1
DIF0
DIF1
DIF0
0
16bit, LSB justified
0
0
0
0
0
1
24bit, MSB justified
1
0
0
0
1
Default
2
24bit, I
2
S Compatible
1
0
1
1
0
3
24bit, LSB justified
0
1
1
1
1
Table 2. AK4114 Audio interface format setting
* DIF1-0 of the AK4122 is set by the register.
2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ
When using PORT5 (DSP1), nothing should be connected to PORT4 (DIR1). BICK is input from J4 (EXT1),
and the LRCK and SDTI are supplied from UPD. JP12 (EXT1) should be open.
JP12
EXT1
JP13
SDTO
JP11
BICK1
EXT
DIR
JP14
LRCK1
3. All clocks are fed through the 10pin port
When using PORT5 (DSP1), nothing should be connected to J4 (EXT1) and PORT4 (DIR1). JP12 (EXT1)
should be short.
JP12
EXT1
JP13
SDTO
JP11
BICK1
EXT
DIR
JP14
LRCK1
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