DUAL N-CHANNEL AND DUAL P-CHANNEL MATCHED PAIR MOSFET
GENERAL DESCRIPTION
The ALD1105 is a monolithic dual N-channel and dual P-channel
complementary matched transistor pair intended for a broad range of
analog applications. These enhancement-mode transistors are
manufactured with Advanced Linear Devices' enhanced ACMOS silicon
gate CMOS process. It consists of an ALD1116 N-channel MOSFET pair
and an ALD1117 P-channel MOSFET pair in one package. The ALD1105
is a low drain current, low leakage current version of the ALD1103.
The ALD1105 offers high input impedance and negative current temperature
coefficient. The transistor pair is matched for minimum offset voltage and
differential thermal response, and it is designed for precision signal
switching and amplifying applications in +1V to +12V systems where low
input bias current, low input capacitance and fast switching speed are
desired. Since these are MOSFET devices, they feature very large (almost
infinite) current gain in a low frequency, or near DC, operating environment.
When used in complementary pairs, a dual CMOS analog switch can be
constructed. In addition, the ALD1105 is intended as a building block for
differential amplifier input stages, transmission gates, and multiplexer
applications.
The ALD1105 is suitable for use in precision applications which require
very high current gain, beta, such as current mirrors and current sources.
The high input impedance and the high DC current gain of the field effect
transistors result in extremely low current loss through the control gate. The
DC current gain is limited by the gate input leakage current, which is
specified at 30pA at room temperature. For example, DC beta of the device
at a drain current of 3mA at 25
C is = 3mA/30pA = 100,000,000.
FEATURES
Thermal tracking between N-channel and P-channel pairs
Low threshold voltage of 0.7V for both N-channel &
P-channel MOSFETs
Low input capacitance
Low Vos -- 10mV
High input impedance -- 10
13
typical
Low input and output leakage currents
Negative current (I
DS
) temperature coefficient
Enhancement mode (normally off)
DC current gain 10
9
Matched N-channel pair and matched P-channel pair in one package
ALD1105
A
DVANCED
L
INEAR
D
EVICES,
I
NC.
PIN CONFIGURATION
APPLICATIONS
Precision current mirrors
Complementary push-pull linear drives
Discrete Analog switches
Analog signal Choppers
Differential amplifier input stage
Voltage comparator
Data converters
Sample and Hold
Analog current inverter
Precision matched current sources
DN2
GN2
SN2
GP2
SP2
GN1
SN1
DP1
GP1
1
2
3
4
DB, PB, SB PACKAGE
5
6
7
8
9
10
11
12
13
14
DN1
V
+
V
-
DP2
SP1
BLOCK DIAGRAM
N SOURCE 1 (3)
SUBSTRATE (4)
N SOURCE 2 (12)
N GATE 2 (13)
N DRAIN 1 (1)
N GATE 1 (2)
N DRAIN 2 (14)
P SOURCE 1 (7)
SUBSTRATE (11)
P SOURCE 2 (8)
P GATE 2 (9)
P DRAIN 1 (5)
P GATE 1 (6)
P DRAIN 2 (10)
Operating Temperature Range*
-55
C to +125
C
0
C to +70
C
0
C to +70
C
14-Pin
14-Pin
14-Pin
CERDIP
Plastic Dip
SOIC
Package
Package
Package
ALD1105 DB
ALD1105 PB
ALD1105 SB
* Contact factory for industrial temperature range.
ORDERING INFORMATION
2005 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, California 94089 -1706 Tel: (408) 747-1155 Fax: (408) 747-1286 http://www.aldinc.com
ALD1105
Advanced Linear Devices
2
ABSOLUTE MAXIMUM RATINGS
Drain-source voltage, V
DS
13.2V
Gate-source voltage, V
GS
13.2V
Power dissipation
500 mW
Operating temperature range
PB, SB package
0
C to +70
C
DB package
-55
C to +125
C
Storage temperature range
-65
C to +150
C
Lead temperature, 10 seconds
+260
C
Gate Threshold
V
T
0.4
0.7
1.0
V
I
DS
= 1
A V
GS
= V
DS
-0.4
-0.7
-1.0
V
I
DS
= -1
A V
GS
= V
DS
Voltage
Offset Voltage
V
OS
2
10
mV
I
DS
= 10
A V
GS
= V
DS
2
10
mV
I
DS
= -10
A V
GS
= V
DS
V
GS1
- V
GS2
Gate Threshold
Temperature
TC
VT
-1.2
mV/
C
-1.3
mV/
C
Drift
On Drain
I
DS (ON)
3
4.8
mA
V
GS
= V
DS
= 5V
-1.3
-2
mA
V
GS
= V
DS
= -5V
Current
Trans-.
G
fs
1
1.8
mmho
V
DS
= 5V I
DS
= 10mA
0.25
0.67
mmho
V
DS
= -5V I
DS
= -10mA
conductance
Mismatch
G
fs
0.5
%
0.5
%
Output
G
OS
200
mho
V
DS
= 5V I
DS
= 10mA
40
mho
V
DS
= -5V I
DS
= -10mA
Conductance
Drain Source
R
DS(ON)
350
500
V
DS
= 0.1V V
GS
= 5V
1200
1800
V
DS
= -0.1V V
GS
= -5V
ON Resistance
Drain Source
ON Resistance
R
DS(ON)
0.5
%
V
DS
= 0.1V V
GS
= 5V
0.5
%
V
DS
= -0.1V V
GS
= -5V
Mismatch
Drain Source
Breakdown
BV
DSS
12
V
I
DS
= 1
A V
GS
=0V
-12
V
I
DS
= -1
A V
GS
=0V
Voltage
Off Drain
I
DS(OFF)
10
400
pA
V
DS
=12V I
GS
= 0V
10
400
pA
V
DS
= -12V V
GS
= 0V
Current
4
nA
T
A
= 125
C
4
nA
T
A
= 125
C
Gate Leakage
I
GSS
0.1
30
pA
V
DS
= 0V V
GS
=12V
1
30
pA
V
DS
= 0V V
GS
=-12V
Current
1
nA
T
A
= 125
C
1
nA
T
A
= 125
C
Input
C
ISS
1
3
pF
1
3
pF
Capacitance
OPERATING ELECTRICAL CHARACTERISTICS
T
A
= 25
C unless otherwise specified
N - Channel
Test
P - Channel
Test
Parameter
Symbol Min
Typ
Max
Unit
Conditions
Min
Typ
Max
Unit
Conditions
ALD1105
Advanced Linear Devices
5
DIFFERENTIAL AMPLIFIER
CURRENT SOURCE MULTIPLICATION
CURRENT SOURCE MIRROR
CURRENT SOURCE WITH GATE CONTROL
TYPICAL APPLICATIONS
ISET
RSET
Q3
V+ = +5V
I SOURCE
Q1, Q2: N - Channel MOSFET
Q3, Q4: P - Channel MOSFET
I SOURCE = ISET
= V+ -Vt
RSET
= 4
RSET
~
Q1
Q2
V+ = +5V
Q4
V+ = +5V
Q4
ISOURCE
RSET
Q1
Q3
ISET
ON
OFF
Digital Logic Control
of Current Source
Q1 : N - Channel MOSFET
Q3,Q4 : P - Channel MOSFET
V+
PMOS PAIR
Q
4
V
OUT
V
IN
-
NMOS PAIR
Q
2
Q
1
V
IN
+
Current
Source
Q
3
Q
1
, Q
2
: N - Channel MOSFET
Q
3
, Q
4
: P - Channel MOSFET
ALD1105
Q
SET,
Q
1
..Q
N
: ALD 1106 or ALD 1105
N - Channel MOSFET
I
SET
V+ = +5V
I
SOURCE
= I
SET
x N
R
SET
Q
2
Q
3
Q
SET
Q
1
Q
N
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