Data Sheet

26113

8-BIT

MICROCONTROLLER

The A4255CA and A4255CLN microcontrollers make designing

with step motors easy, inexpensive, and productive. A reference design
technique is integral to the implementation of a system that includes the
power circuitry, a low-cost, 8-bit, preprogrammed microcontroller and
the other components needed to complete the control hardware. The
A4255Cx eliminates the need for software development, expedites the
product creation, and hastens the time to market.

The reference design can be utilized directly or integrated into a

larger printed wiring board. A further benefit is the compactness of the
circuit layout. Power-driver output ratings presently available with these
devices are 50 V and

±1.5 A (with the A3955 or A3957). A similar

device for 46 V and either 1.5 A (with the SLA7042M) or 3 A (with the
SLA7044M) is planned. The reference design supports stepping formats
that include full-step, half-step, quarter-step, eighth-step, and sixteenth-
step (microstepping) increments for a two-phase stepping motor.

The A4255CA is furnished in an 18-pin dual in-line plastic package

for through-hole applications. The A4255CLN is furnished in a 20-lead
wide-body, shrink-pitch, small-outline plastic package (SSOP) with gull-
wing leads for minimum area, surface-mount applications.

FEATURES

I Full-, Half-, Quarter-, Eighth-, or Sixteenth-Step Increments
I DC to 20 MHz Clock Input
I Power-On Reset
I Brown-Out Reset
I High-Speed CMOS Technology
I Low Power, <20 mA @ 5 V, 20 MHz

(Typically 9 mA)

4255

Always order by complete part number:

Part Number

Package

A4255CA

18-pin DIP

A4255CLN

20-lead shrink-pitch SOIC

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

.......................... 7.0 V

Input Voltage Range,

........................ -0.3 V to V

+ 0.6 V

RESET Voltage, V

RESET

...................... 14 V

Input Clamp Current, I

...............

20 mA

Output Clamp Current, I

............

20 mA

Operating Temperature Range,

.................................... 0

C to +70

Storage Temperature Range,

.............................. -55

C to +150

Caution: These CMOS devices have input
static protection (Class 3) but are still
susceptible to damage if exposed to extremely
high static electrical charges.

Dwg. PP-071A

MODE SELECT

DIRECTION
CONTROL IN

OSC/CLOCK IN

OSC/CLOCK OUT

SUPPLY

PFD

PHASE

PFD

PHASE

MODE SELECT

STEP IN

RESET

GROUND

MONITOR OUT

SHIFT CLOCK

SERIAL DATA OUT

STROBE OUT

A4255CA

4255
8-BIT
MICROCONTROLLER

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000

A4255CLN

0.65 mm (0.026") pitch

RECOMMENDED OPERATING CONDITIONS

over operating temperature range

Logic Supply Voltage Range, V

............... 4.5 V to 5.5 V

High-Level Input Voltage, V

............................

0.85V

Low-level input voltage, V

.................................

0.15V

Dwg. PP-071-1

PFD

PHASE

PFD

PHASE

MONITOR OUT

SHIFT CLOCK

SERIAL DATA OUT

STROBE OUT

MODE SELECT

DIRECTION
CONTROL IN

OSC/CLOCK IN

OSC/CLOCK OUT

SUPPLY

GROUND

MODE SELECT

STEP IN

RESET

SUPPLY

GROUND

To ease and simplify the design effort, the user only

provides the following signals: (a) direction, (b) stepping
clock (8x the full-step frequency), (c) mode logic (three
inputs determine the operation for full, half, quarter, or
eighth stepping), (d) reset input (initiates a `detent'
position), and (e) recirculation control (this allows estab-
lishing the percent of fast- vs slow-decay in the phase
winding). The microcontroller program providess auto-
matic recirculation control. This eliminates the need for
evaluating the impact of stepping rate vs the sinusoidal
current profile.

Although recirculation control can provide slight

improvements (i.e., lower current ripple, reduced motor
heating [a few degrees], and diminish audible noise levels
[minimal differences]), this entails an evaluation of the
motor (and step frequencies) to determine the proper ratio
of fast- and slow-decay. The benefits of tuning the
recirculation ratios are small, and the time and effort
required can be considerable. Hence, the uninitiated user
should opt for the automatic recirculation control, and
avoid the essentially unnecessary activity.

FUNCTIONAL DESCRIPTION

MICROCONTROLLER OPERATION

Although `hardware' control of the microstepping ICs

is feasible, without a specific (ASIC), monolithic IC
controller the prime solution becomes a `software' option.
From the user's perspective, a `preprogrammed' micro-
controller appears little, or no, different than a `dedicated'
controller and sequencer IC expressly created for mi-
crostepping applications of the power-driver ICs. Further,
the flexibility of a software-based drive is certainly a basic
benefit (high-volume production of 8-bit microcontrollers
transposes to low-cost circuitry).

As an indicator of the logic signals needed to control

the power ICs, Table 1 lists the required A3955 inputs to
the 3-bit DAC for eighth-step operation (the similar
A3957 uses a 4-bit DAC for sixteenth-step operation).
These I/O signals are serial data from the microcontroller,
then converted to a parallel mode by a 74HC595 as the
`interface' between the microcontroller and the two
microstepping power ICs.

The versatility offered by software control allows the

operating modes listed in Table 1. This table itemizes the
various logic inputs that determine direction, stepping

4255

8-BIT

MICROCONTROLLER

www.allegromicro.com

format, reset, 1/8th vs 1/16th sub-steps, etc. Note that
during power up, shift clock (SCLK) is sampled for a pull-
up or pull-down resistor to establish the fractional step
limit. A pull up sets up a 1/8th-step format (for the
A3955) and pull down sets up 1/16th-operation (for the
A3957).

Table 2 lists the microcontroller terminal descriptions

and provides the essence of the circuit operation (a
schematic illustrating a typical stepper design follows). A
brief description of the microcontroller I/O should clarify
the connections of the various elements of the drive
electronics.

FUNCTIONAL DESCRIPTION (cont'd)

Table 1 -- Controller/sequencer IC operational logic

Binary inputs

Operating mode

Comments

DIR

MS2

MS1

MS0

(Command executed on L

H of CLK)

(Applicable power ICs)

CW, Full step (single-phase)

A3955/57

CW, Half step (constant torque)

A3955/57

CW, 1/4 step (constant torque)

A3955/57

CW, 1/8th step (constant torque)

A3955/57

CW, 1/16th step (constant torque)

A3957 only

Disable A3955/57 holding torque

At present position

Enable A3955/57 holding torque

From present position

Reset A4255 sequencer IC

A3955/57

CCW, full step (single-phase)

A3955/57

CCW, half step (constant torque)

A3955/57

CCW, 1/4 step (constant torque)

A3955/57

CCW, 1/8th step (constant torque)

A3955/57

CCW, 1/16th step (constant torque)

A3957 only

Disable A3955/57 holding torque

At present position

Enable A3955/57 holding torque

From present position

Reset A4255 sequencer IC

A3955/57

4255
8-BIT
MICROCONTROLLER

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000

Table 2 -- Microcontroller terminal descriptions

A4255CA

A4255CLN

DIP

SSOP

Function

Description

Comments, connections, etc.

Input

Mode select 1

Static and/or dynamic control of stepping mode

Input

Mode select 2

Static and/or dynamic control of stepping mode

Input

Step in

Governs full-step rate (

÷8 for A3955; ÷16 for A3957)

Input

Reset

Resets DIR., MS2, MS1, and MS0 to 0000 (detent)

5, 6

Power

Ground

Logic power return

Output

Monitor out

Signals full-step rotor alignment (active low)

I/O

Shift clock

Pull up for A3955; pull down for A3957

Output

Serial data out

Shifts 8-bit serial data to 74HC595 serial input

Output

Strobe out

Latches 8-bit data into 74HC595 (latch clock in)

Output

Phase B

Controls current direction in phase B

Output

PFD B

Phase B recirculation control

Output

Phase A

Controls current direction in phase A

Output

PFD A

Phase A recirculation control

15, 16

Power

Supply

) Recommended range: 4.5 V to 5.5 V

Output

Osc/clock out

Crystal oscilator connection

Input

Osc/clock in

Crystal oscillator connection/external clock input

Input

Direction control

Determines direction of step motor rotation

Input

Mode select 0

Static and/or dynamic control of stepping mode

FUNCTIONAL DESCRIPTION (cont'd)

Mode-select inputs

These three inputs (MS2, MS1, and MS0) determine

the stepping format, disable/enable motor power, and reset
the controller/sequencer. In conjunction with the direction
input, the mode inputs control the sixteen operating states
listed. Deactivating stepper power in any position except
`detent' (i.e., a single phase activated) results in the motor
rotor advancing, or retracting, from its intermediate
position and alignment with a natural (i.e., minimum-
reluctance flux field) orientation. The absolute position
may be affected by inertia, load, fractional position,
ringing, etc. and cannot be determined without feedback.
Phase currents must be maintained to immobilize the
rotor/load in any intermediate position.

Step (clock) input

The sequencer stepping-clock frequency is a multiple

of the actual stepping rate. The A3955 requires a step-
ping-clock input frequency equal to eight times the
intended stepping rate for the motor; the A3957 requires a
stepping clock rate that is sixteen times the actual stepping
rate of the motor. However, neither design necessitates
that the step frequency be varied should the operating
mode(s) be switched during operation. Shifting from one
stepping format does not mandate a simultaneous (and
equivalent) change in the clock frequency.

Using a 20 MHz crystal (maximum limit for the

A4255) allows a 50 kHz stepping clock for the A3955,
and this equates to 6 250 full steps per second (50 kHz/8).
For the A3957 this 50 kHz stepping clock translates to

4255

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MICROCONTROLLER

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3 125 full steps per second (50 kHz/16). These frequen-
cies represent the attainable limits with the A4255.

Although not a necessity, a stepping clock with a 50%

duty cycle represents the simplest technique for providing
an appropriate (

50 kHz) stepping clock rate. The step

clock varies depending upon the start, acceleration,
slewing, deceleration, and stop trajectories mandated by
the motion system control and `point-to-point' timing
objectives.

Reset input

The preprogrammed microcontroller incorporates two

`software' reset states that are serially loaded with MS2,
MS1, and MS0 all high. However, the direct hardware
reset is actuated with a logic 0 (active low) on this input
An input low level defaults to the 0000 binary state and
sets the rotor to its natural (or detent) position with one-
phase energized.

Monitor output

An output low signal indicates a rotor alignment

corresponding to a single phase on position. Any changes
in the operating mode (microstepping to full-step, etc.)
should coincide with the interval that the monitor output is
in the low state. This alleviates noise problems, excessive
ringing, etc. that may result from changing the stepping
modes on-the-fly. Nonlinear (such as S-curve) accelera-
tion profiles can exploit this signal to achieve very
smooth, quiet stepper operation.

Shift clock output

This I/O terminal serves a dual purpose. On power

up, the microcontroller samples this terminal as an input.
Connecting a pull-up resistor results in 1/8th-step format;
while a pull-down resistor configures the controller for its
1/16th-step mode (A3957 only). This provides versatility,
simplicity, and cost-effectiveness for most users.

Operating in its output mode, this I/O constitutes the

shift clock signal for the 74HC595. Data is transferred
from the microcontroller serial-data output to the serial-
data input of the 74HC595. This 8-bit serial format is
converted into parallel signals controlling the 3-bit (or 4-

bit) DAC input lines to the two microstepping power ICs.
Serial data from the serial data output is valid on the low-
to-high clock transitions and eight clock pulses shift serial
control signals into the 74HC595. A basic timing diagram
(showing serial data, shift clock, and strobe) is depicted.
Signal timing is controlled by the preprogrammed micro-
controller; data entered into the 74HC595 shift register is
then latched by the low-to-high transition of the strobe
input.

SCLK

Dwg. WP-040A

SDO

Serial data, shift clock, and strobe

Serial data output

The binary signal instructions that control each of the

microstepping power ICs is shown in table 1. The first
3-bits (or 4-bits) control the digital-to-analog conversion
in one power IC, while the next 3 (or 4-bits) ratio the
second power driver current. The microcontroller moni-
tors all the various static inputs (i.e., Direction, Mode
Selects, Reset), and by exploiting the Stepping Clock for
its input frequency, transfers the 8-bit data commands to
the power driver ICs via the serial-to-parallel interface IC.
The microcontroller utilizes look-up tables to provide
overall control of direction, stepping format, and recircu-
lation mode (PFD). The microcontroller reads inputs and
then outputs time-based signals to control both microstep-
ping ICs.

Strobe output

After the 8-bit serial data has been loaded into the

shift register, a low-to-high transition on the strobe output
transfers the serial data from the shift register into the
eight `D' flip-flops that compose the parallel-data outputs.
This `latched' data controls microstepping current ratios
for both power ICs, and is `updated' after eight step
clocks.

FUNCTIONAL DESCRIPTION (cont'd)

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