DISCONTINUED PRODUCT
--
FOR REFERENCE ONL
Y
HIGH-VOLTAGE BiMOS III
10-BIT SERIAL-INPUT, LATCHED DRIVERS
Always order by complete part number, e.g., UCN5910A-2 .
The UCN5910x combines a 10-bit CMOS shift register and accompanying
data latches, control circuitry, high-voltage bipolar sourcing outputs with
DMOS active pull-downs. Designed primarily to drive ink-jet and piezoelec-
tric printers, large flat-panel vacuum-fluorescent or ac plasma displays, the
140 V or 150 V and
50 mA output ratings also allow these devices to be used
in many other peripheral power driver applications. The lower-cost (suffix
"-2") devices are identical to the basic devices except for output voltage rating.
The CMOS shift register and latches allow direct interfacing with micro-
processor-based systems. With a 5 V logic supply, serial-data input rates are
typically over 5 MHz, with significantly higher speeds obtainable at 12 V.
Use with TTL may require appropriate pull-up resistors to ensure an input logic
high.
A CMOS serial data output enables cascade connections in applications
requiring additional drive lines. Similar devices for up to 60-volt operation are
available in 10, 12, 20, and 32-bit configurations.
The UCN5910A/LW output source drivers are npn Darlingtons capable of
sourcing at least 40 mA. The DMOS active pull-downs are capable of sinking
at least 30 mA. For inter-digit blanking, all of the output drivers can be
disabled and the DMOS sink drivers turned ON by the BLANKING input high.
The UCN5910A and UCN5910A-2 are furnished in a 20-pin dual in-line
plastic package. The surface-mount UCN5910LW and UCN5910LW-2 are
furnished in a wide-body, small-outline plastic package (SOIC) with gull-wing
leads. Copper lead frames, reduced supply current requirements, and lower
output saturation voltages allow all devices to be operated at
20 mA from all
outputs (50% duty cycle), at ambient temperatures up to +30
C, or at
15 mA
to +55
C.
FEATURES
s High-Speed Source Drivers
s 140 V (suffix "-2") or 150 V
Minimum Output Breakdown
s Improved Replacements
for TL4810B
ABSOLUTE MAXIMUM RATINGS
at T
A
= 25
C
Logic Supply Voltage, V
DD
................ 15 V
Driver Supply Voltage, V
BB
UCN5910A/LW ......................... 150 V
Suffix "-2" .................................. 140 V
Continuous Output Current Range,
I
OUT
....................... -30 mA to +40 mA
Input Voltage Range,
V
IN
.................... -0.3 V to V
DD
+ 0.3 V
Package Power Dissipation, P
D
. See Graph
Operating Temperature Range,
T
A
............................... -20
C to +85
C
Storage Temperature Range,
T
S
.............................. -55
C to +150
C
Caution: CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
Note that the dual in-line package (designator
`A') and small-outline IC package (designator
`LW') are electrically identical and share a
common terminal number assignment.
s Low Output Saturation Voltages
s Low-Power CMOS Logic and Latches
s To 3.3 MHz Data Input Rate
s Active DMOS Pull-Downs
REGISTER
LATCHES
SERIAL
DATA OUT
LOAD
SUPPLY (6-10)
SERIAL
DATA IN
BLANKING
BLNK
V
OUT
1
OUT
2
OUT
3
LOGIC
SUPPLY
STROBE
ST
V
DD
OUT
5
OUT
4
1
2
3
8
9
13
14
15
16
17
19
4
5
6
7
12
18
20
LOGIC
GROUND
CLOCK
CLK
BB
OUT
9
OUT
10
Dwg. PP-029-14
OUT
8
OUT
7
OUT
6
LATCHES
REGISTER
10
11
POWER
GROUND
LOAD
SUPPLY (1-5)
V
BB
SUB
PRELIMINARY INFORMATION
(Subject to change without notice)
January 18, 2000
5910
Data Sheet
26182.2A
5910
HIGH-VOLTAGE BiMOS III
10-BIT SERIAL-INPUT,
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
FUNCTIONAL BLOCK DIAGRAM
Dwg. No. A-14,219
50
75
100
125
150
2.5
0.5
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE IN
C
2.0
1.5
1.0
25
Dwg. GS-004A
SU
FF
IX
'L
W
', R
=
7
0
C/W
JA
SUFFIX 'A', R = 55
C/W
JA
V
OUT
BB
N
Copyright 1984, 1999, Allegro MicroSystems, Inc.
MOS
BIPOLAR
OUT
1
OUT
2
GROUND
Dwg. FP-013-1
OUT
3
OUT
N
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
V
DD
V
BB
LOGIC
SUPPLY
LOAD
SUPPLY
Dwg. EP-010-4A
IN
V
DD
TYPICAL INPUT CIRCUIT
TYPICAL OUTPUT DRIVER
5910
HIGH-VOLTAGE BiMOS III
10-BIT SERIAL-INPUT,
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
TRUTH TABLE
Serial
Shift Register Contents
Serial
Latch Contents
Output Contents
Data Clock
Data
Strobe
Input Input I
1
I
2
I
3
... I
N-1
I
N
Output Input
I
1
I
2
I
3
... I
N-1
I
N
Blanking
I
1
I
2
I
3
... I
N-1
I
N
H
H
R
1
R
2
...
R
N-2
R
N-1
R
N-1
L
L
R
1
R
2
...
R
N-2
R
N-1
R
N-1
X
R
1
R
2
R
3
...
R
N-1
R
N
R
N
X
X
X
...
X
X
X
L
R
1
R
2
R
3
...
R
N-1
R
N
P
1
P
2
P
3
...
P
N-1
P
N
P
N
H
P
1
P
2
P
3
...
P
N-1
P
N
L
P
1
P
2
P
3
... P
N-1
P
N
X
X
X
...
X
X
H
L
L
L
... L L
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
Serial Data present at the input is transferred
to the shift register on the logic "0" to logic "1"
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the BLANKING input be high during
serial data entry.
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON. The information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
TIMING CONDITIONS
(T
A
= +25
C, V
DD
= 12 V, Logic Levels are V
DD
and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) ...........................................................................
75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ...............................................................................
75 ns
C. Minimum Data Pulse Width ............................................................. 150 ns
D. Minimum Clock Pulse Width ........................................................... 100 ns
E. Minimum Time Between Clock Activation and Strobe .................... 300 ns
F. Minimum Strobe Pulse Width .......................................................... 100 ns
G. Typical Time Between Strobe Activation and
Output Transition .............................................................................
750 ns
E F
CLOCK
DATA IN
STROBE
BLANKING
OUT
N
A D
B
C
G
Dwg. No. A-12,649A
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