Data Sheet
29319.36A
3948
DMOS FULL-BRIDGE PWM
MOTOR DRIVER
Always order by complete part number:
Part Number
Package
R
JA
R
JT
A3948SB
24-pin batwing DIP
40
C/W
6
C/W
A3948SLB
24-lead batwing SOIC
77
C/W
6
C/W
Designed for pulse-width modulated (PWM) current control of dc
motors, the A3948SB and A3948SLB are capable of continuous output
currents to
1.5 A and operating voltages to 50 V. Internal fixed off-
time PWM current-control timing circuitry can be programmed via a
serial interface to operate in slow, fast, and mixed current-decay
modes. Similar devices with outputs rated to
2 A are available as the
A3958SB/SLB.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a dc motor with externally
applied PWM-control signals. The ENABLE input can be
programmed via the serial port to PWM the bridge in fast or slow
current decay. Internal synchronous rectification control circuitry is
provided to reduce power dissipation during PWM operation.
Internal circuit protection includes thermal shutdown with
hysteresis, and crossover-current protection. Special power-up
sequencing is not required.
The A3948SB/SLB is supplied in a choice of two power
packages, a 24-pin plastic DIP with a copper batwing tab (package
suffix `B'), and a 24-lead plastic SOIC with a copper batwing tab
(package suffix `LB'). In both cases, the power tab is at ground
potential and needs no electrical isolation.
FEATURES
s
1.5 A, 50 V Continuous Output Rating
s Low
r
DS(on)
Outputs
s Programmable Mixed, Fast, and Slow Current-Decay Modes
s Serial Interface Controls Chip Functions
s Synchronous Rectification for Low Power Dissipation
s Internal UVLO and Thermal-Shutdown Circuitry
s Crossover-Current Protection
A3948SLB
(SOIC)
SERIAL PORT
V
BB
24
23
22
21
20
19
18
17
16
15
14
13
GROUND
GROUND
RANGE
NO
CONNECTION
OUT
B
LOAD SUPPLY
SENSE
OUT
A
NO
CONNECTION
MODE
REF
V
REG
Dwg. PP-069A
1
2
3
4
5
6
7
8
9
12
11
10
9
GROUND
GROUND
CP
CP
2
CP
1
PHASE
V
DD
ENABLE
DATA
CLOCK
STROBE
LOGIC SUPPLY
OSC
LOGIC
NC
NC
CHARGE PUMP
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, V
BB
.................. 50 V
Output Current, I
OUT
........................
1.5 A
Logic Supply Voltage, V
DD
................ 7.0 V
Input Voltage, V
IN
.... -0.3 V to V
DD
+ 0.3 V
Sense Voltage, V
S
.......................... 0.55 V
Reference Voltage, V
REF
.................. 5.5 V
Package Power Dissipation (T
A
= 25
C), P
D
A3948SB ................................. 3.1 W*
A3948SLB ............................... 1.6 W*
Operating Temperature Range,
T
A
............................... -20
C to +85
C
Junction Temperature,
T
J
............................................ +150
C
Storage Temperature Range,
T
S
............................. -55
C to +150
C
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specified
current rating or a junction temperature of 150
C.
* Per SEMI G42-88 Specification.
Note that the A3948SLB(SOIC) and A3948SB
(DIP) do not share a common terminal
assignment.
3948
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
2
Copyright 2001, 2002 Allegro MicroSystems, Inc.
FUNCTIONAL BLOCK DIAGRAM
A3948SB
(DIP)
Note that the A3948SLB (SOIC) and A3948SB
(DIP) do not share a common terminal
assignment.
CHARGE PUMP
BANDGAP
V
DD
C
REG
TSD
UNDER-
VOLTAGE &
FAULT DETECT
CHARGE
PUMP
BANDGAP
REGULATOR
V
DD
V
BB
+
LOGIC
SUPPLY
V
REG
CP1
CP
CP2
LOAD
SUPPLY
GATE DRIVE
Dwg. FP-048
SLEEP
MODE
RANGE
CONTROL LOGIC
PHASE
ENABLE
SYNC RECT MODE
SYNC RECT DISABLE
PWM MODE INT
PWM MODE EXT
PROGRAMMABLE
PWM TIMER
SENSE
R
S
FIXED OFF
BLANK
DECAY
MODE
PHASE
ENABLE
CLOCK
DATA
STROBE
RANGE
REFERENCE
BUFFER &
DIVIDER
CURRENT
SENSE
ZERO
CURRENT
DETECT
OSC
OUT
A
OUT
B
REF
SERIAL
PORT
V
REF
C
S
SERIAL PORT
V
BB
24
23
22
21
20
19
18
17
16
15
14
13
GROUND
GROUND
RANGE
V
REG
OUT
B
LOAD
SUPPLY
SENSE
OUT
A
MODE
REF
Dwg. PP-069-1A
1
2
3
4
5
6
7
8
9
12
11
10
9
GROUND
GROUND
CP
CP
2
CP
1
PHASE
V
DD
LOGIC
SUPPLY
ENABLE
DATA
CLOCK
STROBE
OSC
LOGIC
CHARGE PUMP
GROUND
GROUND
3948
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
www.allegromicro.com
3
ELECTRICAL CHARACTERISTICS at T
A
= +25
C, V
BB
= 50 V, V
DD
= 5.0 V, V
SENSE
= 0.5 V,
f
PWM
< 50 kHz (unless noted otherwise)
Limits
Characteristics
Symbol Test Conditions
Min.
Typ. Max.
Units
Output Drivers
Load Supply Voltage Range
V
BB
Operating
20
50
V
During sleep mode
0
50
V
Output Leakage Current
I
DSS
V
OUT
= V
BB
<1.0
20
A
V
OUT
= 0 V
<-1.0
-20
A
Output On Resistance
r
DS(on)
Source driver, I
OUT
= -1.5 A
500
550
m
Sink driver, I
OUT
= 1.5 A
300
350
m
Body Diode Forward Voltage
V
F
Source diode, I
F
= -1.5 A
1.0
1.3
V
Sink diode, I
F
= 1.5 A
1.0
1.3
V
Load Supply Current
I
BB
f
PWM
< 50 kHz
4.0
7.0
mA
Charge pump on, outputs disabled
2.0
5.0
mA
Sleep Mode
20
A
Control Logic
Logic Supply Voltage Range
V
DD
Operating
4.5
5.0
5.5
V
Logic Input Voltage
V
IN(1)
2.0
V
V
IN(0)
0.8
V
Logic Input Current
I
IN(1)
V
IN
= 2.0 V
<1.0
20
A
(all inputs except ENABLE)
I
IN(0)
V
IN
= 0.8 V
<-2.0
-20
A
ENABLE Input Current
I
IN(1)
V
IN
= 2.0 V
40
100
A
I
IN(0)
V
IN
= 0.8 V
16
40
A
OSC input frequency
f
OSC
Operating
1.8
6.1
MHz
OSC input duty cycle
dc
OSC
Operating
40
60
%
OSC input hysteresis
Operating
200
400
mV
Input Hysterisis
All digital inputs except OSC
50
100
mV
Reference Input Volt. Range
V
REF
Operating
0.0
V
DD
- 0.1
V
Reference Input Current
I
REF
V
REF
= 2.5 V
0.5
A
Comparator Input Offset Volt.
V
IO
V
REF
= 0 V
0
5.0
mV
Continued next page ...
3948
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
4
ELECTRICAL CHARACTERISTICS at T
A
= +25
C, V
BB
= 50 V, V
DD
= 5.0 V, V
SENSE
= 0.5 V,
f
PWM
< 50 kHz (unless noted otherwise), continued.
Limits
Characteristics
Symbol Test Conditions
Min.
Typ. Max.
Units
Control Logic
Buffer Input Offset Volt.
V
IO
0
15
mV
Reference Divider Ratio
D14 = High
9.9
10
10.2
D14 = Low
4.95
5.0
5.05
Propagation Delay Times
t
pd
PWM change to source ON
600
ns
PWM change to source OFF
100
ns
PWM change to sink ON
600
ns
PWM change to sink OFF
100
ns
Phase change to sink ON
600
ns
Phase change to sink OFF
100
ns
Phase change to source ON
600
ns
Phase change to source OFF
100
ns
Thermal Shutdown Temp.
T
J
165
C
Thermal Shutdown Hysteresis
T
J
15
C
UVLO Enable Threshold
UVLO
Increasing V
DD
3.90
4.2
4.45
V
UVLO Hysteresis
UVLO0.05
0.10
V
Logic Supply Current
I
DD
f
PWM
< 50 kHz
6.0
10
mA
Sleep Mode, Inputs < 0.5 V
2.0
mA
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device terminal.
3948
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
www.allegromicro.com
5
FUNCTIONAL DESCRIPTION
Serial Interface. The A3948 is controlled via a 3-wire
(clock, data, strobe) serial port. The programmable
functions allow maximum flexibility in configuring the
PWM to the motor drive requirements. The serial data is
clocked in starting with D19.
Bit
Function
D0
Blank Time LSB
D1
Blank Time MSB
D2
Off Time LSB
D3
Off Time Bit 1
D4
Off Time Bit 2
D5
Off Time Bit 3
D6
Off Time MSB
D7
Fast Decay Time LSB
D8
Fast Decay Time Bit 1
D9
Fast Decay Time Bit 2
D10
Fast Decay Time MSB
D11
Sync. Rect. Mode
D12
Sync. Rect. Enable
D13
External PWM Mode
D14
Enable
D15
Phase
D16
Reference Range Select
D17
Internal PWM Mode
D18
Test Use Only
D19
Sleep Mode
D0 D1 Blank Time. The current-sense comparator is
blanked when any output driver is switched on, according
to the table below. f
osc
is the oscillator input frequency.
D1
D0
Blank Time
0
0
4/f
osc
0
1
6/f
osc
1
0
12/f
osc
1
1
24/f
osc
D2 D6 Fixed-Off Time. A five-bit word sets the
fixed-off time for internal PWM current control. The off
time is defined by
t
off
= (8[1 + N]/f
osc
) - 1/f
osc
where N = 0 ... 31
For example, with an oscillator frequency of 4 MHz, the
off time will be adjustable from 1.75
s to 63.75
s in
increments of 2
s.
D7 D10 Fast Decay Time. A four-bit word sets the
fast-decay portion of the fixed-off time for the internal
PWM control circuitry. This will only have impact if the
mixed-decay mode is selected (via bit D17 and the MODE
input terminal). For t
fd
> t
off
, the device will effectively
operate in the fast-decay mode. The fast decay portion is
defined by
t
fd
= (8[1 + N]/f
osc
) - 1/f
osc
where N = 0 ... 15
For example, with an oscillator frequency of 4 MHz, the
fast decay time will be adjustable from 1.75
s to
31.75
s in increments of 2
s.
D11 Synchronous Rectification Mode. The active
mode prevents reversal of load current by turning off
synchronous rectification when a zero current level is
detected. The passive mode will allow reversal of current
but will turn off the synchronous rectifier circuit if the
load current inversion ramps up to the current limit set by
V
REF
/R
S
.
D11
Mode
0
Active
1
Passive
D12 Synchronous Rectification Enable.
D12
Synchronous Rect.
0
Disabled
1
Enabled
D13 External PWM Decay Mode. Bit D13 determines
the current-decay mode when using ENABLE chopping
for external PWM current control.
D13
Mode
0
Fast
1
Slow
D14 Enable Logic. Bit D14, in conjunction with
ENABLE, determines if the output drivers are in the
chopped (OFF)(ENABLE = D14) or ON (ENABLE
D14) state.
ENABLE
D14
Mode
0
0
Chopped
1
0
O
n
0
1
O
n
1
1
Chopped
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