Data Sheet

29319.37E

3959

DMOS FULL-BRIDGE PWM

MOTOR DRIVER

Always order by complete part number:

Part Number

Package

A3959SB

24-pin batwing DIP

38°C/W 6°C/W

A3959SB-T

24-pin batwing DIP; Lead-free

38°C/W 6°C/W

A3959SLB

24-lead batwing SOIC

50°C/W 6°C/W

A3959SLB-T

24-lead batwing SOIC; Lead-free

50°C/W 6°C/W

A3959SLP

28-lead thin shrink SOIC

40°C/W

A3959SLP-T

28-lead thin shrink SOIC; Lead-free

40°C/W

Designed for pulse-width modulated (PWM) current control of dc

motors, the A3959SB, A3959SLB, and A3959SLP are capable of
output currents to ±3 A and operating voltages to 50 V. Internal fixed
off-time PWM current-control timing circuitry can be adjusted via
control inputs to operate in slow, fast, and mixed current-decay modes.

PHASE and ENABLE input terminals are provided for use in

controlling the speed and direction of a dc motor with externally
applied PWM-control signals. Internal synchronous rectification
control circuitry is provided to reduce power dissipation during PWM
operation.

Internal circuit protection includes thermal shutdown with

hysteresis, undervoltage monitoring of supply and charge pump, and
crossover-current protection. Special power-up sequencing is not
required.

The A3959SB/SLB/SLP is a choice of three power packages, a

24-pin plastic DIP with a copper batwing tab (package suffix `B'), a
24-lead plastic SOIC with a copper batwing tab (package suffix `LB'),
and a thin (<1.2 mm) 28-lead plastic TSSOP with an exposed thermal
pad (suffix `LP'). In all cases, the power tab is at ground potential and
needs no electrical isolation.

Each package is available in a lead-

free version (100% matte tin leadframe).

FEATURES

±3 A, 50 V Output Rating

Low

DS(on)

Outputs (270 m

, Typical)

Mixed, Fast, and Slow Current-Decay Modes

Synchronous Rectification for Low Power Dissipation

Internal UVLO and Thermal-Shutdown Circuitry

Crossover-Current Protection

Internal Oscillator for Digital PWM Timing

A3959SLB

(SOIC)

ABSOLUTE MAXIMUM RATINGS

Load Supply Voltage, V

......................... 50 V

Output Current, I

OUT

(Repetitive) ........... ±3.0 A

(Peak, <3 µs) ................................... ±6.0 A

Logic Supply Voltage, V

....................... 7.0 V

Logic Input Voltage Range, V

(Continuous) ............ -0.3 V to V

+ 0.3 V

<30 ns) ............... -1.0 V to V

+ 1.0 V

Sense Voltage, V

(Continuous) .............. 0.5 V

<3 µs) ........................................... 2.5 V

Reference Voltage, V

REF

............................ V

Package Power Dissipation (T

= 25°C), P

A3959SB ........................................ 3.3 W*
A3959SLB ...................................... 2.5 W*
A3959SLP ...................................... 3.1 W*

Operating Temp. Range, T

.... -20°C to +85°C

Junction Temperature, T

..................... +150°C

Storage Temp. Range, T

..... -55°C to +150°C

Output current rating may be limited by duty cycle,

ambient temperature, and heat sinking. Under any

set of conditions, do not exceed the specified
current rating or a junction temperature of 150°C.

Note that the A3959SLB(SOIC), A3959SB (DIP),

and A3959SLP (TSSOP) do not share a common

terminal assignment.

* Double-sided board, one square inch copper each side. See also, Layout, page 7.

PWM TIMER

GROUND

SLEEP

NO
CONNECTION

OUT

LOAD SUPPLY

SENSE

OUT

NO
CONNECTION

EXT MODE

REF

REG

Dwg. PP-069-4

GROUND

PHASE

ENABLE

PFD

BLANK

PFD

LOGIC SUPPLY

ROSC

LOGIC

CHARGE PUMP

3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000

FUNCTIONAL BLOCK DIAGRAM

A3959SB

(DIP)

Note that the A3959SLB (SOIC), A3959SB (DIP),
and A3959SLP (TSSOP) do not share a common
terminal assignment.

CHARGE PUMP

BANDGAP

REG

TSD

UNDER-

VOLTAGE &

FAULT DETECT

CHARGE

PUMP

BANDGAP

REGULATOR

LOGIC

SUPPLY

REG

CP1

CP2

LOAD
SUPPLY

GATE DRIVE

Dwg. FP-048-2A

CONTROL LOGIC

SENSE

SLEEP

EXT MODE

PHASE

ENABLE

BLANK

PFD1

PFD2

REFERENCE

BUFFER &

CURRENT

SENSE

ZERO

CURRENT

DETECT

OUT

REF

PWM

TIMER

REF

OSC

ROSC

TO V

PWM TIMER

GROUND

SLEEP

REG

OUT

LOAD
SUPPLY

SENSE

OUT

EXT MODE

REF

Dwg. PP-069-5A

GROUND

PHASE

LOGIC

SUPPLY

ENABLE

PFD

BLANK

PFD

ROSC

LOGIC

CHARGE PUMP

GROUND

3959

DMOS FULL-BRIDGE

PWM MOTOR DRIVER

www.allegromicro.com

ELECTRICAL CHARACTERISTICS at T

= +25

C, V

= 50 V, V

= 5.0 V, V

SENSE

= 0.5 V,

PWM

< 50 kHz (unless noted otherwise)

Limits

Characteristics

Symbol Test Conditions

Min.

Typ. Max.

Units

Output Drivers

Load Supply Voltage Range

Operating

9.5

During sleep mode

Output Leakage Current

DSS

OUT

= V

<1.0

OUT

= 0 V

<-1.0

-20

Output On Resistance

DS(on)

Source driver, I

OUT

= -3 A

270

300

Sink driver, I

OUT

= 3 A

270

300

Crossover Delay

300

600

1000

Body Diode Forward Voltage

Source diode, I

= -3 A

1.6

Sink diode, I

= 3 A

1.6

Load Supply Current

PWM

< 50 kHz

4.0

7.0

Charge pump on, outputs disabled

2.0

5.0

Sleep Mode

Control Logic

Logic Supply Voltage Range

Operating

4.5

5.0

5.5

Logic Input Voltage

IN(1)

2.0

IN(0)

0.8

Logic Input Current

IN(1)

= 2.0 V

<1.0

(all inputs except ENABLE)

IN(0)

= 0.8 V

<-2.0

-20

ENABLE Input Current

IN(1)

= 2.0 V

100

IN(0)

= 0.8 V

Internal OSC frequency

OSC

shorted to GROUND

3.25

4.25

5.25

MHz

OSC

= 51 k

3.65

4.25

4.85

MHz

Reference Input Volt. Range

REF

Operating

0.0

Reference Input Current

REF

= V

1.0

Comparator Input Offset Volt.

REF

= 0 V

5.0

Continued next page ...

3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER

115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000

ELECTRICAL CHARACTERISTICS at T

= +25

C, V

= 50 V, V

= 5.0 V, V

SENSE

= 0.5 V,

PWM

< 50 kHz (unless noted otherwise), continued.

Limits

Characteristics

Symbol Test Conditions

Min.

Typ. Max.

Units

Control Logic

Reference Divider Ratio

Error

REF

= V

4.0

(Note 3)

REF

= 0.5 V

Propagation Delay Times

0.5 E

to 0.9 E

out

PWM change to source on

600

750

1200

PWM change to source off

150

350

PWM change to sink on

600

750

1200

PWM change to sink off

100

150

Thermal Shutdown Temp.

165

Thermal Shutdown Hysteresis

UVLO Enable ThresholdUVLO

Increasing V

3.90

4.2

4.45

UVLO Hysteresis

UVLO

0.05

0.10

Logic Supply Current

PWM

< 50 kHz

6.0

Sleep Mode

2.0

NOTES: 1. Typical Data is for design information only.

2. Negative current is defined as coming out of (sourcing) the specified device terminal.

3. G

error = ([V

REF

/10] V

SENSE

)/(V

REF

/10) where

SENSE

= I

TRIP

·R

3959

DMOS FULL-BRIDGE

PWM MOTOR DRIVER

www.allegromicro.com

FUNCTIONAL DESCRIPTION

REG

. This internally generated voltage is used to operate

the sink-side DMOS outputs. The V

REG

terminal should

be decoupled with a 0.22

F capacitor to ground. V

REG

internally monitored and in the case of a fault condition,
the outputs of the device are disabled.

Charge Pump. The charge pump is used to generate a
gate-supply voltage greater than V

to drive the source-

side DMOS gates. A 0.22

F ceramic capacitor should be

connected between CP1 and CP2 for pumping purposes.
A 0.22

F ceramic capacitor should be connected between

CP and V

to act as a reservoir to operate the high-side

DMOS devices. The CP voltage is internally monitored
and, in the case of a fault condition, the source outputs of
the device are disabled.

PHASE Logic. The PHASE input terminal determines if
the device is operating in the "forward" or "reverse" state.

PHASE

OUT

Low

High

Low

ENABLE Logic. The ENABLE input terminal allows
external PWM. ENABLE high turns on the selected sink-
source pair. ENABLE low switches off the source driver
or the source and sink driver, depending on EXT MODE,
and the load current decays. If ENABLE is kept high, the
current will rise until it reaches the level set by the internal
current-control circuit.

ENABLE

Outputs

Chopped

EXT MODE Logic. When using external PWM current
control, the EXT MODE input determines the current path
during the chopped cycle. With EXT MODE low, fast
decay mode, the opposite pair of selected outputs will be
enabled during the off cycle. With EXT MODE high,
slow decay mode, both sink drivers are on with ENABLE
low.

EXT MODE

Decay

Fast

Slow

Current Regulation. Load current is regulated by an
internal fixed off-time PWM control circuit. When the
outputs of the DMOS H bridge are turned on, the current
increases in the motor winding until it reaches a trip value
determined by the external sense resistor (R

) and the

applied analog reference voltage (V

REF

TRIP

= V

REF

/10R

At the trip point, the sense comparator resets the source-
enable latch, turning off the source driver. The load
inductance then causes the current to recirculate for the
fixed off-time period. The current path during
recirculation is determined by the configuration of slow/
mixed/fast current-decay mode via PFD1 and PFD2.

Oscillator. The PWM timer is based on an internal
oscillator set by a resistor connected from the R

OSC

terminal to V

. Typical value of 4 MHz is set with a

51 k

resistor. The allowable range of the resistor is from

20 k

to 100 k

OSC

= 204 x 10

OSC

If R

OSC

is not pulled up to V

, it must be shorted to

ground.

Fixed Off Time. The A3959 is set for a fixed off time of
96 cycles of the internal oscillator, typically 24

s with a

4 MHz oscillator.

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