MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
ABSOLUTE MAXIMUM RATINGS
at T
A
= +25C
Load Supply Voltage, V
BB
............. 35 V
Output Current, I
OUT
.................. 2.5 A
*
Logic Supply Voltage, V
DD
........... 7.0 V
Logic Input Voltage Range, V
IN
(t
w
>30 ns) ..... -0.3 V to V
DD
+ 0.3 V
(t
w
<30 ns) ........... -1 V to V
DD
+ 1 V
Sense Voltage, V
SENSE
................. 0.5 V
Reference Voltage, V
REF
................ V
DD
Package Power Dissipation,
P
D
................................. See page 3
Operating Temperature Range, T
A
(A3977Kx) ............ -40C to +125C
(A3977Sx) .............. -20C to +85C
Junction Temperature, T
J
......... +150C
Storage Temperature Range,
T
S
......................... -55C to +150C
* Output current rating may be limited by
duty cycle, ambient temperature, and heat
sinking. Under any set of conditions, do not
exceed the specified current rating or a
junction temperature of 150C.
Data Sheet
26184.22D
3977
The A3977xED and A3977xLP are complete microstepping motor drivers
with built-in translator. They are designed to operate bipolar stepper motors in
full-, half-, quarter-, and eighth-step modes, with output drive capability of 35
V and 2.5 A. The A3977 includes a fixed off-time current regulator that has
the ability to operate in slow-, fast-, or mixed-decay modes. This current-
decay control scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.
The translator is the key to the easy implementation of the A3977. By
simply inputting one pulse on the STEP input the motor will take one step
(full, half, quarter, or eighth depending on two logic inputs). There are no
phase-sequence tables, high-frequency control lines, or complex interfaces to
program. The A3977 interface is an ideal fit for applications where a complex
P is unavailable or over-burdened.
Internal synchronous-rectification control circuitry is provided to improve
power dissipation during PWM operation.
Internal circuit protection includes thermal shutdown with hysteresis,
under-voltage lockout (UVLO) and crossover-current protection. Special
power-up sequencing is not required.
The A3977 is supplied in a choice of two power packages, a 44-pin
plastic PLCC with copper batwing tabs (suffix ED), and a thin (<1.2 mm), 28-
pin TSSOP with an exposed thermal pad (suffix LP). The SLP package is
available in a lead-free version (100% matte tin leadframe).
FEATURES
2.5 A, 35 V Output Rating
Low r
DS(on)
Outputs, 0.45
Source, 0.36
Sink Typical
Automatic Current Decay Mode Detection/Selection
3.0 V to 5.5 V Logic Supply Voltage Range
Mixed, Fast, and Slow Current Decay Modes
Home Output
Synchronous Rectification for Low Power Dissipation
Internal UVLO and Thermal Shutdown Circuitry
Crossover-Current Protection
A3977xED
(PLCC)
6
5
4
3
2
1
44
43
42
41
40
7
8
9
10
11
12
13
14
15
16
17
29
30
39
38
37
36
35
34
33
32
31
28
27
26
25
24
23
22
21
20
19
18
Dwg. PP-075-1
GND
GND
LOGIC
SUPPLY
NC
GND
GND
REF
RC
2
NC
NC
STEP
V
REG
GND
GND
V
CP
CP
1
CP
2
NC
CHARGE PUMP
V
DD
V
BB1
V
BB2
NC
NC
PFD
RC
1
8
REG
PWM
TIMER
TRANSLATOR
& CONTROL LOGIC
GND
GND
SENSE
1A
1B
ENABLE
LOAD SUPPLY
GND
SLEEP
HOME
DIR
OUT
OUT
1
1
OUT
2A
SENSE
GND
GND
GND
LOAD
SUPPLY
2
OUT
2B
MS
MS
RESET
SR
2
2
1
Always order by complete part number:
Part Number
Package
A3977KED
44-pin PLCC
A3977KLP
28-pin TSSOP
A3977SED
44-pin PLCC
A3977SED-T
44-pin PLCC; Lead-free
A3977SLP
28-pin TSSOP
A3977SLP-T
28-pin TSSOP; Lead-free
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
www.allegromicro.com
3
Table 1. Microstep Resolution Truth Table
MS
1
MS
2
Resolution
L
L
Full step (2 phase)
H
L
Half step
L
H
Quarter step
H
H
Eighth step
A3977xLP
(TSSOP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
LOAD
SUPPLY
1
SLEEP
ENABLE
OUT
1B
CP
2
CP
1
V
CP
PGND
V
REG
STEP
OUT
2B
RESET
SR
LOAD
SUPPLY
2
SENSE
1
HOME
DIR
OUT
1A
PFD
RC
1
AGND
REF
RC
2
LOGIC
SUPPLY
OUT
2A
MS
2
MS
1
SENSE
2
8
REG
CHARGE PUMP
PWM
TIMER
TRANSLATOR
& CONTROL LOGIC
V
BB2
V
BB1
V
DD
Dwg. PP-075
Package Thermal Resistance, R
JA
A3977xLP ......................... 28
C/W
*
A3977xED ........................ 32
C/W
A3977xLP ......................... 33
C/W
*
Measured on JEDEC standard "High-K" four-layer board.
Measured on typical two-sided PCB with three square inches
(1935 mm
2
) copper ground area.
50
75
100
125
150
5.0
1.0
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE IN
C
4.0
3.0
2.0
25
SUFFIX 'LP',
R
JA
= 33
C/W
Dwg. GP-018-2A
SUFFIX 'ED', R
JA
= 32
C/W
SUFFIX 'LP', R
JA
= 28
C/W*
SUFFIX 'K'
SUFFIX 'S'
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
3977
MICROSTEPPING DMOS DRIVER
WITH TRANSLATOR
4
ELECTRICAL CHARACTERISTICS at T
A
= +25
C, V
BB
= 35 V, V
DD
= 3.0 V to 5.5V (unless otherwise
noted)
Limits
Characteristic
Symbol Test Conditions
Min.
Typ.
Max.
Units
Output Drivers
Load Supply Voltage Range
V
BB
Operating
8.0
35
V
During sleep mode
0
35
V
Output Leakage Current
I
DSS
V
OUT
= V
BB
<1.0
20
A
V
OUT
= 0 V
<1.0
-20
A
Output On Resistance
r
DS(on)
Source driver, I
OUT
= -2.5 A
0.45
0.57
Sink driver, I
OUT
= 2.5 A
0.36
0.43
Body Diode Forward Voltage
V
F
Source diode, I
F
= -2.5 A
1.4
V
Sink diode, I
F
= 2.5 A
1.4
V
Motor Supply Current
I
BB
f
PWM
< 50 kHz
8.0
mA
Operating, outputs disabled
6.0
mA
Sleep mode
20
A
Control Logic
Logic Supply Voltage Range
V
DD
Operating
3.0
5.0
5.5
V
Logic Input Voltage
V
IN(1)
0.7V
DD
V
V
IN(0)
0.3V
DD
V
Logic Input Current
I
IN(1)
V
IN
= 0.7V
DD
-20
<1.0
20
A
I
IN(0)
V
IN
= 0.3V
DD
-20
<1.0
20
A
Maximum STEP Frequency
f
STEP
500*
kHz
HOME Output Voltage
V
OH
I
OH
= -200
A
0.7V
DD
V
V
OL
I
OL
= 200
A
0.3V
DD
V
Blank Time
t
BLANK
R
t
= 56 k
, C
t
= 680 pF
700
950
1200
ns
Fixed Off Time
t
off
R
t
= 56 k
, C
t
= 680 pF
30
38
46
s
continued next page ...
3977
MICROSTEPPPING DMOS DRIVER
WITH TRANSLATOR
www.allegromicro.com
5
ELECTRICAL CHARACTERISTICS at T
A
= +25C, V
BB
= 35 V, V
DD
= 3.0 V to 5.5V (unless otherwise
noted)
Characteristic
Symbol
Test Conditions
Limits
Min.
Typ.
Max.
Units
Control Logic (cont'd)
Mixed Decay Trip Point
PFDH
0.6V
DD
V
PFDL
0.21V
DD
V
Ref. Input Voltage Range
V
REF
Operating
0
V
DD
V
Reference Input Current
I
REF
0
3.0
A
Gain (G
m
) Error
(note 3)
E
G
V
REF
= 2 V, Phase Current = 38.27%
10
%
V
REF
= 2 V, Phase Current = 70.71%
5.0
%
V
REF
= 2 V, Phase Current = 100.00%
5.0
%
Crossover Dead Time
t
DT
SR enabled
100
475
800
ns
Thermal Shutdown Temp.
T
J
165
C
Thermal Shutdown Hysteresis
T
J
15
C
UVLO Enable Threshold
V
UVLO
Increasing V
DD
2.45
2.7
2.95
V
UVLO Hysteresis
V
UVLO
0.05
0.10
V
Logic Supply Current
I
DD
f
PWM
< 50 kHz
12
mA
Outputs off
10
mA
Sleep mode
20
A
* Operation at a step frequency greater than the specifi ed minimum value is possible but not warranteed.
NOTES: 1. Typical Data is for design information only.
2. Negative current is defi ned as coming out of (sourcing) the specifi ed device terminal.
3. E
G
= ([V
REF
/8] V
SENSE
)/(V
REF
/8)
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