Description

The A6278 and A6279 devices are specifically designed for
LED display applications. Each of these BiCMOS devices
includes a CMOS shift register, accompanying data latches,
and NPN constant-current sink drivers. The A6278 contains
8 sink drivers, while there are 16 in the A6279.

The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, typical serial data-input rates can reach up to 25 MHz.
The LED drive current is determined by the user's selection of
a single resistor. A CMOS serial data output permits cascading
between multiple devices in applications requiring additional
drive lines. Open LED connections can be detected and signaled
back to the host microprocessor through the SERIAL DATA
OUT pin.

Three package styles are provided: a DIP (type A) for through-
hole applications; and for leaded surface-mount, an SOIC (type
LW) and a TSSOP with exposed thermal pad (type LP). All
package styles for the A6278 are electrically identical to each
other, as are the A6279 package styles. All packages are lead
(Pb) free, with 100% matte tin plated leadframes.

6278-DS, Rev. 2

Features and Benefits

3.0 to 5.5 V logic supply range

Schmitt trigger inputs for improved noise immunity

Power-On Reset (POR)
Up to 90 mA constant-current sinking outputs
LED open circuit detection
Low-power CMOS logic and latches
High data input rate
20 ns typical staggering delay on the outputs
Internal UVLO and thermal shutdown (TSD) circuitry

Serial-Input Constant-Current Latched

LED Drivers with Open LED Detection

Functional Block Diagram

Not to scale

A6278

and

A6279

Packages:
16 and 24 pin DIP (suffix A)
16 and 24 pin TSSOP (suffix LP)
16 and 24 pin SOIC (suffix LW)

SERIAL
DATA OUT

SERIAL

DATA IN

LATCH

ENABLE

OUT0 OUT1

OUT7 (A6278)
OUT15 (A6279)

OUTPUT

ENABLE

UVLO

LOGIC

SUPPLY

Regulator

REXT

Serial - Parallel Shift Register

Control Logic

Block

CLOCK

Output Control Drivers and Open Circuit Detector

GND

LED

Exposed Pad
(LP package)

Latches

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6278

and

A6279

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

Selection Guide

Part Number

Packing

Package Type

Terminals

LED Drive Lines

A6278EA-T

25 pieces per tube

DIP

A6278ELP-T

96 pieces per tube

TSSOP with exposed thermal pad

A6278ELPTR-T

4000 pieces per 13-in. reel

A6278ELW-T

47 pieces per tube

SOICW

A6278ELWTR-T

1000 pieces per 13-in. reel

A6279EA-T

15 pieces per tube

DIP

A6279ELP-T

65 pieces per tube

TSSOP with exposed thermal pad

A6279ELPTR-T

4000 pieces per 13-in. reel

A6279ELW-T

31 pieces per tube

SOICW

A6279ELWTR-T

1000 pieces per 13-in. reel

Parameter

Symbol

Conditions

Min.

Typ. Max. Units

LOGIC SUPPLY Voltage Range

7.0

Load Supply Voltage Range

LED

0.5

OUTx Current (any single output)

Ground Current

GND

A6278

750

A6279

1475

Logic Input Voltage Range

0.4

+ 0.4

Operating Temperature Range (E)

°C

Junction Temperature

150

°C

Storage Temperature Range

150

°C

Absolute Maximum Ratings

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6278

and

A6279

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

3
4
5
6
7
8

14
13
12
11
10
9

GND

SERIAL DATA IN

CLOCK

LATCH ENABLE

OUT0
OUT1
OUT2
OUT3

LOGIC SUPPLY
REXT
SERIAL DATA OUT
OUTPUT ENABLE
OUT7
OUT6
OUT5
OUT4

Terminal List Table

Package A, LW, LP

16-pin

Pin-out Diagrams

Number

Name

Function

A, LW, LP

A6278

A6279

GND

Reference terminal for logic ground and power ground

SERIAL DATA IN

Serial-data input to the shift-register

CLOCK

Clock input terminal; data is shifted on the rising edge of the clock.

LATCH ENABLE

Data strobe input terminal; serial data is latched with a high-level input

5 TO 12

5 TO 20

OUT

Current-sinking output terminals

OUTPUT ENABLE

(Active low) Set low to enable output drivers; set high to turn OFF
(blank) all output drivers

SERIAL DATA OUT

CMOS serial-data output; for cascading to the next device (to that
device SERIAL DATA IN pin); for reading OCD bits.

REXT

An external resistor at this terminal establishes the output current for all
of the sink drivers.

LOGIC SUPPLY

) Logic supply voltage (typically 3.3 or 5.0 V)

No connection

LP and ET packages only; exposed thermal pad for heat dissipation

3
4
5
6
7
8

GND

SERIAL DATA IN

CLOCK

LATCH ENABLE

OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7

LOGIC SUPPLY
REXT
SERIAL DATA OUT
OUTPUT ENABLE
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8

Package A, LW, LP

24-pin

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6278

and

A6279

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

OPERATING CHARACTERISTICS

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max

Unit

ELECTRICAL CHARACTERISTICS valid at T

= 25

C, V

= 3.0 to 5.5 V, unless otherwise noted

LOGIC SUPPLY Voltage Range

Operating

3.0

5.0

5.5

Undervoltage Lockout

DD(UV)

= 0.0 5.0 V

2.4

2.85

= 5.0 0.0 V

2.15

2.55

Output Current (any single output)

= 0.7 V, R

EXT

= 225

64.2

75.5

86.8

= 0.7 V, R

EXT

= 470

34.1

40.0

45.9

= 0.6 V, R

EXT

= 3900

4.25

5.0

5.75

Output Current Matching (difference between any two
outputs at the same V

)

CE(A)

= V

CE(B)

0.7 V, R

EXT

= 225

+1.0

+6.0

CE(A)

= V

CE(B)

0.7 V, R

EXT

= 470

+1.0

+6.0

CE(A)

= V

CE(B)

0.6 V, R

EXT

= 3900

+1.0

+6.0

Output Leakage Current

CEX

= 15 V

1.0

5.0

Logic Input Voltage

0.7V

GND

0.3V

Logic Input Voltage Hysteresis

Ihys

All digital inputs

200

400

SERIAL DATA OUT Voltage

= 500 A

0.4

= 500 A

0.4

Input Resistance

OUTPUT ENABLE input, Pull Up

150

300

600

LATCH ENABLE input, Pull Down

100

200

400

LOGIC SUPPLY Current

DD(OFF)

EXT

= open, V

= 5 V

1.4

EXT

= 470 , V

= 5 V

5.0

EXT

= 225 , V

= 5 V

8.0

DD(ON)

EXT

= 3900 , V

= 0 V

3.0

EXT

= 470 , V

= 0 V

18.0

EXT

= 225 , V

= 0 V

32.0

Thermal Shutdown Temperature

JTSD

Temperature increasing

165

°C

Thermal Shutdown Hysteresis

JTSDhys

°C

Open LED Detection Threshold

CE(ODC)

> 5 mA, V

0.6 V

0.30

SWITCHING CHARACTERISTICS valid at T

= 25

C, V

= V

= 3.0 to 5.5 V, V

= 0.7 V, V

= 0 V, R

EXT

= 470 , I

= 40 mA, V

LED

= 3 V, R

LED

58 , C

LED

= 10 pF, unless otherwise noted

CLOCK Pulse Width

high,

low

Normal Mode

SERIAL DATA IN Setup Time

SU(D)

SERIAL DATA IN Hold Time

H(D)

LATCH ENABLE Setup Time

SU(LE)

LATCH ENABLE Hold Time

H(LE)

OUTPUT ENABLE Set Up Time

SU(OE)

OUTPUT ENABLE Hold Time

H(OE)

OUTPUT ENABLE Pulse Width

W(OE)

600

CLOCK to SERIAL DATA OUT Propagation Delay Time

P(DO)

OUTPUT ENABLE to OUT0 Propagation Delay Time

P(OE)

Staggering Delay (between consecutive outputs)

Total Delay Time (15 × t

)

Dtotal

300

CLOCK Pulse Width

high,

low

Test Mode, V

= 4.5 to 5.5 V

SERIAL DATA IN Setup Time

SU(D)

SERIAL DATA IN Hold Time

H(D)

LATCH ENABLE Setup Time

SU(LE)

LATCH ENABLE Hold Time

H(LE)

OUTPUT ENABLE Set Up Time

SU(OE)

OUTPUT ENABLE Hold Time

H(OE)

OUTPUT ENABLE Pulse Width*

W(OE)

2.0

CLOCK to SERIAL DATA OUT Propagation Delay Time

P(DO)

OUTPUT ENABLE to OUT0 Propagation Delay Time

P(OE)

Staggering Delay (between consecutive outputs)

Total Delay Time (15 × t

)

Dtotal

300

Output Fall Time

90% to 10% voltage

150

Output Rise Time

10% to 90% voltage

150

*See LED Open Circuit Detection (Test) mode timing diagram.

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6278

and

A6279

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

Serial

Data

Input

Clock

Input

Shift Register Contents

Serial

Data

Out

Latch

Enable

Input

Latch Contents

Output

Enable

Input

Output Contents

... I

-1

... I

-1

... I

-1

H R

... R

-2

-1

L R

... R

-2

-1

... R

-1

X X X ... X X

... R

-1

... P

-1

... P

-1

... P

-1

X X X ... X X

H H H ... H H

L = Low logic (voltage) level
H = High logic (voltage) level
X = Don't care
P = Present state
R = Previous state
n = 7 for the A6278, n = 15 for the A6279

Truth Table

Inputs and Outputs Equivalent Circuits

OUT

OUTPUT ENABLE

(active low)

CLOCK and

SERIAL DATA IN

LATCH ENABLE

SERIAL DATA OUT

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6278

and

A6279

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

A6278, n = 7

A6279, n = 15

CLOCK

OUTPUT

ENABLE

LATCH

ENABLE

CLOCK

OUTPUT

ENABLE

LATCH

ENABLE

CLOCK

OUTPUT

ENABLE

SERIAL

DATA OUT

Don't Care

low

high

SU(OE1)

SU(LE1)

H(LE1)

W(OE1)

H(OE1)

low

high

SU(OE1)

H(OE1)

SDO n

SDO n-1 SDO n-2

SDO 0

(A) To enter LED OCD mode, a minimum of one CLOCK pulse is required after LATCH ENABLE is brought back low.

(B) To output the latched error code, OUTPUT ENABLE must be held low a minimum of 3 CLOCK cycles.

Normal Mode Timing Requirements

LED Open Circuit Detection (Test) Mode Timing Requirements

CLOCK

A6278, n = 7

A6279, n = 15

SERIAL

DATA IN

SDI n

SDI n-1

SDI 0

Don't Care

SDO n

SERIAL

DATA OUT

LATCH

ENABLE

OUTPUT

ENABLE

OUT0

Don't Care

OUT1

OUTn

Don't Care

low

high

SU(D)

H(D)

p(DO)

SU(LE)

H(LE)

W(OE)

P(OE)

D(Total)

P(OE)

D(Total)

SU(OE)

Logic Levels: V

and GND

Logic Levels: V

and GND

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6278

and

A6279

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

Normal Mode
Serial data present at the

SERIAL DATA IN

input is transferred

to the shift register on the logic 0-to-logic 1 transition of the
CLOCK input pulse. On succeeding CLOCK pulses, the register
shifts data towards the SERIAL DATA OUT pin. The serial data
must appear at the input prior to the rising edge of the CLOCK
input waveform.

Data present in any register is transferred to the respective latch
when the LATCH ENABLE input is high (serial-to-parallel con-
version). The latches continue to accept new data as long as the
LATCH ENABLE input is held high.

Applications where the latches are bypassed (LATCH ENABLE
tied high) will require that the OUTPUT ENABLE input be high
during serial data entry. When the OUTPUT ENABLE input is
high, the output sink drivers are disabled (OFF).

The data stored in the latches is not affected by the OUTPUT
ENABLE input. With the OUTPUT ENABLE input active (low),
the outputs are controlled by the state of their respective latches.

LED Open Circuit Detection (Test) Mode

The LED Open Circuit Detection (OCD) mode, or Test mode,
is entered by clocking in the LED OCD mode initialization
sequence on the OUTPUT ENABLE (OE) and LATCH ENABLE
(LE) pins. In Normal mode, the OE and LE pins do not change
states while the CLOCK signal is cycling. The initialization
sequence is shown in panel A of the LED OCD timing require-
ments diagram on page 7.

Note: Each step event during mode sequencing happens on the
leading edge of the CLOCK signal. Five step events (CLOCK
pulses) are required to enter OCD mode and five step events are
required to return to Normal mode.

A pattern, such as all highs, should first be loaded into the reg-
isters and latched leaving LE low. The device is then sequenced
into LED OCD mode. It should be noted that data is still being
sent through the shift registers while entering the LED OCD
mode. However, this data is not latched when the LE pin goes
high and sees a CLOCK pulse during the initialization sequence.

Open circuit detection does not take place until the sequence in
Panel B on page 7 is performed. During this sequence, the OE
pin must be held low for a minimum of 2 s (t

W(OE1)

) to ensure

proper settling of the output currents and be given a minimum of
three CLOCK pulses. During the period that the OE pin is low
(active), OCD testing begins. The V

voltage on each of the

output pins is compared to the Open LED Detection Theshold,
V

CE(OCD)

. If the V

of an enabled output is lower than V

CE(OCD)

an error bit value of 0 is set in the corresponding shift register. A
value of 1 will be set if no error is detected. If a particular output
is not enabled, a 0 will be set. The error codes are summarized in
the following table:

After the testing process, setting the OE pin high causes the shift
registers to latch the error code data where it can then be clocked
out of the SERIAL DATA OUT pin. The OCD latching sequence
(OE low, 3 CLOCK pulses, OE high as shown in panel B of the
LED OCD timing diagram) can then be repeated if necessary to
look for intermittent contact problems.

The state of the outputs can be programmed with new data at any
time while in LED OCD mode (the same as in Normal mode).
This allows specific patterns to be tested for open circuits. The
pattern that is latched will then be tested during the OCD latching
sequence and the resulting bit values can be clocked out of the
SERIAL DATA OUT pin.

Note: LED Open Circuit Detection will not work properly if the
current is being externally limited by resistors to within the set
current limit for the device.

To return to Normal mode, perform the clocking sequence shown
in panel C of the timing diagram on the OE and LE pins.

Functional Description

Output State Test Condition Error Code Meaning

Output State

Test Condition

Error Code

Meaning

OFF N/A

N/A

< V

CE(OCD)

Open/TSD

CE(OCD)

Normal

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6278

and

A6279

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

Constant Current (R

EXT

)

The A6278 and A6279 allow the user to set the magnitude of
the constant current to the LEDs. Once set, the current remains
constant regardless of the LED voltage variation, the supply
voltage variation, or other circuit parameters that could otherwise

affect LED current. The output current is determined by the value
of an external current-control resistor (R

EXT

). The relationship of

these parameters is shown in figure 1. Typical characteristics for
output current and V

are shown in figure 2 for common values

of R

EXT

100

200

300

500

700

Figure 1. Output Current versus Current Control Resistance

= 25°C, V

= 0.7 V

(mA/Bit)

EXT

()

100

200

300

500

700

Figure 2. Output Current versus Device Voltage Drop

= 25°C

(mA/Bit)

(V)

EXT

= 225

EXT

= 470

EXT

= 3900

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6278

and

A6279

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

Undervoltage Lockout
The A6278 and A6279 include an internal under-voltage lockout
(UVLO) circuit that disables the outputs in the event that the
logic supply voltage drops below a minimum acceptable level.
This feature prevents the display of erroneous information, a
necessary function for some critical applications.

Upon recovery of the logic supply voltage after a UVLO event,
and on power-up, all internal shift registers and latches are set
to 0. The A6278/A6279 is then in Normal mode.

Output Staggering Delay
The A6278/A6279 has a 20 ns delay between each output. The
staggering of the outputs reduces the in-rush of currents onto the
power and ground planes. This aids in power supply decoupling
and EMI/EMC reduction.

The output staggering delay occurs under the following condi-
tions:

· OUTPUT ENABLE is pulled low

· OUTPUT ENABLE is held low and LATCH ENABLE is

pulled high

· OUTPUT ENABLE is held low, LATCH ENABLE is held high,

and CLOCK is pulled high

The 20 ns delays are cumulative across all the outputs. Under any
of the above conditions, the state of OUT0 gets set after a typical
propagation delay, t

P(OE)

. OUT1 will get set 20 ns after OUT0,

and so forth. In the A6279, OUT15 will get set after 300 ns (15 ×
20 ns) plus t

P(OE)

Note: The maximum CLOCK frequency is reduced in applica-
tions where both the OUTPUT ENABLE pin is held low and the
LATCH ENABLE pin is held high continuously, and the outputs
change state on the CLOCK edges. The staggering delay could
cause spurious output responses at CLOCK speeds greater than
1 MHz.

Thermal Shutdown
When the junction temperature of the A6278/A6279 reaches the
thermal shutdown temperature threshold, T

JTSD

(165°C typical),

the outputs are shut off until the junction temperature cools down
below the recovery threshold, T

JTSD

JTSDhys

(15°C typical).

The shift register and output latches will remain active during
a TSD event. Therefore, there is no need to reset the data in the
output latches.

In LED OCD mode, if the junction temperature reaches the Ther-
mal Shut Down threshold, the outputs will turn off, as in Normal
mode operation. However, all of the shift registers will be set
with 0, the error bit value.

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6278

and

A6279

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

Load Supply Voltage (V

LED

)

These devices are designed to operate with driver voltage
drops (V

) of 0.7 to 3V, with an LED forward voltage, V

, of

1.2 to 4.0 V. If higher voltages are dropped across the driver,
package power dissipation will increase significantly. To mini-
mize package power dissipation, it is recommended to use the
lowest possible load supply voltage, V

LED

, or to set any series

voltage dropping, V

DROP

, according to the following formula:

DROP

= V

LED

CE ,

with V

DROP

= I

× R

DROP

for a single driver or for a Zener diode

), or for a series string of diodes (approximately 0.7 V per

diode) for a group of drivers (see figure 3). If the available volt-
age source, V

LED

, will cause unacceptable power dissipation and

series resistors or diodes are undesirable, a voltage regulator can
be used to provide supply voltages.

For reference, typical LED forward voltages are:

LED Type

(V)

White

3.5 to 4.0

Blue

3.0 to 4.0

Green

1.8 to 2.2

Yellow

2.0 to 2.1

Amber

1.9 to 2.65

Red

1.6 to 2.25

Infrared

1.2 to 1.5

Pattern Layout
This device has a common logic ground and power ground
terminal, GND. For the LP package, the GND pin should be tied
to the exposed metal pad, EP, allowing the ground plane copper
to be used to dissipate heat. If the ground pattern layout contains
large common mode resistance, and the voltage between the
system ground and the LATCH ENABLE, OUTPUT ENABLE,
or CLOCK terminals exceeds 2.5 V (because of switching noise),
these devices may not work properly.
Package Power Dissipation (P

)

The maximum allowable package power dissipation based on
package type is determined by:

D(max)

= (150 T

) / R

where R

is the thermal resistance of the package, determined

experimentally. Power dissipation levels based on the package
are shown in the Package Thermal Characteristics section (see
page 14).
The actual package power dissipation is determined by:

D(act)

= DC × (V

× I

× 16) + (V

× I

) ,

where DC is the duty cycle. The value 16 represents the maxi-
mum number of available device outputs for the A6279, used for
the worst-case scenario (displaying all 16 LEDs; this would be 8
for the A6278).

When the load suppy voltage, V

LED

, is greater than 3 to 5 V, and

D(act)

> P

D(max)

, an external voltage reducer (V

DROP

) must be

used (see figure 3).

Reducing the percent duty cycle, DC, will also reduce power dis-
sipation. Typical results are shown on the following pages.

Application Information

LED

DROP

LED

DROP

LED

DROP

Figure 3. Typical appplications for voltage drops

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6278

and

A6279

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

Characteristic

Symbol

Test Conditions*

Value

Unit

Package Thermal Resistance

A package, 16-pin, measured on 4-layer board based on JEDEC standard

°C/W

A package, 24-pin, measured on 4-layer board based on JEDEC standard

°C/W

LP package, 16-pin, measured on 4-layer board based on JEDEC standard

°C/W

LP package, 24-pin, measured on 4-layer board based on JEDEC standard

°C/W

LW package, 16-pin, measured on 4-layer board based on JEDEC standard

°C/W

LW package, 24-pin, measured on 4-layer board based on JEDEC standard

°C/W

*Additional thermal information is available on the Allegro Web site.

A6278

A6279

5.0

4.0

3.0

2.0

1.0

Ambient Temperature, T

(°C)

Allowable Package Power Dissipation (W)

100

125

150

A, R

26°C/W

LP, R

28°C/W

LW, R

44°C/W

5.0

4.0

3.0

2.0

1.0

Ambient Temperature, T

(°C)

Allowable

Package

Power

Dissipation

(W)

100

125

150

38°C/W

LW,

48°C

LP,

34°C/W

Package Thermal Characteristics

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6278

and

A6279

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

Package A, 16-pin DIP (A6278)

.070
.045

1.78
1.14

.150
.115

3.81
2.92

.195
.115

4.95
2.92

.014
.008

0.36
0.20

.430
MAX

10.92

.015
MIN

0.38

.005
MIN

0.13

.775
.735

19.69
18.67

SEATING
PLANE

.022
.014

.056
.036

16X

.010 [0.25] M C

.100 .2.54

.300 .7.62

.280
.240

7.11
6.10

Preliminary dimensions, for reference only
Dimensions in inches
Metric dimensions (mm) in brackets, for reference only
(reference JEDEC MS-001 BB)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

A Terminal #1 mark area

Package A, 24-pin DIP (A6279)

.070
.045

1.78
1.14

.150
.115

3.81
2.92

.195
.115

4.95
2.92

.014
.008

0.36
0.20

.430
MAX

10.92

.015
MIN

0.38

.005
MIN

0.13

1.280
1.230

32.51
31.24

SEATING
PLANE

.022
.014

.056
.036

24X

.010 [0.25] M C

.100 .2.54

.300 .7.62

.280
.240

7.11
6.10

Preliminary dimensions, for reference only
Dimensions in inches
Metric dimensions (mm) in brackets, for reference only
(reference JEDEC MS-001 AF)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

A Terminal #1 mark area

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6278

and

A6279

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

Package LP, 16-pin TSSOP with Exposed Thermal Pad (A6278)

1.20
MAX

.047

0.15
0.00

.006
.000

0.30
0.19

.012
.007

4.5
4.3

.177
.169

6.6
6.2

.260
.244

0.20
0.09

.008
.004

8º
0º

0.75
0.45

.030
.018

1
REF

.039

5.10
4.90

.201
.193

SEATING
PLANE

16X

0.10 [.004] M C

0.10 [.004]

16X

0.65 .026

0.25 .010

5.9
NOM

.232

0.45
NOM

.018

0.65
NOM

.026

1.85
NOM

.073

0.53
REF

.021

3
NOM

.118

3
NOM

.118

3
NOM

.118

3
NOM

.118

GAUGE PLANE

SEATING PLANE

A Terminal #1 mark area

B Exposed thermal pad (bottom surface) U.S. Customary dimensions controlling

Preliminary dimensions, for reference only
(reference JEDEC MO-153 ABT)
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

C Reference land pattern layout (reference IPC7351

TSOP65P640X120-17M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6278

and

A6279

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

Package LP, 24-pin TSSOP with Exposed Thermal Pad (A6279)

1.20
MAX

.047

0.15
0.00

.006
.000

0.30
0.19

.012
.007

4.5
4.3

.177
.169

6.6
6.2

.260
.244

0.20
0.09

.008
.004

8º
0º

0.75
0.45

.030
.018

1
REF

.039

7.9
7.7

.311
.303

SEATING
PLANE

24X

0.10 [.004] M C

0.10 [.004]

24X

0.65 .026

0.25 .010

5.9
NOM

.232

0.45
NOM

.018

0.65
NOM

.026

1.85
NOM

.073

4.32
NOM

.170

0.53
REF

.021

3
NOM

.118

4.32
NOM

.170

3
NOM

.118

GAUGE PLANE

SEATING PLANE

A Terminal #1 mark area

B Exposed thermal pad (bottom surface) U.S. Customary dimensions controlling

Preliminary dimensions, for reference only
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

C Reference land pattern layout (reference IPC7351

TSOP65P640X120-25M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6278

and

A6279

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

Package LW, 24-pin SOIC (A6279)

Package LW, 16-pin SOIC (A6278)

0.30
0.10

.012
.004

2.65
2.35

.104
.093

7.60
7.40

.299
.291

0.33
0.20

.013
.008

8º
0º

1.27
0.40

.050
.016

10.50
10.10

.614
.598

SEATING
PLANE

0.10 [.004]

16X

0.25 .010

0.51
0.31

.020
.012

16X

0.25 [.010] M C

10.63

9.97

.419
.393

0.25 [.010] M B M

1.27 .050

GAUGE PLANE

SEATING PLANE

Preliminary dimensions, for reference only
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
(reference JEDEC MS-013 AA)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

A Terminal #1 mark area

0.30
0.10

.012
.004

2.65
2.35

.104
.093

7.60
7.40

.299
.291

0.33
0.20

.013
.008

8º
0º

1.27
0.40

.050
.016

15.60
15.20

.614
.598

SEATING
PLANE

0.10 [.004]

24X

0.25 .010

0.51
0.31

.020
.012

24X

0.25 [.010] M C

10.63

9.97

.419
.393

0.25 [.010] M B M

1.27 .050

GAUGE PLANE

SEATING PLANE

Preliminary dimensions, for reference only
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
(reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

A Terminal #1 mark area

Serial-Input, Constant-Current Latched

LED Drivers with Open LED Detection

A6278

and

A6279

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

The products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283; 5,389,889;
5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719; 5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to

permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro products are not authorized for use as critical components in life-support devices or sys tems without express written approval.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its
use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.
Copyright©2005, 2006 Allegro MicroSystems, Inc.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: A6278

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: A6278