DABiC-IV, 10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6810xA
Data Sheet
26182.124D*
ABSOLUTE MAXIMUM RATINGS
at T
A
= 25
C
Logic Supply Voltage, V
DD
................... 7.0 V
Driver Supply Voltage, V
BB
................... 60 V
Continuous Output Current Range,
I
OUT
......................... -40 mA to +15 mA
Input Voltage Range,
V
IN
....................... -0.3 V to V
DD
+ 0.3 V
Package Power Dissipation,
P
D
........................................ See Graph
Operating Temperature Range, T
A
(Suffix `E') .................. -40
C to +85
C
(Suffix `S') .................. -20
C to +85
C
Storage Temperature Range,
T
S
............................... -55
C to +125
C
Caution: These CMOS devices have input
static protection (Class 2) but are still
susceptible to damage if exposed to
extremely high static electrical charges.
The A6810 devices combine 10-bit CMOS shift registers, accom-
panying data latches and control circuitry with bipolar sourcing outputs
and pnp active pull downs. Designed primarily to drive vacuum-
fluorescent displays, the 60 V and -40 mA output ratings also allow
these devices to be used in many other peripheral power driver applica-
tions. The A6810 feature an increased data input rate (compared with
the older UCN/UCQ5810-F) and a controlled output slew rate.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply,
serial-data input rates of at least 10 MHz .
A CMOS serial data output permits cascade connections in applica-
tions requiring additional drive lines. Similar devices are available as
the A6812 (20 bits) and A6818 (32 bits).
The A6810 output source drivers are npn Darlingtons, capable of
sourcing up to 40 mA. The controlled output slew rate reduces electro-
magnetic noise, which is an important consideration in systems that
include telecommunications and/or microprocessors and to meet
government emissions regulations. For inter-digit blanking, all output
drivers can be disabled and all sink drivers turned on with a BLANK-
ING input high. The pnp active pull-downs will sink at least
2.5 mA.
The A6810 are available in two temperature ranges for optimum
performance in commercial (suffix S-) or industrial (suffix E-) applica-
tions. They are provided in two package styles for through-hole DIP
(suffix -A) or minimum-area surface-mount SOIC (suffix -LW).
Copper lead frames, low logic-power dissipation, and low output-
saturation voltages allow all devices to source 25 mA from all outputs
continuously over the maximum operating temperature range.
FEATURES
s
Controlled Output Slew Rate
s
High-Speed Data Storage
s
60 V Minimum
Output Breakdown
s
High Data Input Rate
s
PNP Active Pull-Downs
s
Low Output-Saturation Voltages
s
Low-Power CMOS Logic
and Latches
Complete part number includes a suffix to identify operating
temperature range (E- or S-) and package type (-A or -LW). Always
order by complete part number, e.g., A6810SLW .
6810
s
Improved Replacements
for TL4810, UCN5810,
and UCQ5810
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SERIAL
DATA OUT
LOAD
SUPPLY
SERIAL
DATA IN
BLANKING
LOGIC
SUPPLY
STROBE
GROUND
CLOCK
CLK
V
ST
BLNK
DD
BB
V
OUT
9
OUT
10
OUT
1
OUT
2
OUT
3
Dwg. PP-029
OUT
8
OUT
7
OUT
6
OUT
5
OUT
4
1
LATCHES
REGISTER
REGISTER
LATCHES
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright 1998, 2003 Allegro MicroSystems, Inc.
TYPICAL OUTPUT DRIVER
TYPICAL INPUT CIRCUIT
A6810xLW
13
14
15
16
17
19
12
18
20
SERIAL
DATA OUT
LOAD SUPPLY
SERIAL
DATA IN
BLANKING
OUT
9
OUT
10
OUT
1
OUT
2
OUT
3
11
NO
CONNECTION
1
2
3
8
9
4
5
6
7
LOGIC SUPPLY
STROBE
GROUND
CLOCK
OUT
8
OUT
7
OUT
6
OUT
5
OUT
4
10
NO
CONNECTION
CLK
V
ST
BLNK
DD
BB
V
Dwg. PP-029-2
LATCHES
REGISTER
REGISTER
LATCHES
NC
NC
50
75
100
125
150
2.5
0.5
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE IN
C
2.0
1.5
1.0
25
Dwg. GS-009-1B
SUFFIX 'A', R
JA
= 65
C/W
SUFFIX 'LW', R
JA
= 90
C/W
Dwg. EP-010-5
IN
V
DD
V
BB
Dwg. EP-021-19
OUT
N
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
www.allegromicro.com
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
Serial
Shift Register Contents
Serial
Latch Contents
Output Contents
Data
Clock
Data
Strobe
Input
Input I
1
I
2
I
3
...
I
N-1
I
N
Output
Input
I
1
I
2
I
3
...
I
N-1
I
N
Blanklng
I
1
I
2
I
3
... I
N-1
I
N
H
H
R
1
R
2
...
R
N-2
R
N-1
R
N-1
L
L
R
1
R
2
...
R
N-2
R
N-1
R
N-1
X
R
1
R
2
R
3
...
R
N-1
R
N
R
N
X
X
X
...
X
X
X
L
R
1
R
2
R
3
...
R
N-1
R
N
P
1
P
2
P
3
...
P
N-1
P
N
P
N
H
P
1
P
2
P
3
...
P
N-1
P
N
L
P
1
P
2
P
3
... P
N-1
P
N
X
X
X
...
X
X
H
L
L
L
... L L
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
MOS
BIPOLAR
OUT
1
OUT
2
GROUND
Dwg. FP-013-1
OUT
3
OUT
N
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
V
DD
V
BB
LOGIC
SUPPLY
LOAD
SUPPLY
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Limits @ V
DD
= 3.3 V Limits @ V
DD
= 5 V
Characteristic
Symbol
Test Conditions
Mln.
Typ.
Max.
Min.
Typ.
Max.
Units
Output Leakage Current
I
CEX
V
OUT
= 0 V
--
<-0.1
-15
--
<-0.1
-15
A
Output Voltage
V
OUT(1)
I
OUT
= -25 mA
57.5
58.3
--
57.5
58.3
--
V
V
OUT(0)
I
OUT
= 1 mA
--
1.0
1.5
--
1.0
1.5
V
Output Pull-Down Current
I
OUT(0)
V
OUT
= 5 V to V
BB
2.5
5.0
--
2.5
5.0
--
mA
Input Voltage
V
IN(1)
2.2
--
--
3.3
--
--
V
V
IN(0)
--
--
1.1
--
--
1.7
V
Input Current
I
IN(1)
V
IN
= V
DD
--
<0.01
1.0
--
<0.01
1.0
A
I
IN(0)
V
IN
= 0 V
--
<-0.01
-1.0
--
<-0.01
-1.0
A
Input Clamp Voltage
V
IK
I
IN
= -200
A
--
-0.8
-1.5
--
-0.8
-1.5
V
Serial Data Output Voltage
V
OUT(1)
I
OUT
= -200
A
2.8
3.05
--
4.5
4.75
--
V
V
OUT(0)
I
OUT
= 200
A
--
0.15
0.3
--
0.15
0.3
V
Maximum Clock Frequency
f
c
10*
--
--
10*
--
--
MHz
Logic Supply Current
I
DD(1)
All Outputs High
--
0.25
0.75
--
0.3
1.0
mA
I
DD(0)
All Outputs Low
--
0.25
0.75
--
0.3
1.0
mA
Load Supply Current
I
BB(1)
All Outputs High, No Load
--
1.5
3.0
--
1.5
3.0
mA
I
BB(0)
All Outputs Low
--
0.2
20
--
0.2
20
A
Blanking-to-Output Delay
t
dis(BQ)
C
L
= 30 pF, 50% to 50%
--
0.7
2.0
--
0.7
2.0
s
t
en(BQ)
C
L
= 30 pF, 50% to 50%
--
1.8
3.0
--
1.8
3.0
s
Strobe-to-Output Delay
t
p(STH-QL)
R
L
= 2.3 k
, C
L
30 pF
--
0.7
2.0
--
0.7
2.0
s
t
p(STH-QH)
R
L
= 2.3 k
, C
L
30 pF
--
1.8
3.0
--
1.8
3.0
s
Output Fall Time
t
f
R
L
= 2.3 k
, C
L
30 pF
2.4
--
12
2.4
--
12
s
Output Rise Time
t
r
R
L
= 2.3 k
, C
L
30 pF
2.4
--
12
2.4
--
12
s
Output Slew Rate
dV/dt
R
L
= 2.3 k
, C
L
30 pF
4.0
--
20
4.0
--
20
V/
s
Clock-to-Serial Data Out Delay t
p(CH-SQX)
I
OUT
=
200
A
--
50
--
--
50
--
ns
Negative current is defined as coming out of (sourcing) the specified device terminal.
Typical data is is for design information only and is at T
A
= +25
C.
*Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
ELECTRICAL CHARACTERISTICS at T
A
= +25
C (A6810S-) or over operating temperature
range (A6810E-), V
BB
= 60 V unless otherwise noted.
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
www.allegromicro.com
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are V
DD
and Ground)
Serial Data present at the input is transferred to the shift
register on the logic "0" to logic "1" transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
OUT
N
Dwg. WP-029
50%
SERIAL
DATA OUT
DATA
DATA
10%
90%
50%
50%
50%
C
A
B
D
E
LOW = ALL OUTPUTS ENABLED
p(STH-QL)
t
p(CH-SQX)
t
DATA
p(STH-QH)
t
BLANKING
OUT
N
Dwg. WP-030A
DATA
10%
50%
en(BQ)
t
dis(BQ)
t
HIGH = ALL OUTPUTS BLANKED (DISABLED)
r
t
f
t
50%
90%
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), t
su(D)
......................................... 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), t
h(D)
............................................... 25 ns
C. Clock Pulse Width, t
w(CH)
............................................... 50 ns
D. Time Between Clock Activation and Strobe, t
su(C)
....... 100 ns
E. Strobe Pulse Width, t
w(STH)
............................................. 50 ns
NOTE Timing is representative of a 10 MHz clock. Higher
speeds may be attainable; operation at high temperatures will
reduce the specified maximum clock frequency.
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
A6810EA & A6810SA
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
4. Supplied in standard sticks/tubes of 21 devices.
0.014
0.008
0.300
BSC
Dwg. MA-001-18A in
0.430
MAX
18
1
9
0.280
0.240
0.210
MAX
0.070
0.045
0.015
MIN
0.022
0.014
0.100
BSC
0.005
MIN
0.150
0.115
10
0.920
0.880
0.355
0.204
7.62
BSC
Dwg. MA-001-18A mm
10.92
MAX
18
1
9
7.11
6.10
5.33
MAX
1.77
1.15
0.39
MIN
0.558
0.356
2.54
BSC
0.13
MIN
3.81
2.93
10
23.37
22.35
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
www.allegromicro.com
0
TO
8
1
2
3
0.020
0.013
0.0040
MIN.
0.0125
0.0091
0.050
0.016
Dwg. MA-008-20 in
0.050
BSC
20
11
0.2992
0.2914
0.419
0.394
0.5118
0.4961
0.0926
0.1043
0
TO
8
1
20
2
3
0.51
0.33
0.10
MIN.
Dwg. MA-008-20 mm
1.27
BSC
11
0.32
0.23
1.27
0.40
7.60
7.40
10.65
10.00
13.00
12.60
2.65
2.35
A6810ELW & A6810SLW
Dimensions in Inches
(for reference only)
Dimensions in Millimeters
(controlling dimensions)
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 37 devices or add "TR" to part number for tape and reel.
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
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