4
5
6
7
8
9
10
19
20
21
22
23
24
25
LOAD
SUPPLY
BB
V
OUT
2
OUT
7
OUT
8
Dwg. PP-029-7
OUT
19
OUT
18
OUT
13
12
13
14
27
28
17
18
SERIAL
DATA OUT
BLANKING
LOGIC
SUPPLY
STROBE
GROUND
CLOCK
CLK
ST
BLNK
OUT
9
OUT
10
OUT
12
OUT
11
11
LATCHES
REGISTER
REGISTER
LATCHES
2
3
26
27
28
SERIAL
DATA IN
OUT
6
OUT
1
OUT
4
OUT
3
OUT
20
1
15
16
OUT
5
OUT
17
OUT
16
OUT
15
OUT
14
DD
V
DABiC-IV, 20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6812xA
Data Sheet
26182.126A
ABSOLUTE MAXIMUM RATINGS
at T
A
= 25
C
Logic Supply Voltage, V
DD
................... 7.0 V
Driver Supply Voltage, V
BB
................... 60 V
Continuous Output Current Range,
I
OUT
......................... -40 mA to +15 mA
Input Voltage Range,
V
IN
....................... -0.3 V to V
DD
+ 0.3 V
Package Power Dissipation,
P
D
........................................ See Graph
Operating Temperature Range, T
A
(Suffix `E') .................. -40
C to +85
C
(Suffix `S') .................. -20
C to +85
C
Storage Temperature Range,
T
S
............................... -55
C to +125
C
Caution: These CMOS devices have input static
protection (Class 2) but are still susceptible to
damage if exposed to extremely high static
electrical charges.
The A6812 devices combine a 20-bit CMOS shift register,
accompanying data latches and control circuitry with bipolar sourcing
outputs and pnp active pull downs. Designed primarily to drive
vacuum-fluorescent displays, the 60 V and -40 mA output ratings also
allow these devices to be used in many other peripheral power driver
applications. The A6812 features an increased data input rate (com-
pared with the older UCN/UCQ5812-F) and a controlled output slew
rate.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply, they
will operate to at least 10 MHz.
A CMOS serial data output permits cascade connections in applica-
tions requiring additional drive lines. Similar devices are available as
the A6809 and A6810 (10 bits), A6811 (12 bits), and A6818 (32
bits).
The A6812 output source drivers are npn Darlingtons, capable of
sourcing up to 40 mA. The controlled output slew rate reduces electro-
magnetic noise, which is an important consideration in systems that
include telecommunications and/or microprocessors and to meet
government emissions regulations. For inter-digit blanking, all output
drivers can be disabled and all sink drivers turned on with a BLANK-
ING input high. The pnp active pull-downs will sink at least 2.5 mA.
Two temperature ranges are available for optimum performance in
commercial (suffix S-) or industrial (suffix E-) applications. Package
styles are provided for through-hole DIP (suffix -A), surface-mount
SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix
-EP). Copper lead frames, low logic-power dissipation, and low
output-saturation voltages allow these drivers to source 25 mA from all
outputs continuously to more than +43
C (suffix -LW), +61C (suffix
-EP), or +77
C (suffix -A).
FEATURES
I Controlled Output Slew Rate
I High-Speed Data Storage
I 60 V Minimum
Output Breakdown
I High Data Input Rate
I PNP Active Pull-Downs
Complete part number includes a suffix to identify operating
temperature range (E- or S-) and package type (-A, -EP, or -LW).
Always order by complete part number, e.g., A6812SLW .
6812
I Low Output-Saturation Voltages
I Low-Power CMOS Logic
and Latches
I Improved Replacements
for TL5812, UCN5812,
and UCQ5812
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
ELECTRICAL CHARACTERISTICS at T
A
= +25
C (A6812S-) or over operating temperature
range (A6812E-), V
BB
= 60 V unless otherwise noted.
Limits @ V
DD
= 3.3 V Limits @ V
DD
= 5 V
Characteristic
Symbol
Test Conditions
Mln.
Typ.
Max.
Min.
Typ.
Max.
Units
Output Leakage Current
I
CEX
V
OUT
= 0 V
--
<-0.1
-15
--
<-0.1
-15
A
Output Voltage
V
OUT(1)
I
OUT
= -25 mA
57.5
58.3
--
57.5
58.3
--
V
V
OUT(0)
I
OUT
= 1 mA
--
1.0
1.5
--
1.0
1.5
V
Output Pull-Down Current
I
OUT(0)
V
OUT
= 5 V to V
BB
2.5
5.0
--
2.5
5.0
--
mA
Input Voltage
V
IN(1)
2.2
--
--
3.3
--
--
V
V
IN(0)
--
--
1.1
--
--
1.7
V
Input Current
I
IN(1)
V
IN
= V
DD
--
<0.01
1.0
--
<0.01
1.0
A
I
IN(0)
V
IN
= 0 V
--
<-0.01
-1.0
--
<-0.01
-1.0
A
Input Clamp Voltage
V
IK
I
IN
= -200
A
--
-0.8
-1.5
--
-0.8
-1.5
V
Serial Data Output Voltage
V
OUT(1)
I
OUT
= -200
A
2.8
3.05
--
4.5
4.75
--
V
V
OUT(0)
I
OUT
= 200
A
--
0.15
0.3
--
0.15
0.3
V
Maximum Clock Frequency
f
c
10*
--
--
10*
--
--
MHz
Logic Supply Current
I
DD(1)
All Outputs High
--
0.25
0.75
--
0.3
1.0
mA
I
DD(0)
All Outputs Low
--
0.25
0.75
--
0.3
1.0
mA
Load Supply Current
I
BB(1)
All Outputs High, No Load
--
3.0
6.0
--
3.0
6.0
mA
I
BB(0)
All Outputs Low
--
0.2
20
--
0.2
20
A
Blanking-to-Output Delay
t
dis(BQ)
C
L
= 30 pF, 50% to 50%
--
0.7
2.0
--
0.7
2.0
s
t
en(BQ)
C
L
= 30 pF, 50% to 50%
--
1.8
3.0
--
1.8
3.0
s
Strobe-to-Output Delay
t
p(STH-QL)
R
L
= 2.3 k
, C
L
30 pF
--
0.7
2.0
--
0.7
2.0
s
t
p(STH-QH)
R
L
= 2.3 k
, C
L
30 pF
--
1.8
3.0
--
1.8
3.0
s
Output Fall Time
t
f
R
L
= 2.3 k
, C
L
30 pF
2.4
--
12
2.4
--
12
s
Output Rise Time
t
r
R
L
= 2.3 k
, C
L
30 pF
2.4
--
12
2.4
--
12
s
Output Slew Rate
dV/dt
R
L
= 2.3 k
, C
L
30 pF
4.0
--
20
4.0
--
20
V/
s
Clock-to-Serial Data Out Delay t
p(CH-SQX)
I
OUT
=
200 A
--
50
--
--
50
--
ns
Negative current is defined as coming out of (sourcing) the specified device terminal.
Typical data is is for design information only and is at T
A
= +25
C.
* Operation at a clock frequency greater than the specified minimum is possible but not warranteed.
6812
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
www.allegromicro.com
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are V
DD
and Ground)
Serial Data present at the input is transferred to the shift
register on the logic "0" to logic "1" transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
OUT
N
Dwg. WP-029
50%
SERIAL
DATA OUT
DATA
DATA
10%
90%
50%
50%
50%
C
A
B
D
E
LOW = ALL OUTPUTS ENABLED
p(STH-QL)
t
p(CH-SQX)
t
DATA
p(STH-QH)
t
BLANKING
OUT
N
Dwg. WP-030
DATA
10%
50%
en(BQ)
t
dis(BQ)
t
HIGH = ALL OUTPUTS BLANKED (DISABLED)
90%
r
t
f
t
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), t
su(D)
...................................... 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), t
h(D)
............................................ 25 ns
C. Clock Pulse Width, t
w(CH)
............................................ 50 ns
D. Time Between Clock Activation and Strobe, t
su(C)
.... 100 ns
E. Strobe Pulse Width, t
w(STH)
.......................................... 50 ns
NOTE Timing is representative of a 10 MHz clock. Higher
speeds may be attainable with increased supply voltage;
operation at high temperatures will reduce the specified
maximum clock frequency.
PDF 
ZIP
