Data Sheet
26185.1
12B
Package LW
16-pin Wide Body SOIC
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
A merged combination of bipolar and MOS technology gives these
devices an interface fl exibility beyond the reach of standard logic
buffers and power driver arrays. Typical applications include driving
multiplexed LED displays or incandescent lamps.
The A6821 has an eight-bit CMOS shift register and CMOS control
circuitry, eight CMOS data latches, and eight bipolar current-sinking
Darlington output drivers.
The CMOS inputs are compatible with standard CMOS logic levels.
TTL circuits may require the use of appropriate pull-up resistors. By
using the serial data output, the drivers can be cascaded for interface
applications requiring additional drive lines.
The A6821SA is furnished in a standard 16-pin plastic DIP. The
A6821EA is a 16-pin plastic DIP, capable of operation from -40C to
+85C. The A6821SLW is a 16-lead wide-body SOIC, for surface-
mount applications. These devices are lead (Pb) free, with 100% matte
tin plated leadframes.
3.3 V to 5 V logic supply range
Power on reset (POR)
To 10 MHz data input rate
CMOS, TTL compatible
40C operation available
Use the following complete part numbers when ordering:
AB SO LUTE MAX I MUM RAT INGS
Part Number
Package
Ambient
A6821SA-T
16-pin DIP
20C to +85C
A6821EA-T
16-pin DIP
40C to +85C
A6821SLW-T
16-pin wide body SOIC
20C to +85C
Output Voltage, V
OUT
.........................................50 V
Logic Supply Voltage, V
DD
...................................7 V
Input Voltage Range, V
IN
..............0.3 V to V
DD
+0.3 V
Continuous Output Current (each output), I
OUT
... 500 mA
Package Power Dissipation, P
D
A6821SA/A6821EA..................................2.1 W
A6821SLW............................................... 1.5 W
Operating Temperature Range
Ambient Temperature, T
A
............20C to +85C
Storage Temperature, T
S
..........55C to +150C
Caution: CMOS devices have input-static protection,
but are susceptible to damage when exposed to
extremely high static-electrical charges.
FEATURES
Multiplexed LED displays
Incandescent lamps
APPLICATIONS
Package A
16-pin DIP
Schmitt trigger inputs for improved
noise immunity
Low-power CMOS logic and latches
High-voltage current-sink outputs
Internal pull-up/pull down resistors
2
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Data Sheet
26185.1
12B
Functional Block Diagram
MOS
B IP OLAR
OUT
1
OUT
2
LOG IC
G R OUND
S T R OB E
OUT P UT E NAB LE
(AC T IV E LOW)
S E R IAL
DAT A OUT
OUT
3
C LOC K
S E R IAL
DAT A IN
S E R IAL-P AR ALLE L S HIF T R E G IS T E R
LAT C HE S
V
DD
LOG IC
S UP P LY
OUT
6
OUT
7
OUT
8
OUT
4
OUT
5
P OWE R
G R OUND
S UB
Typical Input Circuits
Typical Output Driver
CLOCK
SERIAL
DATA IN
V
DD
STROBE
OUTPUT
ENABLE
V
DD
OUT
7.2 k
3 k
SUB
3
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Data Sheet
26185.1
12B
ELECTRICAL CHARACTERISTICS
1
Unless otherwise noted: T
A
= 25C, logic supply operating voltage V
dd
= 3.0 V to 5.5 V
Characteristic
Symbol
Test Conditions
V
dd
= 3.3 V
V
dd
= 5 V
Units
Min.
Typ. Max. Min.
Typ.
Max.
Output Leakage Current
I
CEX
V
OUT
= 50 V
10
10
A
CollectorEmitter Saturation
Voltage
V
CE(SAT)
I
OUT
= 100 mA
1.1
1.1
V
I
OUT
= 200 mA
1.3
1.3
V
I
OUT
= 350 mA
1.6
1.6
V
Input Voltage
V
IN(1)
2.2
3.3
V
V
IN(0)
1.1
1.7
V
Input Resistance
R
IN
50
50
k
Serial Data Output Voltage
V
OUT(1)
I
OUT
= 200 A
2.8
3.05
4.5
4.75
V
V
OUT(0)
I
OUT
= 200 A
0.15
0.3
0.15
0.3
V
Maximum Clock Frequency
2
f
c
10
10
MHz
Logic Supply Current
I
DD(1)
One output on, OE = L, ST = H
2.0
2.0
mA
I
DD(0)
All outputs off, OE = H, ST = H,
P1 through P8 = L
100
100
A
Output Enable-to-Output Delay
t
dis(BQ)
V
CC
= 50 V, R1 = 500 , C1 30 pF
1.0
1.0
s
t
en(BQ)
V
CC
= 50 V, R1 = 500 , C1 30 pF
1.0
1.0
s
Strobe-to-Output Delay
t
p(STH-QL)
V
CC
= 50 V, R1 = 500 , C1 30 pF
1.0
1.0
s
t
p(STH-QH)
V
CC
= 50 V, R1 = 500 , C1 30 pF
1.0
1.0
s
Output Fall Time
t
f
V
CC
= 50 V, R1 = 500 , C1 30 pF
1.0
1.0
s
Output Rise Time
t
r
V
CC
= 50 V, R1 = 500 , C1 30 pF
1.0
1.0
s
Clock-to-Serial Data Out Delay
t
p(CH-SQX)
I
OUT
= 200 A
50
50
ns
1
Positive (negative) current is defi ned as conventional current going into (coming out of) the specifi ed device pin.
2
Operation at a clock frequency greater than the specifi ed minimum value is possible but not warran
teed.
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
OE = Output Enable
ST = Strobe
Serial
Shift Register Contents Serial
Latch Contents
Output
Output Contents
Data Clock
Data
Strobe
Enable
Input
Input
I
1
I
2
I
3
... I
8
Output
Input
I
1
I
2
I
3
... I
8
Input
I
1
I
2
I
3
... I
8
R
7
R
7
R
1
R
2
R
3
... R
8
R
8
X
X
X
... X
X
X
L
R
1
R
2
... R
7
L
L
R
1
R
2
R
3
... R
8
P
1
P
2
P
3
... P
8
P
8
P
1
P
2
P
3
... P
8
1
P
2
P
3
... P
8
X
X
X
... X
L
P
H
H
H
H
H
R
1
R
2
... R
7
H
H
H
...
Truth Table
4
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Data Sheet
26185.1
12B
Timing Requirements and Specifi cations
(Logic Levels are V
DD
and Ground)
CLOCK
SERIAL
DATA IN
STROBE
OUTPUT ENABLE
OUT
N
50%
SERIAL
DATA OUT
DATA
DATA
10%
90%
50%
50%
50%
C
A
B
D
E
LOW = ALL OUTP UTS E NABLE D
p(STH-QL)
t
p(CH-SQX)
t
DATA
p(STH-QH)
t
OUTPUT ENABLE
OUT
N
DATA
10%
50%
dis(BQ)
t
en(BQ)
t
HIGH = ALL OUTP UTS BLANKE D (DIS ABLE D)
r
t
f
t
50%
90%
NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be
attainable; operation at high temperatures will reduce the specifi ed maxi-
mum clock frequency.
Powering-on with the inputs in the low state ensures that the registers and
latches power-on in the low state (POR).
S
erial Data present at the input is transferred to the shift register on the logical
0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK
pulses, the registers shift data information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the input prior to the rising edge of the
CLOCK input waveform.
Information present at any register is transferred to the respective latch
when the STROBE is high (serial-to-parallel conversion). The latches will
continue to accept new data as long as the STROBE is held high. Applica-
tions where the latches are bypassed (STROBE tied high) will require that
the OUTPUT ENABLE input be high during serial data entry.
When the OUTPUT ENABLE input is high, all of the output buffers are
disabled (OFF). The information stored in the latches or shift register is not
affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE
input low, the outputs are controlled by the state of their respective latches.
Key
Description
Symbol
Time (ns)
A
Data Active Time Before Clock Pulse (Data Set-Up Time)
t
su(D)
25
B
Data Active Time After Clock Pulse (Data Hold Time)
t
h(D)
25
C
Clock Pulse Width
t
w(CH)
50
D
Time Between Clock Activation and Strobe
t
su(C)
100
E
Strobe Pulse Width
t
w(STH)
50
5
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Data Sheet
26185.1
12B
8
67%
59%
54%
49%
43%
7
77%
68%
62%
56%
49%
6
90%
79%
72%
65%
57%
5
100%
95%
86%
78%
68%
4
100%
100%
100%
98%
86%
3
100%
100%
100%
100%
100%
2
100%
100%
100%
100%
100%
1
100%
100%
100%
100%
100%
A6821SLW
A6821SA/A6821EA
Number of
O utputs O N
A mbient T emperature
25
C
40
C
50
C
60
C
70
C
8
90%
79%
72%
65%
57%
7
100%
90%
82%
74%
65%
6
100%
100%
96%
86%
76%
5
100%
100%
100%
100%
91%
4
100%
100%
100%
100%
100%
3
100%
100%
100%
100%
100%
2
100%
100%
100%
100%
100%
1
100%
100%
100%
100%
100%
Terminal List Table
Name
Description
Pin
CLK
Clock
1
Serial Data In
2
Logic Ground*
3
VDD
Logic Supply
4
Serial Data Out
5
ST
Strobe
6
OE
Output Enable (active low)
7
SUB
Power Ground*
8
OUT
8
Serial Data Output
9
OUT
7
Serial Data Output
10
OUT
6
Serial Data Output
11
OUT
5
Serial Data Output
12
OUT
4
Serial Data Output
13
OUT
3
Serial Data Output
14
OUT
2
Serial Data Output
15
OUT
1
Serial Data Output
16
* There is an indeterminate resistance between logic ground and power ground.
For proper operation, these terminals must be externally connected together.
Maximum Allowable Duty Cycle, I
OUT
= 200 mA, V
DD
= 5 V
6
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Data Sheet
26185.1
12B
Package LW
16-pin Wide Body SOIC
2
3
4
5
6
7
8
SERIAL
DATA OUT
SERIAL
DATA IN
OUTPUT
ENABLE
LOGIC
SUPPLY
STROBE
LOGIC
GROUND
CLOCK
CLK
V
ST
OE
DD
1
SUB
POWER
GROUND
SHIFT REGISTER
LATCHES
9
10
11
12
13
14
15
16
OUT
1
OUT
2
OUT
3
OUT
8
OUT
7
OUT
6
OUT
5
OUT
4
Package A
16-pin DIP
2
3
4
5
6
7
8
S E R IAL
DAT A OUT
S E R IAL
DAT A IN
OUT P UT
E NAB LE
LOG IC
S UP P LY
S T R OB E
LOG IC
G R OUND
C LO C K
C LK
V
S T
OE
DD
1
S UB
P OWE R
G R OUND
S
H
IF
T
R
E
G
IS
T
E
R
LA
T
C
H
E
S
9
10
11
12
13
14
15
16
OUT
1
OUT
2
OUT
3
OUT
8
OUT
7
OUT
6
OUT
5
OUT
4
7
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Data Sheet
26185.1
12B
NOTES: 1. Lead thickness is measured at seating plane or below.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor's option within limits shown.
0.014
0.008
0.300
BSC
Dwg. MA-001-16A in
0.430
MAX
16
1
8
0.280
0.240
0.210
MAX
0.070
0.045
0.015
MIN
0.022
0.014
0.100
BSC
0.005
MIN
0.150
0.115
9
0.775
0.735
0.355
0.204
7.62
BSC
Dwg. MA-001-16A mm
10.92
MAX
16
1
8
7.11
6.10
5.33
MAX
1.77
1.15
0.39
MIN
0.558
0.356
2.54
BSC
0.13
MIN
3.81
2.93
9
19.68
18.67
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
Package A
16-pin DIP
8
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Data Sheet
26185.1
12B
NOTES: 1. Lead spacing tolerance is non-cumulative.
2. Exact body and lead configuration at vendor's option within limits shown.
Dimensions in Inches
(for reference only)
Dimensions in Millimeters
(controlling dimensions)
1
2
3
0.2992
0.2914
0.4133
0.3977
0.419
0.394
0.020
0.013
0.0926
0.1043
0.0040
MIN.
0.0125
0.0091
0.050
0.016
0
TO
8
Dwg. MA-008-16A in
0.050
BSC
16
9
9
16
1
2
3
7.60
7.40
10.50
10.10
10.65
10.00
0.51
0.33
2.65
2.35
0.10
MIN.
0.32
0.23
1.27
0.40
0
TO
8
Dwg. MA-008-16A mm
1.27
BSC
Package LW
16-pin Wide Body SOIC
9
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Data Sheet
26185.1
12B
The products described here are manufactured under one or
more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time
to time, such de par tures from the detail spec i fi ca tions as may be
required to permit improvements in the per for mance, reliability,
or manufacturability of its products. Before placing an order, the
user is cautioned to verify that the information being relied upon is
current.
Allegro products are not authorized for use as critical compo-
nents in life-support devices or sys tems without express written
approval.
The in for ma tion in clud ed herein is believed to be ac cu rate and
reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon -
si bil i ty for its use; nor for any in fringe ment of patents or other
rights of third parties which may result from its use.
Copyright2004, 2005 AllegroMicrosystems, Inc.
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